Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_0.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_0.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_0.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_0.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_0.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_0.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_0.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_0.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_0.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_0.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_0.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_0.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_1.ecc_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_1.ecc_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_1.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_1.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_1.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_1.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_1.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_1.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_1.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_1.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_1.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_1.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_1.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_1.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_2.ecc_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_2.ecc_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_2.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_2.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_2.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_2.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_2.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_2.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_2.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_2.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_2.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_2.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_2.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_2.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_3.ecc_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_3.ecc_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_3.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_3.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_3.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_3.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_3.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_3.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_3.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_3.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_3.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_3.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_3.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_3.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_4.ecc_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_4.ecc_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_4.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_4.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_4.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_4.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_4.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_4.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
104 |
1 |
|
T2 |
6 |
|
T128 |
1 |
|
T118 |
4 |
| others[1] |
105 |
1 |
|
T2 |
4 |
|
T5 |
1 |
|
T15 |
1 |
| others[2] |
113 |
1 |
|
T2 |
2 |
|
T196 |
2 |
|
T48 |
1 |
| others[3] |
168 |
1 |
|
T2 |
4 |
|
T128 |
6 |
|
T198 |
1 |
| false |
53 |
1 |
|
T2 |
1 |
|
T128 |
2 |
|
T118 |
3 |
| true |
6194 |
1 |
|
T1 |
1 |
|
T3 |
1 |
|
T24 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
246 |
1 |
|
T2 |
2 |
|
T77 |
1 |
|
T128 |
7 |
| others[1] |
231 |
1 |
|
T2 |
1 |
|
T3 |
1 |
|
T15 |
1 |
| others[2] |
214 |
1 |
|
T2 |
3 |
|
T5 |
1 |
|
T61 |
1 |
| others[3] |
391 |
1 |
|
T2 |
3 |
|
T77 |
3 |
|
T42 |
1 |
| false |
124 |
1 |
|
T128 |
6 |
|
T196 |
1 |
|
T118 |
5 |
| true |
5531 |
1 |
|
T1 |
1 |
|
T2 |
8 |
|
T24 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1035 |
1 |
|
T2 |
4 |
|
T10 |
1 |
|
T16 |
7 |
| others[1] |
1069 |
1 |
|
T2 |
6 |
|
T3 |
1 |
|
T10 |
1 |
| others[2] |
993 |
1 |
|
T2 |
2 |
|
T10 |
3 |
|
T15 |
1 |
| others[3] |
1811 |
1 |
|
T2 |
5 |
|
T5 |
1 |
|
T24 |
1 |
| false |
534 |
1 |
|
T10 |
3 |
|
T16 |
4 |
|
T36 |
2 |
| true |
1295 |
1 |
|
T1 |
1 |
|
T20 |
1 |
|
T61 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
219 |
1 |
|
T128 |
9 |
|
T118 |
15 |
|
T233 |
1 |
| others[1] |
224 |
1 |
|
T2 |
1 |
|
T128 |
11 |
|
T54 |
1 |
| others[2] |
254 |
1 |
|
T2 |
1 |
|
T42 |
1 |
|
T128 |
11 |
| others[3] |
388 |
1 |
|
T128 |
13 |
|
T118 |
18 |
|
T136 |
16 |
| false |
117 |
1 |
|
T2 |
1 |
|
T128 |
6 |
|
T118 |
6 |
| true |
5535 |
1 |
|
T1 |
1 |
|
T2 |
14 |
|
T3 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
232 |
1 |
|
T2 |
3 |
|
T42 |
1 |
|
T128 |
16 |
| others[1] |
205 |
1 |
|
T2 |
1 |
|
T5 |
1 |
|
T128 |
8 |
| others[2] |
266 |
1 |
|
T2 |
2 |
|
T128 |
14 |
|
T196 |
1 |
| others[3] |
348 |
1 |
|
T2 |
2 |
|
T128 |
18 |
|
T118 |
11 |
| false |
104 |
1 |
|
T3 |
1 |
|
T128 |
3 |
|
T118 |
3 |
| true |
5582 |
1 |
|
T1 |
1 |
|
T2 |
9 |
|
T24 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1236 |
1 |
|
T2 |
5 |
|
T5 |
1 |
|
T10 |
2 |
| others[1] |
1247 |
1 |
|
T2 |
4 |
|
T10 |
1 |
|
T16 |
7 |
| others[2] |
1197 |
1 |
|
T24 |
1 |
|
T10 |
1 |
|
T16 |
10 |
| others[3] |
2082 |
1 |
|
T2 |
6 |
|
T10 |
3 |
|
T16 |
15 |
| false |
639 |
1 |
|
T2 |
2 |
|
T10 |
1 |
|
T16 |
6 |
| true |
336 |
1 |
|
T1 |
1 |
|
T3 |
1 |
|
T20 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1236 |
1 |
|
T1 |
1 |
|
T2 |
3 |
|
T10 |
2 |
| others[1] |
1291 |
1 |
|
T10 |
3 |
|
T16 |
9 |
|
T36 |
4 |
| others[2] |
1205 |
1 |
|
T2 |
6 |
|
T5 |
1 |
|
T10 |
2 |
| others[3] |
2094 |
1 |
|
T2 |
6 |
|
T10 |
1 |
|
T16 |
20 |
| false |
603 |
1 |
|
T2 |
2 |
|
T16 |
1 |
|
T36 |
1 |
| true |
308 |
1 |
|
T3 |
1 |
|
T24 |
1 |
|
T20 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
104 |
1 |
|
T2 |
2 |
|
T128 |
4 |
|
T196 |
2 |
| others[1] |
95 |
1 |
|
T2 |
3 |
|
T128 |
2 |
|
T198 |
1 |
| others[2] |
95 |
1 |
|
T2 |
2 |
|
T3 |
1 |
|
T5 |
1 |
| others[3] |
165 |
1 |
|
T2 |
8 |
|
T42 |
1 |
|
T128 |
4 |
| false |
53 |
1 |
|
T2 |
2 |
|
T128 |
6 |
|
T118 |
2 |
| true |
6225 |
1 |
|
T1 |
1 |
|
T24 |
1 |
|
T10 |
8 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
224 |
1 |
|
T128 |
6 |
|
T196 |
1 |
|
T118 |
14 |
| others[1] |
223 |
1 |
|
T2 |
1 |
|
T128 |
7 |
|
T118 |
11 |
| others[2] |
259 |
1 |
|
T2 |
3 |
|
T3 |
1 |
|
T5 |
1 |
| others[3] |
389 |
1 |
|
T2 |
3 |
|
T128 |
13 |
|
T197 |
1 |
| false |
118 |
1 |
|
T2 |
1 |
|
T128 |
5 |
|
T30 |
1 |
| true |
5524 |
1 |
|
T1 |
1 |
|
T2 |
9 |
|
T24 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1011 |
1 |
|
T2 |
3 |
|
T24 |
1 |
|
T10 |
2 |
| others[1] |
1051 |
1 |
|
T2 |
3 |
|
T10 |
1 |
|
T16 |
8 |
| others[2] |
1035 |
1 |
|
T2 |
5 |
|
T10 |
1 |
|
T15 |
1 |
| others[3] |
1734 |
1 |
|
T2 |
3 |
|
T5 |
1 |
|
T10 |
3 |
| false |
570 |
1 |
|
T2 |
3 |
|
T3 |
1 |
|
T10 |
1 |
| true |
1336 |
1 |
|
T1 |
1 |
|
T77 |
6 |
|
T42 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
196 |
1 |
|
T128 |
7 |
|
T30 |
1 |
|
T198 |
1 |
| others[1] |
219 |
1 |
|
T2 |
2 |
|
T128 |
6 |
|
T118 |
8 |
| others[2] |
256 |
1 |
|
T2 |
1 |
|
T128 |
14 |
|
T198 |
1 |
| others[3] |
374 |
1 |
|
T2 |
6 |
|
T3 |
1 |
|
T5 |
1 |
| false |
103 |
1 |
|
T2 |
1 |
|
T128 |
7 |
|
T54 |
1 |
| true |
5589 |
1 |
|
T1 |
1 |
|
T2 |
7 |
|
T24 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
216 |
1 |
|
T2 |
1 |
|
T15 |
1 |
|
T128 |
11 |
| others[1] |
244 |
1 |
|
T2 |
2 |
|
T5 |
1 |
|
T128 |
8 |
| others[2] |
227 |
1 |
|
T2 |
1 |
|
T128 |
7 |
|
T118 |
5 |
| others[3] |
378 |
1 |
|
T2 |
3 |
|
T128 |
21 |
|
T118 |
19 |
| false |
123 |
1 |
|
T2 |
1 |
|
T128 |
4 |
|
T118 |
6 |
| true |
5549 |
1 |
|
T1 |
1 |
|
T2 |
9 |
|
T3 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1203 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T10 |
3 |
| others[1] |
1242 |
1 |
|
T2 |
2 |
|
T10 |
2 |
|
T16 |
11 |
| others[2] |
1222 |
1 |
|
T2 |
3 |
|
T10 |
1 |
|
T16 |
6 |
| others[3] |
2078 |
1 |
|
T2 |
11 |
|
T5 |
1 |
|
T10 |
1 |
| false |
654 |
1 |
|
T24 |
1 |
|
T10 |
1 |
|
T16 |
5 |
| true |
338 |
1 |
|
T3 |
1 |
|
T20 |
1 |
|
T15 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1234 |
1 |
|
T2 |
3 |
|
T10 |
2 |
|
T16 |
9 |
| others[1] |
1253 |
1 |
|
T2 |
3 |
|
T10 |
1 |
|
T16 |
5 |
| others[2] |
1243 |
1 |
|
T2 |
6 |
|
T10 |
3 |
|
T16 |
7 |
| others[3] |
2054 |
1 |
|
T2 |
3 |
|
T5 |
1 |
|
T10 |
1 |
| false |
651 |
1 |
|
T2 |
2 |
|
T10 |
1 |
|
T16 |
6 |
| true |
302 |
1 |
|
T1 |
1 |
|
T3 |
1 |
|
T24 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
102 |
1 |
|
T2 |
4 |
|
T128 |
1 |
|
T196 |
1 |
| others[1] |
101 |
1 |
|
T2 |
8 |
|
T128 |
3 |
|
T196 |
1 |
| others[2] |
102 |
1 |
|
T128 |
4 |
|
T196 |
1 |
|
T198 |
2 |
| others[3] |
163 |
1 |
|
T2 |
5 |
|
T5 |
1 |
|
T128 |
4 |
| false |
63 |
1 |
|
T128 |
4 |
|
T118 |
2 |
|
T242 |
1 |
| true |
6206 |
1 |
|
T1 |
1 |
|
T3 |
1 |
|
T24 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
220 |
1 |
|
T2 |
1 |
|
T77 |
1 |
|
T128 |
12 |
| others[1] |
219 |
1 |
|
T2 |
1 |
|
T77 |
1 |
|
T128 |
8 |
| others[2] |
228 |
1 |
|
T2 |
2 |
|
T77 |
1 |
|
T42 |
1 |
| others[3] |
388 |
1 |
|
T2 |
2 |
|
T5 |
1 |
|
T15 |
1 |
| false |
129 |
1 |
|
T2 |
1 |
|
T3 |
1 |
|
T128 |
9 |
| true |
5553 |
1 |
|
T1 |
1 |
|
T2 |
10 |
|
T24 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1040 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T3 |
1 |
| others[1] |
1044 |
1 |
|
T2 |
4 |
|
T24 |
1 |
|
T10 |
2 |
| others[2] |
1016 |
1 |
|
T2 |
3 |
|
T16 |
7 |
|
T61 |
1 |
| others[3] |
1743 |
1 |
|
T2 |
4 |
|
T5 |
1 |
|
T10 |
4 |
| false |
558 |
1 |
|
T2 |
5 |
|
T10 |
2 |
|
T16 |
8 |
| true |
1336 |
1 |
|
T15 |
1 |
|
T77 |
6 |
|
T52 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
211 |
1 |
|
T2 |
1 |
|
T77 |
1 |
|
T128 |
10 |
| others[1] |
239 |
1 |
|
T2 |
1 |
|
T128 |
5 |
|
T196 |
1 |
| others[2] |
207 |
1 |
|
T2 |
1 |
|
T15 |
1 |
|
T77 |
1 |
| others[3] |
395 |
1 |
|
T2 |
7 |
|
T3 |
1 |
|
T5 |
1 |
| false |
130 |
1 |
|
T42 |
1 |
|
T128 |
6 |
|
T118 |
5 |
| true |
5555 |
1 |
|
T1 |
1 |
|
T2 |
7 |
|
T24 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
221 |
1 |
|
T2 |
3 |
|
T128 |
9 |
|
T48 |
1 |
| others[1] |
220 |
1 |
|
T2 |
3 |
|
T128 |
17 |
|
T118 |
10 |
| others[2] |
200 |
1 |
|
T2 |
2 |
|
T128 |
5 |
|
T196 |
1 |
| others[3] |
394 |
1 |
|
T2 |
1 |
|
T3 |
1 |
|
T15 |
1 |
| false |
102 |
1 |
|
T128 |
4 |
|
T118 |
3 |
|
T136 |
5 |
| true |
5600 |
1 |
|
T1 |
1 |
|
T2 |
8 |
|
T5 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1213 |
1 |
|
T2 |
1 |
|
T5 |
1 |
|
T10 |
3 |
| others[1] |
1213 |
1 |
|
T2 |
5 |
|
T24 |
1 |
|
T10 |
1 |
| others[2] |
1262 |
1 |
|
T2 |
2 |
|
T10 |
1 |
|
T16 |
10 |
| others[3] |
2049 |
1 |
|
T2 |
7 |
|
T16 |
13 |
|
T36 |
6 |
| false |
664 |
1 |
|
T2 |
2 |
|
T10 |
3 |
|
T16 |
2 |
| true |
336 |
1 |
|
T1 |
1 |
|
T3 |
1 |
|
T20 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1236 |
1 |
|
T2 |
4 |
|
T10 |
2 |
|
T16 |
10 |
| others[1] |
1271 |
1 |
|
T2 |
5 |
|
T10 |
2 |
|
T16 |
6 |
| others[2] |
1252 |
1 |
|
T2 |
2 |
|
T10 |
1 |
|
T15 |
1 |
| others[3] |
1988 |
1 |
|
T2 |
3 |
|
T5 |
1 |
|
T10 |
1 |
| false |
677 |
1 |
|
T2 |
3 |
|
T10 |
2 |
|
T16 |
2 |
| true |
313 |
1 |
|
T1 |
1 |
|
T3 |
1 |
|
T24 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
114 |
1 |
|
T2 |
6 |
|
T128 |
8 |
|
T198 |
1 |
| others[1] |
104 |
1 |
|
T2 |
1 |
|
T128 |
7 |
|
T30 |
1 |
| others[2] |
96 |
1 |
|
T2 |
3 |
|
T128 |
3 |
|
T196 |
1 |
| others[3] |
190 |
1 |
|
T2 |
3 |
|
T128 |
8 |
|
T118 |
7 |
| false |
60 |
1 |
|
T2 |
4 |
|
T15 |
1 |
|
T196 |
1 |
| true |
6173 |
1 |
|
T1 |
1 |
|
T3 |
1 |
|
T5 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
250 |
1 |
|
T2 |
3 |
|
T128 |
10 |
|
T11 |
1 |
| others[1] |
225 |
1 |
|
T2 |
1 |
|
T128 |
12 |
|
T118 |
6 |
| others[2] |
241 |
1 |
|
T2 |
1 |
|
T128 |
15 |
|
T196 |
1 |
| others[3] |
356 |
1 |
|
T2 |
2 |
|
T128 |
10 |
|
T196 |
1 |
| false |
115 |
1 |
|
T2 |
2 |
|
T128 |
3 |
|
T118 |
6 |
| true |
5550 |
1 |
|
T1 |
1 |
|
T2 |
8 |
|
T3 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1042 |
1 |
|
T2 |
5 |
|
T10 |
2 |
|
T16 |
8 |
| others[1] |
1044 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T5 |
1 |
| others[2] |
1050 |
1 |
|
T2 |
3 |
|
T16 |
7 |
|
T36 |
3 |
| others[3] |
1759 |
1 |
|
T2 |
6 |
|
T10 |
4 |
|
T16 |
12 |
| false |
546 |
1 |
|
T2 |
2 |
|
T10 |
2 |
|
T16 |
6 |
| true |
1296 |
1 |
|
T3 |
1 |
|
T24 |
1 |
|
T20 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
238 |
1 |
|
T77 |
1 |
|
T128 |
11 |
|
T118 |
13 |
| others[1] |
212 |
1 |
|
T2 |
3 |
|
T61 |
1 |
|
T128 |
9 |
| others[2] |
231 |
1 |
|
T2 |
4 |
|
T3 |
1 |
|
T77 |
1 |
| others[3] |
403 |
1 |
|
T2 |
3 |
|
T5 |
1 |
|
T77 |
2 |
| false |
115 |
1 |
|
T2 |
1 |
|
T77 |
2 |
|
T128 |
5 |
| true |
5538 |
1 |
|
T1 |
1 |
|
T2 |
6 |
|
T24 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
243 |
1 |
|
T2 |
5 |
|
T128 |
11 |
|
T118 |
8 |
| others[1] |
223 |
1 |
|
T2 |
3 |
|
T3 |
1 |
|
T128 |
7 |
| others[2] |
226 |
1 |
|
T2 |
1 |
|
T128 |
8 |
|
T196 |
2 |
| others[3] |
379 |
1 |
|
T2 |
3 |
|
T42 |
1 |
|
T128 |
19 |
| false |
116 |
1 |
|
T2 |
1 |
|
T128 |
6 |
|
T11 |
1 |
| true |
5550 |
1 |
|
T1 |
1 |
|
T2 |
4 |
|
T5 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1231 |
1 |
|
T2 |
4 |
|
T10 |
2 |
|
T16 |
6 |
| others[1] |
1236 |
1 |
|
T2 |
1 |
|
T5 |
1 |
|
T16 |
13 |
| others[2] |
1259 |
1 |
|
T2 |
3 |
|
T10 |
2 |
|
T16 |
11 |
| others[3] |
2036 |
1 |
|
T2 |
8 |
|
T10 |
3 |
|
T16 |
11 |
| false |
628 |
1 |
|
T2 |
1 |
|
T10 |
1 |
|
T16 |
4 |
| true |
347 |
1 |
|
T1 |
1 |
|
T3 |
1 |
|
T24 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1234 |
1 |
|
T2 |
2 |
|
T16 |
8 |
|
T36 |
3 |
| others[1] |
1268 |
1 |
|
T1 |
1 |
|
T2 |
3 |
|
T5 |
1 |
| others[2] |
1260 |
1 |
|
T2 |
3 |
|
T24 |
1 |
|
T10 |
2 |
| others[3] |
2037 |
1 |
|
T2 |
6 |
|
T10 |
4 |
|
T16 |
17 |
| false |
633 |
1 |
|
T2 |
3 |
|
T10 |
2 |
|
T16 |
5 |
| true |
305 |
1 |
|
T3 |
1 |
|
T20 |
1 |
|
T61 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
103 |
1 |
|
T2 |
3 |
|
T128 |
4 |
|
T196 |
1 |
| others[1] |
109 |
1 |
|
T2 |
4 |
|
T128 |
3 |
|
T196 |
1 |
| others[2] |
107 |
1 |
|
T2 |
4 |
|
T5 |
1 |
|
T128 |
3 |
| others[3] |
191 |
1 |
|
T2 |
5 |
|
T128 |
5 |
|
T30 |
1 |
| false |
52 |
1 |
|
T2 |
1 |
|
T128 |
1 |
|
T118 |
1 |
| true |
6175 |
1 |
|
T1 |
1 |
|
T3 |
1 |
|
T24 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
225 |
1 |
|
T3 |
1 |
|
T128 |
4 |
|
T54 |
1 |
| others[1] |
227 |
1 |
|
T2 |
2 |
|
T128 |
12 |
|
T30 |
1 |
| others[2] |
204 |
1 |
|
T2 |
2 |
|
T128 |
8 |
|
T196 |
1 |
| others[3] |
341 |
1 |
|
T2 |
1 |
|
T15 |
1 |
|
T128 |
21 |
| false |
126 |
1 |
|
T2 |
1 |
|
T128 |
4 |
|
T118 |
5 |
| true |
5614 |
1 |
|
T1 |
1 |
|
T2 |
11 |
|
T5 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
990 |
1 |
|
T2 |
4 |
|
T3 |
1 |
|
T10 |
1 |
| others[1] |
1068 |
1 |
|
T2 |
1 |
|
T5 |
1 |
|
T10 |
2 |
| others[2] |
1095 |
1 |
|
T2 |
3 |
|
T10 |
2 |
|
T15 |
1 |
| others[3] |
1701 |
1 |
|
T2 |
7 |
|
T24 |
1 |
|
T10 |
3 |
| false |
556 |
1 |
|
T2 |
2 |
|
T16 |
2 |
|
T36 |
3 |
| true |
1327 |
1 |
|
T1 |
1 |
|
T20 |
1 |
|
T61 |
1 |
| 0% |
10% |
20% |
30% |
40% |
50% |
60% |
70% |
80% |
90% |
100% |