Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_4.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_4.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_4.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_4.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_4.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_4.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_5.ecc_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_5.ecc_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_5.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_5.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_5.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_5.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_5.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_5.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_5.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_5.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_5.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_5.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_5.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_5.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_6.ecc_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_6.ecc_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_6.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_6.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_6.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_6.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_6.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_6.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_6.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_6.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_6.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_6.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_6.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_6.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_7.ecc_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_7.ecc_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_7.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_7.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_7.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_7.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_7.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_7.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_7.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_7.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_7.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_7.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_7.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_7.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_8.ecc_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_8.ecc_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_8.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_8.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_8.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_8.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_8.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_8.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_8.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_8.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_8.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_8.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_8.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_8.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
222 |
1 |
|
T2 |
1 |
|
T77 |
1 |
|
T128 |
12 |
| others[1] |
215 |
1 |
|
T128 |
15 |
|
T196 |
2 |
|
T197 |
1 |
| others[2] |
232 |
1 |
|
T2 |
3 |
|
T77 |
1 |
|
T42 |
1 |
| others[3] |
390 |
1 |
|
T2 |
5 |
|
T3 |
1 |
|
T5 |
1 |
| false |
123 |
1 |
|
T77 |
1 |
|
T128 |
5 |
|
T118 |
5 |
| true |
5555 |
1 |
|
T1 |
1 |
|
T2 |
8 |
|
T24 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
201 |
1 |
|
T2 |
1 |
|
T5 |
1 |
|
T128 |
8 |
| others[1] |
223 |
1 |
|
T128 |
18 |
|
T118 |
7 |
|
T136 |
12 |
| others[2] |
223 |
1 |
|
T128 |
7 |
|
T118 |
5 |
|
T136 |
6 |
| others[3] |
367 |
1 |
|
T2 |
2 |
|
T42 |
1 |
|
T128 |
12 |
| false |
107 |
1 |
|
T2 |
1 |
|
T128 |
5 |
|
T118 |
5 |
| true |
5616 |
1 |
|
T1 |
1 |
|
T2 |
13 |
|
T3 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1220 |
1 |
|
T2 |
5 |
|
T10 |
2 |
|
T16 |
9 |
| others[1] |
1180 |
1 |
|
T2 |
1 |
|
T5 |
1 |
|
T10 |
2 |
| others[2] |
1226 |
1 |
|
T2 |
3 |
|
T16 |
10 |
|
T33 |
1 |
| others[3] |
2110 |
1 |
|
T2 |
6 |
|
T10 |
3 |
|
T16 |
17 |
| false |
667 |
1 |
|
T2 |
2 |
|
T10 |
1 |
|
T16 |
5 |
| true |
334 |
1 |
|
T1 |
1 |
|
T3 |
1 |
|
T24 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1288 |
1 |
|
T2 |
6 |
|
T16 |
10 |
|
T36 |
4 |
| others[1] |
1218 |
1 |
|
T2 |
4 |
|
T10 |
2 |
|
T16 |
8 |
| others[2] |
1229 |
1 |
|
T2 |
1 |
|
T16 |
7 |
|
T36 |
3 |
| others[3] |
2011 |
1 |
|
T2 |
5 |
|
T5 |
1 |
|
T10 |
6 |
| false |
680 |
1 |
|
T2 |
1 |
|
T16 |
3 |
|
T36 |
6 |
| true |
311 |
1 |
|
T1 |
1 |
|
T3 |
1 |
|
T24 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
101 |
1 |
|
T128 |
1 |
|
T197 |
1 |
|
T118 |
4 |
| others[1] |
99 |
1 |
|
T2 |
4 |
|
T128 |
2 |
|
T198 |
1 |
| others[2] |
109 |
1 |
|
T2 |
7 |
|
T128 |
1 |
|
T30 |
1 |
| others[3] |
181 |
1 |
|
T2 |
5 |
|
T5 |
1 |
|
T128 |
9 |
| false |
48 |
1 |
|
T2 |
1 |
|
T128 |
1 |
|
T118 |
4 |
| true |
6199 |
1 |
|
T1 |
1 |
|
T3 |
1 |
|
T24 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
221 |
1 |
|
T2 |
3 |
|
T128 |
11 |
|
T118 |
7 |
| others[1] |
224 |
1 |
|
T2 |
2 |
|
T61 |
1 |
|
T77 |
2 |
| others[2] |
227 |
1 |
|
T2 |
1 |
|
T15 |
1 |
|
T77 |
2 |
| others[3] |
361 |
1 |
|
T2 |
2 |
|
T77 |
2 |
|
T128 |
21 |
| false |
116 |
1 |
|
T2 |
2 |
|
T3 |
1 |
|
T128 |
8 |
| true |
5588 |
1 |
|
T1 |
1 |
|
T2 |
7 |
|
T5 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
952 |
1 |
|
T2 |
5 |
|
T10 |
2 |
|
T16 |
7 |
| others[1] |
1087 |
1 |
|
T2 |
6 |
|
T10 |
4 |
|
T20 |
1 |
| others[2] |
1040 |
1 |
|
T2 |
1 |
|
T5 |
1 |
|
T16 |
7 |
| others[3] |
1751 |
1 |
|
T2 |
4 |
|
T3 |
1 |
|
T24 |
1 |
| false |
582 |
1 |
|
T2 |
1 |
|
T16 |
3 |
|
T36 |
3 |
| true |
1325 |
1 |
|
T1 |
1 |
|
T77 |
6 |
|
T30 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
221 |
1 |
|
T2 |
2 |
|
T15 |
1 |
|
T128 |
4 |
| others[1] |
224 |
1 |
|
T2 |
2 |
|
T128 |
13 |
|
T196 |
1 |
| others[2] |
218 |
1 |
|
T2 |
3 |
|
T128 |
4 |
|
T198 |
1 |
| others[3] |
426 |
1 |
|
T2 |
1 |
|
T61 |
1 |
|
T128 |
17 |
| false |
115 |
1 |
|
T2 |
1 |
|
T128 |
10 |
|
T198 |
1 |
| true |
5533 |
1 |
|
T1 |
1 |
|
T2 |
8 |
|
T3 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
219 |
1 |
|
T128 |
9 |
|
T196 |
2 |
|
T197 |
1 |
| others[1] |
220 |
1 |
|
T2 |
2 |
|
T128 |
13 |
|
T198 |
1 |
| others[2] |
208 |
1 |
|
T2 |
2 |
|
T5 |
1 |
|
T128 |
4 |
| others[3] |
336 |
1 |
|
T2 |
5 |
|
T128 |
15 |
|
T118 |
13 |
| false |
112 |
1 |
|
T2 |
1 |
|
T128 |
5 |
|
T30 |
1 |
| true |
5642 |
1 |
|
T1 |
1 |
|
T2 |
7 |
|
T3 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1195 |
1 |
|
T2 |
4 |
|
T10 |
2 |
|
T16 |
12 |
| others[1] |
1177 |
1 |
|
T2 |
2 |
|
T10 |
2 |
|
T16 |
5 |
| others[2] |
1232 |
1 |
|
T2 |
1 |
|
T10 |
2 |
|
T16 |
9 |
| others[3] |
2127 |
1 |
|
T2 |
7 |
|
T5 |
1 |
|
T10 |
1 |
| false |
649 |
1 |
|
T2 |
3 |
|
T10 |
1 |
|
T16 |
4 |
| true |
357 |
1 |
|
T1 |
1 |
|
T3 |
1 |
|
T24 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1203 |
1 |
|
T2 |
3 |
|
T10 |
3 |
|
T16 |
6 |
| others[1] |
1247 |
1 |
|
T2 |
3 |
|
T5 |
1 |
|
T10 |
1 |
| others[2] |
1256 |
1 |
|
T2 |
5 |
|
T10 |
1 |
|
T16 |
10 |
| others[3] |
2075 |
1 |
|
T2 |
2 |
|
T10 |
3 |
|
T16 |
17 |
| false |
644 |
1 |
|
T2 |
4 |
|
T16 |
7 |
|
T36 |
1 |
| true |
312 |
1 |
|
T1 |
1 |
|
T3 |
1 |
|
T24 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
107 |
1 |
|
T2 |
3 |
|
T128 |
5 |
|
T118 |
4 |
| others[1] |
87 |
1 |
|
T2 |
3 |
|
T128 |
2 |
|
T196 |
2 |
| others[2] |
89 |
1 |
|
T128 |
4 |
|
T198 |
1 |
|
T11 |
1 |
| others[3] |
185 |
1 |
|
T2 |
7 |
|
T15 |
1 |
|
T128 |
4 |
| false |
62 |
1 |
|
T2 |
4 |
|
T128 |
3 |
|
T118 |
1 |
| true |
6207 |
1 |
|
T1 |
1 |
|
T3 |
1 |
|
T5 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
212 |
1 |
|
T2 |
4 |
|
T128 |
13 |
|
T80 |
1 |
| others[1] |
215 |
1 |
|
T5 |
1 |
|
T15 |
1 |
|
T42 |
1 |
| others[2] |
216 |
1 |
|
T61 |
1 |
|
T128 |
5 |
|
T134 |
1 |
| others[3] |
410 |
1 |
|
T2 |
5 |
|
T128 |
12 |
|
T30 |
1 |
| false |
114 |
1 |
|
T128 |
4 |
|
T54 |
1 |
|
T118 |
4 |
| true |
5570 |
1 |
|
T1 |
1 |
|
T2 |
8 |
|
T3 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1010 |
1 |
|
T2 |
1 |
|
T10 |
2 |
|
T16 |
5 |
| others[1] |
1081 |
1 |
|
T2 |
4 |
|
T5 |
1 |
|
T10 |
3 |
| others[2] |
1002 |
1 |
|
T2 |
5 |
|
T24 |
1 |
|
T20 |
1 |
| others[3] |
1792 |
1 |
|
T2 |
4 |
|
T3 |
1 |
|
T10 |
2 |
| false |
555 |
1 |
|
T2 |
3 |
|
T10 |
1 |
|
T16 |
3 |
| true |
1297 |
1 |
|
T1 |
1 |
|
T15 |
1 |
|
T61 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
208 |
1 |
|
T2 |
2 |
|
T15 |
1 |
|
T77 |
1 |
| others[1] |
215 |
1 |
|
T2 |
3 |
|
T128 |
7 |
|
T118 |
9 |
| others[2] |
222 |
1 |
|
T2 |
3 |
|
T77 |
1 |
|
T128 |
9 |
| others[3] |
349 |
1 |
|
T2 |
4 |
|
T3 |
1 |
|
T77 |
4 |
| false |
118 |
1 |
|
T2 |
1 |
|
T128 |
4 |
|
T118 |
3 |
| true |
5625 |
1 |
|
T1 |
1 |
|
T2 |
4 |
|
T5 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
216 |
1 |
|
T128 |
6 |
|
T196 |
1 |
|
T118 |
14 |
| others[1] |
227 |
1 |
|
T2 |
2 |
|
T128 |
10 |
|
T48 |
1 |
| others[2] |
242 |
1 |
|
T2 |
3 |
|
T128 |
12 |
|
T196 |
1 |
| others[3] |
368 |
1 |
|
T2 |
1 |
|
T5 |
1 |
|
T42 |
1 |
| false |
127 |
1 |
|
T2 |
1 |
|
T128 |
7 |
|
T197 |
1 |
| true |
5557 |
1 |
|
T1 |
1 |
|
T2 |
10 |
|
T3 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1230 |
1 |
|
T10 |
1 |
|
T16 |
8 |
|
T36 |
7 |
| others[1] |
1219 |
1 |
|
T2 |
5 |
|
T16 |
5 |
|
T50 |
9 |
| others[2] |
1247 |
1 |
|
T2 |
4 |
|
T5 |
1 |
|
T10 |
3 |
| others[3] |
2069 |
1 |
|
T2 |
6 |
|
T10 |
3 |
|
T16 |
14 |
| false |
639 |
1 |
|
T2 |
2 |
|
T10 |
1 |
|
T16 |
3 |
| true |
333 |
1 |
|
T1 |
1 |
|
T3 |
1 |
|
T24 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1298 |
1 |
|
T2 |
3 |
|
T10 |
4 |
|
T16 |
8 |
| others[1] |
1246 |
1 |
|
T2 |
4 |
|
T10 |
1 |
|
T16 |
12 |
| others[2] |
1213 |
1 |
|
T2 |
2 |
|
T10 |
1 |
|
T16 |
6 |
| others[3] |
2024 |
1 |
|
T2 |
5 |
|
T5 |
1 |
|
T10 |
2 |
| false |
642 |
1 |
|
T2 |
3 |
|
T16 |
5 |
|
T36 |
3 |
| true |
314 |
1 |
|
T1 |
1 |
|
T3 |
1 |
|
T24 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
118 |
1 |
|
T2 |
3 |
|
T3 |
1 |
|
T128 |
5 |
| others[1] |
117 |
1 |
|
T2 |
5 |
|
T128 |
4 |
|
T196 |
1 |
| others[2] |
97 |
1 |
|
T2 |
4 |
|
T128 |
6 |
|
T197 |
1 |
| others[3] |
181 |
1 |
|
T2 |
3 |
|
T128 |
10 |
|
T196 |
2 |
| false |
48 |
1 |
|
T2 |
2 |
|
T128 |
3 |
|
T118 |
1 |
| true |
6176 |
1 |
|
T1 |
1 |
|
T5 |
1 |
|
T24 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
231 |
1 |
|
T2 |
4 |
|
T15 |
1 |
|
T128 |
13 |
| others[1] |
257 |
1 |
|
T2 |
3 |
|
T3 |
1 |
|
T77 |
2 |
| others[2] |
240 |
1 |
|
T77 |
2 |
|
T128 |
5 |
|
T118 |
11 |
| others[3] |
355 |
1 |
|
T2 |
3 |
|
T5 |
1 |
|
T77 |
2 |
| false |
119 |
1 |
|
T2 |
1 |
|
T128 |
7 |
|
T118 |
5 |
| true |
5535 |
1 |
|
T1 |
1 |
|
T2 |
6 |
|
T24 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1107 |
1 |
|
T1 |
1 |
|
T2 |
5 |
|
T3 |
1 |
| others[1] |
1033 |
1 |
|
T2 |
2 |
|
T10 |
2 |
|
T16 |
8 |
| others[2] |
1018 |
1 |
|
T2 |
3 |
|
T10 |
1 |
|
T16 |
9 |
| others[3] |
1671 |
1 |
|
T2 |
7 |
|
T10 |
4 |
|
T16 |
11 |
| false |
549 |
1 |
|
T5 |
1 |
|
T15 |
1 |
|
T16 |
6 |
| true |
1359 |
1 |
|
T24 |
1 |
|
T20 |
1 |
|
T61 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
248 |
1 |
|
T2 |
2 |
|
T128 |
14 |
|
T196 |
1 |
| others[1] |
219 |
1 |
|
T2 |
2 |
|
T42 |
1 |
|
T128 |
13 |
| others[2] |
213 |
1 |
|
T128 |
7 |
|
T229 |
1 |
|
T118 |
8 |
| others[3] |
384 |
1 |
|
T2 |
6 |
|
T3 |
1 |
|
T128 |
18 |
| false |
101 |
1 |
|
T2 |
1 |
|
T128 |
2 |
|
T118 |
3 |
| true |
5572 |
1 |
|
T1 |
1 |
|
T2 |
6 |
|
T5 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
223 |
1 |
|
T2 |
1 |
|
T128 |
10 |
|
T118 |
9 |
| others[1] |
208 |
1 |
|
T128 |
10 |
|
T196 |
1 |
|
T198 |
1 |
| others[2] |
222 |
1 |
|
T2 |
5 |
|
T15 |
1 |
|
T128 |
10 |
| others[3] |
364 |
1 |
|
T2 |
2 |
|
T128 |
17 |
|
T30 |
1 |
| false |
114 |
1 |
|
T3 |
1 |
|
T128 |
6 |
|
T196 |
1 |
| true |
5606 |
1 |
|
T1 |
1 |
|
T2 |
9 |
|
T5 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1270 |
1 |
|
T10 |
1 |
|
T16 |
8 |
|
T36 |
3 |
| others[1] |
1243 |
1 |
|
T2 |
3 |
|
T5 |
1 |
|
T10 |
2 |
| others[2] |
1228 |
1 |
|
T2 |
3 |
|
T10 |
1 |
|
T16 |
4 |
| others[3] |
2036 |
1 |
|
T2 |
8 |
|
T24 |
1 |
|
T10 |
2 |
| false |
621 |
1 |
|
T2 |
3 |
|
T10 |
2 |
|
T16 |
4 |
| true |
339 |
1 |
|
T1 |
1 |
|
T3 |
1 |
|
T20 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1252 |
1 |
|
T2 |
7 |
|
T5 |
1 |
|
T10 |
1 |
| others[1] |
1220 |
1 |
|
T2 |
2 |
|
T10 |
4 |
|
T16 |
7 |
| others[2] |
1212 |
1 |
|
T2 |
2 |
|
T16 |
12 |
|
T36 |
7 |
| others[3] |
2087 |
1 |
|
T2 |
5 |
|
T24 |
1 |
|
T10 |
3 |
| false |
649 |
1 |
|
T2 |
1 |
|
T16 |
3 |
|
T36 |
3 |
| true |
317 |
1 |
|
T1 |
1 |
|
T3 |
1 |
|
T20 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
115 |
1 |
|
T2 |
7 |
|
T128 |
2 |
|
T196 |
1 |
| others[1] |
103 |
1 |
|
T2 |
1 |
|
T5 |
1 |
|
T128 |
4 |
| others[2] |
99 |
1 |
|
T2 |
4 |
|
T128 |
6 |
|
T118 |
6 |
| others[3] |
213 |
1 |
|
T2 |
4 |
|
T128 |
11 |
|
T196 |
2 |
| false |
57 |
1 |
|
T2 |
1 |
|
T128 |
1 |
|
T197 |
1 |
| true |
6150 |
1 |
|
T1 |
1 |
|
T3 |
1 |
|
T24 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
248 |
1 |
|
T2 |
2 |
|
T3 |
1 |
|
T42 |
1 |
| others[1] |
230 |
1 |
|
T2 |
1 |
|
T128 |
17 |
|
T196 |
1 |
| others[2] |
213 |
1 |
|
T2 |
2 |
|
T15 |
1 |
|
T128 |
6 |
| others[3] |
381 |
1 |
|
T2 |
2 |
|
T61 |
1 |
|
T128 |
13 |
| false |
108 |
1 |
|
T128 |
6 |
|
T118 |
4 |
|
T136 |
6 |
| true |
5557 |
1 |
|
T1 |
1 |
|
T2 |
10 |
|
T5 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1067 |
1 |
|
T2 |
2 |
|
T16 |
5 |
|
T77 |
2 |
| others[1] |
1050 |
1 |
|
T2 |
1 |
|
T5 |
1 |
|
T10 |
2 |
| others[2] |
1020 |
1 |
|
T1 |
1 |
|
T2 |
4 |
|
T10 |
2 |
| others[3] |
1731 |
1 |
|
T2 |
7 |
|
T3 |
1 |
|
T24 |
1 |
| false |
549 |
1 |
|
T2 |
3 |
|
T10 |
1 |
|
T16 |
8 |
| true |
1320 |
1 |
|
T33 |
1 |
|
T30 |
1 |
|
T45 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
205 |
1 |
|
T2 |
1 |
|
T77 |
2 |
|
T128 |
6 |
| others[1] |
228 |
1 |
|
T2 |
1 |
|
T77 |
1 |
|
T128 |
7 |
| others[2] |
220 |
1 |
|
T2 |
1 |
|
T77 |
2 |
|
T128 |
10 |
| others[3] |
364 |
1 |
|
T2 |
4 |
|
T15 |
1 |
|
T61 |
1 |
| false |
113 |
1 |
|
T77 |
1 |
|
T128 |
8 |
|
T48 |
1 |
| true |
5607 |
1 |
|
T1 |
1 |
|
T2 |
10 |
|
T3 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
239 |
1 |
|
T2 |
1 |
|
T128 |
11 |
|
T196 |
2 |
| others[1] |
206 |
1 |
|
T2 |
2 |
|
T5 |
1 |
|
T128 |
14 |
| others[2] |
225 |
1 |
|
T2 |
2 |
|
T128 |
15 |
|
T198 |
1 |
| others[3] |
377 |
1 |
|
T2 |
1 |
|
T128 |
15 |
|
T30 |
1 |
| false |
93 |
1 |
|
T2 |
1 |
|
T128 |
1 |
|
T118 |
4 |
| true |
5597 |
1 |
|
T1 |
1 |
|
T2 |
10 |
|
T3 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1228 |
1 |
|
T2 |
2 |
|
T10 |
4 |
|
T16 |
6 |
| others[1] |
1173 |
1 |
|
T2 |
2 |
|
T10 |
1 |
|
T16 |
11 |
| others[2] |
1289 |
1 |
|
T2 |
4 |
|
T10 |
1 |
|
T16 |
7 |
| others[3] |
2099 |
1 |
|
T2 |
8 |
|
T5 |
1 |
|
T10 |
2 |
| false |
620 |
1 |
|
T2 |
1 |
|
T16 |
2 |
|
T36 |
2 |
| true |
328 |
1 |
|
T1 |
1 |
|
T3 |
1 |
|
T24 |
1 |
| 0% |
10% |
20% |
30% |
40% |
50% |
60% |
70% |
80% |
90% |
100% |