Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_9.ecc_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_9.ecc_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_9.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_9.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_9.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_9.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_9.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_9.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_9.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_9.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_9.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_9.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_9.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_9.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info1_page_cfg.ecc_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info1_page_cfg.ecc_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info1_page_cfg.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info1_page_cfg.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info1_page_cfg.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info1_page_cfg.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info1_page_cfg.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info1_page_cfg.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info1_page_cfg.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info1_page_cfg.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info1_page_cfg.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info1_page_cfg.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info1_page_cfg.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info1_page_cfg.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_0.ecc_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_0.ecc_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_0.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_0.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_0.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_0.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_0.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_0.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_0.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_0.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_0.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_0.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_0.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_0.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_1.ecc_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_1.ecc_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_1.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_1.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_1.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_1.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_1.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_1.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_1.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_1.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_1.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_1.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_1.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_1.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.dis.val
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.dis.val
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.hw_info_cfg_override.ecc_dis
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.hw_info_cfg_override.ecc_dis
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.hw_info_cfg_override.scramble_dis
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.hw_info_cfg_override.scramble_dis
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1262 |
1 |
|
T2 |
3 |
|
T10 |
2 |
|
T16 |
6 |
| others[1] |
1222 |
1 |
|
T2 |
5 |
|
T16 |
14 |
|
T36 |
3 |
| others[2] |
1230 |
1 |
|
T2 |
3 |
|
T10 |
2 |
|
T16 |
8 |
| others[3] |
2069 |
1 |
|
T2 |
4 |
|
T5 |
1 |
|
T10 |
3 |
| false |
642 |
1 |
|
T2 |
2 |
|
T10 |
1 |
|
T16 |
2 |
| true |
312 |
1 |
|
T1 |
1 |
|
T3 |
1 |
|
T24 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
108 |
1 |
|
T2 |
3 |
|
T128 |
4 |
|
T196 |
1 |
| others[1] |
91 |
1 |
|
T2 |
1 |
|
T128 |
4 |
|
T118 |
3 |
| others[2] |
100 |
1 |
|
T2 |
4 |
|
T128 |
3 |
|
T196 |
1 |
| others[3] |
192 |
1 |
|
T2 |
6 |
|
T3 |
1 |
|
T128 |
9 |
| false |
66 |
1 |
|
T2 |
3 |
|
T128 |
3 |
|
T198 |
1 |
| true |
6180 |
1 |
|
T1 |
1 |
|
T5 |
1 |
|
T24 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
209 |
1 |
|
T128 |
11 |
|
T118 |
10 |
|
T136 |
11 |
| others[1] |
253 |
1 |
|
T2 |
2 |
|
T15 |
1 |
|
T77 |
1 |
| others[2] |
232 |
1 |
|
T2 |
2 |
|
T3 |
1 |
|
T77 |
2 |
| others[3] |
372 |
1 |
|
T2 |
5 |
|
T61 |
1 |
|
T77 |
2 |
| false |
110 |
1 |
|
T77 |
1 |
|
T42 |
1 |
|
T128 |
5 |
| true |
5561 |
1 |
|
T1 |
1 |
|
T2 |
8 |
|
T5 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1060 |
1 |
|
T2 |
2 |
|
T24 |
1 |
|
T10 |
2 |
| others[1] |
1039 |
1 |
|
T2 |
5 |
|
T10 |
2 |
|
T16 |
13 |
| others[2] |
1065 |
1 |
|
T2 |
4 |
|
T5 |
1 |
|
T16 |
10 |
| others[3] |
1677 |
1 |
|
T2 |
4 |
|
T10 |
3 |
|
T20 |
1 |
| false |
561 |
1 |
|
T2 |
2 |
|
T10 |
1 |
|
T16 |
4 |
| true |
1335 |
1 |
|
T1 |
1 |
|
T3 |
1 |
|
T61 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
220 |
1 |
|
T2 |
3 |
|
T128 |
12 |
|
T30 |
1 |
| others[1] |
239 |
1 |
|
T2 |
1 |
|
T128 |
6 |
|
T11 |
1 |
| others[2] |
239 |
1 |
|
T42 |
1 |
|
T128 |
3 |
|
T118 |
8 |
| others[3] |
387 |
1 |
|
T2 |
3 |
|
T5 |
1 |
|
T128 |
25 |
| false |
119 |
1 |
|
T2 |
2 |
|
T128 |
8 |
|
T196 |
1 |
| true |
5533 |
1 |
|
T1 |
1 |
|
T2 |
8 |
|
T3 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
222 |
1 |
|
T2 |
1 |
|
T128 |
9 |
|
T118 |
7 |
| others[1] |
205 |
1 |
|
T2 |
2 |
|
T128 |
7 |
|
T118 |
8 |
| others[2] |
220 |
1 |
|
T2 |
3 |
|
T128 |
13 |
|
T197 |
1 |
| others[3] |
369 |
1 |
|
T2 |
3 |
|
T15 |
1 |
|
T128 |
15 |
| false |
108 |
1 |
|
T2 |
1 |
|
T128 |
1 |
|
T196 |
1 |
| true |
5613 |
1 |
|
T1 |
1 |
|
T2 |
7 |
|
T3 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1206 |
1 |
|
T2 |
3 |
|
T16 |
12 |
|
T36 |
5 |
| others[1] |
1255 |
1 |
|
T1 |
1 |
|
T2 |
4 |
|
T16 |
7 |
| others[2] |
1245 |
1 |
|
T2 |
2 |
|
T5 |
1 |
|
T16 |
8 |
| others[3] |
2077 |
1 |
|
T2 |
7 |
|
T10 |
6 |
|
T16 |
14 |
| false |
619 |
1 |
|
T2 |
1 |
|
T10 |
2 |
|
T16 |
4 |
| true |
335 |
1 |
|
T3 |
1 |
|
T24 |
1 |
|
T20 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1221 |
1 |
|
T2 |
4 |
|
T10 |
1 |
|
T16 |
4 |
| others[1] |
1267 |
1 |
|
T2 |
4 |
|
T10 |
2 |
|
T16 |
13 |
| others[2] |
1284 |
1 |
|
T2 |
3 |
|
T10 |
1 |
|
T16 |
6 |
| others[3] |
2020 |
1 |
|
T2 |
5 |
|
T10 |
3 |
|
T16 |
15 |
| false |
628 |
1 |
|
T2 |
1 |
|
T5 |
1 |
|
T10 |
1 |
| true |
317 |
1 |
|
T1 |
1 |
|
T3 |
1 |
|
T24 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
108 |
1 |
|
T2 |
4 |
|
T128 |
3 |
|
T118 |
5 |
| others[1] |
102 |
1 |
|
T2 |
4 |
|
T5 |
1 |
|
T128 |
1 |
| others[2] |
107 |
1 |
|
T2 |
6 |
|
T128 |
3 |
|
T198 |
1 |
| others[3] |
151 |
1 |
|
T2 |
3 |
|
T3 |
1 |
|
T128 |
3 |
| false |
51 |
1 |
|
T196 |
1 |
|
T197 |
1 |
|
T118 |
4 |
| true |
6218 |
1 |
|
T1 |
1 |
|
T24 |
1 |
|
T10 |
8 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
230 |
1 |
|
T2 |
2 |
|
T15 |
1 |
|
T77 |
1 |
| others[1] |
252 |
1 |
|
T2 |
3 |
|
T5 |
1 |
|
T42 |
1 |
| others[2] |
218 |
1 |
|
T2 |
1 |
|
T77 |
1 |
|
T128 |
12 |
| others[3] |
371 |
1 |
|
T2 |
2 |
|
T77 |
2 |
|
T128 |
11 |
| false |
122 |
1 |
|
T2 |
1 |
|
T77 |
2 |
|
T128 |
2 |
| true |
5544 |
1 |
|
T1 |
1 |
|
T2 |
8 |
|
T3 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1062 |
1 |
|
T2 |
4 |
|
T24 |
1 |
|
T10 |
2 |
| others[1] |
1017 |
1 |
|
T2 |
1 |
|
T5 |
1 |
|
T10 |
2 |
| others[2] |
1081 |
1 |
|
T2 |
3 |
|
T3 |
1 |
|
T10 |
2 |
| others[3] |
1724 |
1 |
|
T2 |
7 |
|
T10 |
2 |
|
T20 |
1 |
| false |
532 |
1 |
|
T2 |
2 |
|
T16 |
4 |
|
T50 |
4 |
| true |
1321 |
1 |
|
T1 |
1 |
|
T15 |
1 |
|
T77 |
6 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
242 |
1 |
|
T2 |
3 |
|
T42 |
1 |
|
T128 |
10 |
| others[1] |
226 |
1 |
|
T128 |
15 |
|
T118 |
9 |
|
T136 |
13 |
| others[2] |
191 |
1 |
|
T2 |
2 |
|
T128 |
4 |
|
T118 |
5 |
| others[3] |
376 |
1 |
|
T2 |
1 |
|
T128 |
17 |
|
T30 |
1 |
| false |
106 |
1 |
|
T2 |
2 |
|
T61 |
1 |
|
T128 |
7 |
| true |
5596 |
1 |
|
T1 |
1 |
|
T2 |
9 |
|
T3 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
219 |
1 |
|
T2 |
3 |
|
T15 |
1 |
|
T128 |
8 |
| others[1] |
207 |
1 |
|
T2 |
3 |
|
T5 |
1 |
|
T128 |
13 |
| others[2] |
211 |
1 |
|
T128 |
14 |
|
T80 |
1 |
|
T118 |
8 |
| others[3] |
366 |
1 |
|
T2 |
2 |
|
T128 |
16 |
|
T198 |
1 |
| false |
121 |
1 |
|
T3 |
1 |
|
T128 |
4 |
|
T118 |
6 |
| true |
5613 |
1 |
|
T1 |
1 |
|
T2 |
9 |
|
T24 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1192 |
1 |
|
T2 |
5 |
|
T10 |
2 |
|
T16 |
9 |
| others[1] |
1240 |
1 |
|
T2 |
4 |
|
T16 |
9 |
|
T36 |
2 |
| others[2] |
1275 |
1 |
|
T2 |
2 |
|
T10 |
3 |
|
T16 |
8 |
| others[3] |
2078 |
1 |
|
T2 |
4 |
|
T5 |
1 |
|
T10 |
2 |
| false |
614 |
1 |
|
T2 |
2 |
|
T10 |
1 |
|
T16 |
4 |
| true |
338 |
1 |
|
T1 |
1 |
|
T3 |
1 |
|
T24 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1235 |
1 |
|
T2 |
1 |
|
T10 |
3 |
|
T16 |
15 |
| others[1] |
1201 |
1 |
|
T2 |
2 |
|
T5 |
1 |
|
T10 |
1 |
| others[2] |
1263 |
1 |
|
T2 |
7 |
|
T10 |
2 |
|
T16 |
8 |
| others[3] |
2092 |
1 |
|
T2 |
5 |
|
T24 |
1 |
|
T10 |
1 |
| false |
638 |
1 |
|
T2 |
2 |
|
T10 |
1 |
|
T16 |
1 |
| true |
308 |
1 |
|
T1 |
1 |
|
T3 |
1 |
|
T20 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
108 |
1 |
|
T2 |
2 |
|
T128 |
3 |
|
T196 |
1 |
| others[1] |
86 |
1 |
|
T2 |
3 |
|
T128 |
4 |
|
T196 |
1 |
| others[2] |
113 |
1 |
|
T2 |
4 |
|
T3 |
1 |
|
T5 |
1 |
| others[3] |
168 |
1 |
|
T2 |
6 |
|
T128 |
7 |
|
T196 |
1 |
| false |
58 |
1 |
|
T2 |
2 |
|
T128 |
4 |
|
T118 |
1 |
| true |
6204 |
1 |
|
T1 |
1 |
|
T24 |
1 |
|
T10 |
8 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
208 |
1 |
|
T128 |
9 |
|
T229 |
1 |
|
T118 |
7 |
| others[1] |
232 |
1 |
|
T2 |
1 |
|
T5 |
1 |
|
T61 |
1 |
| others[2] |
220 |
1 |
|
T2 |
2 |
|
T128 |
6 |
|
T196 |
1 |
| others[3] |
398 |
1 |
|
T2 |
4 |
|
T3 |
1 |
|
T15 |
1 |
| false |
114 |
1 |
|
T2 |
2 |
|
T128 |
7 |
|
T118 |
7 |
| true |
5565 |
1 |
|
T1 |
1 |
|
T2 |
8 |
|
T24 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
987 |
1 |
|
T2 |
2 |
|
T10 |
1 |
|
T16 |
6 |
| others[1] |
1032 |
1 |
|
T2 |
2 |
|
T10 |
3 |
|
T16 |
8 |
| others[2] |
1091 |
1 |
|
T2 |
6 |
|
T5 |
1 |
|
T10 |
1 |
| others[3] |
1752 |
1 |
|
T1 |
1 |
|
T2 |
6 |
|
T24 |
1 |
| false |
564 |
1 |
|
T2 |
1 |
|
T16 |
7 |
|
T50 |
5 |
| true |
1311 |
1 |
|
T3 |
1 |
|
T20 |
1 |
|
T15 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
234 |
1 |
|
T2 |
1 |
|
T128 |
11 |
|
T118 |
11 |
| others[1] |
247 |
1 |
|
T2 |
3 |
|
T128 |
6 |
|
T196 |
1 |
| others[2] |
218 |
1 |
|
T2 |
1 |
|
T128 |
9 |
|
T197 |
1 |
| others[3] |
369 |
1 |
|
T2 |
1 |
|
T15 |
1 |
|
T42 |
1 |
| false |
113 |
1 |
|
T128 |
3 |
|
T196 |
1 |
|
T118 |
5 |
| true |
5556 |
1 |
|
T1 |
1 |
|
T2 |
11 |
|
T3 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
252 |
1 |
|
T2 |
3 |
|
T3 |
1 |
|
T5 |
1 |
| others[1] |
243 |
1 |
|
T2 |
1 |
|
T128 |
7 |
|
T197 |
1 |
| others[2] |
216 |
1 |
|
T2 |
2 |
|
T128 |
7 |
|
T118 |
11 |
| others[3] |
356 |
1 |
|
T2 |
5 |
|
T128 |
19 |
|
T30 |
1 |
| false |
91 |
1 |
|
T128 |
5 |
|
T118 |
5 |
|
T136 |
4 |
| true |
5579 |
1 |
|
T1 |
1 |
|
T2 |
6 |
|
T24 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1228 |
1 |
|
T2 |
5 |
|
T10 |
1 |
|
T16 |
5 |
| others[1] |
1219 |
1 |
|
T2 |
4 |
|
T5 |
1 |
|
T10 |
2 |
| others[2] |
1234 |
1 |
|
T2 |
2 |
|
T10 |
2 |
|
T16 |
7 |
| others[3] |
2071 |
1 |
|
T2 |
4 |
|
T10 |
3 |
|
T16 |
20 |
| false |
653 |
1 |
|
T2 |
2 |
|
T16 |
6 |
|
T36 |
1 |
| true |
332 |
1 |
|
T1 |
1 |
|
T3 |
1 |
|
T24 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1240 |
1 |
|
T2 |
4 |
|
T16 |
5 |
|
T36 |
4 |
| others[1] |
1314 |
1 |
|
T2 |
1 |
|
T5 |
1 |
|
T10 |
2 |
| others[2] |
1280 |
1 |
|
T2 |
3 |
|
T10 |
2 |
|
T16 |
10 |
| others[3] |
2004 |
1 |
|
T2 |
8 |
|
T24 |
1 |
|
T10 |
4 |
| false |
590 |
1 |
|
T2 |
1 |
|
T16 |
4 |
|
T36 |
3 |
| true |
309 |
1 |
|
T1 |
1 |
|
T3 |
1 |
|
T20 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
104 |
1 |
|
T2 |
5 |
|
T128 |
5 |
|
T196 |
1 |
| others[1] |
109 |
1 |
|
T2 |
4 |
|
T128 |
4 |
|
T118 |
3 |
| others[2] |
85 |
1 |
|
T2 |
2 |
|
T128 |
5 |
|
T196 |
1 |
| others[3] |
193 |
1 |
|
T2 |
5 |
|
T5 |
1 |
|
T128 |
5 |
| false |
59 |
1 |
|
T2 |
1 |
|
T128 |
1 |
|
T242 |
1 |
| true |
6187 |
1 |
|
T1 |
1 |
|
T3 |
1 |
|
T24 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
235 |
1 |
|
T2 |
1 |
|
T128 |
11 |
|
T118 |
7 |
| others[1] |
237 |
1 |
|
T2 |
2 |
|
T42 |
1 |
|
T128 |
15 |
| others[2] |
237 |
1 |
|
T2 |
2 |
|
T128 |
13 |
|
T48 |
1 |
| others[3] |
379 |
1 |
|
T2 |
2 |
|
T3 |
1 |
|
T128 |
15 |
| false |
109 |
1 |
|
T128 |
4 |
|
T118 |
6 |
|
T136 |
4 |
| true |
5540 |
1 |
|
T1 |
1 |
|
T2 |
10 |
|
T5 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
985 |
1 |
|
T2 |
1 |
|
T5 |
1 |
|
T10 |
2 |
| others[1] |
1044 |
1 |
|
T2 |
4 |
|
T10 |
2 |
|
T16 |
5 |
| others[2] |
1052 |
1 |
|
T2 |
3 |
|
T16 |
11 |
|
T77 |
1 |
| others[3] |
1815 |
1 |
|
T2 |
6 |
|
T3 |
1 |
|
T10 |
3 |
| false |
529 |
1 |
|
T2 |
3 |
|
T10 |
1 |
|
T16 |
8 |
| true |
1312 |
1 |
|
T1 |
1 |
|
T24 |
1 |
|
T20 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
232 |
1 |
|
T2 |
2 |
|
T15 |
1 |
|
T61 |
1 |
| others[1] |
250 |
1 |
|
T2 |
1 |
|
T128 |
10 |
|
T30 |
1 |
| others[2] |
232 |
1 |
|
T2 |
3 |
|
T128 |
11 |
|
T196 |
1 |
| others[3] |
365 |
1 |
|
T2 |
3 |
|
T3 |
1 |
|
T5 |
1 |
| false |
108 |
1 |
|
T128 |
5 |
|
T118 |
5 |
|
T242 |
1 |
| true |
5550 |
1 |
|
T1 |
1 |
|
T2 |
8 |
|
T24 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
230 |
1 |
|
T128 |
11 |
|
T118 |
7 |
|
T136 |
8 |
| others[1] |
213 |
1 |
|
T2 |
2 |
|
T5 |
1 |
|
T128 |
4 |
| others[2] |
218 |
1 |
|
T2 |
4 |
|
T3 |
1 |
|
T15 |
1 |
| others[3] |
337 |
1 |
|
T2 |
2 |
|
T128 |
21 |
|
T196 |
1 |
| false |
114 |
1 |
|
T2 |
2 |
|
T128 |
5 |
|
T30 |
1 |
| true |
5625 |
1 |
|
T1 |
1 |
|
T2 |
7 |
|
T24 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1241 |
1 |
|
T2 |
3 |
|
T16 |
10 |
|
T36 |
2 |
| others[1] |
1214 |
1 |
|
T2 |
6 |
|
T10 |
2 |
|
T16 |
11 |
| others[2] |
1239 |
1 |
|
T5 |
1 |
|
T10 |
4 |
|
T16 |
7 |
| others[3] |
2087 |
1 |
|
T2 |
5 |
|
T10 |
2 |
|
T16 |
12 |
| false |
627 |
1 |
|
T2 |
3 |
|
T16 |
5 |
|
T36 |
2 |
| true |
329 |
1 |
|
T1 |
1 |
|
T3 |
1 |
|
T24 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
4 |
1 |
|
T367 |
1 |
|
T368 |
1 |
|
T369 |
1 |
| others[1] |
5 |
1 |
|
T248 |
1 |
|
T169 |
1 |
|
T370 |
1 |
| others[2] |
10 |
1 |
|
T52 |
1 |
|
T63 |
1 |
|
T371 |
1 |
| others[3] |
13 |
1 |
|
T83 |
1 |
|
T107 |
1 |
|
T110 |
1 |
| false |
8 |
1 |
|
T372 |
1 |
|
T373 |
1 |
|
T374 |
1 |
| true |
48 |
1 |
|
T29 |
2 |
|
T107 |
1 |
|
T28 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
5 |
1 |
|
T27 |
1 |
|
T360 |
1 |
|
T375 |
1 |
| others[1] |
1 |
1 |
|
T79 |
1 |
|
- |
- |
|
- |
- |
| others[2] |
4 |
1 |
|
T376 |
1 |
|
T377 |
1 |
|
T378 |
1 |
| others[3] |
8 |
1 |
|
T379 |
1 |
|
T380 |
1 |
|
T381 |
1 |
| false |
9 |
1 |
|
T214 |
1 |
|
T258 |
1 |
|
T382 |
1 |
| true |
20 |
1 |
|
T22 |
1 |
|
T85 |
1 |
|
T383 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1 |
1 |
|
T384 |
1 |
|
- |
- |
|
- |
- |
| others[1] |
5 |
1 |
|
T22 |
1 |
|
T385 |
1 |
|
T386 |
1 |
| others[2] |
3 |
1 |
|
T79 |
1 |
|
T360 |
1 |
|
T387 |
1 |
| others[3] |
5 |
1 |
|
T388 |
1 |
|
T378 |
1 |
|
T389 |
1 |
| false |
10 |
1 |
|
T27 |
1 |
|
T390 |
1 |
|
T381 |
1 |
| true |
23 |
1 |
|
T85 |
1 |
|
T214 |
1 |
|
T383 |
1 |
| 0% |
10% |
20% |
30% |
40% |
50% |
60% |
70% |
80% |
90% |
100% |