Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_0.ecc_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_0.ecc_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_0.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_0.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_0.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_0.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_0.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_0.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_0.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_0.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_0.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_0.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_0.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_0.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_1.ecc_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_1.ecc_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_1.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_1.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_1.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_1.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_1.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_1.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_1.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_1.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_1.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_1.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_1.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_1.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_2.ecc_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_2.ecc_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_2.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_2.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_2.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_2.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_2.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_2.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_2.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_2.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_2.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_2.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_2.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_2.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_3.ecc_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_3.ecc_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_3.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_3.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_3.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_3.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_3.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_3.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_3.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_3.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_3.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_3.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_3.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_3.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_4.ecc_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_4.ecc_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_4.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_4.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_4.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_4.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10168 |
1 |
|
T2 |
4 |
|
T4 |
66 |
|
T9 |
2 |
| others[1] |
791 |
1 |
|
T2 |
1 |
|
T10 |
3 |
|
T16 |
7 |
| others[2] |
776 |
1 |
|
T2 |
2 |
|
T5 |
1 |
|
T10 |
2 |
| others[3] |
1268 |
1 |
|
T10 |
3 |
|
T16 |
14 |
|
T36 |
8 |
| false |
431 |
1 |
|
T16 |
3 |
|
T50 |
5 |
|
T128 |
12 |
| true |
418 |
1 |
|
T1 |
1 |
|
T2 |
14 |
|
T3 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
2495 |
1 |
|
T2 |
2 |
|
T4 |
12 |
|
T9 |
1 |
| others[1] |
2415 |
1 |
|
T2 |
5 |
|
T3 |
1 |
|
T4 |
14 |
| others[2] |
2321 |
1 |
|
T2 |
4 |
|
T4 |
11 |
|
T10 |
1 |
| others[3] |
3973 |
1 |
|
T2 |
4 |
|
T4 |
24 |
|
T9 |
1 |
| false |
1233 |
1 |
|
T2 |
2 |
|
T4 |
5 |
|
T10 |
1 |
| true |
1415 |
1 |
|
T1 |
1 |
|
T2 |
4 |
|
T5 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
9577 |
1 |
|
T2 |
1 |
|
T4 |
66 |
|
T9 |
2 |
| others[1] |
275 |
1 |
|
T2 |
2 |
|
T3 |
1 |
|
T128 |
14 |
| others[2] |
274 |
1 |
|
T5 |
1 |
|
T128 |
9 |
|
T118 |
9 |
| others[3] |
406 |
1 |
|
T2 |
4 |
|
T128 |
11 |
|
T144 |
1 |
| false |
143 |
1 |
|
T2 |
1 |
|
T128 |
5 |
|
T135 |
2 |
| true |
3177 |
1 |
|
T1 |
1 |
|
T2 |
13 |
|
T23 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
9828 |
1 |
|
T2 |
8 |
|
T3 |
1 |
|
T4 |
66 |
| others[1] |
455 |
1 |
|
T2 |
4 |
|
T10 |
1 |
|
T16 |
3 |
| others[2] |
439 |
1 |
|
T2 |
3 |
|
T10 |
1 |
|
T16 |
2 |
| others[3] |
762 |
1 |
|
T2 |
5 |
|
T10 |
1 |
|
T16 |
5 |
| false |
207 |
1 |
|
T2 |
1 |
|
T16 |
2 |
|
T50 |
3 |
| true |
2161 |
1 |
|
T1 |
1 |
|
T5 |
1 |
|
T10 |
5 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
9597 |
1 |
|
T2 |
2 |
|
T4 |
66 |
|
T9 |
2 |
| others[1] |
273 |
1 |
|
T77 |
2 |
|
T128 |
11 |
|
T7 |
1 |
| others[2] |
216 |
1 |
|
T2 |
1 |
|
T5 |
1 |
|
T15 |
1 |
| others[3] |
431 |
1 |
|
T2 |
5 |
|
T77 |
2 |
|
T128 |
21 |
| false |
146 |
1 |
|
T77 |
1 |
|
T128 |
5 |
|
T144 |
1 |
| true |
3189 |
1 |
|
T1 |
1 |
|
T2 |
13 |
|
T3 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
9622 |
1 |
|
T2 |
2 |
|
T4 |
66 |
|
T9 |
2 |
| others[1] |
234 |
1 |
|
T2 |
3 |
|
T128 |
15 |
|
T144 |
1 |
| others[2] |
241 |
1 |
|
T128 |
11 |
|
T144 |
1 |
|
T118 |
13 |
| others[3] |
432 |
1 |
|
T2 |
1 |
|
T5 |
1 |
|
T15 |
1 |
| false |
114 |
1 |
|
T2 |
2 |
|
T128 |
5 |
|
T13 |
1 |
| true |
3209 |
1 |
|
T1 |
1 |
|
T2 |
13 |
|
T3 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10162 |
1 |
|
T2 |
6 |
|
T4 |
66 |
|
T9 |
2 |
| others[1] |
811 |
1 |
|
T2 |
1 |
|
T10 |
1 |
|
T16 |
4 |
| others[2] |
793 |
1 |
|
T2 |
2 |
|
T10 |
2 |
|
T16 |
11 |
| others[3] |
1298 |
1 |
|
T2 |
3 |
|
T5 |
1 |
|
T10 |
3 |
| false |
385 |
1 |
|
T2 |
2 |
|
T10 |
2 |
|
T16 |
5 |
| true |
403 |
1 |
|
T1 |
1 |
|
T2 |
7 |
|
T3 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10087 |
1 |
|
T2 |
1 |
|
T4 |
66 |
|
T9 |
2 |
| others[1] |
821 |
1 |
|
T2 |
1 |
|
T10 |
1 |
|
T16 |
7 |
| others[2] |
795 |
1 |
|
T2 |
2 |
|
T10 |
1 |
|
T16 |
13 |
| others[3] |
1291 |
1 |
|
T2 |
3 |
|
T5 |
1 |
|
T10 |
4 |
| false |
427 |
1 |
|
T2 |
1 |
|
T16 |
4 |
|
T50 |
4 |
| true |
401 |
1 |
|
T1 |
1 |
|
T2 |
9 |
|
T3 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
2378 |
1 |
|
T2 |
2 |
|
T4 |
11 |
|
T9 |
1 |
| others[1] |
2330 |
1 |
|
T2 |
3 |
|
T4 |
16 |
|
T10 |
2 |
| others[2] |
2416 |
1 |
|
T2 |
4 |
|
T4 |
15 |
|
T10 |
2 |
| others[3] |
3981 |
1 |
|
T2 |
5 |
|
T4 |
14 |
|
T9 |
1 |
| false |
1283 |
1 |
|
T2 |
3 |
|
T3 |
1 |
|
T4 |
10 |
| true |
1434 |
1 |
|
T1 |
1 |
|
T5 |
1 |
|
T24 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
9575 |
1 |
|
T2 |
2 |
|
T4 |
66 |
|
T5 |
1 |
| others[1] |
287 |
1 |
|
T2 |
1 |
|
T77 |
1 |
|
T42 |
1 |
| others[2] |
281 |
1 |
|
T77 |
3 |
|
T128 |
9 |
|
T134 |
1 |
| others[3] |
466 |
1 |
|
T2 |
3 |
|
T77 |
1 |
|
T128 |
19 |
| false |
131 |
1 |
|
T2 |
1 |
|
T128 |
6 |
|
T196 |
1 |
| true |
3082 |
1 |
|
T1 |
1 |
|
T2 |
10 |
|
T3 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
9786 |
1 |
|
T2 |
5 |
|
T4 |
66 |
|
T5 |
1 |
| others[1] |
471 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T10 |
1 |
| others[2] |
460 |
1 |
|
T2 |
7 |
|
T10 |
1 |
|
T16 |
5 |
| others[3] |
766 |
1 |
|
T2 |
3 |
|
T10 |
2 |
|
T20 |
1 |
| false |
229 |
1 |
|
T2 |
1 |
|
T16 |
3 |
|
T36 |
1 |
| true |
2110 |
1 |
|
T3 |
1 |
|
T10 |
4 |
|
T15 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
9598 |
1 |
|
T2 |
1 |
|
T3 |
1 |
|
T4 |
66 |
| others[1] |
248 |
1 |
|
T2 |
2 |
|
T42 |
1 |
|
T128 |
9 |
| others[2] |
233 |
1 |
|
T2 |
2 |
|
T77 |
2 |
|
T128 |
11 |
| others[3] |
445 |
1 |
|
T2 |
3 |
|
T15 |
1 |
|
T77 |
3 |
| false |
137 |
1 |
|
T2 |
2 |
|
T128 |
2 |
|
T144 |
1 |
| true |
3161 |
1 |
|
T1 |
1 |
|
T2 |
7 |
|
T5 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
9550 |
1 |
|
T2 |
1 |
|
T4 |
66 |
|
T9 |
2 |
| others[1] |
239 |
1 |
|
T5 |
1 |
|
T42 |
1 |
|
T128 |
7 |
| others[2] |
244 |
1 |
|
T2 |
3 |
|
T128 |
11 |
|
T144 |
1 |
| others[3] |
408 |
1 |
|
T2 |
3 |
|
T128 |
17 |
|
T144 |
1 |
| false |
130 |
1 |
|
T2 |
1 |
|
T15 |
1 |
|
T128 |
6 |
| true |
3251 |
1 |
|
T1 |
1 |
|
T2 |
9 |
|
T3 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10132 |
1 |
|
T2 |
2 |
|
T4 |
66 |
|
T9 |
2 |
| others[1] |
798 |
1 |
|
T2 |
1 |
|
T10 |
4 |
|
T16 |
13 |
| others[2] |
788 |
1 |
|
T2 |
2 |
|
T10 |
1 |
|
T16 |
5 |
| others[3] |
1266 |
1 |
|
T2 |
1 |
|
T5 |
1 |
|
T10 |
1 |
| false |
437 |
1 |
|
T2 |
1 |
|
T10 |
1 |
|
T16 |
4 |
| true |
401 |
1 |
|
T1 |
1 |
|
T2 |
10 |
|
T3 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10130 |
1 |
|
T2 |
2 |
|
T4 |
66 |
|
T9 |
2 |
| others[1] |
788 |
1 |
|
T2 |
1 |
|
T10 |
2 |
|
T16 |
9 |
| others[2] |
762 |
1 |
|
T5 |
1 |
|
T16 |
5 |
|
T36 |
5 |
| others[3] |
1353 |
1 |
|
T2 |
2 |
|
T10 |
5 |
|
T16 |
13 |
| false |
393 |
1 |
|
T16 |
5 |
|
T36 |
2 |
|
T50 |
6 |
| true |
396 |
1 |
|
T1 |
1 |
|
T2 |
12 |
|
T3 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
2364 |
1 |
|
T2 |
4 |
|
T4 |
7 |
|
T10 |
1 |
| others[1] |
2333 |
1 |
|
T2 |
1 |
|
T4 |
13 |
|
T10 |
3 |
| others[2] |
2421 |
1 |
|
T2 |
7 |
|
T4 |
10 |
|
T16 |
10 |
| others[3] |
3961 |
1 |
|
T2 |
4 |
|
T4 |
21 |
|
T9 |
1 |
| false |
1271 |
1 |
|
T2 |
1 |
|
T4 |
15 |
|
T9 |
1 |
| true |
1472 |
1 |
|
T1 |
1 |
|
T3 |
1 |
|
T5 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
9601 |
1 |
|
T4 |
66 |
|
T9 |
2 |
|
T21 |
2 |
| others[1] |
266 |
1 |
|
T2 |
1 |
|
T61 |
1 |
|
T128 |
8 |
| others[2] |
263 |
1 |
|
T2 |
3 |
|
T3 |
1 |
|
T15 |
1 |
| others[3] |
419 |
1 |
|
T2 |
5 |
|
T5 |
1 |
|
T128 |
14 |
| false |
133 |
1 |
|
T2 |
1 |
|
T128 |
5 |
|
T144 |
1 |
| true |
3140 |
1 |
|
T1 |
1 |
|
T2 |
7 |
|
T24 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
9787 |
1 |
|
T2 |
3 |
|
T4 |
66 |
|
T9 |
2 |
| others[1] |
439 |
1 |
|
T2 |
6 |
|
T5 |
1 |
|
T16 |
7 |
| others[2] |
443 |
1 |
|
T2 |
1 |
|
T16 |
4 |
|
T50 |
10 |
| others[3] |
744 |
1 |
|
T1 |
1 |
|
T2 |
6 |
|
T10 |
3 |
| false |
216 |
1 |
|
T2 |
1 |
|
T16 |
1 |
|
T36 |
2 |
| true |
2193 |
1 |
|
T3 |
1 |
|
T24 |
1 |
|
T10 |
5 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
9604 |
1 |
|
T4 |
66 |
|
T5 |
1 |
|
T9 |
2 |
| others[1] |
263 |
1 |
|
T2 |
2 |
|
T61 |
1 |
|
T42 |
1 |
| others[2] |
274 |
1 |
|
T77 |
2 |
|
T128 |
17 |
|
T54 |
1 |
| others[3] |
393 |
1 |
|
T2 |
4 |
|
T15 |
1 |
|
T77 |
3 |
| false |
121 |
1 |
|
T2 |
2 |
|
T128 |
2 |
|
T144 |
2 |
| true |
3167 |
1 |
|
T1 |
1 |
|
T2 |
9 |
|
T3 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
9580 |
1 |
|
T2 |
1 |
|
T4 |
66 |
|
T9 |
2 |
| others[1] |
245 |
1 |
|
T2 |
1 |
|
T3 |
1 |
|
T5 |
1 |
| others[2] |
259 |
1 |
|
T2 |
2 |
|
T128 |
9 |
|
T12 |
1 |
| others[3] |
427 |
1 |
|
T2 |
3 |
|
T128 |
18 |
|
T30 |
1 |
| false |
125 |
1 |
|
T15 |
1 |
|
T128 |
10 |
|
T144 |
1 |
| true |
3186 |
1 |
|
T1 |
1 |
|
T2 |
10 |
|
T24 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10120 |
1 |
|
T2 |
1 |
|
T4 |
66 |
|
T5 |
1 |
| others[1] |
754 |
1 |
|
T2 |
2 |
|
T10 |
1 |
|
T16 |
7 |
| others[2] |
811 |
1 |
|
T10 |
1 |
|
T16 |
4 |
|
T36 |
3 |
| others[3] |
1323 |
1 |
|
T2 |
2 |
|
T10 |
3 |
|
T16 |
13 |
| false |
405 |
1 |
|
T16 |
5 |
|
T36 |
2 |
|
T50 |
4 |
| true |
409 |
1 |
|
T1 |
1 |
|
T2 |
12 |
|
T3 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10119 |
1 |
|
T2 |
1 |
|
T4 |
66 |
|
T9 |
2 |
| others[1] |
823 |
1 |
|
T10 |
2 |
|
T16 |
15 |
|
T36 |
5 |
| others[2] |
755 |
1 |
|
T2 |
1 |
|
T10 |
1 |
|
T16 |
7 |
| others[3] |
1330 |
1 |
|
T2 |
7 |
|
T5 |
1 |
|
T10 |
3 |
| false |
393 |
1 |
|
T15 |
1 |
|
T16 |
4 |
|
T36 |
3 |
| true |
402 |
1 |
|
T1 |
1 |
|
T2 |
8 |
|
T3 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
2399 |
1 |
|
T2 |
3 |
|
T4 |
8 |
|
T10 |
1 |
| others[1] |
2287 |
1 |
|
T2 |
5 |
|
T4 |
14 |
|
T9 |
1 |
| others[2] |
2427 |
1 |
|
T2 |
3 |
|
T4 |
14 |
|
T10 |
3 |
| others[3] |
4026 |
1 |
|
T2 |
5 |
|
T3 |
1 |
|
T4 |
23 |
| false |
1232 |
1 |
|
T2 |
1 |
|
T4 |
7 |
|
T9 |
1 |
| true |
1451 |
1 |
|
T1 |
1 |
|
T5 |
1 |
|
T24 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
9602 |
1 |
|
T2 |
2 |
|
T4 |
66 |
|
T9 |
2 |
| others[1] |
253 |
1 |
|
T2 |
1 |
|
T128 |
7 |
|
T144 |
1 |
| others[2] |
249 |
1 |
|
T2 |
1 |
|
T128 |
10 |
|
T144 |
2 |
| others[3] |
415 |
1 |
|
T2 |
2 |
|
T3 |
1 |
|
T15 |
1 |
| false |
139 |
1 |
|
T2 |
2 |
|
T77 |
1 |
|
T128 |
7 |
| true |
3164 |
1 |
|
T1 |
1 |
|
T2 |
9 |
|
T5 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
9806 |
1 |
|
T2 |
1 |
|
T4 |
66 |
|
T9 |
2 |
| others[1] |
424 |
1 |
|
T2 |
3 |
|
T5 |
1 |
|
T15 |
1 |
| others[2] |
505 |
1 |
|
T2 |
5 |
|
T16 |
6 |
|
T26 |
1 |
| others[3] |
753 |
1 |
|
T2 |
6 |
|
T3 |
1 |
|
T10 |
1 |
| false |
222 |
1 |
|
T2 |
2 |
|
T24 |
1 |
|
T16 |
2 |
| true |
2112 |
1 |
|
T1 |
1 |
|
T10 |
4 |
|
T20 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
9606 |
1 |
|
T2 |
1 |
|
T4 |
66 |
|
T9 |
2 |
| others[1] |
254 |
1 |
|
T2 |
1 |
|
T61 |
1 |
|
T128 |
6 |
| others[2] |
245 |
1 |
|
T2 |
2 |
|
T128 |
7 |
|
T144 |
1 |
| others[3] |
402 |
1 |
|
T2 |
3 |
|
T5 |
1 |
|
T128 |
22 |
| false |
141 |
1 |
|
T2 |
2 |
|
T128 |
4 |
|
T196 |
1 |
| true |
3174 |
1 |
|
T1 |
1 |
|
T2 |
8 |
|
T3 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
9588 |
1 |
|
T2 |
3 |
|
T4 |
66 |
|
T9 |
2 |
| others[1] |
230 |
1 |
|
T2 |
1 |
|
T128 |
10 |
|
T118 |
7 |
| others[2] |
235 |
1 |
|
T5 |
1 |
|
T128 |
8 |
|
T13 |
1 |
| others[3] |
417 |
1 |
|
T2 |
3 |
|
T3 |
1 |
|
T128 |
14 |
| false |
131 |
1 |
|
T2 |
2 |
|
T128 |
3 |
|
T144 |
1 |
| true |
3221 |
1 |
|
T1 |
1 |
|
T2 |
8 |
|
T24 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10115 |
1 |
|
T2 |
4 |
|
T4 |
66 |
|
T9 |
2 |
| others[1] |
758 |
1 |
|
T10 |
1 |
|
T16 |
8 |
|
T26 |
1 |
| others[2] |
810 |
1 |
|
T2 |
2 |
|
T10 |
1 |
|
T16 |
11 |
| others[3] |
1295 |
1 |
|
T2 |
1 |
|
T5 |
1 |
|
T10 |
5 |
| false |
411 |
1 |
|
T16 |
3 |
|
T36 |
2 |
|
T50 |
6 |
| true |
433 |
1 |
|
T1 |
1 |
|
T2 |
10 |
|
T3 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10099 |
1 |
|
T2 |
2 |
|
T4 |
66 |
|
T9 |
2 |
| others[1] |
807 |
1 |
|
T2 |
2 |
|
T5 |
1 |
|
T10 |
2 |
| others[2] |
715 |
1 |
|
T2 |
2 |
|
T10 |
2 |
|
T16 |
4 |
| others[3] |
1361 |
1 |
|
T2 |
2 |
|
T10 |
3 |
|
T16 |
19 |
| false |
415 |
1 |
|
T2 |
1 |
|
T16 |
3 |
|
T26 |
1 |
| true |
425 |
1 |
|
T1 |
1 |
|
T2 |
8 |
|
T3 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
2442 |
1 |
|
T2 |
3 |
|
T4 |
23 |
|
T9 |
1 |
| others[1] |
2370 |
1 |
|
T2 |
3 |
|
T4 |
9 |
|
T10 |
2 |
| others[2] |
2382 |
1 |
|
T2 |
5 |
|
T4 |
10 |
|
T10 |
1 |
| others[3] |
4000 |
1 |
|
T2 |
6 |
|
T3 |
1 |
|
T4 |
17 |
| false |
1165 |
1 |
|
T4 |
7 |
|
T16 |
7 |
|
T50 |
3 |
| true |
1463 |
1 |
|
T1 |
1 |
|
T5 |
1 |
|
T24 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
9585 |
1 |
|
T2 |
1 |
|
T4 |
66 |
|
T9 |
2 |
| others[1] |
260 |
1 |
|
T2 |
2 |
|
T77 |
1 |
|
T128 |
12 |
| others[2] |
259 |
1 |
|
T2 |
4 |
|
T3 |
1 |
|
T77 |
2 |
| others[3] |
475 |
1 |
|
T2 |
1 |
|
T5 |
1 |
|
T15 |
1 |
| false |
143 |
1 |
|
T77 |
1 |
|
T128 |
4 |
|
T134 |
1 |
| true |
3100 |
1 |
|
T1 |
1 |
|
T2 |
9 |
|
T24 |
1 |
| 0% |
10% |
20% |
30% |
40% |
50% |
60% |
70% |
80% |
90% |
100% |