Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_4.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_4.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_4.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_4.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_4.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_4.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_4.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_4.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_5.ecc_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_5.ecc_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_5.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_5.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_5.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_5.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_5.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_5.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_5.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_5.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_5.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_5.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_5.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_5.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_6.ecc_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_6.ecc_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_6.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_6.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_6.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_6.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_6.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_6.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_6.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_6.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_6.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_6.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_6.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_6.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_7.ecc_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_7.ecc_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_7.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_7.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_7.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_7.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_7.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_7.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_7.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_7.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_7.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_7.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_7.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_7.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
9794 |
1 |
|
T2 |
3 |
|
T4 |
66 |
|
T9 |
2 |
| others[1] |
466 |
1 |
|
T1 |
1 |
|
T2 |
5 |
|
T10 |
1 |
| others[2] |
431 |
1 |
|
T2 |
2 |
|
T10 |
1 |
|
T16 |
5 |
| others[3] |
733 |
1 |
|
T2 |
4 |
|
T3 |
1 |
|
T16 |
6 |
| false |
243 |
1 |
|
T2 |
3 |
|
T16 |
2 |
|
T77 |
1 |
| true |
2155 |
1 |
|
T5 |
1 |
|
T24 |
1 |
|
T10 |
6 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
9592 |
1 |
|
T2 |
2 |
|
T4 |
66 |
|
T9 |
2 |
| others[1] |
233 |
1 |
|
T2 |
1 |
|
T61 |
1 |
|
T128 |
8 |
| others[2] |
262 |
1 |
|
T2 |
1 |
|
T128 |
15 |
|
T144 |
2 |
| others[3] |
445 |
1 |
|
T2 |
6 |
|
T3 |
1 |
|
T5 |
1 |
| false |
136 |
1 |
|
T2 |
3 |
|
T128 |
5 |
|
T48 |
1 |
| true |
3154 |
1 |
|
T1 |
1 |
|
T2 |
4 |
|
T24 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
9590 |
1 |
|
T2 |
2 |
|
T3 |
1 |
|
T4 |
66 |
| others[1] |
217 |
1 |
|
T2 |
1 |
|
T128 |
9 |
|
T144 |
1 |
| others[2] |
249 |
1 |
|
T2 |
4 |
|
T128 |
14 |
|
T144 |
1 |
| others[3] |
434 |
1 |
|
T2 |
4 |
|
T128 |
13 |
|
T30 |
1 |
| false |
130 |
1 |
|
T128 |
5 |
|
T48 |
1 |
|
T118 |
4 |
| true |
3202 |
1 |
|
T1 |
1 |
|
T2 |
6 |
|
T5 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10114 |
1 |
|
T4 |
66 |
|
T9 |
2 |
|
T10 |
3 |
| others[1] |
789 |
1 |
|
T16 |
12 |
|
T36 |
6 |
|
T50 |
4 |
| others[2] |
769 |
1 |
|
T2 |
2 |
|
T10 |
1 |
|
T16 |
8 |
| others[3] |
1298 |
1 |
|
T2 |
1 |
|
T5 |
1 |
|
T24 |
1 |
| false |
448 |
1 |
|
T2 |
3 |
|
T16 |
4 |
|
T26 |
1 |
| true |
404 |
1 |
|
T1 |
1 |
|
T2 |
11 |
|
T3 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10073 |
1 |
|
T2 |
2 |
|
T4 |
66 |
|
T9 |
2 |
| others[1] |
798 |
1 |
|
T2 |
2 |
|
T10 |
2 |
|
T16 |
7 |
| others[2] |
808 |
1 |
|
T5 |
1 |
|
T10 |
2 |
|
T16 |
10 |
| others[3] |
1305 |
1 |
|
T2 |
2 |
|
T10 |
3 |
|
T16 |
17 |
| false |
427 |
1 |
|
T2 |
3 |
|
T10 |
1 |
|
T16 |
2 |
| true |
411 |
1 |
|
T1 |
1 |
|
T2 |
8 |
|
T3 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
2422 |
1 |
|
T2 |
4 |
|
T4 |
11 |
|
T21 |
1 |
| others[1] |
2413 |
1 |
|
T2 |
4 |
|
T4 |
14 |
|
T10 |
3 |
| others[2] |
2339 |
1 |
|
T2 |
1 |
|
T4 |
13 |
|
T9 |
1 |
| others[3] |
3972 |
1 |
|
T2 |
7 |
|
T3 |
1 |
|
T4 |
18 |
| false |
1259 |
1 |
|
T2 |
1 |
|
T4 |
10 |
|
T9 |
1 |
| true |
1417 |
1 |
|
T1 |
1 |
|
T5 |
1 |
|
T24 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
9594 |
1 |
|
T2 |
1 |
|
T4 |
66 |
|
T5 |
1 |
| others[1] |
251 |
1 |
|
T2 |
2 |
|
T128 |
7 |
|
T48 |
1 |
| others[2] |
268 |
1 |
|
T2 |
2 |
|
T42 |
1 |
|
T128 |
4 |
| others[3] |
452 |
1 |
|
T2 |
4 |
|
T128 |
21 |
|
T144 |
2 |
| false |
135 |
1 |
|
T2 |
1 |
|
T61 |
1 |
|
T128 |
10 |
| true |
3122 |
1 |
|
T1 |
1 |
|
T2 |
7 |
|
T3 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
9771 |
1 |
|
T2 |
2 |
|
T4 |
66 |
|
T9 |
2 |
| others[1] |
471 |
1 |
|
T2 |
4 |
|
T24 |
1 |
|
T10 |
1 |
| others[2] |
431 |
1 |
|
T2 |
4 |
|
T10 |
2 |
|
T16 |
4 |
| others[3] |
735 |
1 |
|
T2 |
7 |
|
T16 |
7 |
|
T36 |
5 |
| false |
236 |
1 |
|
T16 |
2 |
|
T61 |
1 |
|
T36 |
4 |
| true |
2178 |
1 |
|
T1 |
1 |
|
T3 |
1 |
|
T5 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
9576 |
1 |
|
T2 |
1 |
|
T4 |
66 |
|
T9 |
2 |
| others[1] |
245 |
1 |
|
T2 |
2 |
|
T128 |
7 |
|
T144 |
2 |
| others[2] |
277 |
1 |
|
T2 |
1 |
|
T5 |
1 |
|
T15 |
1 |
| others[3] |
415 |
1 |
|
T2 |
2 |
|
T128 |
16 |
|
T135 |
1 |
| false |
133 |
1 |
|
T42 |
1 |
|
T128 |
3 |
|
T30 |
1 |
| true |
3176 |
1 |
|
T1 |
1 |
|
T2 |
11 |
|
T3 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
9586 |
1 |
|
T2 |
3 |
|
T3 |
1 |
|
T4 |
66 |
| others[1] |
259 |
1 |
|
T2 |
4 |
|
T42 |
1 |
|
T128 |
6 |
| others[2] |
253 |
1 |
|
T2 |
2 |
|
T128 |
14 |
|
T196 |
1 |
| others[3] |
378 |
1 |
|
T2 |
2 |
|
T15 |
1 |
|
T128 |
20 |
| false |
137 |
1 |
|
T128 |
8 |
|
T144 |
1 |
|
T80 |
1 |
| true |
3209 |
1 |
|
T1 |
1 |
|
T2 |
6 |
|
T5 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10144 |
1 |
|
T2 |
2 |
|
T4 |
66 |
|
T9 |
2 |
| others[1] |
792 |
1 |
|
T2 |
1 |
|
T10 |
1 |
|
T16 |
5 |
| others[2] |
759 |
1 |
|
T2 |
2 |
|
T10 |
2 |
|
T16 |
10 |
| others[3] |
1317 |
1 |
|
T2 |
1 |
|
T5 |
1 |
|
T10 |
4 |
| false |
404 |
1 |
|
T2 |
2 |
|
T10 |
1 |
|
T16 |
4 |
| true |
406 |
1 |
|
T1 |
1 |
|
T2 |
9 |
|
T3 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10111 |
1 |
|
T2 |
2 |
|
T4 |
66 |
|
T9 |
2 |
| others[1] |
789 |
1 |
|
T2 |
2 |
|
T10 |
4 |
|
T16 |
8 |
| others[2] |
815 |
1 |
|
T2 |
1 |
|
T10 |
2 |
|
T16 |
6 |
| others[3] |
1242 |
1 |
|
T2 |
2 |
|
T5 |
1 |
|
T10 |
2 |
| false |
449 |
1 |
|
T2 |
1 |
|
T16 |
6 |
|
T36 |
5 |
| true |
416 |
1 |
|
T1 |
1 |
|
T2 |
9 |
|
T3 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
2316 |
1 |
|
T2 |
1 |
|
T4 |
9 |
|
T10 |
1 |
| others[1] |
2424 |
1 |
|
T2 |
3 |
|
T4 |
16 |
|
T10 |
1 |
| others[2] |
2424 |
1 |
|
T2 |
5 |
|
T4 |
12 |
|
T9 |
2 |
| others[3] |
4009 |
1 |
|
T2 |
6 |
|
T4 |
24 |
|
T10 |
3 |
| false |
1198 |
1 |
|
T2 |
2 |
|
T4 |
5 |
|
T16 |
1 |
| true |
1451 |
1 |
|
T1 |
1 |
|
T3 |
1 |
|
T5 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
9615 |
1 |
|
T2 |
1 |
|
T4 |
66 |
|
T9 |
2 |
| others[1] |
245 |
1 |
|
T2 |
2 |
|
T5 |
1 |
|
T128 |
9 |
| others[2] |
291 |
1 |
|
T2 |
3 |
|
T128 |
11 |
|
T144 |
1 |
| others[3] |
452 |
1 |
|
T2 |
1 |
|
T3 |
1 |
|
T128 |
17 |
| false |
105 |
1 |
|
T128 |
7 |
|
T144 |
1 |
|
T135 |
1 |
| true |
3114 |
1 |
|
T1 |
1 |
|
T2 |
10 |
|
T24 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
9816 |
1 |
|
T2 |
4 |
|
T3 |
1 |
|
T4 |
66 |
| others[1] |
431 |
1 |
|
T2 |
4 |
|
T24 |
1 |
|
T16 |
4 |
| others[2] |
435 |
1 |
|
T2 |
3 |
|
T16 |
6 |
|
T36 |
5 |
| others[3] |
763 |
1 |
|
T2 |
2 |
|
T16 |
8 |
|
T42 |
1 |
| false |
223 |
1 |
|
T2 |
4 |
|
T10 |
2 |
|
T16 |
6 |
| true |
2154 |
1 |
|
T1 |
1 |
|
T10 |
6 |
|
T15 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
9561 |
1 |
|
T2 |
1 |
|
T4 |
66 |
|
T9 |
2 |
| others[1] |
265 |
1 |
|
T15 |
1 |
|
T77 |
1 |
|
T128 |
4 |
| others[2] |
247 |
1 |
|
T2 |
2 |
|
T77 |
1 |
|
T128 |
15 |
| others[3] |
422 |
1 |
|
T2 |
2 |
|
T77 |
1 |
|
T128 |
18 |
| false |
135 |
1 |
|
T2 |
2 |
|
T128 |
5 |
|
T144 |
1 |
| true |
3192 |
1 |
|
T1 |
1 |
|
T2 |
10 |
|
T3 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
9604 |
1 |
|
T2 |
3 |
|
T4 |
66 |
|
T9 |
2 |
| others[1] |
242 |
1 |
|
T2 |
3 |
|
T128 |
13 |
|
T48 |
1 |
| others[2] |
246 |
1 |
|
T2 |
1 |
|
T128 |
10 |
|
T144 |
2 |
| others[3] |
412 |
1 |
|
T2 |
4 |
|
T3 |
1 |
|
T128 |
11 |
| false |
132 |
1 |
|
T2 |
2 |
|
T128 |
6 |
|
T241 |
1 |
| true |
3186 |
1 |
|
T1 |
1 |
|
T2 |
4 |
|
T5 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10139 |
1 |
|
T2 |
2 |
|
T4 |
66 |
|
T9 |
2 |
| others[1] |
782 |
1 |
|
T1 |
1 |
|
T2 |
2 |
|
T16 |
7 |
| others[2] |
807 |
1 |
|
T2 |
1 |
|
T10 |
1 |
|
T16 |
11 |
| others[3] |
1272 |
1 |
|
T5 |
1 |
|
T24 |
1 |
|
T10 |
5 |
| false |
421 |
1 |
|
T2 |
2 |
|
T10 |
1 |
|
T16 |
2 |
| true |
401 |
1 |
|
T2 |
10 |
|
T3 |
1 |
|
T20 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10110 |
1 |
|
T2 |
2 |
|
T4 |
66 |
|
T5 |
1 |
| others[1] |
814 |
1 |
|
T2 |
3 |
|
T10 |
2 |
|
T16 |
11 |
| others[2] |
778 |
1 |
|
T2 |
2 |
|
T10 |
2 |
|
T16 |
10 |
| others[3] |
1290 |
1 |
|
T2 |
2 |
|
T10 |
4 |
|
T16 |
12 |
| false |
411 |
1 |
|
T16 |
7 |
|
T50 |
4 |
|
T128 |
9 |
| true |
419 |
1 |
|
T1 |
1 |
|
T2 |
8 |
|
T3 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
2379 |
1 |
|
T2 |
4 |
|
T4 |
13 |
|
T16 |
8 |
| others[1] |
2461 |
1 |
|
T2 |
3 |
|
T4 |
13 |
|
T9 |
1 |
| others[2] |
2355 |
1 |
|
T2 |
5 |
|
T4 |
14 |
|
T9 |
1 |
| others[3] |
4013 |
1 |
|
T2 |
4 |
|
T4 |
22 |
|
T10 |
3 |
| false |
1190 |
1 |
|
T2 |
1 |
|
T4 |
4 |
|
T10 |
1 |
| true |
1424 |
1 |
|
T1 |
1 |
|
T3 |
1 |
|
T5 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
9588 |
1 |
|
T2 |
1 |
|
T4 |
66 |
|
T5 |
1 |
| others[1] |
255 |
1 |
|
T2 |
2 |
|
T15 |
1 |
|
T128 |
8 |
| others[2] |
261 |
1 |
|
T2 |
2 |
|
T128 |
7 |
|
T144 |
1 |
| others[3] |
439 |
1 |
|
T2 |
3 |
|
T42 |
1 |
|
T128 |
13 |
| false |
148 |
1 |
|
T2 |
1 |
|
T128 |
11 |
|
T118 |
7 |
| true |
3131 |
1 |
|
T1 |
1 |
|
T2 |
8 |
|
T3 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
9841 |
1 |
|
T2 |
5 |
|
T4 |
66 |
|
T9 |
2 |
| others[1] |
430 |
1 |
|
T2 |
1 |
|
T24 |
1 |
|
T16 |
3 |
| others[2] |
471 |
1 |
|
T1 |
1 |
|
T2 |
4 |
|
T10 |
2 |
| others[3] |
752 |
1 |
|
T2 |
6 |
|
T10 |
3 |
|
T20 |
1 |
| false |
240 |
1 |
|
T2 |
1 |
|
T10 |
1 |
|
T16 |
4 |
| true |
2088 |
1 |
|
T3 |
1 |
|
T5 |
1 |
|
T10 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
9570 |
1 |
|
T4 |
66 |
|
T9 |
2 |
|
T21 |
2 |
| others[1] |
268 |
1 |
|
T2 |
4 |
|
T5 |
1 |
|
T128 |
8 |
| others[2] |
261 |
1 |
|
T2 |
4 |
|
T15 |
1 |
|
T128 |
9 |
| others[3] |
399 |
1 |
|
T2 |
2 |
|
T3 |
1 |
|
T61 |
1 |
| false |
119 |
1 |
|
T2 |
1 |
|
T128 |
5 |
|
T144 |
1 |
| true |
3205 |
1 |
|
T1 |
1 |
|
T2 |
6 |
|
T24 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
9562 |
1 |
|
T2 |
1 |
|
T4 |
66 |
|
T5 |
1 |
| others[1] |
237 |
1 |
|
T2 |
2 |
|
T128 |
6 |
|
T196 |
1 |
| others[2] |
253 |
1 |
|
T2 |
1 |
|
T128 |
9 |
|
T144 |
2 |
| others[3] |
377 |
1 |
|
T2 |
5 |
|
T3 |
1 |
|
T128 |
11 |
| false |
118 |
1 |
|
T2 |
1 |
|
T128 |
8 |
|
T118 |
4 |
| true |
3275 |
1 |
|
T1 |
1 |
|
T2 |
7 |
|
T24 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10105 |
1 |
|
T2 |
1 |
|
T4 |
66 |
|
T9 |
2 |
| others[1] |
782 |
1 |
|
T2 |
1 |
|
T10 |
1 |
|
T16 |
12 |
| others[2] |
797 |
1 |
|
T2 |
1 |
|
T5 |
1 |
|
T16 |
7 |
| others[3] |
1303 |
1 |
|
T2 |
3 |
|
T10 |
3 |
|
T16 |
12 |
| false |
426 |
1 |
|
T2 |
1 |
|
T10 |
2 |
|
T16 |
5 |
| true |
409 |
1 |
|
T1 |
1 |
|
T2 |
10 |
|
T3 |
1 |
| 0% |
10% |
20% |
30% |
40% |
50% |
60% |
70% |
80% |
90% |
100% |