Unified Coverage Report :: Group :: flash_ctrl_env_pkg::flash_ctrl_env_cov::control_cg

Group : flash_ctrl_env_pkg::flash_ctrl_env_cov::control_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_flash_ctrl_env_0.1/flash_ctrl_env_cov.sv

---

Summary for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::control_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	15	0	15	100.00
Crosses	16	0	16	100.00

Variables for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::control_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
erase_cp	2	0	2	100.00	100	1	1	0
op_cp	4	0	4	100.00	100	1	1	0
op_evict_cp	5	0	5	100.00	100	1	1	0
part_cp	4	0	4	100.00	100	1	1	0

Crosses for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::control_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
op_part_cross	16	0	16	100.00	100	1	1	0

Summary for Variable erase_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for erase_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[FlashErasePage]	193032	1		T2	28		T3	1490		T4	397
auto[FlashEraseBank]	223147	1		T2	29		T3	1921		T5	47

---

Summary for Variable op_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for op_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[FlashOpRead]	231520	1		T2	34		T3	1409		T4	201
auto[FlashOpProgram]	165262	1		T2	22		T3	2002		T4	98
auto[FlashOpErase]	15397	1		T2	1		T4	98		T5	27
auto[FlashOpInvalid]	4000	1		T182	200		T183	200		T300	200

---

Summary for Variable op_evict_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for op_evict_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
op[FlashOpRead]	231520	1		T2	34		T3	1409		T4	201
op[FlashOpProgram]	165262	1		T2	22		T3	2002		T4	98
op[FlashOpErase]	15397	1		T2	1		T4	98		T5	27
read_erase_read	792	1		T5	5		T22	2		T26	2
read_prog_read	561	1		T2	11		T3	7		T5	17

---

Summary for Variable part_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for part_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[FlashPartData]	291961	1		T2	57		T3	2939		T5	196
auto[FlashPartInfo]	121346	1		T3	456		T4	397		T5	4
auto[FlashPartInfo1]	750	1		T3	5		T15	1		T42	1
auto[FlashPartInfo2]	2122	1		T3	11		T15	26		T61	1

---

Summary for Cross op_part_cross

Samples crossed: part_cp op_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for op_part_cross

Bins

part_cp	op_cp	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[FlashPartData]	auto[FlashOpRead]	167138	1		T2	34		T3	1165		T5	86
auto[FlashPartData]	auto[FlashOpProgram]	117291	1		T2	22		T3	1774		T5	83
auto[FlashPartData]	auto[FlashOpErase]	3612	1		T2	1		T5	27		T26	4
auto[FlashPartData]	auto[FlashOpInvalid]	3920	1		T182	196		T183	196		T300	192
auto[FlashPartInfo]	auto[FlashOpRead]	62395	1		T3	233		T4	201		T22	8
auto[FlashPartInfo]	auto[FlashOpProgram]	47158	1		T3	223		T4	98		T5	4
auto[FlashPartInfo]	auto[FlashOpErase]	11733	1		T4	98		T22	10		T27	10
auto[FlashPartInfo]	auto[FlashOpInvalid]	60	1		T182	4		T183	4		T300	8
auto[FlashPartInfo1]	auto[FlashOpRead]	575	1		T3	5		T15	1		T42	1
auto[FlashPartInfo1]	auto[FlashOpProgram]	165	1		T136	1		T153	1		T155	1
auto[FlashPartInfo1]	auto[FlashOpErase]	4	1		T153	1		T155	1		T141	1
auto[FlashPartInfo1]	auto[FlashOpInvalid]	6	1		T153	2		T155	2		T393	2
auto[FlashPartInfo2]	auto[FlashOpRead]	1412	1		T3	6		T15	15		T61	1
auto[FlashPartInfo2]	auto[FlashOpProgram]	648	1		T3	5		T15	11		T30	7
auto[FlashPartInfo2]	auto[FlashOpErase]	48	1		T128	2		T394	1		T395	1
auto[FlashPartInfo2]	auto[FlashOpInvalid]	14	1		T394	2		T395	2		T155	4