Unified Coverage Report :: Group :: flash_ctrl_env_pkg::flash_ctrl_env_cov::eviction_cg

Group : flash_ctrl_env_pkg::flash_ctrl_env_cov::eviction_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
69.05	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_flash_ctrl_env_0.1/flash_ctrl_env_cov.sv

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Summary for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::eviction_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	32	13	19	59.38

Variables for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::eviction_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
evic_cfg_cp	4	0	4	100.00	100	1	1	4
evic_idx_cp	4	0	4	100.00	100	1	1	0
evic_op_cp	2	0	2	100.00	100	1	1	0

Crosses for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::eviction_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
evic_all_cross	32	13	19	59.38	100	1	1	0

Summary for Variable evic_cfg_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for evic_cfg_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	29716	1		T2	4		T4	192		T5	24
auto[1]	3	1		T314	2		T315	1		-	-
auto[2]	24	1		T165	12		T201	8		T316	4
auto[3]	31	1		T15	1		T74	1		T78	1

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Summary for Variable evic_idx_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for evic_idx_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
evic_idx[0]	7445	1		T2	1		T4	48		T5	6
evic_idx[1]	7445	1		T2	1		T4	48		T5	6
evic_idx[2]	7445	1		T2	1		T4	48		T5	6
evic_idx[3]	7439	1		T2	1		T4	48		T5	6

---

Summary for Variable evic_op_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for evic_op_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
evic_op[1]	28911	1		T4	192		T26	16		T43	372
evic_op[2]	265	1		T15	1		T26	16		T145	1

---

Summary for Cross evic_all_cross

Samples crossed: evic_idx_cp evic_op_cp evic_cfg_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	13	19	59.38	13

Automatically Generated Cross Bins for evic_all_cross

Element holes

evic_idx_cp	evic_op_cp	evic_cfg_cp	COUNT	AT LEAST	NUMBER
[evic_idx[3]]	*	[auto[1] - auto[2]]	--	--	4

Uncovered bins

evic_idx_cp	evic_op_cp	evic_cfg_cp	COUNT	AT LEAST	NUMBER
[evic_idx[0] , evic_idx[1] , evic_idx[2]]	[evic_op[1]]	[auto[2]]	--	--	3
[evic_idx[0] , evic_idx[1] , evic_idx[2]]	[evic_op[2]]	[auto[1] - auto[2]]	--	--	6

Covered bins

evic_idx_cp	evic_op_cp	evic_cfg_cp	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
evic_idx[0]	evic_op[1]	auto[0]	7227	1		T4	48		T26	4		T43	93
evic_idx[0]	evic_op[1]	auto[1]	1	1		T314	1		-	-		-	-
evic_idx[0]	evic_op[1]	auto[3]	2	1		T317	1		T180	1		-	-
evic_idx[0]	evic_op[2]	auto[0]	59	1		T26	4		T79	1		T161	4
evic_idx[0]	evic_op[2]	auto[3]	6	1		T78	1		T70	1		T72	1
evic_idx[1]	evic_op[1]	auto[0]	7225	1		T4	48		T26	4		T43	93
evic_idx[1]	evic_op[1]	auto[1]	1	1		T314	1		-	-		-	-
evic_idx[1]	evic_op[1]	auto[3]	1	1		T317	1		-	-		-	-
evic_idx[1]	evic_op[2]	auto[0]	59	1		T26	4		T79	1		T161	4
evic_idx[1]	evic_op[2]	auto[3]	9	1		T74	1		T318	1		T319	1
evic_idx[2]	evic_op[1]	auto[0]	7226	1		T4	48		T26	4		T43	93
evic_idx[2]	evic_op[1]	auto[1]	1	1		T315	1		-	-		-	-
evic_idx[2]	evic_op[1]	auto[3]	1	1		T317	1		-	-		-	-
evic_idx[2]	evic_op[2]	auto[0]	62	1		T26	4		T145	1		T79	1
evic_idx[2]	evic_op[2]	auto[3]	6	1		T320	1		T321	1		T322	1
evic_idx[3]	evic_op[1]	auto[0]	7225	1		T4	48		T26	4		T43	93
evic_idx[3]	evic_op[1]	auto[3]	1	1		T317	1		-	-		-	-
evic_idx[3]	evic_op[2]	auto[0]	59	1		T26	4		T79	1		T161	4
evic_idx[3]	evic_op[2]	auto[3]	5	1		T15	1		T323	1		T324	1