Unified Coverage Report :: Group :: flash_ctrl_env_pkg::flash_ctrl_env_cov::msgfifo_level_cg

Group : flash_ctrl_env_pkg::flash_ctrl_env_cov::msgfifo_level_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
83.33	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_flash_ctrl_env_0.1/flash_ctrl_env_cov.sv

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Summary for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::msgfifo_level_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	18	3	15	83.33

Variables for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::msgfifo_level_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
prog_lvl_cp	3	3	0	0.00	100	1	1	0
rd_lvl_cp	15	0	15	100.00	100	1	1	0

Summary for Variable prog_lvl_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	3	0	0.00

User Defined Bins for prog_lvl_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER
prog_lvl[1]	0	1	1
prog_lvl[2]	0	1	1
prog_lvl[3]	0	1	1

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Summary for Variable rd_lvl_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	15	0	15	100.00

User Defined Bins for rd_lvl_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
rd_lvl[1]	47737	1		T331	8631		T332	7889		T333	9981
rd_lvl[2]	36175	1		T289	1725		T331	4441		T332	3839
rd_lvl[3]	14598	1		T54	1384		T289	1573		T288	1296
rd_lvl[4]	24159	1		T54	2529		T289	414		T288	3365
rd_lvl[5]	17506	1		T54	148		T134	805		T289	1200
rd_lvl[6]	13569	1		T54	23		T134	1482		T229	661
rd_lvl[7]	11283	1		T54	9		T134	566		T229	1043
rd_lvl[8]	18084	1		T54	5		T134	42		T229	645
rd_lvl[9]	7566	1		T289	37		T334	476		T290	109
rd_lvl[10]	6316	1		T14	595		T54	1		T334	333
rd_lvl[11]	6973	1		T13	621		T14	296		T134	42
rd_lvl[12]	4588	1		T13	220		T289	5		T335	139
rd_lvl[13]	3850	1		T54	12		T289	5		T288	28
rd_lvl[14]	4940	1		T336	804		T337	171		T338	88
rd_lvl[15]	5892	1		T12	459		T75	524		T76	502