Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=5}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=5}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

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Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=5}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	24	0	24	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=5}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	6	0	6	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=5}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	24	0	24	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	6	0	6	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	328450	1		T1	1		T2	25		T3	2
all_pins[1]	328450	1		T1	1		T2	25		T3	2
all_pins[2]	328450	1		T1	1		T2	25		T3	2
all_pins[3]	328450	1		T1	1		T2	25		T3	2
all_pins[4]	328450	1		T1	1		T2	25		T3	2
all_pins[5]	328450	1		T1	1		T2	25		T3	2

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Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	1658502	1		T1	6		T2	150		T3	12
values[0x1]	312198	1		T12	1758		T13	1682		T14	1782
transitions[0x0=>0x1]	279116	1		T12	1338		T13	1682		T14	1782
transitions[0x1=>0x0]	279100	1		T12	1338		T13	1682		T14	1782

---

Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	24	0	24	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	328287	1		T1	1		T2	25		T3	2
all_pins[0]	values[0x1]	163	1		T268	3		T269	2		T270	5
all_pins[0]	transitions[0x0=>0x1]	73	1		T268	3		T269	1		T270	2
all_pins[0]	transitions[0x1=>0x0]	86	1		T268	1		T269	3		T325	1
all_pins[1]	values[0x0]	328274	1		T1	1		T2	25		T3	2
all_pins[1]	values[0x1]	176	1		T268	1		T269	4		T270	3
all_pins[1]	transitions[0x0=>0x1]	139	1		T269	4		T270	3		T325	1
all_pins[1]	transitions[0x1=>0x0]	2691	1		T12	210		T75	499		T76	315
all_pins[2]	values[0x0]	325722	1		T1	1		T2	25		T3	2
all_pins[2]	values[0x1]	2728	1		T12	210		T75	499		T76	315
all_pins[2]	transitions[0x0=>0x1]	43	1		T268	1		T270	1		T325	1
all_pins[2]	transitions[0x1=>0x0]	223692	1		T12	459		T13	841		T14	891
all_pins[3]	values[0x0]	102073	1		T1	1		T2	25		T3	2
all_pins[3]	values[0x1]	226377	1		T12	669		T13	841		T14	891
all_pins[3]	transitions[0x0=>0x1]	196151	1		T12	459		T13	841		T14	891
all_pins[3]	transitions[0x1=>0x0]	52470	1		T12	669		T13	841		T14	891
all_pins[4]	values[0x0]	245754	1		T1	1		T2	25		T3	2
all_pins[4]	values[0x1]	82696	1		T12	879		T13	841		T14	891
all_pins[4]	transitions[0x0=>0x1]	82684	1		T12	879		T13	841		T14	891
all_pins[4]	transitions[0x1=>0x0]	46	1		T270	1		T326	2		T330	1
all_pins[5]	values[0x0]	328392	1		T1	1		T2	25		T3	2
all_pins[5]	values[0x1]	58	1		T268	2		T270	1		T326	2
all_pins[5]	transitions[0x0=>0x1]	26	1		T268	1		T326	2		T342	2
all_pins[5]	transitions[0x1=>0x0]	115	1		T268	1		T269	2		T270	3