Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=5}
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Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=5}
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
83.33 1 100 1 64 64


Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv



Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=5}

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 12 0 12 100.00
Crosses 36 8 28 77.78


Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=5}
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_intr 6 0 6 100.00 100 1 1 0
cp_intr_en 2 0 2 100.00 100 1 1 2
cp_intr_state 2 0 2 100.00 100 1 1 2
cp_intr_test 2 0 2 100.00 100 1 1 2


Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=5}
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
intr_test_cg_cc 36 8 28 77.78 100 1 1 0


Summary for Variable cp_intr

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 6 0 6 100.00


User Defined Bins for cp_intr

Bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
all_values[0] 275 1 T268 4 T269 7 T270 7
all_values[1] 275 1 T268 4 T269 7 T270 7
all_values[2] 275 1 T268 4 T269 7 T270 7
all_values[3] 275 1 T268 4 T269 7 T270 7
all_values[4] 275 1 T268 4 T269 7 T270 7
all_values[5] 275 1 T268 4 T269 7 T270 7



Summary for Variable cp_intr_en

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_intr_en

Bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 847 1 T268 15 T269 28 T270 20
auto[1] 803 1 T268 9 T269 14 T270 22



Summary for Variable cp_intr_state

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_intr_state

Bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 525 1 T268 5 T269 20 T270 12
auto[1] 1125 1 T268 19 T269 22 T270 30



Summary for Variable cp_intr_test

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_intr_test

Bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 954 1 T268 11 T269 29 T270 20
auto[1] 696 1 T268 13 T269 13 T270 22



Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
TOTAL 36 8 28 77.78 8
Automatically Generated Cross Bins 36 8 28 77.78 8
User Defined Cross Bins 0 0 0


Automatically Generated Cross Bins for intr_test_cg_cc

Element holes
cp_intrcp_intr_testcp_intr_encp_intr_stateCOUNTAT LEASTNUMBER
[all_values[0] , all_values[1]] [auto[0]] * [auto[0]] -- -- 4
[all_values[2] , all_values[3]] [auto[0]] * [auto[1]] -- -- 4


Covered bins
cp_intrcp_intr_testcp_intr_encp_intr_stateCOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
all_values[0] auto[0] auto[0] auto[1] 90 1 T268 1 T269 3 T270 2
all_values[0] auto[0] auto[1] auto[1] 75 1 T268 1 T269 1 T270 1
all_values[0] auto[1] auto[0] auto[1] 57 1 T268 1 T269 2 T270 1
all_values[0] auto[1] auto[1] auto[1] 53 1 T268 1 T269 1 T270 3
all_values[1] auto[0] auto[0] auto[1] 83 1 T268 2 T269 3 T270 2
all_values[1] auto[0] auto[1] auto[1] 69 1 T269 2 T270 1 T325 1
all_values[1] auto[1] auto[0] auto[1] 55 1 T268 2 T270 3 T325 2
all_values[1] auto[1] auto[1] auto[1] 68 1 T269 2 T270 1 T326 2
all_values[2] auto[0] auto[0] auto[0] 72 1 T268 1 T269 5 T325 1
all_values[2] auto[0] auto[1] auto[0] 81 1 T270 4 T325 2 T327 1
all_values[2] auto[1] auto[0] auto[1] 74 1 T268 2 T269 2 T325 1
all_values[2] auto[1] auto[1] auto[1] 48 1 T268 1 T270 3 T327 1
all_values[3] auto[0] auto[0] auto[0] 74 1 T268 1 T269 2 T325 2
all_values[3] auto[0] auto[1] auto[0] 83 1 T269 2 T270 5 T325 2
all_values[3] auto[1] auto[0] auto[1] 62 1 T268 2 T269 1 T327 1
all_values[3] auto[1] auto[1] auto[1] 56 1 T268 1 T269 2 T270 2
all_values[4] auto[0] auto[0] auto[0] 58 1 T268 1 T269 4 T270 1
all_values[4] auto[0] auto[0] auto[1] 26 1 T270 2 T325 1 T327 1
all_values[4] auto[0] auto[1] auto[0] 41 1 T269 1 T326 2 T328 1
all_values[4] auto[0] auto[1] auto[1] 30 1 T268 1 T329 2 T330 1
all_values[4] auto[1] auto[0] auto[1] 57 1 T268 1 T269 2 T270 4
all_values[4] auto[1] auto[1] auto[1] 63 1 T268 1 T325 1 T326 3
all_values[5] auto[0] auto[0] auto[0] 66 1 T268 1 T269 4 T270 2
all_values[5] auto[0] auto[0] auto[1] 30 1 T325 1 T327 1 T330 1
all_values[5] auto[0] auto[1] auto[0] 50 1 T268 1 T269 2 T325 1
all_values[5] auto[0] auto[1] auto[1] 26 1 T268 1 T326 1 T330 1
all_values[5] auto[1] auto[0] auto[1] 43 1 T270 3 T325 1 T327 1
all_values[5] auto[1] auto[1] auto[1] 60 1 T268 1 T269 1 T270 2


User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins
NAMECOUNTSTATUS
test_1_state_0 0 Illegal

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