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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
95.05 95.85 93.23 94.81 91.16 98.07 94.61 97.60


Total test records in report: 1101
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html | tests10.html | tests11.html | tests12.html | tests13.html | tests14.html | tests15.html | tests16.html | tests17.html | tests18.html | tests19.html | tests20.html | tests21.html | tests22.html
T840 /workspace/coverage/default/38.flash_ctrl_otp_reset.4107199236 Apr 28 03:16:36 PM PDT 24 Apr 28 03:18:27 PM PDT 24 249011500 ps
T841 /workspace/coverage/default/3.flash_ctrl_error_prog_type.4056181636 Apr 28 03:09:53 PM PDT 24 Apr 28 03:40:03 PM PDT 24 682304400 ps
T842 /workspace/coverage/default/6.flash_ctrl_alert_test.1304658422 Apr 28 03:11:25 PM PDT 24 Apr 28 03:11:39 PM PDT 24 37053800 ps
T843 /workspace/coverage/default/39.flash_ctrl_otp_reset.378173813 Apr 28 03:16:50 PM PDT 24 Apr 28 03:19:01 PM PDT 24 176317900 ps
T109 /workspace/coverage/default/3.flash_ctrl_host_ctrl_arb.3043066212 Apr 28 03:09:53 PM PDT 24 Apr 28 03:59:09 PM PDT 24 255215876200 ps
T844 /workspace/coverage/default/12.flash_ctrl_smoke.4246904506 Apr 28 03:12:45 PM PDT 24 Apr 28 03:15:16 PM PDT 24 95492200 ps
T845 /workspace/coverage/default/11.flash_ctrl_alert_test.3015379688 Apr 28 03:12:47 PM PDT 24 Apr 28 03:13:02 PM PDT 24 196046800 ps
T846 /workspace/coverage/default/4.flash_ctrl_read_word_sweep_derr.167404173 Apr 28 03:10:38 PM PDT 24 Apr 28 03:11:02 PM PDT 24 33033900 ps
T847 /workspace/coverage/default/3.flash_ctrl_rand_ops.3079239661 Apr 28 03:09:47 PM PDT 24 Apr 28 03:17:57 PM PDT 24 2987304400 ps
T848 /workspace/coverage/default/31.flash_ctrl_sec_info_access.1051873951 Apr 28 03:15:53 PM PDT 24 Apr 28 03:16:57 PM PDT 24 6035306300 ps
T849 /workspace/coverage/default/62.flash_ctrl_connect.36152055 Apr 28 03:17:33 PM PDT 24 Apr 28 03:17:49 PM PDT 24 95238600 ps
T850 /workspace/coverage/default/23.flash_ctrl_smoke.2927090878 Apr 28 03:15:07 PM PDT 24 Apr 28 03:15:59 PM PDT 24 67126400 ps
T851 /workspace/coverage/default/0.flash_ctrl_hw_rma_reset.2142296779 Apr 28 03:08:38 PM PDT 24 Apr 28 03:24:11 PM PDT 24 160190285000 ps
T82 /workspace/coverage/default/12.flash_ctrl_hw_rma_reset.2539705501 Apr 28 03:12:46 PM PDT 24 Apr 28 03:27:10 PM PDT 24 80147173900 ps
T852 /workspace/coverage/default/45.flash_ctrl_otp_reset.1818884712 Apr 28 03:17:09 PM PDT 24 Apr 28 03:19:02 PM PDT 24 75039000 ps
T853 /workspace/coverage/default/9.flash_ctrl_lcmgr_intg.72468781 Apr 28 03:12:22 PM PDT 24 Apr 28 03:12:36 PM PDT 24 15099400 ps
T854 /workspace/coverage/default/2.flash_ctrl_fetch_code.3317375288 Apr 28 03:09:20 PM PDT 24 Apr 28 03:09:42 PM PDT 24 941257800 ps
T855 /workspace/coverage/default/24.flash_ctrl_smoke.1676190490 Apr 28 03:15:12 PM PDT 24 Apr 28 03:16:52 PM PDT 24 65967000 ps
T856 /workspace/coverage/default/7.flash_ctrl_hw_prog_rma_wipe_err.3401397325 Apr 28 03:11:41 PM PDT 24 Apr 28 03:12:28 PM PDT 24 10054727200 ps
T857 /workspace/coverage/default/46.flash_ctrl_connect.1844384599 Apr 28 03:17:12 PM PDT 24 Apr 28 03:17:25 PM PDT 24 46198500 ps
T858 /workspace/coverage/default/29.flash_ctrl_smoke.568889013 Apr 28 03:15:41 PM PDT 24 Apr 28 03:18:07 PM PDT 24 34820300 ps
T859 /workspace/coverage/default/15.flash_ctrl_sec_info_access.1236931918 Apr 28 03:13:45 PM PDT 24 Apr 28 03:14:51 PM PDT 24 2107905800 ps
T860 /workspace/coverage/default/0.flash_ctrl_intr_rd_slow_flash.3190791098 Apr 28 03:08:49 PM PDT 24 Apr 28 03:11:58 PM PDT 24 10765225700 ps
T861 /workspace/coverage/default/41.flash_ctrl_alert_test.2908882860 Apr 28 03:16:53 PM PDT 24 Apr 28 03:17:07 PM PDT 24 20941700 ps
T387 /workspace/coverage/default/35.flash_ctrl_sec_info_access.3461390839 Apr 28 03:16:21 PM PDT 24 Apr 28 03:17:39 PM PDT 24 8427282900 ps
T862 /workspace/coverage/default/39.flash_ctrl_connect.2012931052 Apr 28 03:16:48 PM PDT 24 Apr 28 03:17:05 PM PDT 24 53710200 ps
T863 /workspace/coverage/default/5.flash_ctrl_wo.1871149485 Apr 28 03:10:58 PM PDT 24 Apr 28 03:14:10 PM PDT 24 10350915300 ps
T864 /workspace/coverage/default/8.flash_ctrl_hw_prog_rma_wipe_err.3068513414 Apr 28 03:12:06 PM PDT 24 Apr 28 03:13:00 PM PDT 24 10031728900 ps
T865 /workspace/coverage/default/4.flash_ctrl_otp_reset.3779515409 Apr 28 03:10:24 PM PDT 24 Apr 28 03:12:35 PM PDT 24 132961300 ps
T199 /workspace/coverage/default/0.flash_ctrl_wr_intg.1885997875 Apr 28 03:08:53 PM PDT 24 Apr 28 03:09:09 PM PDT 24 176822000 ps
T866 /workspace/coverage/default/5.flash_ctrl_prog_reset.1216064070 Apr 28 03:11:02 PM PDT 24 Apr 28 03:11:16 PM PDT 24 61459800 ps
T867 /workspace/coverage/default/2.flash_ctrl_otp_reset.3189412445 Apr 28 03:09:14 PM PDT 24 Apr 28 03:11:29 PM PDT 24 79637000 ps
T868 /workspace/coverage/default/5.flash_ctrl_intr_rd.2634227850 Apr 28 03:11:02 PM PDT 24 Apr 28 03:13:42 PM PDT 24 2572164000 ps
T869 /workspace/coverage/default/65.flash_ctrl_connect.307891749 Apr 28 03:17:33 PM PDT 24 Apr 28 03:17:47 PM PDT 24 34302300 ps
T870 /workspace/coverage/default/22.flash_ctrl_intr_rd.222530280 Apr 28 03:14:57 PM PDT 24 Apr 28 03:17:32 PM PDT 24 1481189500 ps
T871 /workspace/coverage/default/13.flash_ctrl_sec_info_access.3402859346 Apr 28 03:13:12 PM PDT 24 Apr 28 03:14:28 PM PDT 24 8341549000 ps
T872 /workspace/coverage/default/17.flash_ctrl_disable.930812775 Apr 28 03:14:15 PM PDT 24 Apr 28 03:14:38 PM PDT 24 11558800 ps
T873 /workspace/coverage/default/14.flash_ctrl_ro.4019847585 Apr 28 03:13:24 PM PDT 24 Apr 28 03:15:50 PM PDT 24 1356134500 ps
T874 /workspace/coverage/default/6.flash_ctrl_rand_ops.3405163394 Apr 28 03:11:14 PM PDT 24 Apr 28 03:19:31 PM PDT 24 77942900 ps
T875 /workspace/coverage/default/19.flash_ctrl_hw_rma_reset.765608172 Apr 28 03:14:32 PM PDT 24 Apr 28 03:28:39 PM PDT 24 40126841700 ps
T876 /workspace/coverage/default/76.flash_ctrl_connect.3988720800 Apr 28 03:17:42 PM PDT 24 Apr 28 03:17:59 PM PDT 24 79426400 ps
T877 /workspace/coverage/default/0.flash_ctrl_hw_sec_otp.2154212888 Apr 28 03:08:37 PM PDT 24 Apr 28 03:11:01 PM PDT 24 31438506500 ps
T878 /workspace/coverage/default/47.flash_ctrl_otp_reset.1396694217 Apr 28 03:17:13 PM PDT 24 Apr 28 03:19:27 PM PDT 24 45556000 ps
T879 /workspace/coverage/default/13.flash_ctrl_wo.964051852 Apr 28 03:13:09 PM PDT 24 Apr 28 03:16:17 PM PDT 24 2772981600 ps
T880 /workspace/coverage/default/27.flash_ctrl_rw_evict_all_en.725453212 Apr 28 03:15:46 PM PDT 24 Apr 28 03:16:18 PM PDT 24 73148500 ps
T881 /workspace/coverage/default/10.flash_ctrl_mp_regions.2275581342 Apr 28 03:12:25 PM PDT 24 Apr 28 03:16:10 PM PDT 24 7642395600 ps
T882 /workspace/coverage/default/1.flash_ctrl_hw_read_seed_err.1527828722 Apr 28 03:09:10 PM PDT 24 Apr 28 03:09:24 PM PDT 24 16455200 ps
T883 /workspace/coverage/default/2.flash_ctrl_disable.2705011914 Apr 28 03:09:42 PM PDT 24 Apr 28 03:10:05 PM PDT 24 33732900 ps
T884 /workspace/coverage/default/65.flash_ctrl_otp_reset.2480607154 Apr 28 03:17:34 PM PDT 24 Apr 28 03:19:45 PM PDT 24 77074100 ps
T885 /workspace/coverage/default/0.flash_ctrl_hw_read_seed_err.3463603879 Apr 28 03:09:00 PM PDT 24 Apr 28 03:09:15 PM PDT 24 15345300 ps
T886 /workspace/coverage/default/26.flash_ctrl_alert_test.3851821147 Apr 28 03:15:30 PM PDT 24 Apr 28 03:15:44 PM PDT 24 189434800 ps
T887 /workspace/coverage/default/8.flash_ctrl_error_prog_win.4238134374 Apr 28 03:11:51 PM PDT 24 Apr 28 03:27:03 PM PDT 24 865865500 ps
T888 /workspace/coverage/default/35.flash_ctrl_connect.1805693148 Apr 28 03:16:21 PM PDT 24 Apr 28 03:16:37 PM PDT 24 31218100 ps
T889 /workspace/coverage/default/8.flash_ctrl_wo.413081563 Apr 28 03:11:51 PM PDT 24 Apr 28 03:15:22 PM PDT 24 2478129500 ps
T890 /workspace/coverage/default/1.flash_ctrl_fs_sup.697094105 Apr 28 03:09:10 PM PDT 24 Apr 28 03:09:47 PM PDT 24 579089800 ps
T891 /workspace/coverage/default/6.flash_ctrl_error_mp.688855401 Apr 28 03:11:12 PM PDT 24 Apr 28 03:48:07 PM PDT 24 10961284100 ps
T127 /workspace/coverage/default/3.flash_ctrl_disable.1588067449 Apr 28 03:10:09 PM PDT 24 Apr 28 03:10:30 PM PDT 24 23975200 ps
T892 /workspace/coverage/default/28.flash_ctrl_sec_info_access.4289006227 Apr 28 03:15:40 PM PDT 24 Apr 28 03:16:36 PM PDT 24 440555600 ps
T124 /workspace/coverage/default/2.flash_ctrl_phy_ack_consistency.3690723049 Apr 28 03:09:48 PM PDT 24 Apr 28 03:10:03 PM PDT 24 44271400 ps
T893 /workspace/coverage/default/9.flash_ctrl_intr_rd_slow_flash.3475920829 Apr 28 03:12:21 PM PDT 24 Apr 28 03:17:20 PM PDT 24 9030228600 ps
T894 /workspace/coverage/default/15.flash_ctrl_re_evict.3488272825 Apr 28 03:13:45 PM PDT 24 Apr 28 03:14:19 PM PDT 24 158980900 ps
T895 /workspace/coverage/default/20.flash_ctrl_otp_reset.2099562549 Apr 28 03:14:48 PM PDT 24 Apr 28 03:17:00 PM PDT 24 46357300 ps
T896 /workspace/coverage/default/4.flash_ctrl_rand_ops.2424168505 Apr 28 03:10:20 PM PDT 24 Apr 28 03:14:04 PM PDT 24 39565200 ps
T897 /workspace/coverage/default/67.flash_ctrl_otp_reset.3787674497 Apr 28 03:17:41 PM PDT 24 Apr 28 03:19:51 PM PDT 24 76984100 ps
T898 /workspace/coverage/default/45.flash_ctrl_connect.1591758083 Apr 28 03:17:09 PM PDT 24 Apr 28 03:17:25 PM PDT 24 40179600 ps
T899 /workspace/coverage/default/0.flash_ctrl_mp_regions.1225829242 Apr 28 03:08:38 PM PDT 24 Apr 28 03:13:56 PM PDT 24 35320849900 ps
T900 /workspace/coverage/default/14.flash_ctrl_mp_regions.3224079228 Apr 28 03:13:24 PM PDT 24 Apr 28 03:28:39 PM PDT 24 34985542500 ps
T901 /workspace/coverage/default/2.flash_ctrl_sw_op.271004310 Apr 28 03:09:14 PM PDT 24 Apr 28 03:09:41 PM PDT 24 90813800 ps
T902 /workspace/coverage/default/0.flash_ctrl_hw_rma.4245727071 Apr 28 03:08:39 PM PDT 24 Apr 28 03:38:57 PM PDT 24 317051460300 ps
T903 /workspace/coverage/default/2.flash_ctrl_read_word_sweep_serr.4126117097 Apr 28 03:09:36 PM PDT 24 Apr 28 03:09:59 PM PDT 24 62249000 ps
T188 /workspace/coverage/default/3.flash_ctrl_phy_ack_consistency.3369228625 Apr 28 03:10:14 PM PDT 24 Apr 28 03:10:28 PM PDT 24 48924300 ps
T904 /workspace/coverage/default/17.flash_ctrl_otp_reset.3225561415 Apr 28 03:14:12 PM PDT 24 Apr 28 03:16:03 PM PDT 24 139029500 ps
T905 /workspace/coverage/default/5.flash_ctrl_hw_prog_rma_wipe_err.2157384130 Apr 28 03:11:06 PM PDT 24 Apr 28 03:12:13 PM PDT 24 10032491000 ps
T906 /workspace/coverage/default/16.flash_ctrl_hw_rma_reset.1512833927 Apr 28 03:13:53 PM PDT 24 Apr 28 03:28:44 PM PDT 24 80148432600 ps
T907 /workspace/coverage/default/0.flash_ctrl_read_word_sweep_serr.4251262559 Apr 28 03:08:44 PM PDT 24 Apr 28 03:09:08 PM PDT 24 296656300 ps
T393 /workspace/coverage/default/1.flash_ctrl_invalid_op.4104987650 Apr 28 03:09:07 PM PDT 24 Apr 28 03:10:39 PM PDT 24 4069343100 ps
T908 /workspace/coverage/default/23.flash_ctrl_hw_sec_otp.612015329 Apr 28 03:15:02 PM PDT 24 Apr 28 03:15:56 PM PDT 24 523032600 ps
T909 /workspace/coverage/default/30.flash_ctrl_alert_test.851748792 Apr 28 03:15:55 PM PDT 24 Apr 28 03:16:09 PM PDT 24 86375600 ps
T910 /workspace/coverage/default/37.flash_ctrl_alert_test.2972722100 Apr 28 03:16:38 PM PDT 24 Apr 28 03:16:52 PM PDT 24 224158900 ps
T911 /workspace/coverage/default/48.flash_ctrl_hw_sec_otp.1401852517 Apr 28 03:17:17 PM PDT 24 Apr 28 03:18:15 PM PDT 24 2376905800 ps
T912 /workspace/coverage/default/21.flash_ctrl_otp_reset.727413934 Apr 28 03:14:52 PM PDT 24 Apr 28 03:17:05 PM PDT 24 40445400 ps
T913 /workspace/coverage/default/34.flash_ctrl_alert_test.3457586279 Apr 28 03:16:20 PM PDT 24 Apr 28 03:16:34 PM PDT 24 63857700 ps
T914 /workspace/coverage/default/19.flash_ctrl_intr_rd_slow_flash.1459681184 Apr 28 03:14:38 PM PDT 24 Apr 28 03:18:17 PM PDT 24 40104248900 ps
T915 /workspace/coverage/default/19.flash_ctrl_intr_rd.4293166471 Apr 28 03:14:37 PM PDT 24 Apr 28 03:17:57 PM PDT 24 4284335300 ps
T916 /workspace/coverage/default/14.flash_ctrl_phy_arb.1636182655 Apr 28 03:13:21 PM PDT 24 Apr 28 03:20:21 PM PDT 24 1099531600 ps
T917 /workspace/coverage/default/10.flash_ctrl_re_evict.3884845869 Apr 28 03:12:30 PM PDT 24 Apr 28 03:13:06 PM PDT 24 207959500 ps
T918 /workspace/coverage/default/19.flash_ctrl_connect.2251068149 Apr 28 03:14:42 PM PDT 24 Apr 28 03:14:56 PM PDT 24 58284800 ps
T131 /workspace/coverage/default/0.flash_ctrl_phy_arb_redun.1909982482 Apr 28 03:08:58 PM PDT 24 Apr 28 03:09:17 PM PDT 24 649752000 ps
T919 /workspace/coverage/default/1.flash_ctrl_mp_regions.701256148 Apr 28 03:09:01 PM PDT 24 Apr 28 03:17:19 PM PDT 24 15603560300 ps
T920 /workspace/coverage/default/71.flash_ctrl_connect.2970388123 Apr 28 03:17:41 PM PDT 24 Apr 28 03:17:57 PM PDT 24 21418600 ps
T921 /workspace/coverage/default/33.flash_ctrl_otp_reset.2600644138 Apr 28 03:16:04 PM PDT 24 Apr 28 03:18:17 PM PDT 24 38893900 ps
T922 /workspace/coverage/default/10.flash_ctrl_smoke.1968374596 Apr 28 03:12:21 PM PDT 24 Apr 28 03:14:48 PM PDT 24 43081800 ps
T923 /workspace/coverage/default/11.flash_ctrl_otp_reset.914055940 Apr 28 03:12:37 PM PDT 24 Apr 28 03:14:44 PM PDT 24 145824300 ps
T924 /workspace/coverage/default/17.flash_ctrl_ro.2311930956 Apr 28 03:14:09 PM PDT 24 Apr 28 03:16:29 PM PDT 24 7829023900 ps
T925 /workspace/coverage/default/15.flash_ctrl_intr_rd.751404433 Apr 28 03:13:43 PM PDT 24 Apr 28 03:16:54 PM PDT 24 13852248400 ps
T926 /workspace/coverage/default/10.flash_ctrl_lcmgr_intg.3388858169 Apr 28 03:12:30 PM PDT 24 Apr 28 03:12:44 PM PDT 24 46256500 ps
T927 /workspace/coverage/default/2.flash_ctrl_phy_arb.3576801442 Apr 28 03:09:10 PM PDT 24 Apr 28 03:14:31 PM PDT 24 260226500 ps
T928 /workspace/coverage/default/39.flash_ctrl_intr_rd.3956083691 Apr 28 03:16:42 PM PDT 24 Apr 28 03:20:36 PM PDT 24 4379925900 ps
T929 /workspace/coverage/default/11.flash_ctrl_rand_ops.1121630570 Apr 28 03:12:37 PM PDT 24 Apr 28 03:28:02 PM PDT 24 3578343400 ps
T930 /workspace/coverage/default/2.flash_ctrl_host_dir_rd.2682680124 Apr 28 03:09:11 PM PDT 24 Apr 28 03:09:38 PM PDT 24 277356600 ps
T931 /workspace/coverage/default/6.flash_ctrl_phy_arb.890643397 Apr 28 03:11:11 PM PDT 24 Apr 28 03:14:35 PM PDT 24 1857687700 ps
T932 /workspace/coverage/default/17.flash_ctrl_invalid_op.3754859734 Apr 28 03:14:09 PM PDT 24 Apr 28 03:15:25 PM PDT 24 967224300 ps
T933 /workspace/coverage/default/5.flash_ctrl_alert_test.2963957921 Apr 28 03:11:06 PM PDT 24 Apr 28 03:11:21 PM PDT 24 34994000 ps
T255 /workspace/coverage/default/12.flash_ctrl_hw_sec_otp.1721489460 Apr 28 03:12:47 PM PDT 24 Apr 28 03:15:49 PM PDT 24 2408612500 ps
T934 /workspace/coverage/default/21.flash_ctrl_connect.2342468603 Apr 28 03:14:57 PM PDT 24 Apr 28 03:15:13 PM PDT 24 29070200 ps
T935 /workspace/coverage/default/5.flash_ctrl_otp_reset.4015984319 Apr 28 03:10:53 PM PDT 24 Apr 28 03:13:00 PM PDT 24 106447300 ps
T936 /workspace/coverage/default/16.flash_ctrl_intr_rd_slow_flash.4272875708 Apr 28 03:13:53 PM PDT 24 Apr 28 03:17:18 PM PDT 24 8107616200 ps
T937 /workspace/coverage/default/45.flash_ctrl_smoke.1240120315 Apr 28 03:17:02 PM PDT 24 Apr 28 03:17:52 PM PDT 24 64758500 ps
T938 /workspace/coverage/default/74.flash_ctrl_connect.1799173554 Apr 28 03:17:41 PM PDT 24 Apr 28 03:17:57 PM PDT 24 16325700 ps
T939 /workspace/coverage/default/43.flash_ctrl_connect.2600195236 Apr 28 03:17:00 PM PDT 24 Apr 28 03:17:14 PM PDT 24 17119000 ps
T940 /workspace/coverage/default/25.flash_ctrl_intr_rd.2231085371 Apr 28 03:15:21 PM PDT 24 Apr 28 03:18:02 PM PDT 24 11128662100 ps
T941 /workspace/coverage/default/3.flash_ctrl_invalid_op.180823891 Apr 28 03:09:58 PM PDT 24 Apr 28 03:11:15 PM PDT 24 997664300 ps
T942 /workspace/coverage/default/17.flash_ctrl_smoke.3989338584 Apr 28 03:14:05 PM PDT 24 Apr 28 03:15:45 PM PDT 24 105973500 ps
T943 /workspace/coverage/default/22.flash_ctrl_connect.1722628935 Apr 28 03:15:06 PM PDT 24 Apr 28 03:15:22 PM PDT 24 14859700 ps
T944 /workspace/coverage/default/19.flash_ctrl_sec_info_access.3185835851 Apr 28 03:14:42 PM PDT 24 Apr 28 03:15:34 PM PDT 24 337229100 ps
T945 /workspace/coverage/default/20.flash_ctrl_hw_sec_otp.2270516560 Apr 28 03:14:47 PM PDT 24 Apr 28 03:15:38 PM PDT 24 1357197600 ps
T946 /workspace/coverage/default/32.flash_ctrl_disable.1293737470 Apr 28 03:16:04 PM PDT 24 Apr 28 03:16:25 PM PDT 24 10208000 ps
T947 /workspace/coverage/default/31.flash_ctrl_alert_test.1958841929 Apr 28 03:16:01 PM PDT 24 Apr 28 03:16:15 PM PDT 24 52240600 ps
T948 /workspace/coverage/default/7.flash_ctrl_error_prog_win.438072119 Apr 28 03:11:29 PM PDT 24 Apr 28 03:25:03 PM PDT 24 330834400 ps
T949 /workspace/coverage/default/33.flash_ctrl_smoke.962410906 Apr 28 03:16:06 PM PDT 24 Apr 28 03:18:08 PM PDT 24 68437100 ps
T950 /workspace/coverage/default/16.flash_ctrl_invalid_op.3032200882 Apr 28 03:13:54 PM PDT 24 Apr 28 03:14:57 PM PDT 24 3405169000 ps
T951 /workspace/coverage/default/19.flash_ctrl_mp_regions.2765213055 Apr 28 03:14:33 PM PDT 24 Apr 28 03:22:54 PM PDT 24 29266099200 ps
T952 /workspace/coverage/default/54.flash_ctrl_otp_reset.2898951473 Apr 28 03:17:29 PM PDT 24 Apr 28 03:19:39 PM PDT 24 51940000 ps
T953 /workspace/coverage/default/6.flash_ctrl_hw_rma_reset.215564028 Apr 28 03:11:11 PM PDT 24 Apr 28 03:25:18 PM PDT 24 80136418900 ps
T954 /workspace/coverage/default/35.flash_ctrl_alert_test.3516000549 Apr 28 03:16:22 PM PDT 24 Apr 28 03:16:36 PM PDT 24 48588200 ps
T955 /workspace/coverage/default/0.flash_ctrl_lcmgr_intg.3495606433 Apr 28 03:08:59 PM PDT 24 Apr 28 03:09:14 PM PDT 24 35573700 ps
T956 /workspace/coverage/default/19.flash_ctrl_rw.2576274054 Apr 28 03:14:38 PM PDT 24 Apr 28 03:25:17 PM PDT 24 32535372700 ps
T163 /workspace/coverage/default/0.flash_ctrl_mid_op_rst.810370350 Apr 28 03:08:44 PM PDT 24 Apr 28 03:10:01 PM PDT 24 2686695200 ps
T957 /workspace/coverage/default/2.flash_ctrl_error_prog_type.3468764817 Apr 28 03:09:20 PM PDT 24 Apr 28 03:49:20 PM PDT 24 866587000 ps
T958 /workspace/coverage/default/8.flash_ctrl_hw_sec_otp.1530713078 Apr 28 03:11:41 PM PDT 24 Apr 28 03:13:34 PM PDT 24 22683642000 ps
T959 /workspace/coverage/default/25.flash_ctrl_alert_test.3451560945 Apr 28 03:15:28 PM PDT 24 Apr 28 03:15:42 PM PDT 24 38609100 ps
T960 /workspace/coverage/default/10.flash_ctrl_hw_sec_otp.225775166 Apr 28 03:12:22 PM PDT 24 Apr 28 03:13:35 PM PDT 24 914664500 ps
T961 /workspace/coverage/default/7.flash_ctrl_rw_evict_all_en.1110557689 Apr 28 03:11:41 PM PDT 24 Apr 28 03:12:14 PM PDT 24 75732400 ps
T962 /workspace/coverage/default/0.flash_ctrl_wo.4095171973 Apr 28 03:08:43 PM PDT 24 Apr 28 03:12:50 PM PDT 24 4033318200 ps
T963 /workspace/coverage/default/14.flash_ctrl_smoke.1292648380 Apr 28 03:13:22 PM PDT 24 Apr 28 03:14:15 PM PDT 24 27244500 ps
T964 /workspace/coverage/default/32.flash_ctrl_smoke.4234068624 Apr 28 03:15:59 PM PDT 24 Apr 28 03:18:01 PM PDT 24 71781500 ps
T55 /workspace/coverage/cover_reg_top/6.flash_ctrl_csr_rw.1519821670 Apr 28 02:55:49 PM PDT 24 Apr 28 02:56:07 PM PDT 24 75477000 ps
T56 /workspace/coverage/cover_reg_top/4.flash_ctrl_csr_mem_rw_with_rand_reset.3104864058 Apr 28 02:55:46 PM PDT 24 Apr 28 02:56:04 PM PDT 24 65547200 ps
T57 /workspace/coverage/cover_reg_top/12.flash_ctrl_tl_errors.3036351459 Apr 28 02:55:59 PM PDT 24 Apr 28 02:56:17 PM PDT 24 67383300 ps
T268 /workspace/coverage/cover_reg_top/10.flash_ctrl_intr_test.3129229370 Apr 28 02:55:55 PM PDT 24 Apr 28 02:56:09 PM PDT 24 20751300 ps
T125 /workspace/coverage/cover_reg_top/3.flash_ctrl_same_csr_outstanding.61507355 Apr 28 02:55:43 PM PDT 24 Apr 28 02:56:18 PM PDT 24 94719900 ps
T220 /workspace/coverage/cover_reg_top/13.flash_ctrl_same_csr_outstanding.174107394 Apr 28 02:56:04 PM PDT 24 Apr 28 02:56:25 PM PDT 24 347930400 ps
T965 /workspace/coverage/cover_reg_top/19.flash_ctrl_shadow_reg_errors_with_csr_rw.1473391696 Apr 28 02:56:28 PM PDT 24 Apr 28 02:56:44 PM PDT 24 13670600 ps
T60 /workspace/coverage/cover_reg_top/2.flash_ctrl_csr_bit_bash.3242895803 Apr 28 02:55:42 PM PDT 24 Apr 28 02:56:56 PM PDT 24 12270226200 ps
T269 /workspace/coverage/cover_reg_top/4.flash_ctrl_intr_test.2570269932 Apr 28 02:55:46 PM PDT 24 Apr 28 02:56:00 PM PDT 24 50060600 ps
T270 /workspace/coverage/cover_reg_top/32.flash_ctrl_intr_test.413308130 Apr 28 02:56:35 PM PDT 24 Apr 28 02:56:49 PM PDT 24 55852000 ps
T58 /workspace/coverage/cover_reg_top/14.flash_ctrl_tl_intg_err.126671945 Apr 28 02:56:04 PM PDT 24 Apr 28 03:11:03 PM PDT 24 2591772300 ps
T325 /workspace/coverage/cover_reg_top/42.flash_ctrl_intr_test.1367907837 Apr 28 02:56:36 PM PDT 24 Apr 28 02:56:50 PM PDT 24 29801400 ps
T221 /workspace/coverage/cover_reg_top/4.flash_ctrl_same_csr_outstanding.2694885694 Apr 28 02:55:44 PM PDT 24 Apr 28 02:56:04 PM PDT 24 234800400 ps
T966 /workspace/coverage/cover_reg_top/10.flash_ctrl_shadow_reg_errors_with_csr_rw.659820762 Apr 28 02:55:54 PM PDT 24 Apr 28 02:56:11 PM PDT 24 15475700 ps
T194 /workspace/coverage/cover_reg_top/16.flash_ctrl_tl_errors.179174605 Apr 28 02:56:17 PM PDT 24 Apr 28 02:56:33 PM PDT 24 51992200 ps
T59 /workspace/coverage/cover_reg_top/12.flash_ctrl_csr_mem_rw_with_rand_reset.931441682 Apr 28 02:56:01 PM PDT 24 Apr 28 02:56:19 PM PDT 24 87551500 ps
T205 /workspace/coverage/cover_reg_top/10.flash_ctrl_csr_mem_rw_with_rand_reset.2158985840 Apr 28 02:55:56 PM PDT 24 Apr 28 02:56:14 PM PDT 24 25981300 ps
T967 /workspace/coverage/cover_reg_top/17.flash_ctrl_shadow_reg_errors_with_csr_rw.2269757507 Apr 28 02:56:19 PM PDT 24 Apr 28 02:56:36 PM PDT 24 11745100 ps
T968 /workspace/coverage/cover_reg_top/7.flash_ctrl_shadow_reg_errors_with_csr_rw.3788430770 Apr 28 02:55:51 PM PDT 24 Apr 28 02:56:08 PM PDT 24 67678000 ps
T969 /workspace/coverage/cover_reg_top/0.flash_ctrl_mem_walk.730115376 Apr 28 02:55:30 PM PDT 24 Apr 28 02:55:44 PM PDT 24 14629100 ps
T222 /workspace/coverage/cover_reg_top/7.flash_ctrl_same_csr_outstanding.148377437 Apr 28 02:55:51 PM PDT 24 Apr 28 02:56:09 PM PDT 24 91006700 ps
T223 /workspace/coverage/cover_reg_top/11.flash_ctrl_csr_rw.2641186534 Apr 28 02:55:59 PM PDT 24 Apr 28 02:56:14 PM PDT 24 52797600 ps
T327 /workspace/coverage/cover_reg_top/28.flash_ctrl_intr_test.2501233066 Apr 28 02:56:30 PM PDT 24 Apr 28 02:56:44 PM PDT 24 28137200 ps
T970 /workspace/coverage/cover_reg_top/18.flash_ctrl_shadow_reg_errors.1517344864 Apr 28 02:56:24 PM PDT 24 Apr 28 02:56:40 PM PDT 24 47780400 ps
T224 /workspace/coverage/cover_reg_top/6.flash_ctrl_same_csr_outstanding.2065589951 Apr 28 02:55:50 PM PDT 24 Apr 28 02:56:11 PM PDT 24 295509600 ps
T225 /workspace/coverage/cover_reg_top/16.flash_ctrl_same_csr_outstanding.1474339147 Apr 28 02:56:21 PM PDT 24 Apr 28 02:56:39 PM PDT 24 163481400 ps
T195 /workspace/coverage/cover_reg_top/14.flash_ctrl_tl_errors.4068206683 Apr 28 02:56:05 PM PDT 24 Apr 28 02:56:24 PM PDT 24 421449100 ps
T326 /workspace/coverage/cover_reg_top/30.flash_ctrl_intr_test.1593952359 Apr 28 02:56:35 PM PDT 24 Apr 28 02:56:49 PM PDT 24 22993800 ps
T226 /workspace/coverage/cover_reg_top/13.flash_ctrl_csr_rw.3433005752 Apr 28 02:56:06 PM PDT 24 Apr 28 02:56:23 PM PDT 24 39367700 ps
T231 /workspace/coverage/cover_reg_top/6.flash_ctrl_tl_intg_err.2245425783 Apr 28 02:55:45 PM PDT 24 Apr 28 03:03:27 PM PDT 24 846060100 ps
T329 /workspace/coverage/cover_reg_top/12.flash_ctrl_intr_test.3767946468 Apr 28 02:55:59 PM PDT 24 Apr 28 02:56:13 PM PDT 24 31192800 ps
T328 /workspace/coverage/cover_reg_top/44.flash_ctrl_intr_test.738087425 Apr 28 02:56:37 PM PDT 24 Apr 28 02:56:52 PM PDT 24 43596900 ps
T227 /workspace/coverage/cover_reg_top/17.flash_ctrl_same_csr_outstanding.3260883269 Apr 28 02:56:21 PM PDT 24 Apr 28 02:56:41 PM PDT 24 226229000 ps
T401 /workspace/coverage/cover_reg_top/10.flash_ctrl_csr_rw.2463083230 Apr 28 02:55:56 PM PDT 24 Apr 28 02:56:11 PM PDT 24 53003600 ps
T330 /workspace/coverage/cover_reg_top/5.flash_ctrl_intr_test.3433136477 Apr 28 02:55:46 PM PDT 24 Apr 28 02:56:00 PM PDT 24 27025400 ps
T206 /workspace/coverage/cover_reg_top/15.flash_ctrl_csr_mem_rw_with_rand_reset.3932629899 Apr 28 02:56:16 PM PDT 24 Apr 28 02:56:34 PM PDT 24 132312500 ps
T971 /workspace/coverage/cover_reg_top/2.flash_ctrl_shadow_reg_errors_with_csr_rw.51683307 Apr 28 02:55:40 PM PDT 24 Apr 28 02:55:57 PM PDT 24 22863700 ps
T207 /workspace/coverage/cover_reg_top/10.flash_ctrl_tl_intg_err.3550394959 Apr 28 02:55:54 PM PDT 24 Apr 28 03:10:51 PM PDT 24 355386600 ps
T972 /workspace/coverage/cover_reg_top/3.flash_ctrl_intr_test.1693775822 Apr 28 02:55:43 PM PDT 24 Apr 28 02:55:57 PM PDT 24 52406700 ps
T208 /workspace/coverage/cover_reg_top/12.flash_ctrl_tl_intg_err.3850713893 Apr 28 02:55:59 PM PDT 24 Apr 28 03:08:47 PM PDT 24 2755046000 ps
T973 /workspace/coverage/cover_reg_top/13.flash_ctrl_shadow_reg_errors.4177448809 Apr 28 02:55:58 PM PDT 24 Apr 28 02:56:15 PM PDT 24 15229800 ps
T974 /workspace/coverage/cover_reg_top/16.flash_ctrl_intr_test.641992404 Apr 28 02:56:15 PM PDT 24 Apr 28 02:56:29 PM PDT 24 41606100 ps
T975 /workspace/coverage/cover_reg_top/18.flash_ctrl_shadow_reg_errors_with_csr_rw.3926074583 Apr 28 02:56:26 PM PDT 24 Apr 28 02:56:40 PM PDT 24 42370300 ps
T209 /workspace/coverage/cover_reg_top/7.flash_ctrl_csr_mem_rw_with_rand_reset.3628076592 Apr 28 02:55:51 PM PDT 24 Apr 28 02:56:11 PM PDT 24 204883700 ps
T976 /workspace/coverage/cover_reg_top/15.flash_ctrl_shadow_reg_errors.515946231 Apr 28 02:56:15 PM PDT 24 Apr 28 02:56:32 PM PDT 24 11809500 ps
T977 /workspace/coverage/cover_reg_top/23.flash_ctrl_intr_test.1751486996 Apr 28 02:56:31 PM PDT 24 Apr 28 02:56:44 PM PDT 24 15595500 ps
T978 /workspace/coverage/cover_reg_top/2.flash_ctrl_intr_test.1663447177 Apr 28 02:55:39 PM PDT 24 Apr 28 02:55:54 PM PDT 24 128477800 ps
T979 /workspace/coverage/cover_reg_top/8.flash_ctrl_same_csr_outstanding.4020510201 Apr 28 02:55:49 PM PDT 24 Apr 28 02:56:09 PM PDT 24 374194300 ps
T210 /workspace/coverage/cover_reg_top/19.flash_ctrl_tl_intg_err.3556345557 Apr 28 02:56:27 PM PDT 24 Apr 28 03:11:40 PM PDT 24 3334966500 ps
T980 /workspace/coverage/cover_reg_top/14.flash_ctrl_same_csr_outstanding.1581965182 Apr 28 02:56:09 PM PDT 24 Apr 28 02:56:25 PM PDT 24 567442200 ps
T211 /workspace/coverage/cover_reg_top/3.flash_ctrl_tl_errors.2136881099 Apr 28 02:55:40 PM PDT 24 Apr 28 02:55:57 PM PDT 24 49703900 ps
T212 /workspace/coverage/cover_reg_top/14.flash_ctrl_csr_mem_rw_with_rand_reset.1093526217 Apr 28 02:56:08 PM PDT 24 Apr 28 02:56:26 PM PDT 24 177098500 ps
T981 /workspace/coverage/cover_reg_top/9.flash_ctrl_shadow_reg_errors.884407163 Apr 28 02:55:56 PM PDT 24 Apr 28 02:56:10 PM PDT 24 34615700 ps
T982 /workspace/coverage/cover_reg_top/39.flash_ctrl_intr_test.2295826303 Apr 28 02:56:38 PM PDT 24 Apr 28 02:56:53 PM PDT 24 39544600 ps
T983 /workspace/coverage/cover_reg_top/8.flash_ctrl_csr_mem_rw_with_rand_reset.1475837523 Apr 28 02:55:49 PM PDT 24 Apr 28 02:56:09 PM PDT 24 85860700 ps
T265 /workspace/coverage/cover_reg_top/2.flash_ctrl_tl_errors.3508982007 Apr 28 02:55:33 PM PDT 24 Apr 28 02:55:53 PM PDT 24 905448800 ps
T984 /workspace/coverage/cover_reg_top/0.flash_ctrl_csr_bit_bash.749207382 Apr 28 02:55:29 PM PDT 24 Apr 28 02:56:36 PM PDT 24 2193392000 ps
T985 /workspace/coverage/cover_reg_top/1.flash_ctrl_shadow_reg_errors.1744150048 Apr 28 02:55:29 PM PDT 24 Apr 28 02:55:43 PM PDT 24 17585700 ps
T986 /workspace/coverage/cover_reg_top/3.flash_ctrl_csr_rw.2221541827 Apr 28 02:55:41 PM PDT 24 Apr 28 02:55:58 PM PDT 24 26524200 ps
T342 /workspace/coverage/cover_reg_top/11.flash_ctrl_intr_test.957078654 Apr 28 02:56:00 PM PDT 24 Apr 28 02:56:15 PM PDT 24 16025600 ps
T262 /workspace/coverage/cover_reg_top/10.flash_ctrl_tl_errors.1523256565 Apr 28 02:55:55 PM PDT 24 Apr 28 02:56:12 PM PDT 24 33778200 ps
T305 /workspace/coverage/cover_reg_top/2.flash_ctrl_csr_hw_reset.3067651834 Apr 28 02:55:39 PM PDT 24 Apr 28 02:56:27 PM PDT 24 634961500 ps
T306 /workspace/coverage/cover_reg_top/0.flash_ctrl_csr_aliasing.4139866252 Apr 28 02:55:28 PM PDT 24 Apr 28 02:56:09 PM PDT 24 3265554600 ps
T263 /workspace/coverage/cover_reg_top/15.flash_ctrl_tl_errors.691125138 Apr 28 02:56:15 PM PDT 24 Apr 28 02:56:35 PM PDT 24 297312900 ps
T987 /workspace/coverage/cover_reg_top/27.flash_ctrl_intr_test.228595849 Apr 28 02:56:30 PM PDT 24 Apr 28 02:56:44 PM PDT 24 14965700 ps
T988 /workspace/coverage/cover_reg_top/0.flash_ctrl_shadow_reg_errors_with_csr_rw.3798959107 Apr 28 02:55:29 PM PDT 24 Apr 28 02:55:45 PM PDT 24 106028600 ps
T989 /workspace/coverage/cover_reg_top/4.flash_ctrl_csr_aliasing.1696403855 Apr 28 02:55:44 PM PDT 24 Apr 28 02:56:16 PM PDT 24 409863200 ps
T990 /workspace/coverage/cover_reg_top/6.flash_ctrl_shadow_reg_errors.1517550084 Apr 28 02:55:45 PM PDT 24 Apr 28 02:55:59 PM PDT 24 14167800 ps
T991 /workspace/coverage/cover_reg_top/18.flash_ctrl_same_csr_outstanding.1398944094 Apr 28 02:56:25 PM PDT 24 Apr 28 02:56:45 PM PDT 24 57753100 ps
T992 /workspace/coverage/cover_reg_top/8.flash_ctrl_shadow_reg_errors_with_csr_rw.335723301 Apr 28 02:55:50 PM PDT 24 Apr 28 02:56:04 PM PDT 24 16056000 ps
T993 /workspace/coverage/cover_reg_top/15.flash_ctrl_intr_test.251997442 Apr 28 02:56:15 PM PDT 24 Apr 28 02:56:29 PM PDT 24 35214800 ps
T277 /workspace/coverage/cover_reg_top/17.flash_ctrl_tl_intg_err.3577311333 Apr 28 02:56:19 PM PDT 24 Apr 28 03:11:29 PM PDT 24 774655100 ps
T994 /workspace/coverage/cover_reg_top/41.flash_ctrl_intr_test.1800393869 Apr 28 02:56:35 PM PDT 24 Apr 28 02:56:50 PM PDT 24 16809000 ps
T995 /workspace/coverage/cover_reg_top/13.flash_ctrl_csr_mem_rw_with_rand_reset.1115131081 Apr 28 02:56:05 PM PDT 24 Apr 28 02:56:24 PM PDT 24 41378500 ps
T273 /workspace/coverage/cover_reg_top/4.flash_ctrl_tl_errors.1860261033 Apr 28 02:55:39 PM PDT 24 Apr 28 02:55:56 PM PDT 24 114757200 ps
T307 /workspace/coverage/cover_reg_top/4.flash_ctrl_csr_hw_reset.1779891553 Apr 28 02:55:44 PM PDT 24 Apr 28 02:56:30 PM PDT 24 120614500 ps
T996 /workspace/coverage/cover_reg_top/33.flash_ctrl_intr_test.2381044382 Apr 28 02:56:31 PM PDT 24 Apr 28 02:56:45 PM PDT 24 28771800 ps
T997 /workspace/coverage/cover_reg_top/8.flash_ctrl_shadow_reg_errors.968047434 Apr 28 02:55:49 PM PDT 24 Apr 28 02:56:05 PM PDT 24 16259300 ps
T998 /workspace/coverage/cover_reg_top/3.flash_ctrl_shadow_reg_errors_with_csr_rw.1811980220 Apr 28 02:55:39 PM PDT 24 Apr 28 02:55:53 PM PDT 24 13130100 ps
T999 /workspace/coverage/cover_reg_top/1.flash_ctrl_same_csr_outstanding.3440181269 Apr 28 02:55:34 PM PDT 24 Apr 28 02:55:50 PM PDT 24 180572100 ps
T1000 /workspace/coverage/cover_reg_top/5.flash_ctrl_same_csr_outstanding.2022148598 Apr 28 02:55:49 PM PDT 24 Apr 28 02:56:09 PM PDT 24 347447700 ps
T1001 /workspace/coverage/cover_reg_top/20.flash_ctrl_intr_test.444655442 Apr 28 02:56:33 PM PDT 24 Apr 28 02:56:46 PM PDT 24 31249200 ps
T1002 /workspace/coverage/cover_reg_top/36.flash_ctrl_intr_test.3633029372 Apr 28 02:56:36 PM PDT 24 Apr 28 02:56:50 PM PDT 24 41465000 ps
T1003 /workspace/coverage/cover_reg_top/1.flash_ctrl_csr_aliasing.257177234 Apr 28 02:55:36 PM PDT 24 Apr 28 02:56:10 PM PDT 24 483695100 ps
T1004 /workspace/coverage/cover_reg_top/2.flash_ctrl_shadow_reg_errors.2462494993 Apr 28 02:55:35 PM PDT 24 Apr 28 02:55:49 PM PDT 24 46101100 ps
T1005 /workspace/coverage/cover_reg_top/2.flash_ctrl_mem_walk.2108366334 Apr 28 02:55:39 PM PDT 24 Apr 28 02:55:53 PM PDT 24 24466000 ps
T350 /workspace/coverage/cover_reg_top/2.flash_ctrl_tl_intg_err.1415763629 Apr 28 02:55:34 PM PDT 24 Apr 28 03:08:17 PM PDT 24 710737100 ps
T1006 /workspace/coverage/cover_reg_top/15.flash_ctrl_same_csr_outstanding.2119157352 Apr 28 02:56:16 PM PDT 24 Apr 28 02:56:51 PM PDT 24 58578500 ps
T1007 /workspace/coverage/cover_reg_top/26.flash_ctrl_intr_test.2863061492 Apr 28 02:56:31 PM PDT 24 Apr 28 02:56:45 PM PDT 24 17099400 ps
T1008 /workspace/coverage/cover_reg_top/16.flash_ctrl_shadow_reg_errors_with_csr_rw.392912837 Apr 28 02:56:15 PM PDT 24 Apr 28 02:56:32 PM PDT 24 17242800 ps
T1009 /workspace/coverage/cover_reg_top/21.flash_ctrl_intr_test.2734797232 Apr 28 02:56:32 PM PDT 24 Apr 28 02:56:46 PM PDT 24 150662600 ps
T1010 /workspace/coverage/cover_reg_top/40.flash_ctrl_intr_test.1867702776 Apr 28 02:56:36 PM PDT 24 Apr 28 02:56:50 PM PDT 24 74150800 ps
T1011 /workspace/coverage/cover_reg_top/19.flash_ctrl_same_csr_outstanding.504726923 Apr 28 02:56:26 PM PDT 24 Apr 28 02:56:42 PM PDT 24 338417800 ps
T343 /workspace/coverage/cover_reg_top/9.flash_ctrl_tl_errors.3454152734 Apr 28 02:55:55 PM PDT 24 Apr 28 02:56:12 PM PDT 24 38819600 ps
T1012 /workspace/coverage/cover_reg_top/11.flash_ctrl_shadow_reg_errors_with_csr_rw.392170732 Apr 28 02:55:59 PM PDT 24 Apr 28 02:56:13 PM PDT 24 12213000 ps
T310 /workspace/coverage/cover_reg_top/17.flash_ctrl_csr_mem_rw_with_rand_reset.1258181879 Apr 28 02:56:19 PM PDT 24 Apr 28 02:56:37 PM PDT 24 443965000 ps
T1013 /workspace/coverage/cover_reg_top/19.flash_ctrl_csr_mem_rw_with_rand_reset.3378567616 Apr 28 02:56:28 PM PDT 24 Apr 28 02:56:44 PM PDT 24 317499800 ps
T1014 /workspace/coverage/cover_reg_top/29.flash_ctrl_intr_test.1131857774 Apr 28 02:56:35 PM PDT 24 Apr 28 02:56:49 PM PDT 24 22250400 ps
T1015 /workspace/coverage/cover_reg_top/25.flash_ctrl_intr_test.2372146446 Apr 28 02:56:30 PM PDT 24 Apr 28 02:56:45 PM PDT 24 42206700 ps
T1016 /workspace/coverage/cover_reg_top/0.flash_ctrl_shadow_reg_errors.1772683108 Apr 28 02:55:24 PM PDT 24 Apr 28 02:55:41 PM PDT 24 15119300 ps
T1017 /workspace/coverage/cover_reg_top/43.flash_ctrl_intr_test.1427810693 Apr 28 02:56:37 PM PDT 24 Apr 28 02:56:51 PM PDT 24 33287400 ps
T1018 /workspace/coverage/cover_reg_top/1.flash_ctrl_csr_rw.2453714748 Apr 28 02:55:35 PM PDT 24 Apr 28 02:55:51 PM PDT 24 21116800 ps
T308 /workspace/coverage/cover_reg_top/0.flash_ctrl_same_csr_outstanding.1172524907 Apr 28 02:55:30 PM PDT 24 Apr 28 02:55:49 PM PDT 24 111399200 ps
T355 /workspace/coverage/cover_reg_top/3.flash_ctrl_tl_intg_err.1361772126 Apr 28 02:55:40 PM PDT 24 Apr 28 03:10:50 PM PDT 24 719020500 ps
T272 /workspace/coverage/cover_reg_top/18.flash_ctrl_tl_errors.2922770084 Apr 28 02:56:21 PM PDT 24 Apr 28 02:56:40 PM PDT 24 230609400 ps
T1019 /workspace/coverage/cover_reg_top/48.flash_ctrl_intr_test.2324627894 Apr 28 02:56:38 PM PDT 24 Apr 28 02:56:52 PM PDT 24 152277100 ps
T309 /workspace/coverage/cover_reg_top/4.flash_ctrl_tl_intg_err.3315076584 Apr 28 02:55:49 PM PDT 24 Apr 28 03:10:52 PM PDT 24 1542546700 ps
T275 /workspace/coverage/cover_reg_top/17.flash_ctrl_tl_errors.2904772744 Apr 28 02:56:20 PM PDT 24 Apr 28 02:56:39 PM PDT 24 100156200 ps
T1020 /workspace/coverage/cover_reg_top/9.flash_ctrl_csr_rw.1103997069 Apr 28 02:55:54 PM PDT 24 Apr 28 02:56:10 PM PDT 24 106971500 ps
T1021 /workspace/coverage/cover_reg_top/8.flash_ctrl_intr_test.1871129840 Apr 28 02:55:48 PM PDT 24 Apr 28 02:56:02 PM PDT 24 18223000 ps
T215 /workspace/coverage/cover_reg_top/3.flash_ctrl_mem_partial_access.1050213503 Apr 28 02:55:39 PM PDT 24 Apr 28 02:55:53 PM PDT 24 30538300 ps
T279 /workspace/coverage/cover_reg_top/0.flash_ctrl_tl_errors.2373193696 Apr 28 02:55:26 PM PDT 24 Apr 28 02:55:45 PM PDT 24 95259100 ps
T1022 /workspace/coverage/cover_reg_top/18.flash_ctrl_intr_test.3958589114 Apr 28 02:56:26 PM PDT 24 Apr 28 02:56:40 PM PDT 24 43989200 ps
T1023 /workspace/coverage/cover_reg_top/17.flash_ctrl_shadow_reg_errors.2999658443 Apr 28 02:56:20 PM PDT 24 Apr 28 02:56:37 PM PDT 24 34258100 ps
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