FLASH_CTRL Simulation Results

Friday December 03 2021 07:00:05 UTC

GitHub Revision: 4e9df5489

Branch: master

Testplan

Simulator: VCS

Test Results

Milestone Name Tests Passing Total Pass Rate
V1 smoke flash_ctrl_smoke 5 5 100.00
V1 smoke_hw_rd smoke_hw_rd 0 0 --
V1 csr_hw_reset flash_ctrl_csr_hw_reset 5 5 100.00
V1 csr_rw flash_ctrl_csr_rw 20 20 100.00
V1 csr_bit_bash flash_ctrl_csr_bit_bash 5 5 100.00
V1 csr_aliasing flash_ctrl_csr_aliasing 5 5 100.00
V1 csr_mem_rw_with_rand_reset flash_ctrl_csr_mem_rw_with_rand_reset 20 20 100.00
V1 mem_walk flash_ctrl_mem_walk 5 5 100.00
V1 mem_partial_access flash_ctrl_mem_partial_access 5 5 100.00
V1 shadow_reg_update_error flash_ctrl_shadow_reg_errors 20 20 100.00
V1 shadow_reg_read_clear_staged_value flash_ctrl_shadow_reg_errors 20 20 100.00
V1 shadow_reg_storage_error flash_ctrl_shadow_reg_errors 20 20 100.00
V1 shadowed_reset_glitch flash_ctrl_shadow_reg_errors 20 20 100.00
V1 shadow_reg_update_error_with_csr_rw flash_ctrl_shadow_reg_errors_with_csr_rw 18 20 90.00
V1 TOTAL 108 110 98.18
V2 sw_op sw_op 0 0 --
V2 host_read_direct host_read_direct 0 0 --
V2 host_ctrl_hw_if host_ctrl_hw_if 0 0 --
V2 host_controller_arb host_controller_arb 0 0 --
V2 erase_suspend erase_suspend 0 0 --
V2 full_memory_access full_memory_access 0 0 --
V2 fifo_eviction fifo_eviction 0 0 --
V2 host_arb host_arb 0 0 --
V2 host_interleave host_interleave 0 0 --
V2 memory_protection memory_protection 0 0 --
V2 all_partitions flash_ctrl_rand_ops 50 50 100.00
V2 error_oob error_oob 0 0 --
V2 error_mp error_mp 0 0 --
V2 error_rd error_rd 0 0 --
V2 error_prog_win error_prog_win 0 0 --
V2 error_prog_type error_prog_type 0 0 --
V2 error_flash_phy error_flash_phy 0 0 --
V2 error_lc error_lc 0 0 --
V2 secret_partition secret_partition 0 0 --
V2 isolation_partition isolation_partition 0 0 --
V2 interrupts interrupts 0 0 --
V2 ecc ecc 0 0 --
V2 alert_test flash_ctrl_alert_test 50 50 100.00
V2 intr_test flash_ctrl_intr_test 50 50 100.00
V2 tl_d_oob_addr_access flash_ctrl_tl_errors 20 20 100.00
V2 tl_d_illegal_access flash_ctrl_tl_errors 20 20 100.00
V2 tl_d_outstanding_access flash_ctrl_csr_hw_reset 5 5 100.00
flash_ctrl_csr_rw 20 20 100.00
flash_ctrl_csr_aliasing 5 5 100.00
flash_ctrl_same_csr_outstanding 20 20 100.00
V2 tl_d_partial_access flash_ctrl_csr_hw_reset 5 5 100.00
flash_ctrl_csr_rw 20 20 100.00
flash_ctrl_csr_aliasing 5 5 100.00
flash_ctrl_same_csr_outstanding 20 20 100.00
V2 TOTAL 190 190 100.00
V2S tl_intg_err flash_ctrl_tl_intg_err 0 20 0.00
V2S TOTAL 0 20 0.00
V3 scramble scramble 0 0 --
V3 robustness robustness 0 0 --
V3 stress_all_with_rand_reset flash_ctrl_stress_all_with_rand_reset 0 50 0.00
V3 TOTAL 0 50 0.00
Unmapped tests flash_ctrl_stress_all 0 50 0.00
TOTAL 298 420 70.95

Testplan Progress

Items Total Written Passing Progress
N.A. 1 1 0 0.00
V1 11 10 9 81.82
V2 26 5 5 19.23
V2S 1 1 0 0.00
V3 3 1 0 0.00

Coverage Results

Coverage Dashboard

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP
65.14 96.74 89.98 16.99 34.84 94.77 86.01 36.64

Failure Buckets

Past Results