60490355a60490355a| Milestone | Name | Tests | Passing | Total | Pass Rate |
|---|---|---|---|---|---|
| V1 | smoke | flash_ctrl_smoke | 50 | 50 | 100.00 |
| V1 | smoke_hw | flash_ctrl_smoke_hw | 50 | 50 | 100.00 |
| V1 | csr_hw_reset | flash_ctrl_csr_hw_reset | 5 | 5 | 100.00 |
| V1 | csr_rw | flash_ctrl_csr_rw | 20 | 20 | 100.00 |
| V1 | csr_bit_bash | flash_ctrl_csr_bit_bash | 5 | 5 | 100.00 |
| V1 | csr_aliasing | flash_ctrl_csr_aliasing | 5 | 5 | 100.00 |
| V1 | csr_mem_rw_with_rand_reset | flash_ctrl_csr_mem_rw_with_rand_reset | 20 | 20 | 100.00 |
| V1 | regwen_csr_and_corresponding_lockable_csr | flash_ctrl_csr_rw | 20 | 20 | 100.00 |
| flash_ctrl_csr_aliasing | 5 | 5 | 100.00 | ||
| V1 | mem_walk | flash_ctrl_mem_walk | 5 | 5 | 100.00 |
| V1 | mem_partial_access | flash_ctrl_mem_partial_access | 5 | 5 | 100.00 |
| V1 | TOTAL | 165 | 165 | 100.00 | |
| V2 | sw_op | flash_ctrl_sw_op | 5 | 5 | 100.00 |
| V2 | host_read_direct | flash_ctrl_host_dir_rd | 5 | 5 | 100.00 |
| V2 | rma_hw_if | flash_ctrl_hw_rma | 3 | 3 | 100.00 |
| V2 | host_controller_arb | flash_ctrl_host_ctrl_arb | 0 | 5 | 0.00 |
| V2 | erase_suspend | flash_ctrl_erase_suspend | 5 | 5 | 100.00 |
| V2 | full_memory_access | flash_ctrl_full_mem_access | 5 | 5 | 100.00 |
| V2 | rd_buff_eviction | flash_ctrl_rd_buff_evict | 5 | 5 | 100.00 |
| V2 | host_arb | flash_ctrl_phy_arb | 19 | 20 | 95.00 |
| V2 | host_interleave | flash_ctrl_phy_arb | 19 | 20 | 95.00 |
| V2 | memory_protection | flash_ctrl_mp_regions | 8 | 8 | 100.00 |
| V2 | fetch_code | flash_ctrl_fetch_code | 5 | 5 | 100.00 |
| V2 | all_partitions | flash_ctrl_rand_ops | 3 | 5 | 60.00 |
| V2 | error_mp | flash_ctrl_error_mp | 0 | 10 | 0.00 |
| V2 | error_prog_win | flash_ctrl_error_prog_win | 0 | 10 | 0.00 |
| V2 | error_prog_type | flash_ctrl_error_prog_type | 0 | 5 | 0.00 |
| V2 | secret_partition | flash_ctrl_hw_sec_otp | 5 | 5 | 100.00 |
| V2 | isolation_partition | flash_ctrl_hw_rma | 3 | 3 | 100.00 |
| V2 | interrupts | interrupts | 0 | 0 | -- |
| V2 | alert_test | flash_ctrl_alert_test | 50 | 50 | 100.00 |
| V2 | intr_test | flash_ctrl_intr_test | 50 | 50 | 100.00 |
| V2 | tl_d_oob_addr_access | flash_ctrl_tl_errors | 20 | 20 | 100.00 |
| V2 | tl_d_illegal_access | flash_ctrl_tl_errors | 20 | 20 | 100.00 |
| V2 | tl_d_outstanding_access | flash_ctrl_csr_hw_reset | 5 | 5 | 100.00 |
| flash_ctrl_csr_rw | 20 | 20 | 100.00 | ||
| flash_ctrl_csr_aliasing | 5 | 5 | 100.00 | ||
| flash_ctrl_same_csr_outstanding | 20 | 20 | 100.00 | ||
| V2 | tl_d_partial_access | flash_ctrl_csr_hw_reset | 5 | 5 | 100.00 |
| flash_ctrl_csr_rw | 20 | 20 | 100.00 | ||
| flash_ctrl_csr_aliasing | 5 | 5 | 100.00 | ||
| flash_ctrl_same_csr_outstanding | 20 | 20 | 100.00 | ||
| V2 | TOTAL | 208 | 241 | 86.31 | |
| V2S | error_rd | error_rd | 0 | 0 | -- |
| V2S | error_flash_phy | error_flash_phy | 0 | 0 | -- |
| V2S | error_lc | error_lc | 0 | 0 | -- |
| V2S | ecc | ecc | 0 | 0 | -- |
| V2S | scramble | scramble | 0 | 0 | -- |
| V2S | shadow_reg_update_error | flash_ctrl_shadow_reg_errors | 20 | 20 | 100.00 |
| V2S | shadow_reg_read_clear_staged_value | flash_ctrl_shadow_reg_errors | 20 | 20 | 100.00 |
| V2S | shadow_reg_storage_error | flash_ctrl_shadow_reg_errors | 20 | 20 | 100.00 |
| V2S | shadowed_reset_glitch | flash_ctrl_shadow_reg_errors | 20 | 20 | 100.00 |
| V2S | shadow_reg_update_error_with_csr_rw | flash_ctrl_shadow_reg_errors_with_csr_rw | 20 | 20 | 100.00 |
| V2S | tl_intg_err | flash_ctrl_tl_intg_err | 0 | 20 | 0.00 |
| V2S | sec_cm_reg_bus_integrity | sec_cm_reg_bus_integrity | 0 | 0 | -- |
| V2S | sec_cm_host_bus_integrity | sec_cm_host_bus_integrity | 0 | 0 | -- |
| V2S | sec_cm_mem_bus_integrity | sec_cm_mem_bus_integrity | 0 | 0 | -- |
| V2S | sec_cm_scramble_key_sideload | sec_cm_scramble_key_sideload | 0 | 0 | -- |
| V2S | sec_cm_lc_ctrl_intersig_mubi | sec_cm_lc_ctrl_intersig_mubi | 0 | 0 | -- |
| V2S | sec_cm_ctrl_config_regwen | sec_cm_ctrl_config_regwen | 0 | 0 | -- |
| V2S | sec_cm_data_regions_config_regwen | sec_cm_data_regions_config_regwen | 0 | 0 | -- |
| V2S | sec_cm_data_regions_config_shadow | sec_cm_data_regions_config_shadow | 0 | 0 | -- |
| V2S | sec_cm_info_regions_config_regwen | sec_cm_info_regions_config_regwen | 0 | 0 | -- |
| V2S | sec_cm_info_regions_config_shadow | sec_cm_info_regions_config_shadow | 0 | 0 | -- |
| V2S | sec_cm_bank_config_regwen | sec_cm_bank_config_regwen | 0 | 0 | -- |
| V2S | sec_cm_bank_config_shadow | sec_cm_bank_config_shadow | 0 | 0 | -- |
| V2S | sec_cm_mem_ctrl_global_esc | sec_cm_mem_ctrl_global_esc | 0 | 0 | -- |
| V2S | sec_cm_mem_ctrl_local_esc | sec_cm_mem_ctrl_local_esc | 0 | 0 | -- |
| V2S | sec_cm_mem_disable_config_mubi | sec_cm_mem_disable_config_mubi | 0 | 0 | -- |
| V2S | sec_cm_exec_config_redun | sec_cm_exec_config_redun | 0 | 0 | -- |
| V2S | sec_cm_mem_scramble | sec_cm_mem_scramble | 0 | 0 | -- |
| V2S | sec_cm_mem_integrity | sec_cm_mem_integrity | 0 | 0 | -- |
| V2S | sec_cm_rma_entry_mem_sec_wipe | sec_cm_rma_entry_mem_sec_wipe | 0 | 0 | -- |
| V2S | sec_cm_ctrl_fsm_sparse | sec_cm_ctrl_fsm_sparse | 0 | 0 | -- |
| V2S | sec_cm_phy_fsm_sparse | sec_cm_phy_fsm_sparse | 0 | 0 | -- |
| V2S | sec_cm_phy_prog_fsm_sparse | sec_cm_phy_prog_fsm_sparse | 0 | 0 | -- |
| V2S | sec_cm_ctr_redun | sec_cm_ctr_redun | 0 | 0 | -- |
| V2S | sec_cm_phy_arbiter_ctrl_redun | sec_cm_phy_arbiter_ctrl_redun | 0 | 0 | -- |
| V2S | sec_cm_phy_host_grant_ctrl_consistency | sec_cm_phy_host_grant_ctrl_consistency | 0 | 0 | -- |
| V2S | sec_cm_phy_ack_ctrl_consistency | sec_cm_phy_ack_ctrl_consistency | 0 | 0 | -- |
| V2S | TOTAL | 40 | 60 | 66.67 | |
| V3 | robustness | robustness | 0 | 0 | -- |
| V3 | stress_all_with_rand_reset | flash_ctrl_stress_all_with_rand_reset | 0 | 50 | 0.00 |
| V3 | TOTAL | 0 | 50 | 0.00 | |
| Unmapped tests | flash_ctrl_stress_all | 0 | 50 | 0.00 | |
| TOTAL | 413 | 566 | 72.97 |
| Items | Total | Written | Passing | Progress |
|---|---|---|---|---|
| N.A. | 1 | 1 | 0 | 0.00 |
| V1 | 9 | 9 | 9 | 100.00 |
| V2 | 20 | 19 | 13 | 65.00 |
| V2S | 34 | 3 | 2 | 5.88 |
| V3 | 2 | 1 | 0 | 0.00 |
| Score | Block | Branch | Statement | Expression | Toggle | Fsm | Assertion | CoverGroup |
|---|---|---|---|---|---|---|---|---|
| 88.83 | 95.23 | 90.52 | 96.33 | 79.61 | 87.98 | 67.84 | 74.19 | 58.40 |
UVM_WARNING [BDTYP] Cannot create an object of type 'flash_ctrl_stress_all_vseq' because it is not registered with the factory. has 100 failures:
0.flash_ctrl_stress_all.1985419912
Line 79, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-xcelium/0.flash_ctrl_stress_all/out/run.log
UVM_WARNING @ 0 ps: [BDTYP] Cannot create an object of type 'flash_ctrl_stress_all_vseq' because it is not registered with the factory.
UVM_INFO @ 0 ps: (uvm_factory.svh:1645) [UVM/FACTORY/PRINT]
#### Factory Configuration (*)
No instance overrides are registered with this factory
1.flash_ctrl_stress_all.2257296623
Line 79, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-xcelium/1.flash_ctrl_stress_all/out/run.log
UVM_WARNING @ 0 ps: [BDTYP] Cannot create an object of type 'flash_ctrl_stress_all_vseq' because it is not registered with the factory.
UVM_INFO @ 0 ps: (uvm_factory.svh:1645) [UVM/FACTORY/PRINT]
#### Factory Configuration (*)
No instance overrides are registered with this factory
... and 48 more failures.
0.flash_ctrl_stress_all_with_rand_reset.653573566
Line 91, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-xcelium/0.flash_ctrl_stress_all_with_rand_reset/out/run.log
UVM_WARNING @ 6812065 ps: [BDTYP] Cannot create an object of type 'flash_ctrl_stress_all_vseq' because it is not registered with the factory.
UVM_INFO @ 6812065 ps: (uvm_factory.svh:1645) [UVM/FACTORY/PRINT]
#### Factory Configuration (*)
No instance overrides are registered with this factory
1.flash_ctrl_stress_all_with_rand_reset.3421561921
Line 91, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-xcelium/1.flash_ctrl_stress_all_with_rand_reset/out/run.log
UVM_WARNING @ 7682711 ps: [BDTYP] Cannot create an object of type 'flash_ctrl_stress_all_vseq' because it is not registered with the factory.
UVM_INFO @ 7682711 ps: (uvm_factory.svh:1645) [UVM/FACTORY/PRINT]
#### Factory Configuration (*)
No instance overrides are registered with this factory
... and 48 more failures.
UVM_FATAL (dv_utils_pkg.sv:147) [flash_ctrl_common_vseq] Timeout waiting tl_access : addr=* has 20 failures:
0.flash_ctrl_tl_intg_err.244637557
Line 105, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-xcelium/0.flash_ctrl_tl_intg_err/out/run.log
UVM_FATAL @ 10005453219 ps: (dv_utils_pkg.sv:147) [uvm_test_top.env.virtual_sequencer.flash_ctrl_common_vseq] Timeout waiting tl_access : addr=0xe373db12
UVM_INFO @ 10005453219 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
1.flash_ctrl_tl_intg_err.4173620667
Line 102, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-xcelium/1.flash_ctrl_tl_intg_err/out/run.log
UVM_FATAL @ 10002701287 ps: (dv_utils_pkg.sv:147) [uvm_test_top.env.virtual_sequencer.flash_ctrl_common_vseq] Timeout waiting tl_access : addr=0xa16aa329
UVM_INFO @ 10002701287 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 18 more failures.