GPIO Simulation Results

Wednesday May 18 2022 08:08:47 UTC

GitHub Revision: d498f91d6
Foundry Revision: d498f91d6

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 1087921459

Test Results

Milestone Name Tests Passing Total Pass Rate
V1 smoke gpio_smoke 50 50 100.00
gpio_smoke_no_pullup_pulldown 50 50 100.00
V1 csr_hw_reset gpio_csr_hw_reset 5 5 100.00
V1 csr_rw gpio_csr_rw 20 20 100.00
V1 csr_bit_bash gpio_csr_bit_bash 5 5 100.00
V1 csr_aliasing gpio_csr_aliasing 5 5 100.00
V1 csr_mem_rw_with_rand_reset gpio_csr_mem_rw_with_rand_reset 20 20 100.00
V1 regwen_csr_and_corresponding_lockable_csr gpio_csr_rw 20 20 100.00
gpio_csr_aliasing 5 5 100.00
V1 TOTAL 155 155 100.00
V2 direct_and_masked_out gpio_random_dout_din 48 50 96.00
gpio_random_dout_din_no_pullup_pulldown 48 50 96.00
V2 out_in_regs_read_write gpio_dout_din_regs_random_rw 47 50 94.00
V2 gpio_interrupt_programming gpio_intr_rand_pgm 49 50 98.00
V2 random_interrupt_trigger gpio_rand_intr_trigger 50 50 100.00
V2 interrupt_and_noise_filter gpio_intr_with_filter_rand_intr_event 50 50 100.00
V2 noise_filter_stress gpio_filter_stress 50 50 100.00
V2 regs_long_reads_and_writes gpio_random_long_reg_writes_reg_reads 49 50 98.00
V2 full_random gpio_full_random 50 50 100.00
V2 stress_all gpio_stress_all 50 50 100.00
V2 alert_test gpio_alert_test 50 50 100.00
V2 intr_test gpio_intr_test 49 50 98.00
V2 tl_d_oob_addr_access gpio_tl_errors 20 20 100.00
V2 tl_d_illegal_access gpio_tl_errors 20 20 100.00
V2 tl_d_outstanding_access gpio_csr_rw 20 20 100.00
gpio_same_csr_outstanding 20 20 100.00
gpio_csr_aliasing 5 5 100.00
gpio_csr_hw_reset 5 5 100.00
V2 tl_d_partial_access gpio_csr_rw 20 20 100.00
gpio_same_csr_outstanding 20 20 100.00
gpio_csr_aliasing 5 5 100.00
gpio_csr_hw_reset 5 5 100.00
V2 TOTAL 630 640 98.44
V2S tl_intg_err gpio_tl_intg_err 20 20 100.00
V2S sec_cm_bus_integrity sec_cm_bus_integrity 0 0 --
V2S TOTAL 20 20 100.00
V3 stress_all_with_rand_reset gpio_stress_all_with_rand_reset 48 50 96.00
V3 TOTAL 48 50 96.00
TOTAL 853 865 98.61

Testplan Progress

Items Total Written Passing Progress
V1 7 7 7 100.00
V2 14 14 8 57.14
V2S 2 1 1 50.00
V3 1 1 0 0.00

Coverage Results

Coverage Dashboard

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP
97.68 99.61 87.47 100.00 -- 100.00 99.04 99.99

Failure Buckets

Past Results