26b0ee226
Stage | Name | Tests | Max Job Runtime | Simulated Time | Passing | Total | Pass Rate |
---|---|---|---|---|---|---|---|
V1 | smoke | gpio_smoke | 1.550s | 84.659us | 50 | 50 | 100.00 |
gpio_smoke_no_pullup_pulldown | 1.530s | 96.448us | 50 | 50 | 100.00 | ||
V1 | csr_hw_reset | gpio_csr_hw_reset | 0.630s | 16.829us | 5 | 5 | 100.00 |
V1 | csr_rw | gpio_csr_rw | 0.690s | 24.937us | 20 | 20 | 100.00 |
V1 | csr_bit_bash | gpio_csr_bit_bash | 3.220s | 801.535us | 5 | 5 | 100.00 |
V1 | csr_aliasing | gpio_csr_aliasing | 0.810s | 71.100us | 5 | 5 | 100.00 |
V1 | csr_mem_rw_with_rand_reset | gpio_csr_mem_rw_with_rand_reset | 1.600s | 121.750us | 20 | 20 | 100.00 |
V1 | regwen_csr_and_corresponding_lockable_csr | gpio_csr_rw | 0.690s | 24.937us | 20 | 20 | 100.00 |
gpio_csr_aliasing | 0.810s | 71.100us | 5 | 5 | 100.00 | ||
V1 | TOTAL | 155 | 155 | 100.00 | |||
V2 | direct_and_masked_out | gpio_random_dout_din | 1.390s | 62.462us | 50 | 50 | 100.00 |
gpio_random_dout_din_no_pullup_pulldown | 1.480s | 234.102us | 50 | 50 | 100.00 | ||
V2 | out_in_regs_read_write | gpio_dout_din_regs_random_rw | 0.990s | 189.374us | 50 | 50 | 100.00 |
V2 | gpio_interrupt_programming | gpio_intr_rand_pgm | 1.490s | 90.572us | 50 | 50 | 100.00 |
V2 | random_interrupt_trigger | gpio_rand_intr_trigger | 3.720s | 107.919us | 50 | 50 | 100.00 |
V2 | interrupt_and_noise_filter | gpio_intr_with_filter_rand_intr_event | 4.170s | 92.222us | 50 | 50 | 100.00 |
V2 | noise_filter_stress | gpio_filter_stress | 29.570s | 1.046ms | 50 | 50 | 100.00 |
V2 | regs_long_reads_and_writes | gpio_random_long_reg_writes_reg_reads | 6.660s | 2.270ms | 50 | 50 | 100.00 |
V2 | full_random | gpio_full_random | 1.220s | 377.391us | 50 | 50 | 100.00 |
V2 | stress_all | gpio_stress_all | 4.064m | 40.466ms | 50 | 50 | 100.00 |
V2 | alert_test | gpio_alert_test | 0.680s | 13.179us | 50 | 50 | 100.00 |
V2 | intr_test | gpio_intr_test | 0.640s | 11.333us | 22 | 50 | 44.00 |
V2 | tl_d_oob_addr_access | gpio_tl_errors | 2.700s | 127.532us | 20 | 20 | 100.00 |
V2 | tl_d_illegal_access | gpio_tl_errors | 2.700s | 127.532us | 20 | 20 | 100.00 |
V2 | tl_d_outstanding_access | gpio_csr_rw | 0.690s | 24.937us | 20 | 20 | 100.00 |
gpio_same_csr_outstanding | 0.870s | 20.573us | 20 | 20 | 100.00 | ||
gpio_csr_aliasing | 0.810s | 71.100us | 5 | 5 | 100.00 | ||
gpio_csr_hw_reset | 0.630s | 16.829us | 5 | 5 | 100.00 | ||
V2 | tl_d_partial_access | gpio_csr_rw | 0.690s | 24.937us | 20 | 20 | 100.00 |
gpio_same_csr_outstanding | 0.870s | 20.573us | 20 | 20 | 100.00 | ||
gpio_csr_aliasing | 0.810s | 71.100us | 5 | 5 | 100.00 | ||
gpio_csr_hw_reset | 0.630s | 16.829us | 5 | 5 | 100.00 | ||
V2 | TOTAL | 612 | 640 | 95.62 | |||
V2S | tl_intg_err | gpio_tl_intg_err | 1.480s | 853.725us | 20 | 20 | 100.00 |
gpio_sec_cm | 1.020s | 323.270us | 5 | 5 | 100.00 | ||
V2S | sec_cm_bus_integrity | gpio_tl_intg_err | 1.480s | 853.725us | 20 | 20 | 100.00 |
V2S | TOTAL | 25 | 25 | 100.00 | |||
V3 | stress_all_with_rand_reset | gpio_stress_all_with_rand_reset | 36.155m | 91.078ms | 50 | 50 | 100.00 |
V3 | TOTAL | 50 | 50 | 100.00 | |||
TOTAL | 842 | 870 | 96.78 |
Items | Total | Written | Passing | Progress |
---|---|---|---|---|
V1 | 7 | 7 | 7 | 100.00 |
V2 | 14 | 14 | 13 | 92.86 |
V2S | 2 | 2 | 2 | 100.00 |
V3 | 1 | 1 | 1 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | GROUP |
---|---|---|---|---|---|---|---|
99.61 | 99.07 | 99.10 | 100.00 | -- | 99.80 | 99.68 | 100.00 |
UVM_ERROR (cip_base_vseq.sv:455) [gpio_common_vseq] Check failed exp_val == act_val (* [*] vs * [*]) when reading the intr CSRgpio_reg_block.intr_state
has 28 failures:
0.gpio_intr_test.3168843143
Line 217, in log /container/opentitan-public/scratch/os_regression/gpio-sim-vcs/0.gpio_intr_test/latest/run.log
UVM_ERROR @ 1135814 ps: (cip_base_vseq.sv:455) [uvm_test_top.env.virtual_sequencer.gpio_common_vseq] Check failed exp_val == act_val (0 [0x0] vs 576012652 [0x2255416c]) when reading the intr CSRgpio_reg_block.intr_state
UVM_INFO @ 1135814 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
2.gpio_intr_test.3905434028
Line 217, in log /container/opentitan-public/scratch/os_regression/gpio-sim-vcs/2.gpio_intr_test/latest/run.log
UVM_ERROR @ 23316892 ps: (cip_base_vseq.sv:455) [uvm_test_top.env.virtual_sequencer.gpio_common_vseq] Check failed exp_val == act_val (0 [0x0] vs 4290897002 [0xffc1e46a]) when reading the intr CSRgpio_reg_block.intr_state
UVM_INFO @ 23316892 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 26 more failures.