GPIO Simulation Results

Thursday May 25 2023 07:02:34 UTC

GitHub Revision: `94eb0df12`

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 77475240

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	gpio_smoke	1.530s	486.626us	50	50	100.00
		gpio_smoke_no_pullup_pulldown	1.510s	344.835us	50	50	100.00
V1	csr_hw_reset	gpio_csr_hw_reset	0.660s	31.011us	5	5	100.00
V1	csr_rw	gpio_csr_rw	0.660s	47.189us	20	20	100.00
V1	csr_bit_bash	gpio_csr_bit_bash	2.840s	686.951us	5	5	100.00
V1	csr_aliasing	gpio_csr_aliasing	0.760s	49.122us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	gpio_csr_mem_rw_with_rand_reset	1.750s	35.198us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	gpio_csr_rw	0.660s	47.189us	20	20	100.00
		gpio_csr_aliasing	0.760s	49.122us	5	5	100.00
V1		TOTAL			155	155	100.00
V2	direct_and_masked_out	gpio_random_dout_din	1.330s	75.408us	50	50	100.00
		gpio_random_dout_din_no_pullup_pulldown	1.450s	67.063us	50	50	100.00
V2	out_in_regs_read_write	gpio_dout_din_regs_random_rw	0.960s	46.000us	50	50	100.00
V2	gpio_interrupt_programming	gpio_intr_rand_pgm	1.390s	186.012us	50	50	100.00
V2	random_interrupt_trigger	gpio_rand_intr_trigger	3.490s	485.603us	50	50	100.00
V2	interrupt_and_noise_filter	gpio_intr_with_filter_rand_intr_event	3.620s	182.694us	50	50	100.00
V2	noise_filter_stress	gpio_filter_stress	28.000s	2.131ms	50	50	100.00
V2	regs_long_reads_and_writes	gpio_random_long_reg_writes_reg_reads	6.020s	154.953us	50	50	100.00
V2	full_random	gpio_full_random	1.080s	62.273us	50	50	100.00
V2	stress_all	gpio_stress_all	3.353m	71.391ms	50	50	100.00
V2	alert_test	gpio_alert_test	0.710s	14.578us	50	50	100.00
V2	intr_test	gpio_intr_test	0.700s	69.354us	21	50	42.00
V2	tl_d_oob_addr_access	gpio_tl_errors	3.430s	769.601us	20	20	100.00
V2	tl_d_illegal_access	gpio_tl_errors	3.430s	769.601us	20	20	100.00
V2	tl_d_outstanding_access	gpio_csr_rw	0.660s	47.189us	20	20	100.00
		gpio_same_csr_outstanding	0.870s	38.402us	20	20	100.00
		gpio_csr_aliasing	0.760s	49.122us	5	5	100.00
		gpio_csr_hw_reset	0.660s	31.011us	5	5	100.00
V2	tl_d_partial_access	gpio_csr_rw	0.660s	47.189us	20	20	100.00
		gpio_same_csr_outstanding	0.870s	38.402us	20	20	100.00
		gpio_csr_aliasing	0.760s	49.122us	5	5	100.00
		gpio_csr_hw_reset	0.660s	31.011us	5	5	100.00
V2		TOTAL			611	640	95.47
V2S	tl_intg_err	gpio_tl_intg_err	1.510s	133.058us	20	20	100.00
		gpio_sec_cm	0.970s	77.923us	5	5	100.00
V2S	sec_cm_bus_integrity	gpio_tl_intg_err	1.510s	133.058us	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	stress_all_with_rand_reset	gpio_stress_all_with_rand_reset	34.132m	105.107ms	50	50	100.00
V3		TOTAL			50	50	100.00
		TOTAL			841	870	96.67

Testplan Progress

Items	Total	Written	Passing	Progress
V1	7	7	7	100.00
V2	14	14	13	92.86
V2S	2	2	2	100.00
V3	1	1	1	100.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
99.61	99.07	99.10	100.00	--	99.80	99.68	100.00

Failure Buckets

UVM_ERROR (cip_base_vseq.sv:455) [gpio_common_vseq] Check failed exp_val == act_val (* [*] vs * [*]) when reading the intr CSRgpio_reg_block.intr_state

has 29 failures:

Test gpio_intr_test has 29 failures.

0.gpio_intr_test.776235906
Line 222, in log /container/opentitan-public/scratch/os_regression/gpio-sim-vcs/0.gpio_intr_test/latest/run.log

  UVM_ERROR @   3896796 ps: (cip_base_vseq.sv:455) [uvm_test_top.env.virtual_sequencer.gpio_common_vseq] Check failed exp_val == act_val (1 [0x1] vs 4252921527 [0xfd7e6eb7]) when reading the intr CSRgpio_reg_block.intr_state
  UVM_INFO @   3896796 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

1.gpio_intr_test.1053830565
Line 218, in log /container/opentitan-public/scratch/os_regression/gpio-sim-vcs/1.gpio_intr_test/latest/run.log

  UVM_ERROR @   8574153 ps: (cip_base_vseq.sv:455) [uvm_test_top.env.virtual_sequencer.gpio_common_vseq] Check failed exp_val == act_val (1 [0x1] vs 3463526775 [0xce713977]) when reading the intr CSRgpio_reg_block.intr_state
  UVM_INFO @   8574153 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 27 more failures.