GPIO Simulation Results

Saturday May 27 2023 07:02:22 UTC

GitHub Revision: `c06cc3921`

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 2359737659

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	gpio_smoke	1.430s	286.042us	50	50	100.00
		gpio_smoke_no_pullup_pulldown	1.460s	416.861us	50	50	100.00
V1	csr_hw_reset	gpio_csr_hw_reset	0.650s	55.727us	5	5	100.00
V1	csr_rw	gpio_csr_rw	0.650s	16.414us	20	20	100.00
V1	csr_bit_bash	gpio_csr_bit_bash	3.430s	1.479ms	5	5	100.00
V1	csr_aliasing	gpio_csr_aliasing	0.850s	31.488us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	gpio_csr_mem_rw_with_rand_reset	1.770s	35.999us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	gpio_csr_rw	0.650s	16.414us	20	20	100.00
		gpio_csr_aliasing	0.850s	31.488us	5	5	100.00
V1		TOTAL			155	155	100.00
V2	direct_and_masked_out	gpio_random_dout_din	1.390s	68.196us	50	50	100.00
		gpio_random_dout_din_no_pullup_pulldown	1.380s	70.839us	50	50	100.00
V2	out_in_regs_read_write	gpio_dout_din_regs_random_rw	1.020s	200.317us	50	50	100.00
V2	gpio_interrupt_programming	gpio_intr_rand_pgm	1.490s	210.195us	50	50	100.00
V2	random_interrupt_trigger	gpio_rand_intr_trigger	3.560s	634.386us	50	50	100.00
V2	interrupt_and_noise_filter	gpio_intr_with_filter_rand_intr_event	4.040s	96.997us	50	50	100.00
V2	noise_filter_stress	gpio_filter_stress	28.740s	1.835ms	50	50	100.00
V2	regs_long_reads_and_writes	gpio_random_long_reg_writes_reg_reads	6.600s	370.562us	50	50	100.00
V2	full_random	gpio_full_random	1.100s	283.519us	50	50	100.00
V2	stress_all	gpio_stress_all	3.908m	104.963ms	50	50	100.00
V2	alert_test	gpio_alert_test	0.620s	12.357us	50	50	100.00
V2	intr_test	gpio_intr_test	0.620s	34.151us	27	50	54.00
V2	tl_d_oob_addr_access	gpio_tl_errors	3.000s	275.638us	20	20	100.00
V2	tl_d_illegal_access	gpio_tl_errors	3.000s	275.638us	20	20	100.00
V2	tl_d_outstanding_access	gpio_csr_rw	0.650s	16.414us	20	20	100.00
		gpio_same_csr_outstanding	0.850s	21.625us	20	20	100.00
		gpio_csr_aliasing	0.850s	31.488us	5	5	100.00
		gpio_csr_hw_reset	0.650s	55.727us	5	5	100.00
V2	tl_d_partial_access	gpio_csr_rw	0.650s	16.414us	20	20	100.00
		gpio_same_csr_outstanding	0.850s	21.625us	20	20	100.00
		gpio_csr_aliasing	0.850s	31.488us	5	5	100.00
		gpio_csr_hw_reset	0.650s	55.727us	5	5	100.00
V2		TOTAL			617	640	96.41
V2S	tl_intg_err	gpio_tl_intg_err	1.480s	246.332us	20	20	100.00
		gpio_sec_cm	0.920s	160.351us	5	5	100.00
V2S	sec_cm_bus_integrity	gpio_tl_intg_err	1.480s	246.332us	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	stress_all_with_rand_reset	gpio_stress_all_with_rand_reset	38.768m	341.956ms	50	50	100.00
V3		TOTAL			50	50	100.00
		TOTAL			847	870	97.36

Testplan Progress

Items	Total	Written	Passing	Progress
V1	7	7	7	100.00
V2	14	14	13	92.86
V2S	2	2	2	100.00
V3	1	1	1	100.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
99.61	99.07	99.10	100.00	--	99.80	99.68	100.00

Failure Buckets

UVM_ERROR (cip_base_vseq.sv:455) [gpio_common_vseq] Check failed exp_val == act_val (* [*] vs * [*]) when reading the intr CSRgpio_reg_block.intr_state

has 23 failures:

Test gpio_intr_test has 23 failures.

0.gpio_intr_test.386404896
Line 220, in log /container/opentitan-public/scratch/os_regression/gpio-sim-vcs/0.gpio_intr_test/latest/run.log

  UVM_ERROR @   3392094 ps: (cip_base_vseq.sv:455) [uvm_test_top.env.virtual_sequencer.gpio_common_vseq] Check failed exp_val == act_val (0 [0x0] vs 435821130 [0x19fa1a4a]) when reading the intr CSRgpio_reg_block.intr_state
  UVM_INFO @   3392094 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

12.gpio_intr_test.1250204964
Line 218, in log /container/opentitan-public/scratch/os_regression/gpio-sim-vcs/12.gpio_intr_test/latest/run.log

  UVM_ERROR @   7988228 ps: (cip_base_vseq.sv:455) [uvm_test_top.env.virtual_sequencer.gpio_common_vseq] Check failed exp_val == act_val (1 [0x1] vs 2634597721 [0x9d08c559]) when reading the intr CSRgpio_reg_block.intr_state
  UVM_INFO @   7988228 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 21 more failures.