Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=31}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=31}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=31}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	36	0	36	100.00
Crosses	128	0	128	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=31}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	32	0	32	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=31}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	128	0	128	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	32	0	32	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	5944384	1			T22	65		T23	26		T24	18
all_pins[1]	5944384	1			T22	65		T23	26		T24	18
all_pins[2]	5944384	1			T22	65		T23	26		T24	18
all_pins[3]	5944384	1			T22	65		T23	26		T24	18
all_pins[4]	5944384	1			T22	65		T23	26		T24	18
all_pins[5]	5944384	1			T22	65		T23	26		T24	18
all_pins[6]	5944384	1			T22	65		T23	26		T24	18
all_pins[7]	5944384	1			T22	65		T23	26		T24	18
all_pins[8]	5944384	1			T22	65		T23	26		T24	18
all_pins[9]	5944384	1			T22	65		T23	26		T24	18
all_pins[10]	5944384	1			T22	65		T23	26		T24	18
all_pins[11]	5944384	1			T22	65		T23	26		T24	18
all_pins[12]	5944384	1			T22	65		T23	26		T24	18
all_pins[13]	5944384	1			T22	65		T23	26		T24	18
all_pins[14]	5944384	1			T22	65		T23	26		T24	18
all_pins[15]	5944384	1			T22	65		T23	26		T24	18
all_pins[16]	5944384	1			T22	65		T23	26		T24	18
all_pins[17]	5944384	1			T22	65		T23	26		T24	18
all_pins[18]	5944384	1			T22	65		T23	26		T24	18
all_pins[19]	5944384	1			T22	65		T23	26		T24	18
all_pins[20]	5944384	1			T22	65		T23	26		T24	18
all_pins[21]	5944384	1			T22	65		T23	26		T24	18
all_pins[22]	5944384	1			T22	65		T23	26		T24	18
all_pins[23]	5944384	1			T22	65		T23	26		T24	18
all_pins[24]	5944384	1			T22	65		T23	26		T24	18
all_pins[25]	5944384	1			T22	65		T23	26		T24	18
all_pins[26]	5944384	1			T22	65		T23	26		T24	18
all_pins[27]	5944384	1			T22	65		T23	26		T24	18
all_pins[28]	5944384	1			T22	65		T23	26		T24	18
all_pins[29]	5944384	1			T22	65		T23	26		T24	18
all_pins[30]	5944384	1			T22	65		T23	26		T24	18
all_pins[31]	5944384	1			T22	65		T23	26		T24	18

---

Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	117904174	1			T22	2048		T23	644		T24	431
values[0x1]	72316114	1			T22	32		T23	188		T24	145
transitions[0x0=>0x1]	43267098	1			T22	32		T23	147		T24	90
transitions[0x1=>0x0]	43266958	1			T22	32		T23	147		T24	90

---

Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	128	0	128	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	3683801	1			T22	64		T23	22		T24	15
all_pins[0]	values[0x1]	2260583	1			T22	1		T23	4		T24	3
all_pins[0]	transitions[0x0=>0x1]	1395674	1			T22	1		T23	4		T24	1
all_pins[0]	transitions[0x1=>0x0]	1398991	1			T22	1		T23	3		T24	2
all_pins[1]	values[0x0]	3685276	1			T22	64		T23	24		T24	11
all_pins[1]	values[0x1]	2259108	1			T22	1		T23	2		T24	7
all_pins[1]	transitions[0x0=>0x1]	1350861	1			T22	1		T23	1		T24	6
all_pins[1]	transitions[0x1=>0x0]	1352336	1			T22	1		T23	3		T24	2
all_pins[2]	values[0x0]	3680455	1			T22	64		T23	20		T24	11
all_pins[2]	values[0x1]	2263929	1			T22	1		T23	6		T24	7
all_pins[2]	transitions[0x0=>0x1]	1353497	1			T22	1		T23	6		T24	6
all_pins[2]	transitions[0x1=>0x0]	1348676	1			T22	1		T23	2		T24	6
all_pins[3]	values[0x0]	3684807	1			T22	64		T23	23		T24	13
all_pins[3]	values[0x1]	2259577	1			T22	1		T23	3		T24	5
all_pins[3]	transitions[0x0=>0x1]	1349104	1			T22	1		T23	3		T24	4
all_pins[3]	transitions[0x1=>0x0]	1353456	1			T22	1		T23	6		T24	6
all_pins[4]	values[0x0]	3691295	1			T22	64		T23	18		T24	14
all_pins[4]	values[0x1]	2253089	1			T22	1		T23	8		T24	4
all_pins[4]	transitions[0x0=>0x1]	1348934	1			T22	1		T23	8		T24	2
all_pins[4]	transitions[0x1=>0x0]	1355422	1			T22	1		T23	3		T24	3
all_pins[5]	values[0x0]	3679509	1			T22	64		T23	10		T24	17
all_pins[5]	values[0x1]	2264875	1			T22	1		T23	16		T24	1
all_pins[5]	transitions[0x0=>0x1]	1357604	1			T22	1		T23	12		T25	11
all_pins[5]	transitions[0x1=>0x0]	1345818	1			T22	1		T23	4		T24	3
all_pins[6]	values[0x0]	3689458	1			T22	64		T23	22		T24	13
all_pins[6]	values[0x1]	2254926	1			T22	1		T23	4		T24	5
all_pins[6]	transitions[0x0=>0x1]	1346626	1			T22	1		T23	1		T24	5
all_pins[6]	transitions[0x1=>0x0]	1356575	1			T22	1		T23	13		T24	1
all_pins[7]	values[0x0]	3684244	1			T22	64		T23	23		T24	14
all_pins[7]	values[0x1]	2260140	1			T22	1		T23	3		T24	4
all_pins[7]	transitions[0x0=>0x1]	1349361	1			T22	1		T23	2		T24	2
all_pins[7]	transitions[0x1=>0x0]	1344147	1			T22	1		T23	3		T24	3
all_pins[8]	values[0x0]	3680426	1			T22	64		T23	20		T24	13
all_pins[8]	values[0x1]	2263958	1			T22	1		T23	6		T24	5
all_pins[8]	transitions[0x0=>0x1]	1351858	1			T22	1		T23	5		T24	5
all_pins[8]	transitions[0x1=>0x0]	1348040	1			T22	1		T23	2		T24	4
all_pins[9]	values[0x0]	3685548	1			T22	64		T23	19		T24	10
all_pins[9]	values[0x1]	2258836	1			T22	1		T23	7		T24	8
all_pins[9]	transitions[0x0=>0x1]	1350106	1			T22	1		T23	7		T24	4
all_pins[9]	transitions[0x1=>0x0]	1355228	1			T22	1		T23	6		T24	1
all_pins[10]	values[0x0]	3681883	1			T22	64		T23	25		T24	15
all_pins[10]	values[0x1]	2262501	1			T22	1		T23	1		T24	3
all_pins[10]	transitions[0x0=>0x1]	1349863	1			T22	1		T23	1		T24	2
all_pins[10]	transitions[0x1=>0x0]	1346198	1			T22	1		T23	7		T24	7
all_pins[11]	values[0x0]	3691132	1			T22	64		T23	15		T24	12
all_pins[11]	values[0x1]	2253252	1			T22	1		T23	11		T24	6
all_pins[11]	transitions[0x0=>0x1]	1347202	1			T22	1		T23	10		T24	3
all_pins[11]	transitions[0x1=>0x0]	1356451	1			T22	1		T25	16		T11	5
all_pins[12]	values[0x0]	3689572	1			T22	64		T23	22		T24	16
all_pins[12]	values[0x1]	2254812	1			T22	1		T23	4		T24	2
all_pins[12]	transitions[0x0=>0x1]	1347672	1			T22	1		T23	2		T24	2
all_pins[12]	transitions[0x1=>0x0]	1346112	1			T22	1		T23	9		T24	6
all_pins[13]	values[0x0]	3682647	1			T22	64		T23	24		T24	15
all_pins[13]	values[0x1]	2261737	1			T22	1		T23	2		T24	3
all_pins[13]	transitions[0x0=>0x1]	1356527	1			T22	1		T23	2		T24	3
all_pins[13]	transitions[0x1=>0x0]	1349602	1			T22	1		T23	4		T24	2
all_pins[14]	values[0x0]	3683702	1			T22	64		T23	17		T24	14
all_pins[14]	values[0x1]	2260682	1			T22	1		T23	9		T24	4
all_pins[14]	transitions[0x0=>0x1]	1351426	1			T22	1		T23	7		T24	1
all_pins[14]	transitions[0x1=>0x0]	1352481	1			T22	1		T25	5		T1	2
all_pins[15]	values[0x0]	3680872	1			T22	64		T23	25		T24	17
all_pins[15]	values[0x1]	2263512	1			T22	1		T23	1		T24	1
all_pins[15]	transitions[0x0=>0x1]	1354216	1			T22	1		T25	8		T11	4
all_pins[15]	transitions[0x1=>0x0]	1351386	1			T22	1		T23	8		T24	3
all_pins[16]	values[0x0]	3681423	1			T22	64		T23	16		T24	15
all_pins[16]	values[0x1]	2262961	1			T22	1		T23	10		T24	3
all_pins[16]	transitions[0x0=>0x1]	1351054	1			T22	1		T23	9		T24	2
all_pins[16]	transitions[0x1=>0x0]	1351605	1			T22	1		T25	12		T27	4
all_pins[17]	values[0x0]	3685434	1			T22	64		T23	25		T24	6
all_pins[17]	values[0x1]	2258950	1			T22	1		T23	1		T24	12
all_pins[17]	transitions[0x0=>0x1]	1348692	1			T22	1		T24	9		T25	14
all_pins[17]	transitions[0x1=>0x0]	1352703	1			T22	1		T23	9		T25	12
all_pins[18]	values[0x0]	3684193	1			T22	64		T23	12		T24	12
all_pins[18]	values[0x1]	2260191	1			T22	1		T23	14		T24	6
all_pins[18]	transitions[0x0=>0x1]	1349423	1			T22	1		T23	13		T24	1
all_pins[18]	transitions[0x1=>0x0]	1348182	1			T22	1		T24	7		T25	13
all_pins[19]	values[0x0]	3687517	1			T22	64		T23	17		T24	12
all_pins[19]	values[0x1]	2256867	1			T22	1		T23	9		T24	6
all_pins[19]	transitions[0x0=>0x1]	1348113	1			T22	1		T23	4		T25	5
all_pins[19]	transitions[0x1=>0x0]	1351437	1			T22	1		T23	9		T25	7
all_pins[20]	values[0x0]	3681380	1			T22	64		T23	17		T24	16
all_pins[20]	values[0x1]	2263004	1			T22	1		T23	9		T24	2
all_pins[20]	transitions[0x0=>0x1]	1353633	1			T22	1		T23	5		T24	1
all_pins[20]	transitions[0x1=>0x0]	1347496	1			T22	1		T23	5		T24	5
all_pins[21]	values[0x0]	3687861	1			T22	64		T23	22		T24	14
all_pins[21]	values[0x1]	2256523	1			T22	1		T23	4		T24	4
all_pins[21]	transitions[0x0=>0x1]	1346728	1			T22	1		T23	2		T24	3
all_pins[21]	transitions[0x1=>0x0]	1353209	1			T22	1		T23	7		T24	1
all_pins[22]	values[0x0]	3678843	1			T22	64		T23	17		T24	17
all_pins[22]	values[0x1]	2265541	1			T22	1		T23	9		T24	1
all_pins[22]	transitions[0x0=>0x1]	1352108	1			T22	1		T23	7		T25	9
all_pins[22]	transitions[0x1=>0x0]	1343090	1			T22	1		T23	2		T24	3
all_pins[23]	values[0x0]	3679630	1			T22	64		T23	17		T24	12
all_pins[23]	values[0x1]	2264754	1			T22	1		T23	9		T24	6
all_pins[23]	transitions[0x0=>0x1]	1351314	1			T22	1		T23	6		T24	6
all_pins[23]	transitions[0x1=>0x0]	1352101	1			T22	1		T23	6		T24	1
all_pins[24]	values[0x0]	3684978	1			T22	64		T23	24		T24	16
all_pins[24]	values[0x1]	2259406	1			T22	1		T23	2		T24	2
all_pins[24]	transitions[0x0=>0x1]	1348423	1			T22	1		T23	2		T24	1
all_pins[24]	transitions[0x1=>0x0]	1353771	1			T22	1		T23	9		T24	5
all_pins[25]	values[0x0]	3689373	1			T22	64		T23	21		T24	12
all_pins[25]	values[0x1]	2255011	1			T22	1		T23	5		T24	6
all_pins[25]	transitions[0x0=>0x1]	1350440	1			T22	1		T23	5		T24	5
all_pins[25]	transitions[0x1=>0x0]	1354835	1			T22	1		T23	2		T24	1
all_pins[26]	values[0x0]	3689549	1			T22	64		T23	22		T24	11
all_pins[26]	values[0x1]	2254835	1			T22	1		T23	4		T24	7
all_pins[26]	transitions[0x0=>0x1]	1345908	1			T22	1		T23	1		T24	2
all_pins[26]	transitions[0x1=>0x0]	1346084	1			T22	1		T23	2		T24	1
all_pins[27]	values[0x0]	3683264	1			T22	64		T23	23		T24	15
all_pins[27]	values[0x1]	2261120	1			T22	1		T23	3		T24	3
all_pins[27]	transitions[0x0=>0x1]	1353444	1			T22	1		T23	3		T24	3
all_pins[27]	transitions[0x1=>0x0]	1347159	1			T22	1		T23	4		T24	7
all_pins[28]	values[0x0]	3679485	1			T22	64		T23	21		T24	13
all_pins[28]	values[0x1]	2264899	1			T22	1		T23	5		T24	5
all_pins[28]	transitions[0x0=>0x1]	1353739	1			T22	1		T23	5		T24	3
all_pins[28]	transitions[0x1=>0x0]	1349960	1			T22	1		T23	3		T24	1
all_pins[29]	values[0x0]	3688394	1			T22	64		T23	16		T24	9
all_pins[29]	values[0x1]	2255990	1			T22	1		T23	10		T24	9
all_pins[29]	transitions[0x0=>0x1]	1349790	1			T22	1		T23	9		T24	4
all_pins[29]	transitions[0x1=>0x0]	1358699	1			T22	1		T23	4		T25	11
all_pins[30]	values[0x0]	3687879	1			T22	64		T23	22		T24	17
all_pins[30]	values[0x1]	2256505	1			T22	1		T23	4		T24	1
all_pins[30]	transitions[0x0=>0x1]	1350116	1			T22	1		T23	2		T25	17
all_pins[30]	transitions[0x1=>0x0]	1349601	1			T22	1		T23	8		T24	8
all_pins[31]	values[0x0]	3680344	1			T22	64		T23	23		T24	14
all_pins[31]	values[0x1]	2264040	1			T22	1		T23	3		T24	4
all_pins[31]	transitions[0x0=>0x1]	1353642	1			T22	1		T23	3		T24	4
all_pins[31]	transitions[0x1=>0x0]	1346107	1			T22	1		T23	4		T24	1