Unified Coverage Report :: Group :: cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=31}

Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=31}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=31}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	192	0	192	100.00

Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=31}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	32	0	32	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2
cp_intr_test	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=31}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_test_cg_cc	192	0	192	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	32	0	32	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	20123460	1			T22	1		T23	30		T24	21
all_values[1]	20123460	1			T22	1		T23	30		T24	21
all_values[2]	20123460	1			T22	1		T23	30		T24	21
all_values[3]	20123460	1			T22	1		T23	30		T24	21
all_values[4]	20123460	1			T22	1		T23	30		T24	21
all_values[5]	20123460	1			T22	1		T23	30		T24	21
all_values[6]	20123460	1			T22	1		T23	30		T24	21
all_values[7]	20123460	1			T22	1		T23	30		T24	21
all_values[8]	20123460	1			T22	1		T23	30		T24	21
all_values[9]	20123460	1			T22	1		T23	30		T24	21
all_values[10]	20123460	1			T22	1		T23	30		T24	21
all_values[11]	20123460	1			T22	1		T23	30		T24	21
all_values[12]	20123460	1			T22	1		T23	30		T24	21
all_values[13]	20123460	1			T22	1		T23	30		T24	21
all_values[14]	20123460	1			T22	1		T23	30		T24	21
all_values[15]	20123460	1			T22	1		T23	30		T24	21
all_values[16]	20123460	1			T22	1		T23	30		T24	21
all_values[17]	20123460	1			T22	1		T23	30		T24	21
all_values[18]	20123460	1			T22	1		T23	30		T24	21
all_values[19]	20123460	1			T22	1		T23	30		T24	21
all_values[20]	20123460	1			T22	1		T23	30		T24	21
all_values[21]	20123460	1			T22	1		T23	30		T24	21
all_values[22]	20123460	1			T22	1		T23	30		T24	21
all_values[23]	20123460	1			T22	1		T23	30		T24	21
all_values[24]	20123460	1			T22	1		T23	30		T24	21
all_values[25]	20123460	1			T22	1		T23	30		T24	21
all_values[26]	20123460	1			T22	1		T23	30		T24	21
all_values[27]	20123460	1			T22	1		T23	30		T24	21
all_values[28]	20123460	1			T22	1		T23	30		T24	21
all_values[29]	20123460	1			T22	1		T23	30		T24	21
all_values[30]	20123460	1			T22	1		T23	30		T24	21
all_values[31]	20123460	1			T22	1		T23	30		T24	21

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

355296724

1

T22

32

T23

498

T24

304

auto[1]

288653996

1

T23

462

T24

368

T25

357

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

119091623

1

T22

32

T23

505

T24

418

auto[1]

524859097

1

T23

455

T24

254

T25

431

---

Summary for Variable cp_intr_test

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_test

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

636668459

1

T22

32

T23

808

T24

585

auto[1]

7282261

1

T23

152

T24

87

T31

137

---

Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	192	0	192	100.00
Automatically Generated Cross Bins	192	0	192	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for intr_test_cg_cc

Bins

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	auto[0]	2897638	1			T22	1		T23	11		T24	4
all_values[0]	auto[0]	auto[0]	auto[1]	8095736	1			T23	2		T25	9		T11	5
all_values[0]	auto[0]	auto[1]	auto[0]	828898	1			T23	12		T24	14		T25	7
all_values[0]	auto[0]	auto[1]	auto[1]	8073668	1			T23	1		T24	1		T25	4
all_values[0]	auto[1]	auto[0]	auto[1]	114438	1			T31	1		T94	1		T18	1
all_values[0]	auto[1]	auto[1]	auto[1]	113082	1			T23	4		T24	2		T31	1
all_values[1]	auto[0]	auto[0]	auto[0]	2880186	1			T22	1		T23	9		T24	9
all_values[1]	auto[0]	auto[0]	auto[1]	8082724	1			T23	7		T24	1		T25	5
all_values[1]	auto[0]	auto[1]	auto[0]	830716	1			T23	6		T24	2		T25	4
all_values[1]	auto[0]	auto[1]	auto[1]	8102582	1			T23	1		T24	7		T25	9
all_values[1]	auto[1]	auto[0]	auto[1]	113256	1			T23	5		T24	1		T31	3
all_values[1]	auto[1]	auto[1]	auto[1]	113996	1			T23	2		T24	1		T31	1
all_values[2]	auto[0]	auto[0]	auto[0]	2896914	1			T22	1		T23	5		T24	7
all_values[2]	auto[0]	auto[0]	auto[1]	8068909	1			T23	3		T25	8		T11	5
all_values[2]	auto[0]	auto[1]	auto[0]	830092	1			T23	13		T24	7		T25	6
all_values[2]	auto[0]	auto[1]	auto[1]	8100025	1			T23	4		T24	5		T25	7
all_values[2]	auto[1]	auto[0]	auto[1]	113826	1			T23	3		T31	5		T94	2
all_values[2]	auto[1]	auto[1]	auto[1]	113694	1			T23	2		T24	2		T31	1
all_values[3]	auto[0]	auto[0]	auto[0]	2899196	1			T22	1		T23	9		T24	6
all_values[3]	auto[0]	auto[0]	auto[1]	8124033	1			T23	9		T24	4		T25	4
all_values[3]	auto[0]	auto[1]	auto[0]	823169	1			T23	4		T24	2		T25	9
all_values[3]	auto[0]	auto[1]	auto[1]	8049537	1			T23	3		T24	5		T25	6
all_values[3]	auto[1]	auto[0]	auto[1]	114204	1			T23	4		T24	3		T31	3
all_values[3]	auto[1]	auto[1]	auto[1]	113321	1			T23	1		T24	1		T31	1
all_values[4]	auto[0]	auto[0]	auto[0]	2880857	1			T22	1		T23	7		T24	7
all_values[4]	auto[0]	auto[0]	auto[1]	8140429	1			T23	1		T24	6		T25	3
all_values[4]	auto[0]	auto[1]	auto[0]	824552	1			T23	12		T24	2		T25	8
all_values[4]	auto[0]	auto[1]	auto[1]	8050088	1			T23	4		T24	3		T25	8
all_values[4]	auto[1]	auto[0]	auto[1]	114516	1			T23	1		T24	2		T31	1
all_values[4]	auto[1]	auto[1]	auto[1]	113018	1			T23	5		T24	1		T31	3
all_values[5]	auto[0]	auto[0]	auto[0]	2888660	1			T22	1		T23	1		T24	5
all_values[5]	auto[0]	auto[0]	auto[1]	8057816	1			T23	5		T25	11		T27	4
all_values[5]	auto[0]	auto[1]	auto[0]	828292	1			T23	7		T24	14		T25	4
all_values[5]	auto[0]	auto[1]	auto[1]	8120923	1			T23	12		T24	1		T25	5
all_values[5]	auto[1]	auto[0]	auto[1]	113595	1			T24	1		T31	1		T18	2
all_values[5]	auto[1]	auto[1]	auto[1]	114174	1			T23	5		T94	2		T18	1
all_values[6]	auto[0]	auto[0]	auto[0]	2898377	1			T22	1		T23	6		T24	6
all_values[6]	auto[0]	auto[0]	auto[1]	8137152	1			T24	4		T25	8		T1	1
all_values[6]	auto[0]	auto[1]	auto[0]	830742	1			T23	17		T24	5		T25	1
all_values[6]	auto[0]	auto[1]	auto[1]	8029676	1			T23	4		T24	2		T25	8
all_values[6]	auto[1]	auto[0]	auto[1]	114561	1			T23	1		T24	1		T31	1
all_values[6]	auto[1]	auto[1]	auto[1]	112952	1			T23	2		T24	3		T31	4
all_values[7]	auto[0]	auto[0]	auto[0]	2897026	1			T22	1		T23	10		T24	4
all_values[7]	auto[0]	auto[0]	auto[1]	8100351	1			T23	5		T25	9		T11	13
all_values[7]	auto[0]	auto[1]	auto[0]	833940	1			T23	9		T24	13		T25	4
all_values[7]	auto[0]	auto[1]	auto[1]	8064053	1			T23	1		T24	1		T25	5
all_values[7]	auto[1]	auto[0]	auto[1]	114248	1			T23	2		T31	1		T19	2
all_values[7]	auto[1]	auto[1]	auto[1]	113842	1			T23	3		T24	3		T31	2
all_values[8]	auto[0]	auto[0]	auto[0]	2902838	1			T22	1		T23	13		T24	4
all_values[8]	auto[0]	auto[0]	auto[1]	8089522	1			T23	3		T24	1		T25	9
all_values[8]	auto[0]	auto[1]	auto[0]	833805	1			T23	1		T24	8		T25	3
all_values[8]	auto[0]	auto[1]	auto[1]	8068960	1			T23	6		T24	4		T25	3
all_values[8]	auto[1]	auto[0]	auto[1]	114322	1			T23	6		T24	3		T31	1
all_values[8]	auto[1]	auto[1]	auto[1]	114013	1			T23	1		T24	1		T31	1
all_values[9]	auto[0]	auto[0]	auto[0]	2881938	1			T22	1		T23	5		T24	4
all_values[9]	auto[0]	auto[0]	auto[1]	8075390	1			T23	14		T25	7		T11	4
all_values[9]	auto[0]	auto[1]	auto[0]	827524	1			T23	1		T24	9		T25	8
all_values[9]	auto[0]	auto[1]	auto[1]	8110900	1			T23	6		T24	6		T25	9
all_values[9]	auto[1]	auto[0]	auto[1]	114391	1			T23	2		T31	5		T18	2
all_values[9]	auto[1]	auto[1]	auto[1]	113317	1			T23	2		T24	2		T31	2
all_values[10]	auto[0]	auto[0]	auto[0]	2888729	1			T22	1		T23	17		T24	7
all_values[10]	auto[0]	auto[0]	auto[1]	8077753	1			T23	3		T24	5		T25	5
all_values[10]	auto[0]	auto[1]	auto[0]	824762	1			T23	5		T24	5		T25	5
all_values[10]	auto[0]	auto[1]	auto[1]	8104719	1			T24	1		T25	9		T27	3
all_values[10]	auto[1]	auto[0]	auto[1]	114089	1			T23	4		T24	1		T31	4
all_values[10]	auto[1]	auto[1]	auto[1]	113408	1			T23	1		T24	2		T31	2
all_values[11]	auto[0]	auto[0]	auto[0]	2893586	1			T22	1		T23	1		T24	4
all_values[11]	auto[0]	auto[0]	auto[1]	8098741	1			T23	9		T24	2		T25	6
all_values[11]	auto[0]	auto[1]	auto[0]	822772	1			T23	6		T24	8		T25	4
all_values[11]	auto[0]	auto[1]	auto[1]	8081175	1			T23	10		T24	4		T25	7
all_values[11]	auto[1]	auto[0]	auto[1]	113728	1			T23	1		T24	1		T31	4
all_values[11]	auto[1]	auto[1]	auto[1]	113458	1			T23	3		T24	2		T31	2
all_values[12]	auto[0]	auto[0]	auto[0]	2909028	1			T22	1		T23	11		T24	9
all_values[12]	auto[0]	auto[0]	auto[1]	8094085	1			T23	6		T24	5		T25	12
all_values[12]	auto[0]	auto[1]	auto[0]	828361	1			T23	4		T24	2		T25	8
all_values[12]	auto[0]	auto[1]	auto[1]	8064265	1			T23	4		T24	1		T25	4
all_values[12]	auto[1]	auto[0]	auto[1]	114930	1			T23	4		T24	3		T31	6
all_values[12]	auto[1]	auto[1]	auto[1]	112791	1			T23	1		T24	1		T94	1
all_values[13]	auto[0]	auto[0]	auto[0]	2889242	1			T22	1		T23	11		T24	4
all_values[13]	auto[0]	auto[0]	auto[1]	8098093	1			T23	2		T24	5		T25	9
all_values[13]	auto[0]	auto[1]	auto[0]	821286	1			T23	13		T24	6		T25	5
all_values[13]	auto[0]	auto[1]	auto[1]	8086914	1			T23	1		T24	2		T25	5
all_values[13]	auto[1]	auto[0]	auto[1]	113900	1			T23	2		T24	3		T31	2
all_values[13]	auto[1]	auto[1]	auto[1]	114025	1			T23	1		T24	1		T31	3
all_values[14]	auto[0]	auto[0]	auto[0]	2894583	1			T22	1		T23	4		T24	2
all_values[14]	auto[0]	auto[0]	auto[1]	8073845	1			T23	3		T24	9		T25	5
all_values[14]	auto[0]	auto[1]	auto[0]	828006	1			T23	13		T24	5		T25	2
all_values[14]	auto[0]	auto[1]	auto[1]	8099745	1			T23	7		T24	3		T25	11
all_values[14]	auto[1]	auto[0]	auto[1]	114267	1			T24	1		T31	3		T94	2
all_values[14]	auto[1]	auto[1]	auto[1]	113014	1			T23	3		T24	1		T94	1
all_values[15]	auto[0]	auto[0]	auto[0]	2880945	1			T22	1		T23	14		T24	15
all_values[15]	auto[0]	auto[0]	auto[1]	8114842	1			T23	3		T25	6		T11	25
all_values[15]	auto[0]	auto[1]	auto[0]	823077	1			T23	10		T24	5		T25	3
all_values[15]	auto[0]	auto[1]	auto[1]	8077115	1			T23	1		T25	9		T12	9
all_values[15]	auto[1]	auto[0]	auto[1]	113647	1			T23	2		T31	2		T94	1
all_values[15]	auto[1]	auto[1]	auto[1]	113834	1			T24	1		T31	1		T18	1
all_values[16]	auto[0]	auto[0]	auto[0]	2888097	1			T22	1		T23	5		T24	8
all_values[16]	auto[0]	auto[0]	auto[1]	8079266	1			T23	1		T24	5		T25	8
all_values[16]	auto[0]	auto[1]	auto[0]	840531	1			T23	11		T24	5		T25	6
all_values[16]	auto[0]	auto[1]	auto[1]	8088424	1			T23	7		T24	1		T25	5
all_values[16]	auto[1]	auto[0]	auto[1]	113576	1			T23	2		T31	2		T94	1
all_values[16]	auto[1]	auto[1]	auto[1]	113566	1			T23	4		T24	2		T31	3
all_values[17]	auto[0]	auto[0]	auto[0]	2891060	1			T22	1		T23	13		T24	1
all_values[17]	auto[0]	auto[0]	auto[1]	8075061	1			T23	3		T25	11		T11	11
all_values[17]	auto[0]	auto[1]	auto[0]	838698	1			T23	10		T24	7		T25	4
all_values[17]	auto[0]	auto[1]	auto[1]	8090852	1			T23	1		T24	8		T25	7
all_values[17]	auto[1]	auto[0]	auto[1]	114521	1			T23	2		T31	5		T19	3
all_values[17]	auto[1]	auto[1]	auto[1]	113268	1			T23	1		T24	5		T31	2
all_values[18]	auto[0]	auto[0]	auto[0]	2882583	1			T22	1		T23	1		T24	4
all_values[18]	auto[0]	auto[0]	auto[1]	8098744	1			T23	2		T25	7		T11	29
all_values[18]	auto[0]	auto[1]	auto[0]	832924	1			T23	10		T24	11		T25	4
all_values[18]	auto[0]	auto[1]	auto[1]	8081792	1			T23	9		T24	4		T25	5
all_values[18]	auto[1]	auto[0]	auto[1]	114319	1			T31	4		T94	1		T19	1
all_values[18]	auto[1]	auto[1]	auto[1]	113098	1			T23	8		T24	2		T31	1
all_values[19]	auto[0]	auto[0]	auto[0]	2893611	1			T22	1		T23	5		T24	1
all_values[19]	auto[0]	auto[0]	auto[1]	8103964	1			T23	10		T25	5		T11	14
all_values[19]	auto[0]	auto[1]	auto[0]	825239	1			T23	1		T24	14		T25	4
all_values[19]	auto[0]	auto[1]	auto[1]	8073420	1			T23	7		T24	3		T25	8
all_values[19]	auto[1]	auto[0]	auto[1]	113897	1			T23	4		T31	2		T94	1
all_values[19]	auto[1]	auto[1]	auto[1]	113329	1			T23	3		T24	3		T94	2
all_values[20]	auto[0]	auto[0]	auto[0]	2892243	1			T22	1		T23	9		T24	10
all_values[20]	auto[0]	auto[0]	auto[1]	8121805	1			T23	4		T25	8		T1	1
all_values[20]	auto[0]	auto[1]	auto[0]	823769	1			T23	4		T24	8		T25	5
all_values[20]	auto[0]	auto[1]	auto[1]	8057624	1			T23	8		T25	4		T27	4
all_values[20]	auto[1]	auto[0]	auto[1]	113913	1			T23	3		T24	1		T31	4
all_values[20]	auto[1]	auto[1]	auto[1]	114106	1			T23	2		T24	2		T31	2
all_values[21]	auto[0]	auto[0]	auto[0]	2896664	1			T22	1		T23	6		T24	7
all_values[21]	auto[0]	auto[0]	auto[1]	8096483	1			T23	2		T24	1		T25	8
all_values[21]	auto[0]	auto[1]	auto[0]	834147	1			T23	18		T24	9		T25	5
all_values[21]	auto[0]	auto[1]	auto[1]	8067933	1			T23	1		T24	1		T25	5
all_values[21]	auto[1]	auto[0]	auto[1]	114238	1			T31	4		T94	3		T19	1
all_values[21]	auto[1]	auto[1]	auto[1]	113995	1			T23	3		T24	3		T94	1
all_values[22]	auto[0]	auto[0]	auto[0]	2893032	1			T22	1		T23	7		T24	13
all_values[22]	auto[0]	auto[0]	auto[1]	8086294	1			T23	4		T25	7		T11	11
all_values[22]	auto[0]	auto[1]	auto[0]	820109	1			T23	6		T24	6		T25	6
all_values[22]	auto[0]	auto[1]	auto[1]	8095876	1			T23	6		T25	5		T27	4
all_values[22]	auto[1]	auto[0]	auto[1]	113738	1			T23	4		T24	1		T31	2
all_values[22]	auto[1]	auto[1]	auto[1]	114411	1			T23	3		T24	1		T31	3
all_values[23]	auto[0]	auto[0]	auto[0]	2899205	1			T22	1		T23	2		T24	7
all_values[23]	auto[0]	auto[0]	auto[1]	8085827	1			T23	11		T24	2		T25	6
all_values[23]	auto[0]	auto[1]	auto[0]	827576	1			T23	5		T24	5		T25	6
all_values[23]	auto[0]	auto[1]	auto[1]	8083182	1			T23	7		T24	4		T25	3
all_values[23]	auto[1]	auto[0]	auto[1]	113559	1			T23	1		T24	1		T31	3
all_values[23]	auto[1]	auto[1]	auto[1]	114111	1			T23	4		T24	2		T31	1
all_values[24]	auto[0]	auto[0]	auto[0]	2885675	1			T22	1		T23	8		T24	7
all_values[24]	auto[0]	auto[0]	auto[1]	8103502	1			T23	10		T24	1		T25	9
all_values[24]	auto[0]	auto[1]	auto[0]	821542	1			T23	5		T24	10		T25	4
all_values[24]	auto[0]	auto[1]	auto[1]	8085263	1			T23	1		T25	8		T27	4
all_values[24]	auto[1]	auto[0]	auto[1]	114052	1			T23	5		T24	1		T31	4
all_values[24]	auto[1]	auto[1]	auto[1]	113426	1			T23	1		T24	2		T31	3
all_values[25]	auto[0]	auto[0]	auto[0]	2888917	1			T22	1		T23	6		T24	3
all_values[25]	auto[0]	auto[0]	auto[1]	8149118	1			T23	10		T24	3		T25	6
all_values[25]	auto[0]	auto[1]	auto[0]	828996	1			T23	2		T24	6		T25	10
all_values[25]	auto[0]	auto[1]	auto[1]	8028794	1			T23	6		T24	6		T25	2
all_values[25]	auto[1]	auto[0]	auto[1]	113795	1			T23	6		T24	2		T31	2
all_values[25]	auto[1]	auto[1]	auto[1]	113840	1			T24	1		T31	1		T94	3
all_values[26]	auto[0]	auto[0]	auto[0]	2899954	1			T22	1		T23	6		T24	4
all_values[26]	auto[0]	auto[0]	auto[1]	8110335	1			T23	11		T24	7		T25	11
all_values[26]	auto[0]	auto[1]	auto[0]	833566	1			T23	5		T24	2		T25	4
all_values[26]	auto[0]	auto[1]	auto[1]	8052284	1			T23	2		T24	5		T25	2
all_values[26]	auto[1]	auto[0]	auto[1]	114060	1			T23	3		T24	1		T31	1
all_values[26]	auto[1]	auto[1]	auto[1]	113261	1			T23	3		T24	2		T31	1
all_values[27]	auto[0]	auto[0]	auto[0]	2894225	1			T22	1		T23	12		T24	11
all_values[27]	auto[0]	auto[0]	auto[1]	8079685	1			T23	6		T24	1		T25	8
all_values[27]	auto[0]	auto[1]	auto[0]	828561	1			T23	5		T24	5		T25	6
all_values[27]	auto[0]	auto[1]	auto[1]	8093934	1			T23	3		T24	1		T25	8
all_values[27]	auto[1]	auto[0]	auto[1]	114030	1			T23	4		T24	1		T31	4
all_values[27]	auto[1]	auto[1]	auto[1]	113025	1			T24	2		T31	1		T94	1
all_values[28]	auto[0]	auto[0]	auto[0]	2900623	1			T22	1		T23	11		T24	11
all_values[28]	auto[0]	auto[0]	auto[1]	8104759	1			T23	4		T25	9		T27	4
all_values[28]	auto[0]	auto[1]	auto[0]	827927	1			T23	6		T24	5		T25	5
all_values[28]	auto[0]	auto[1]	auto[1]	8062860	1			T23	4		T24	4		T25	6
all_values[28]	auto[1]	auto[0]	auto[1]	114350	1			T23	3		T31	1		T18	2
all_values[28]	auto[1]	auto[1]	auto[1]	112941	1			T23	2		T24	1		T31	4
all_values[29]	auto[0]	auto[0]	auto[0]	2892904	1			T22	1		T23	15		T24	3
all_values[29]	auto[0]	auto[0]	auto[1]	8107576	1			T23	1		T24	5		T25	7
all_values[29]	auto[0]	auto[1]	auto[0]	839191	1			T23	3		T24	3		T25	8
all_values[29]	auto[0]	auto[1]	auto[1]	8056932	1			T23	8		T24	8		T25	2
all_values[29]	auto[1]	auto[0]	auto[1]	113892	1			T23	1		T24	1		T31	2
all_values[29]	auto[1]	auto[1]	auto[1]	112965	1			T23	2		T24	1		T94	3
all_values[30]	auto[0]	auto[0]	auto[0]	2896865	1			T22	1		T23	7		T24	6
all_values[30]	auto[0]	auto[0]	auto[1]	8099659	1			T23	8		T24	5		T25	4
all_values[30]	auto[0]	auto[1]	auto[0]	826325	1			T23	10		T24	7		T25	4
all_values[30]	auto[0]	auto[1]	auto[1]	8072909	1			T23	3		T25	7		T27	4
all_values[30]	auto[1]	auto[0]	auto[1]	114493	1			T24	2		T31	4		T94	2
all_values[30]	auto[1]	auto[1]	auto[1]	113209	1			T23	2		T24	1		T31	1
all_values[31]	auto[0]	auto[0]	auto[0]	2883460	1			T22	1		T23	12		T24	6
all_values[31]	auto[0]	auto[0]	auto[1]	8056149	1			T24	1		T25	9		T27	3
all_values[31]	auto[0]	auto[1]	auto[0]	843667	1			T23	12		T24	9		T25	3
all_values[31]	auto[0]	auto[1]	auto[1]	8112764	1			T23	3		T24	3		T25	6
all_values[31]	auto[1]	auto[0]	auto[1]	113864	1			T23	2		T24	1		T31	2
all_values[31]	auto[1]	auto[1]	auto[1]	113556	1			T23	1		T24	1		T31	1

User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins

NAME	COUNT	STATUS
test_1_state_0	0	Illegal