Unified Coverage Report :: Group :: gpio_env_pkg::gpio_env_cov::data_out_data_oe_data_in_cross_cg

Group : gpio_env_pkg::gpio_env_cov::data_out_data_oe_data_in_cross_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_gpio_env_0.1/gpio_env_cov.sv

---

Summary for Group gpio_env_pkg::gpio_env_cov::data_out_data_oe_data_in_cross_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	192	0	192	100.00

Variables for Group gpio_env_pkg::gpio_env_cov::data_out_data_oe_data_in_cross_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_pin	32	0	32	100.00	100	1	1	0
data_in	2	0	2	100.00	100	1	1	2
data_oe	2	0	2	100.00	100	1	1	2
data_out	2	0	2	100.00	100	1	1	2

Crosses for Group gpio_env_pkg::gpio_env_cov::data_out_data_oe_data_in_cross_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_cross_all	192	0	192	100.00	100	1	1	0

Summary for Variable cp_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	32	0	32	100.00

User Defined Bins for cp_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
bins_for_gpio_bits[0]	19813216	1			T22	1		T23	1		T24	1
bins_for_gpio_bits[1]	19813216	1			T22	1		T23	1		T24	1
bins_for_gpio_bits[2]	19813216	1			T22	1		T23	1		T24	1
bins_for_gpio_bits[3]	19813216	1			T22	1		T23	1		T24	1
bins_for_gpio_bits[4]	19813216	1			T22	1		T23	1		T24	1
bins_for_gpio_bits[5]	19813216	1			T22	1		T23	1		T24	1
bins_for_gpio_bits[6]	19813216	1			T22	1		T23	1		T24	1
bins_for_gpio_bits[7]	19813216	1			T22	1		T23	1		T24	1
bins_for_gpio_bits[8]	19813216	1			T22	1		T23	1		T24	1
bins_for_gpio_bits[9]	19813216	1			T22	1		T23	1		T24	1
bins_for_gpio_bits[10]	19813216	1			T22	1		T23	1		T24	1
bins_for_gpio_bits[11]	19813216	1			T22	1		T23	1		T24	1
bins_for_gpio_bits[12]	19813216	1			T22	1		T23	1		T24	1
bins_for_gpio_bits[13]	19813216	1			T22	1		T23	1		T24	1
bins_for_gpio_bits[14]	19813216	1			T22	1		T23	1		T24	1
bins_for_gpio_bits[15]	19813216	1			T22	1		T23	1		T24	1
bins_for_gpio_bits[16]	19813216	1			T22	1		T23	1		T24	1
bins_for_gpio_bits[17]	19813216	1			T22	1		T23	1		T24	1
bins_for_gpio_bits[18]	19813216	1			T22	1		T23	1		T24	1
bins_for_gpio_bits[19]	19813216	1			T22	1		T23	1		T24	1
bins_for_gpio_bits[20]	19813216	1			T22	1		T23	1		T24	1
bins_for_gpio_bits[21]	19813216	1			T22	1		T23	1		T24	1
bins_for_gpio_bits[22]	19813216	1			T22	1		T23	1		T24	1
bins_for_gpio_bits[23]	19813216	1			T22	1		T23	1		T24	1
bins_for_gpio_bits[24]	19813216	1			T22	1		T23	1		T24	1
bins_for_gpio_bits[25]	19813216	1			T22	1		T23	1		T24	1
bins_for_gpio_bits[26]	19813216	1			T22	1		T23	1		T24	1
bins_for_gpio_bits[27]	19813216	1			T22	1		T23	1		T24	1
bins_for_gpio_bits[28]	19813216	1			T22	1		T23	1		T24	1
bins_for_gpio_bits[29]	19813216	1			T22	1		T23	1		T24	1
bins_for_gpio_bits[30]	19813216	1			T22	1		T23	1		T24	1
bins_for_gpio_bits[31]	19813216	1			T22	1		T23	1		T24	1

---

Summary for Variable data_in

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for data_in

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

392247673

1

T22

32

T23

32

T24

32

auto[1]

241775239

1

T43

2317

T44

2607

T45

4931

---

Summary for Variable data_oe

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for data_oe

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

504865098

1

T22

32

T23

32

T24

32

auto[1]

129157814

1

T43

1560

T44

2477

T45

2919

---

Summary for Variable data_out

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for data_out

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

466918827

1

T22

32

T23

32

T24

32

auto[1]

167104085

1

T43

1608

T44

2625

T45

2871

---

Summary for Cross cp_cross_all

Samples crossed: cp_pin data_out data_oe data_in

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	192	0	192	100.00
Automatically Generated Cross Bins	192	0	192	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cp_cross_all

Bins

cp_pin	data_out	data_oe	data_in	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
bins_for_gpio_bits[0]	auto[0]	auto[0]	auto[0]	7467658	1			T22	1		T23	1		T24	1
bins_for_gpio_bits[0]	auto[0]	auto[0]	auto[1]	5091779	1			T43	43		T44	51		T45	73
bins_for_gpio_bits[0]	auto[0]	auto[1]	auto[0]	2029666	1			T43	16		T44	45		T45	56
bins_for_gpio_bits[0]	auto[1]	auto[0]	auto[0]	2758558	1			T43	28		T44	40		T52	60
bins_for_gpio_bits[0]	auto[1]	auto[0]	auto[1]	454873	1			T45	40		T99	165		T100	120
bins_for_gpio_bits[0]	auto[1]	auto[1]	auto[1]	2010682	1			T43	28		T44	40		T45	28
bins_for_gpio_bits[1]	auto[0]	auto[0]	auto[0]	7464537	1			T22	1		T23	1		T24	1
bins_for_gpio_bits[1]	auto[0]	auto[0]	auto[1]	5096512	1			T43	42		T44	41		T45	73
bins_for_gpio_bits[1]	auto[0]	auto[1]	auto[0]	2026448	1			T43	28		T44	46		T45	34
bins_for_gpio_bits[1]	auto[1]	auto[0]	auto[0]	2758134	1			T43	31		T44	34		T52	39
bins_for_gpio_bits[1]	auto[1]	auto[0]	auto[1]	451725	1			T45	41		T99	178		T100	131
bins_for_gpio_bits[1]	auto[1]	auto[1]	auto[1]	2015860	1			T43	24		T44	38		T45	54
bins_for_gpio_bits[2]	auto[0]	auto[0]	auto[0]	7472399	1			T22	1		T23	1		T24	1
bins_for_gpio_bits[2]	auto[0]	auto[0]	auto[1]	5082913	1			T43	50		T44	34		T45	65
bins_for_gpio_bits[2]	auto[0]	auto[1]	auto[0]	2031104	1			T43	25		T44	32		T45	42
bins_for_gpio_bits[2]	auto[1]	auto[0]	auto[0]	2760934	1			T43	24		T44	67		T52	57
bins_for_gpio_bits[2]	auto[1]	auto[0]	auto[1]	454695	1			T45	45		T99	158		T100	96
bins_for_gpio_bits[2]	auto[1]	auto[1]	auto[1]	2011171	1			T43	36		T44	32		T45	46
bins_for_gpio_bits[3]	auto[0]	auto[0]	auto[0]	7468182	1			T22	1		T23	1		T24	1
bins_for_gpio_bits[3]	auto[0]	auto[0]	auto[1]	5098533	1			T43	45		T44	39		T45	71
bins_for_gpio_bits[3]	auto[0]	auto[1]	auto[0]	2027670	1			T43	12		T44	46		T45	48
bins_for_gpio_bits[3]	auto[1]	auto[0]	auto[0]	2759699	1			T43	26		T44	36		T52	58
bins_for_gpio_bits[3]	auto[1]	auto[0]	auto[1]	455033	1			T45	43		T99	156		T100	107
bins_for_gpio_bits[3]	auto[1]	auto[1]	auto[1]	2004099	1			T43	37		T44	43		T45	44
bins_for_gpio_bits[4]	auto[0]	auto[0]	auto[0]	7465044	1			T22	1		T23	1		T24	1
bins_for_gpio_bits[4]	auto[0]	auto[0]	auto[1]	5095172	1			T43	54		T44	44		T45	62
bins_for_gpio_bits[4]	auto[0]	auto[1]	auto[0]	2023897	1			T43	28		T44	30		T45	60
bins_for_gpio_bits[4]	auto[1]	auto[0]	auto[0]	2762962	1			T43	26		T44	44		T52	61
bins_for_gpio_bits[4]	auto[1]	auto[0]	auto[1]	452776	1			T45	38		T99	202		T100	83
bins_for_gpio_bits[4]	auto[1]	auto[1]	auto[1]	2013365	1			T43	29		T44	31		T45	37
bins_for_gpio_bits[5]	auto[0]	auto[0]	auto[0]	7470095	1			T22	1		T23	1		T24	1
bins_for_gpio_bits[5]	auto[0]	auto[0]	auto[1]	5093664	1			T43	49		T44	39		T45	49
bins_for_gpio_bits[5]	auto[0]	auto[1]	auto[0]	2029765	1			T43	26		T44	41		T45	34
bins_for_gpio_bits[5]	auto[1]	auto[0]	auto[0]	2753312	1			T43	29		T44	48		T52	73
bins_for_gpio_bits[5]	auto[1]	auto[0]	auto[1]	453981	1			T45	48		T99	182		T100	78
bins_for_gpio_bits[5]	auto[1]	auto[1]	auto[1]	2012399	1			T43	14		T44	32		T45	67
bins_for_gpio_bits[6]	auto[0]	auto[0]	auto[0]	7467195	1			T22	1		T23	1		T24	1
bins_for_gpio_bits[6]	auto[0]	auto[0]	auto[1]	5096682	1			T43	36		T44	39		T45	71
bins_for_gpio_bits[6]	auto[0]	auto[1]	auto[0]	2031236	1			T43	18		T44	58		T45	39
bins_for_gpio_bits[6]	auto[1]	auto[0]	auto[0]	2752772	1			T43	42		T44	26		T52	62
bins_for_gpio_bits[6]	auto[1]	auto[0]	auto[1]	452835	1			T45	42		T99	174		T100	106
bins_for_gpio_bits[6]	auto[1]	auto[1]	auto[1]	2012496	1			T43	14		T44	42		T45	46
bins_for_gpio_bits[7]	auto[0]	auto[0]	auto[0]	7465304	1			T22	1		T23	1		T24	1
bins_for_gpio_bits[7]	auto[0]	auto[0]	auto[1]	5091322	1			T43	57		T44	38		T45	60
bins_for_gpio_bits[7]	auto[0]	auto[1]	auto[0]	2030173	1			T43	22		T44	24		T45	40
bins_for_gpio_bits[7]	auto[1]	auto[0]	auto[0]	2754009	1			T43	26		T44	43		T52	65
bins_for_gpio_bits[7]	auto[1]	auto[0]	auto[1]	452795	1			T45	58		T99	124		T100	94
bins_for_gpio_bits[7]	auto[1]	auto[1]	auto[1]	2019613	1			T43	30		T44	56		T45	33
bins_for_gpio_bits[8]	auto[0]	auto[0]	auto[0]	7474397	1			T22	1		T23	1		T24	1
bins_for_gpio_bits[8]	auto[0]	auto[0]	auto[1]	5089157	1			T43	52		T44	43		T45	44
bins_for_gpio_bits[8]	auto[0]	auto[1]	auto[0]	2028326	1			T43	17		T44	18		T45	42
bins_for_gpio_bits[8]	auto[1]	auto[0]	auto[0]	2756657	1			T43	32		T44	53		T52	54
bins_for_gpio_bits[8]	auto[1]	auto[0]	auto[1]	453237	1			T45	72		T99	200		T100	96
bins_for_gpio_bits[8]	auto[1]	auto[1]	auto[1]	2011442	1			T43	28		T44	34		T45	43
bins_for_gpio_bits[9]	auto[0]	auto[0]	auto[0]	7467105	1			T22	1		T23	1		T24	1
bins_for_gpio_bits[9]	auto[0]	auto[0]	auto[1]	5098392	1			T43	52		T44	41		T45	84
bins_for_gpio_bits[9]	auto[0]	auto[1]	auto[0]	2028880	1			T43	30		T44	24		T45	30
bins_for_gpio_bits[9]	auto[1]	auto[0]	auto[0]	2753711	1			T43	14		T44	50		T52	81
bins_for_gpio_bits[9]	auto[1]	auto[0]	auto[1]	454699	1			T45	50		T99	140		T100	84
bins_for_gpio_bits[9]	auto[1]	auto[1]	auto[1]	2010429	1			T43	34		T44	57		T45	34
bins_for_gpio_bits[10]	auto[0]	auto[0]	auto[0]	7470879	1			T22	1		T23	1		T24	1
bins_for_gpio_bits[10]	auto[0]	auto[0]	auto[1]	5096200	1			T43	48		T44	42		T45	48
bins_for_gpio_bits[10]	auto[0]	auto[1]	auto[0]	2034496	1			T43	20		T44	48		T45	58
bins_for_gpio_bits[10]	auto[1]	auto[0]	auto[0]	2746796	1			T43	24		T44	42		T52	60
bins_for_gpio_bits[10]	auto[1]	auto[0]	auto[1]	452639	1			T45	38		T99	194		T100	77
bins_for_gpio_bits[10]	auto[1]	auto[1]	auto[1]	2012206	1			T43	20		T44	45		T45	54
bins_for_gpio_bits[11]	auto[0]	auto[0]	auto[0]	7455041	1			T22	1		T23	1		T24	1
bins_for_gpio_bits[11]	auto[0]	auto[0]	auto[1]	5095943	1			T43	46		T44	37		T45	80
bins_for_gpio_bits[11]	auto[0]	auto[1]	auto[0]	2032763	1			T43	14		T44	52		T45	54
bins_for_gpio_bits[11]	auto[1]	auto[0]	auto[0]	2764555	1			T43	30		T44	48		T52	78
bins_for_gpio_bits[11]	auto[1]	auto[0]	auto[1]	455798	1			T45	28		T99	190		T100	84
bins_for_gpio_bits[11]	auto[1]	auto[1]	auto[1]	2009116	1			T43	26		T44	28		T45	39
bins_for_gpio_bits[12]	auto[0]	auto[0]	auto[0]	7473516	1			T22	1		T23	1		T24	1
bins_for_gpio_bits[12]	auto[0]	auto[0]	auto[1]	5081611	1			T43	46		T44	37		T45	53
bins_for_gpio_bits[12]	auto[0]	auto[1]	auto[0]	2032396	1			T43	16		T44	43		T45	72
bins_for_gpio_bits[12]	auto[1]	auto[0]	auto[0]	2760004	1			T43	32		T44	34		T52	66
bins_for_gpio_bits[12]	auto[1]	auto[0]	auto[1]	455629	1			T45	35		T99	145		T100	103
bins_for_gpio_bits[12]	auto[1]	auto[1]	auto[1]	2010060	1			T43	24		T44	42		T45	40
bins_for_gpio_bits[13]	auto[0]	auto[0]	auto[0]	7471589	1			T22	1		T23	1		T24	1
bins_for_gpio_bits[13]	auto[0]	auto[0]	auto[1]	5089090	1			T43	46		T44	47		T45	55
bins_for_gpio_bits[13]	auto[0]	auto[1]	auto[0]	2031853	1			T43	26		T44	44		T45	50
bins_for_gpio_bits[13]	auto[1]	auto[0]	auto[0]	2748350	1			T43	16		T44	43		T52	70
bins_for_gpio_bits[13]	auto[1]	auto[0]	auto[1]	454597	1			T45	36		T99	159		T100	83
bins_for_gpio_bits[13]	auto[1]	auto[1]	auto[1]	2017737	1			T43	39		T44	48		T45	55
bins_for_gpio_bits[14]	auto[0]	auto[0]	auto[0]	7461090	1			T22	1		T23	1		T24	1
bins_for_gpio_bits[14]	auto[0]	auto[0]	auto[1]	5087493	1			T43	44		T44	42		T45	64
bins_for_gpio_bits[14]	auto[0]	auto[1]	auto[0]	2030651	1			T43	28		T44	53		T45	22
bins_for_gpio_bits[14]	auto[1]	auto[0]	auto[0]	2758380	1			T43	27		T44	32		T52	72
bins_for_gpio_bits[14]	auto[1]	auto[0]	auto[1]	454344	1			T45	60		T99	157		T100	91
bins_for_gpio_bits[14]	auto[1]	auto[1]	auto[1]	2021258	1			T43	16		T44	12		T45	55
bins_for_gpio_bits[15]	auto[0]	auto[0]	auto[0]	7474808	1			T22	1		T23	1		T24	1
bins_for_gpio_bits[15]	auto[0]	auto[0]	auto[1]	5086342	1			T43	46		T44	47		T45	49
bins_for_gpio_bits[15]	auto[0]	auto[1]	auto[0]	2029801	1			T43	17		T44	36		T45	42
bins_for_gpio_bits[15]	auto[1]	auto[0]	auto[0]	2760616	1			T43	32		T44	31		T52	66
bins_for_gpio_bits[15]	auto[1]	auto[0]	auto[1]	450913	1			T45	50		T99	138		T100	83
bins_for_gpio_bits[15]	auto[1]	auto[1]	auto[1]	2010736	1			T43	36		T44	48		T45	54
bins_for_gpio_bits[16]	auto[0]	auto[0]	auto[0]	7478538	1			T22	1		T23	1		T24	1
bins_for_gpio_bits[16]	auto[0]	auto[0]	auto[1]	5086788	1			T43	52		T44	44		T45	65
bins_for_gpio_bits[16]	auto[0]	auto[1]	auto[0]	2024028	1			T43	28		T44	42		T45	30
bins_for_gpio_bits[16]	auto[1]	auto[0]	auto[0]	2763919	1			T43	20		T44	25		T52	56
bins_for_gpio_bits[16]	auto[1]	auto[0]	auto[1]	455686	1			T45	54		T99	130		T100	95
bins_for_gpio_bits[16]	auto[1]	auto[1]	auto[1]	2004257	1			T43	16		T44	38		T45	50
bins_for_gpio_bits[17]	auto[0]	auto[0]	auto[0]	7479921	1			T22	1		T23	1		T24	1
bins_for_gpio_bits[17]	auto[0]	auto[0]	auto[1]	5095534	1			T43	47		T44	48		T45	63
bins_for_gpio_bits[17]	auto[0]	auto[1]	auto[0]	2026214	1			T43	28		T44	38		T45	52
bins_for_gpio_bits[17]	auto[1]	auto[0]	auto[0]	2756842	1			T43	40		T44	32		T52	62
bins_for_gpio_bits[17]	auto[1]	auto[0]	auto[1]	451813	1			T45	39		T99	160		T100	74
bins_for_gpio_bits[17]	auto[1]	auto[1]	auto[1]	2002892	1			T43	8		T44	51		T45	44
bins_for_gpio_bits[18]	auto[0]	auto[0]	auto[0]	7483169	1			T22	1		T23	1		T24	1
bins_for_gpio_bits[18]	auto[0]	auto[0]	auto[1]	5087152	1			T43	48		T44	45		T45	76
bins_for_gpio_bits[18]	auto[0]	auto[1]	auto[0]	2023481	1			T43	23		T44	32		T45	34
bins_for_gpio_bits[18]	auto[1]	auto[0]	auto[0]	2760179	1			T43	38		T44	74		T52	78
bins_for_gpio_bits[18]	auto[1]	auto[0]	auto[1]	453858	1			T45	45		T99	149		T100	86
bins_for_gpio_bits[18]	auto[1]	auto[1]	auto[1]	2005377	1			T43	18		T44	33		T45	46
bins_for_gpio_bits[19]	auto[0]	auto[0]	auto[0]	7484326	1			T22	1		T23	1		T24	1
bins_for_gpio_bits[19]	auto[0]	auto[0]	auto[1]	5088676	1			T43	48		T44	34		T45	59
bins_for_gpio_bits[19]	auto[0]	auto[1]	auto[0]	2021854	1			T43	32		T44	40		T45	46
bins_for_gpio_bits[19]	auto[1]	auto[0]	auto[0]	2758121	1			T43	16		T44	42		T52	56
bins_for_gpio_bits[19]	auto[1]	auto[0]	auto[1]	454044	1			T45	50		T99	136		T100	93
bins_for_gpio_bits[19]	auto[1]	auto[1]	auto[1]	2006195	1			T43	20		T44	29		T45	46
bins_for_gpio_bits[20]	auto[0]	auto[0]	auto[0]	7482154	1			T22	1		T23	1		T24	1
bins_for_gpio_bits[20]	auto[0]	auto[0]	auto[1]	5090461	1			T43	51		T44	46		T45	61
bins_for_gpio_bits[20]	auto[0]	auto[1]	auto[0]	2027269	1			T43	32		T44	40		T45	39
bins_for_gpio_bits[20]	auto[1]	auto[0]	auto[0]	2752594	1			T43	28		T44	28		T52	64
bins_for_gpio_bits[20]	auto[1]	auto[0]	auto[1]	453546	1			T45	38		T99	159		T100	104
bins_for_gpio_bits[20]	auto[1]	auto[1]	auto[1]	2007192	1			T43	20		T44	44		T45	58
bins_for_gpio_bits[21]	auto[0]	auto[0]	auto[0]	7465376	1			T22	1		T23	1		T24	1
bins_for_gpio_bits[21]	auto[0]	auto[0]	auto[1]	5092579	1			T43	46		T44	46		T45	56
bins_for_gpio_bits[21]	auto[0]	auto[1]	auto[0]	2020617	1			T43	18		T44	24		T45	32
bins_for_gpio_bits[21]	auto[1]	auto[0]	auto[0]	2767485	1			T43	21		T44	52		T52	62
bins_for_gpio_bits[21]	auto[1]	auto[0]	auto[1]	456524	1			T45	64		T99	153		T100	111
bins_for_gpio_bits[21]	auto[1]	auto[1]	auto[1]	2010635	1			T43	22		T44	56		T45	48
bins_for_gpio_bits[22]	auto[0]	auto[0]	auto[0]	7469625	1			T22	1		T23	1		T24	1
bins_for_gpio_bits[22]	auto[0]	auto[0]	auto[1]	5095968	1			T43	50		T44	57		T45	80
bins_for_gpio_bits[22]	auto[0]	auto[1]	auto[0]	2027851	1			T43	36		T44	26		T45	40
bins_for_gpio_bits[22]	auto[1]	auto[0]	auto[0]	2760507	1			T43	15		T44	48		T52	53
bins_for_gpio_bits[22]	auto[1]	auto[0]	auto[1]	454971	1			T45	42		T99	166		T100	121
bins_for_gpio_bits[22]	auto[1]	auto[1]	auto[1]	2004294	1			T43	16		T44	51		T45	37
bins_for_gpio_bits[23]	auto[0]	auto[0]	auto[0]	7468851	1			T22	1		T23	1		T24	1
bins_for_gpio_bits[23]	auto[0]	auto[0]	auto[1]	5092753	1			T43	44		T44	41		T45	79
bins_for_gpio_bits[23]	auto[0]	auto[1]	auto[0]	2021222	1			T43	28		T44	50		T45	64
bins_for_gpio_bits[23]	auto[1]	auto[0]	auto[0]	2764769	1			T43	26		T44	40		T52	64
bins_for_gpio_bits[23]	auto[1]	auto[0]	auto[1]	456248	1			T45	24		T99	188		T100	118
bins_for_gpio_bits[23]	auto[1]	auto[1]	auto[1]	2009373	1			T43	21		T44	31		T45	32
bins_for_gpio_bits[24]	auto[0]	auto[0]	auto[0]	7488219	1			T22	1		T23	1		T24	1
bins_for_gpio_bits[24]	auto[0]	auto[0]	auto[1]	5089637	1			T43	43		T44	41		T45	57
bins_for_gpio_bits[24]	auto[0]	auto[1]	auto[0]	2022776	1			T43	24		T44	35		T45	61
bins_for_gpio_bits[24]	auto[1]	auto[0]	auto[0]	2758153	1			T43	23		T44	66		T52	56
bins_for_gpio_bits[24]	auto[1]	auto[0]	auto[1]	456120	1			T45	36		T99	140		T100	77
bins_for_gpio_bits[24]	auto[1]	auto[1]	auto[1]	1998311	1			T43	36		T44	22		T45	44
bins_for_gpio_bits[25]	auto[0]	auto[0]	auto[0]	7464381	1			T22	1		T23	1		T24	1
bins_for_gpio_bits[25]	auto[0]	auto[0]	auto[1]	5097038	1			T43	53		T44	38		T45	69
bins_for_gpio_bits[25]	auto[0]	auto[1]	auto[0]	2024709	1			T43	32		T44	35		T45	35
bins_for_gpio_bits[25]	auto[1]	auto[0]	auto[0]	2765225	1			T43	19		T44	38		T52	45
bins_for_gpio_bits[25]	auto[1]	auto[0]	auto[1]	453845	1			T45	42		T99	178		T100	100
bins_for_gpio_bits[25]	auto[1]	auto[1]	auto[1]	2008018	1			T43	20		T44	38		T45	50
bins_for_gpio_bits[26]	auto[0]	auto[0]	auto[0]	7473025	1			T22	1		T23	1		T24	1
bins_for_gpio_bits[26]	auto[0]	auto[0]	auto[1]	5100242	1			T43	51		T44	43		T45	52
bins_for_gpio_bits[26]	auto[0]	auto[1]	auto[0]	2027492	1			T43	20		T44	28		T45	50
bins_for_gpio_bits[26]	auto[1]	auto[0]	auto[0]	2752967	1			T43	18		T44	47		T52	48
bins_for_gpio_bits[26]	auto[1]	auto[0]	auto[1]	452125	1			T45	38		T99	155		T100	97
bins_for_gpio_bits[26]	auto[1]	auto[1]	auto[1]	2007365	1			T43	17		T44	52		T45	58
bins_for_gpio_bits[27]	auto[0]	auto[0]	auto[0]	7459252	1			T22	1		T23	1		T24	1
bins_for_gpio_bits[27]	auto[0]	auto[0]	auto[1]	5106492	1			T43	46		T44	53		T45	55
bins_for_gpio_bits[27]	auto[0]	auto[1]	auto[0]	2031338	1			T43	18		T44	44		T45	48
bins_for_gpio_bits[27]	auto[1]	auto[0]	auto[0]	2763757	1			T43	25		T44	44		T52	60
bins_for_gpio_bits[27]	auto[1]	auto[0]	auto[1]	454154	1			T45	36		T99	149		T100	104
bins_for_gpio_bits[27]	auto[1]	auto[1]	auto[1]	1998223	1			T43	26		T44	32		T45	60
bins_for_gpio_bits[28]	auto[0]	auto[0]	auto[0]	7482966	1			T22	1		T23	1		T24	1
bins_for_gpio_bits[28]	auto[0]	auto[0]	auto[1]	5081306	1			T43	46		T44	30		T45	60
bins_for_gpio_bits[28]	auto[0]	auto[1]	auto[0]	2019164	1			T43	16		T44	37		T45	48
bins_for_gpio_bits[28]	auto[1]	auto[0]	auto[0]	2767752	1			T43	30		T44	36		T52	42
bins_for_gpio_bits[28]	auto[1]	auto[0]	auto[1]	454317	1			T45	42		T99	160		T100	92
bins_for_gpio_bits[28]	auto[1]	auto[1]	auto[1]	2007711	1			T43	37		T44	40		T45	49
bins_for_gpio_bits[29]	auto[0]	auto[0]	auto[0]	7470997	1			T22	1		T23	1		T24	1
bins_for_gpio_bits[29]	auto[0]	auto[0]	auto[1]	5097596	1			T43	50		T44	41		T45	89
bins_for_gpio_bits[29]	auto[0]	auto[1]	auto[0]	2025559	1			T43	30		T44	36		T45	50
bins_for_gpio_bits[29]	auto[1]	auto[0]	auto[0]	2758616	1			T43	21		T44	51		T52	66
bins_for_gpio_bits[29]	auto[1]	auto[0]	auto[1]	454894	1			T45	30		T99	188		T100	94
bins_for_gpio_bits[29]	auto[1]	auto[1]	auto[1]	2005554	1			T43	18		T44	28		T45	34
bins_for_gpio_bits[30]	auto[0]	auto[0]	auto[0]	7478290	1			T22	1		T23	1		T24	1
bins_for_gpio_bits[30]	auto[0]	auto[0]	auto[1]	5092173	1			T43	45		T44	43		T45	49
bins_for_gpio_bits[30]	auto[0]	auto[1]	auto[0]	2020638	1			T43	37		T44	32		T45	50
bins_for_gpio_bits[30]	auto[1]	auto[0]	auto[0]	2762919	1			T43	20		T44	46		T52	63
bins_for_gpio_bits[30]	auto[1]	auto[0]	auto[1]	454919	1			T45	40		T99	141		T100	92
bins_for_gpio_bits[30]	auto[1]	auto[1]	auto[1]	2004277	1			T43	24		T44	29		T45	59
bins_for_gpio_bits[31]	auto[0]	auto[0]	auto[0]	7477267	1			T22	1		T23	1		T24	1
bins_for_gpio_bits[31]	auto[0]	auto[0]	auto[1]	5089872	1			T43	50		T44	36		T45	89
bins_for_gpio_bits[31]	auto[0]	auto[1]	auto[0]	2025222	1			T43	24		T44	38		T45	32
bins_for_gpio_bits[31]	auto[1]	auto[0]	auto[0]	2760664	1			T43	18		T44	25		T52	60
bins_for_gpio_bits[31]	auto[1]	auto[0]	auto[1]	453279	1			T45	42		T99	178		T100	125
bins_for_gpio_bits[31]	auto[1]	auto[1]	auto[1]	2006912	1			T43	37		T44	58		T45	41

User Defined Cross Bins for cp_cross_all

Excluded/Illegal bins

NAME	COUNT	STATUS
data_oe_1_data_out_0_data_in_1	0	Illegal
data_oe_1_data_out_1_data_in_0	0	Illegal