Unified Coverage Report :: Group :: gpio_env_pkg::gpio_env_cov::gpio_pins_data_in_cross_cg

Group : gpio_env_pkg::gpio_env_cov::gpio_pins_data_in_cross_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_gpio_env_0.1/gpio_env_cov.sv

---

Summary for Group gpio_env_pkg::gpio_env_cov::gpio_pins_data_in_cross_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	36	0	36	100.00
Crosses	128	0	128	100.00

Variables for Group gpio_env_pkg::gpio_env_cov::gpio_pins_data_in_cross_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_pin	32	0	32	100.00	100	1	1	0
data_in	2	0	2	100.00	100	1	1	2
gpio_value	2	0	2	100.00	100	1	1	2

Crosses for Group gpio_env_pkg::gpio_env_cov::gpio_pins_data_in_cross_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_cross_pins_data_in	128	0	128	100.00	100	1	1	0

Summary for Variable cp_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	32	0	32	100.00

User Defined Bins for cp_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
bins_for_gpio_bits[0]	19813216	1			T22	1		T23	1		T24	1
bins_for_gpio_bits[1]	19813216	1			T22	1		T23	1		T24	1
bins_for_gpio_bits[2]	19813216	1			T22	1		T23	1		T24	1
bins_for_gpio_bits[3]	19813216	1			T22	1		T23	1		T24	1
bins_for_gpio_bits[4]	19813216	1			T22	1		T23	1		T24	1
bins_for_gpio_bits[5]	19813216	1			T22	1		T23	1		T24	1
bins_for_gpio_bits[6]	19813216	1			T22	1		T23	1		T24	1
bins_for_gpio_bits[7]	19813216	1			T22	1		T23	1		T24	1
bins_for_gpio_bits[8]	19813216	1			T22	1		T23	1		T24	1
bins_for_gpio_bits[9]	19813216	1			T22	1		T23	1		T24	1
bins_for_gpio_bits[10]	19813216	1			T22	1		T23	1		T24	1
bins_for_gpio_bits[11]	19813216	1			T22	1		T23	1		T24	1
bins_for_gpio_bits[12]	19813216	1			T22	1		T23	1		T24	1
bins_for_gpio_bits[13]	19813216	1			T22	1		T23	1		T24	1
bins_for_gpio_bits[14]	19813216	1			T22	1		T23	1		T24	1
bins_for_gpio_bits[15]	19813216	1			T22	1		T23	1		T24	1
bins_for_gpio_bits[16]	19813216	1			T22	1		T23	1		T24	1
bins_for_gpio_bits[17]	19813216	1			T22	1		T23	1		T24	1
bins_for_gpio_bits[18]	19813216	1			T22	1		T23	1		T24	1
bins_for_gpio_bits[19]	19813216	1			T22	1		T23	1		T24	1
bins_for_gpio_bits[20]	19813216	1			T22	1		T23	1		T24	1
bins_for_gpio_bits[21]	19813216	1			T22	1		T23	1		T24	1
bins_for_gpio_bits[22]	19813216	1			T22	1		T23	1		T24	1
bins_for_gpio_bits[23]	19813216	1			T22	1		T23	1		T24	1
bins_for_gpio_bits[24]	19813216	1			T22	1		T23	1		T24	1
bins_for_gpio_bits[25]	19813216	1			T22	1		T23	1		T24	1
bins_for_gpio_bits[26]	19813216	1			T22	1		T23	1		T24	1
bins_for_gpio_bits[27]	19813216	1			T22	1		T23	1		T24	1
bins_for_gpio_bits[28]	19813216	1			T22	1		T23	1		T24	1
bins_for_gpio_bits[29]	19813216	1			T22	1		T23	1		T24	1
bins_for_gpio_bits[30]	19813216	1			T22	1		T23	1		T24	1
bins_for_gpio_bits[31]	19813216	1			T22	1		T23	1		T24	1

---

Summary for Variable data_in

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for data_in

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

392247673

1

T22

32

T23

32

T24

32

auto[1]

241775239

1

T43

2317

T44

2607

T45

4931

---

Summary for Variable gpio_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for gpio_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

392237096

1

T22

32

T23

32

T24

32

auto[1]

241785816

1

T25

236

T27

28

T1

8

---

Summary for Cross cp_cross_pins_data_in

Samples crossed: cp_pin gpio_value data_in

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	128	0	128	100.00

Automatically Generated Cross Bins for cp_cross_pins_data_in

Bins

cp_pin	gpio_value	data_in	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
bins_for_gpio_bits[0]	auto[0]	auto[0]	11896298	1			T22	1		T23	1		T24	1
bins_for_gpio_bits[0]	auto[0]	auto[1]	359262	1			T43	5		T44	10		T45	12
bins_for_gpio_bits[0]	auto[1]	auto[0]	359584	1			T25	8		T11	5		T12	7
bins_for_gpio_bits[0]	auto[1]	auto[1]	7198072	1			T43	66		T44	81		T45	129
bins_for_gpio_bits[1]	auto[0]	auto[0]	11888457	1			T22	1		T23	1		T24	1
bins_for_gpio_bits[1]	auto[0]	auto[1]	360367	1			T43	7		T44	9		T45	9
bins_for_gpio_bits[1]	auto[1]	auto[0]	360662	1			T25	6		T27	2		T11	12
bins_for_gpio_bits[1]	auto[1]	auto[1]	7203730	1			T43	59		T44	70		T45	159
bins_for_gpio_bits[2]	auto[0]	auto[0]	11903691	1			T22	1		T23	1		T24	1
bins_for_gpio_bits[2]	auto[0]	auto[1]	360442	1			T43	8		T44	9		T45	13
bins_for_gpio_bits[2]	auto[1]	auto[0]	360746	1			T25	6		T11	12		T12	6
bins_for_gpio_bits[2]	auto[1]	auto[1]	7188337	1			T43	78		T44	57		T45	143
bins_for_gpio_bits[3]	auto[0]	auto[0]	11895859	1			T22	1		T23	1		T24	1
bins_for_gpio_bits[3]	auto[0]	auto[1]	359357	1			T43	7		T44	9		T45	10
bins_for_gpio_bits[3]	auto[1]	auto[0]	359692	1			T25	10		T27	1		T11	14
bins_for_gpio_bits[3]	auto[1]	auto[1]	7198308	1			T43	75		T44	73		T45	148
bins_for_gpio_bits[4]	auto[0]	auto[0]	11892051	1			T22	1		T23	1		T24	1
bins_for_gpio_bits[4]	auto[0]	auto[1]	359518	1			T43	5		T44	9		T45	11
bins_for_gpio_bits[4]	auto[1]	auto[0]	359852	1			T25	9		T27	2		T11	3
bins_for_gpio_bits[4]	auto[1]	auto[1]	7201795	1			T43	78		T44	66		T45	126
bins_for_gpio_bits[5]	auto[0]	auto[0]	11892851	1			T22	1		T23	1		T24	1
bins_for_gpio_bits[5]	auto[0]	auto[1]	359999	1			T43	6		T44	12		T45	11
bins_for_gpio_bits[5]	auto[1]	auto[0]	360321	1			T25	7		T27	2		T11	6
bins_for_gpio_bits[5]	auto[1]	auto[1]	7200045	1			T43	57		T44	59		T45	153
bins_for_gpio_bits[6]	auto[0]	auto[0]	11890663	1			T22	1		T23	1		T24	1
bins_for_gpio_bits[6]	auto[0]	auto[1]	360199	1			T43	6		T44	12		T45	10
bins_for_gpio_bits[6]	auto[1]	auto[0]	360540	1			T25	8		T27	2		T1	1
bins_for_gpio_bits[6]	auto[1]	auto[1]	7201814	1			T43	44		T44	69		T45	149
bins_for_gpio_bits[7]	auto[0]	auto[0]	11888995	1			T22	1		T23	1		T24	1
bins_for_gpio_bits[7]	auto[0]	auto[1]	360111	1			T43	9		T44	12		T45	12
bins_for_gpio_bits[7]	auto[1]	auto[0]	360491	1			T25	6		T11	16		T12	5
bins_for_gpio_bits[7]	auto[1]	auto[1]	7203619	1			T43	78		T44	82		T45	139
bins_for_gpio_bits[8]	auto[0]	auto[0]	11899261	1			T22	1		T23	1		T24	1
bins_for_gpio_bits[8]	auto[0]	auto[1]	359802	1			T43	8		T44	11		T45	9
bins_for_gpio_bits[8]	auto[1]	auto[0]	360119	1			T25	4		T27	3		T11	3
bins_for_gpio_bits[8]	auto[1]	auto[1]	7194034	1			T43	72		T44	66		T45	150
bins_for_gpio_bits[9]	auto[0]	auto[0]	11889377	1			T22	1		T23	1		T24	1
bins_for_gpio_bits[9]	auto[0]	auto[1]	359996	1			T43	6		T44	11		T45	9
bins_for_gpio_bits[9]	auto[1]	auto[0]	360319	1			T25	7		T12	6		T13	1
bins_for_gpio_bits[9]	auto[1]	auto[1]	7203524	1			T43	80		T44	87		T45	159
bins_for_gpio_bits[10]	auto[0]	auto[0]	11892303	1			T22	1		T23	1		T24	1
bins_for_gpio_bits[10]	auto[0]	auto[1]	359517	1			T43	5		T44	10		T45	13
bins_for_gpio_bits[10]	auto[1]	auto[0]	359868	1			T25	7		T27	3		T11	7
bins_for_gpio_bits[10]	auto[1]	auto[1]	7201528	1			T43	63		T44	77		T45	127
bins_for_gpio_bits[11]	auto[0]	auto[0]	11892546	1			T22	1		T23	1		T24	1
bins_for_gpio_bits[11]	auto[0]	auto[1]	359499	1			T43	7		T44	6		T45	9
bins_for_gpio_bits[11]	auto[1]	auto[0]	359813	1			T25	7		T27	3		T11	8
bins_for_gpio_bits[11]	auto[1]	auto[1]	7201358	1			T43	65		T44	59		T45	138
bins_for_gpio_bits[12]	auto[0]	auto[0]	11905887	1			T22	1		T23	1		T24	1
bins_for_gpio_bits[12]	auto[0]	auto[1]	359698	1			T43	6		T44	11		T45	10
bins_for_gpio_bits[12]	auto[1]	auto[0]	360029	1			T25	6		T1	1		T11	3
bins_for_gpio_bits[12]	auto[1]	auto[1]	7187602	1			T43	64		T44	68		T45	118
bins_for_gpio_bits[13]	auto[0]	auto[0]	11890860	1			T22	1		T23	1		T24	1
bins_for_gpio_bits[13]	auto[0]	auto[1]	360609	1			T43	8		T44	11		T45	14
bins_for_gpio_bits[13]	auto[1]	auto[0]	360932	1			T25	10		T11	14		T12	9
bins_for_gpio_bits[13]	auto[1]	auto[1]	7200815	1			T43	77		T44	84		T45	132
bins_for_gpio_bits[14]	auto[0]	auto[0]	11889568	1			T22	1		T23	1		T24	1
bins_for_gpio_bits[14]	auto[0]	auto[1]	360225	1			T43	6		T44	4		T45	7
bins_for_gpio_bits[14]	auto[1]	auto[0]	360553	1			T25	10		T11	9		T12	1
bins_for_gpio_bits[14]	auto[1]	auto[1]	7202870	1			T43	54		T44	50		T45	172
bins_for_gpio_bits[15]	auto[0]	auto[0]	11904659	1			T22	1		T23	1		T24	1
bins_for_gpio_bits[15]	auto[0]	auto[1]	360203	1			T43	6		T44	10		T45	13
bins_for_gpio_bits[15]	auto[1]	auto[0]	360566	1			T25	6		T27	1		T11	16
bins_for_gpio_bits[15]	auto[1]	auto[1]	7187788	1			T43	76		T44	85		T45	140
bins_for_gpio_bits[16]	auto[0]	auto[0]	11905524	1			T22	1		T23	1		T24	1
bins_for_gpio_bits[16]	auto[0]	auto[1]	360616	1			T43	6		T44	7		T45	11
bins_for_gpio_bits[16]	auto[1]	auto[0]	360961	1			T25	8		T11	3		T12	6
bins_for_gpio_bits[16]	auto[1]	auto[1]	7186115	1			T43	62		T44	75		T45	158
bins_for_gpio_bits[17]	auto[0]	auto[0]	11903088	1			T22	1		T23	1		T24	1
bins_for_gpio_bits[17]	auto[0]	auto[1]	359576	1			T43	4		T44	9		T45	12
bins_for_gpio_bits[17]	auto[1]	auto[0]	359889	1			T25	8		T1	1		T11	2
bins_for_gpio_bits[17]	auto[1]	auto[1]	7190663	1			T43	51		T44	90		T45	134
bins_for_gpio_bits[18]	auto[0]	auto[0]	11906992	1			T22	1		T23	1		T24	1
bins_for_gpio_bits[18]	auto[0]	auto[1]	359529	1			T43	4		T44	10		T45	12
bins_for_gpio_bits[18]	auto[1]	auto[0]	359837	1			T25	4		T11	21		T12	6
bins_for_gpio_bits[18]	auto[1]	auto[1]	7186858	1			T43	62		T44	68		T45	155
bins_for_gpio_bits[19]	auto[0]	auto[0]	11903740	1			T22	1		T23	1		T24	1
bins_for_gpio_bits[19]	auto[0]	auto[1]	360202	1			T43	6		T44	9		T45	12
bins_for_gpio_bits[19]	auto[1]	auto[0]	360561	1			T25	9		T1	1		T11	9
bins_for_gpio_bits[19]	auto[1]	auto[1]	7188713	1			T43	62		T44	54		T45	143
bins_for_gpio_bits[20]	auto[0]	auto[0]	11902356	1			T22	1		T23	1		T24	1
bins_for_gpio_bits[20]	auto[0]	auto[1]	359319	1			T43	7		T44	6		T45	8
bins_for_gpio_bits[20]	auto[1]	auto[0]	359661	1			T25	8		T11	4		T12	6
bins_for_gpio_bits[20]	auto[1]	auto[1]	7191880	1			T43	64		T44	84		T45	149
bins_for_gpio_bits[21]	auto[0]	auto[0]	11892640	1			T22	1		T23	1		T24	1
bins_for_gpio_bits[21]	auto[0]	auto[1]	360496	1			T43	5		T44	13		T45	10
bins_for_gpio_bits[21]	auto[1]	auto[0]	360838	1			T25	5		T27	1		T11	14
bins_for_gpio_bits[21]	auto[1]	auto[1]	7199242	1			T43	63		T44	89		T45	158
bins_for_gpio_bits[22]	auto[0]	auto[0]	11897802	1			T22	1		T23	1		T24	1
bins_for_gpio_bits[22]	auto[0]	auto[1]	359848	1			T43	6		T44	9		T45	11
bins_for_gpio_bits[22]	auto[1]	auto[0]	360181	1			T25	6		T11	15		T12	5
bins_for_gpio_bits[22]	auto[1]	auto[1]	7195385	1			T43	60		T44	99		T45	148
bins_for_gpio_bits[23]	auto[0]	auto[0]	11894299	1			T22	1		T23	1		T24	1
bins_for_gpio_bits[23]	auto[0]	auto[1]	360173	1			T43	5		T44	11		T45	11
bins_for_gpio_bits[23]	auto[1]	auto[0]	360543	1			T25	5		T27	3		T1	1
bins_for_gpio_bits[23]	auto[1]	auto[1]	7198201	1			T43	60		T44	61		T45	124
bins_for_gpio_bits[24]	auto[0]	auto[0]	11909943	1			T22	1		T23	1		T24	1
bins_for_gpio_bits[24]	auto[0]	auto[1]	358882	1			T43	8		T44	7		T45	12
bins_for_gpio_bits[24]	auto[1]	auto[0]	359205	1			T25	5		T11	16		T12	9
bins_for_gpio_bits[24]	auto[1]	auto[1]	7185186	1			T43	71		T44	56		T45	125
bins_for_gpio_bits[25]	auto[0]	auto[0]	11894641	1			T22	1		T23	1		T24	1
bins_for_gpio_bits[25]	auto[0]	auto[1]	359401	1			T43	3		T44	10		T45	12
bins_for_gpio_bits[25]	auto[1]	auto[0]	359674	1			T25	6		T27	1		T11	10
bins_for_gpio_bits[25]	auto[1]	auto[1]	7199500	1			T43	70		T44	66		T45	149
bins_for_gpio_bits[26]	auto[0]	auto[0]	11893682	1			T22	1		T23	1		T24	1
bins_for_gpio_bits[26]	auto[0]	auto[1]	359512	1			T43	4		T44	12		T45	13
bins_for_gpio_bits[26]	auto[1]	auto[0]	359802	1			T25	10		T27	1		T11	6
bins_for_gpio_bits[26]	auto[1]	auto[1]	7200220	1			T43	64		T44	83		T45	135
bins_for_gpio_bits[27]	auto[0]	auto[0]	11893768	1			T22	1		T23	1		T24	1
bins_for_gpio_bits[27]	auto[0]	auto[1]	360234	1			T43	7		T44	11		T45	16
bins_for_gpio_bits[27]	auto[1]	auto[0]	360579	1			T25	7		T27	1		T11	7
bins_for_gpio_bits[27]	auto[1]	auto[1]	7198635	1			T43	65		T44	74		T45	135
bins_for_gpio_bits[28]	auto[0]	auto[0]	11908924	1			T22	1		T23	1		T24	1
bins_for_gpio_bits[28]	auto[0]	auto[1]	360646	1			T43	7		T44	12		T45	13
bins_for_gpio_bits[28]	auto[1]	auto[0]	360958	1			T25	12		T1	1		T12	10
bins_for_gpio_bits[28]	auto[1]	auto[1]	7182688	1			T43	76		T44	58		T45	138
bins_for_gpio_bits[29]	auto[0]	auto[0]	11894427	1			T22	1		T23	1		T24	1
bins_for_gpio_bits[29]	auto[0]	auto[1]	360365	1			T43	5		T44	8		T45	12
bins_for_gpio_bits[29]	auto[1]	auto[0]	360745	1			T25	6		T11	14		T12	5
bins_for_gpio_bits[29]	auto[1]	auto[1]	7197679	1			T43	63		T44	61		T45	141
bins_for_gpio_bits[30]	auto[0]	auto[0]	11901727	1			T22	1		T23	1		T24	1
bins_for_gpio_bits[30]	auto[0]	auto[1]	359816	1			T43	7		T44	9		T45	13
bins_for_gpio_bits[30]	auto[1]	auto[0]	360120	1			T25	9		T1	1		T11	5
bins_for_gpio_bits[30]	auto[1]	auto[1]	7191553	1			T43	62		T44	63		T45	135
bins_for_gpio_bits[31]	auto[0]	auto[0]	11902526	1			T22	1		T23	1		T24	1
bins_for_gpio_bits[31]	auto[0]	auto[1]	360272	1			T43	8		T44	10		T45	12
bins_for_gpio_bits[31]	auto[1]	auto[0]	360627	1			T25	11		T27	2		T1	1
bins_for_gpio_bits[31]	auto[1]	auto[1]	7189791	1			T43	79		T44	84		T45	160