Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11107812 |
1 |
|
|
T22 |
1 |
|
T23 |
13 |
|
T24 |
4 |
| auto[1] |
9015648 |
1 |
|
|
T23 |
17 |
|
T24 |
17 |
|
T25 |
11 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
18946465 |
1 |
|
|
T22 |
1 |
|
T23 |
30 |
|
T24 |
21 |
| auto[1] |
1176995 |
1 |
|
|
T4 |
1 |
|
T87 |
7 |
|
T8 |
3 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11096092 |
1 |
|
|
T22 |
1 |
|
T23 |
30 |
|
T24 |
21 |
| auto[1] |
9027368 |
1 |
|
|
T25 |
11 |
|
T27 |
4 |
|
T11 |
25 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
3935145 |
1 |
|
|
T25 |
6 |
|
T11 |
25 |
|
T12 |
6 |
| auto[1] |
auto[0] |
auto[1] |
590249 |
1 |
|
|
T87 |
1 |
|
T8 |
3 |
|
T38 |
8247 |
| auto[1] |
auto[1] |
auto[0] |
3915228 |
1 |
|
|
T25 |
5 |
|
T27 |
4 |
|
T12 |
1 |
| auto[1] |
auto[1] |
auto[1] |
586746 |
1 |
|
|
T4 |
1 |
|
T87 |
6 |
|
T89 |
2 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11076166 |
1 |
|
|
T22 |
1 |
|
T23 |
21 |
|
T24 |
11 |
| auto[1] |
9047294 |
1 |
|
|
T23 |
9 |
|
T24 |
10 |
|
T25 |
13 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
18954847 |
1 |
|
|
T22 |
1 |
|
T23 |
30 |
|
T24 |
21 |
| auto[1] |
1168613 |
1 |
|
|
T27 |
1 |
|
T11 |
4 |
|
T72 |
1 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11142036 |
1 |
|
|
T22 |
1 |
|
T23 |
30 |
|
T24 |
21 |
| auto[1] |
8981424 |
1 |
|
|
T25 |
11 |
|
T27 |
4 |
|
T1 |
1 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
3910272 |
1 |
|
|
T25 |
6 |
|
T27 |
3 |
|
T11 |
20 |
| auto[1] |
auto[0] |
auto[1] |
585056 |
1 |
|
|
T27 |
1 |
|
T11 |
4 |
|
T72 |
1 |
| auto[1] |
auto[1] |
auto[0] |
3902539 |
1 |
|
|
T25 |
5 |
|
T1 |
1 |
|
T12 |
3 |
| auto[1] |
auto[1] |
auto[1] |
583557 |
1 |
|
|
T88 |
2 |
|
T89 |
2 |
|
T38 |
8902 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11080571 |
1 |
|
|
T22 |
1 |
|
T23 |
24 |
|
T24 |
13 |
| auto[1] |
9042889 |
1 |
|
|
T23 |
6 |
|
T24 |
8 |
|
T25 |
14 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
18945564 |
1 |
|
|
T22 |
1 |
|
T23 |
30 |
|
T24 |
21 |
| auto[1] |
1177896 |
1 |
|
|
T11 |
4 |
|
T72 |
1 |
|
T87 |
5 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11093642 |
1 |
|
|
T22 |
1 |
|
T23 |
30 |
|
T24 |
21 |
| auto[1] |
9029818 |
1 |
|
|
T25 |
5 |
|
T11 |
29 |
|
T12 |
8 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
3909259 |
1 |
|
|
T25 |
2 |
|
T11 |
9 |
|
T12 |
4 |
| auto[1] |
auto[0] |
auto[1] |
585986 |
1 |
|
|
T11 |
4 |
|
T87 |
2 |
|
T88 |
4 |
| auto[1] |
auto[1] |
auto[0] |
3942663 |
1 |
|
|
T25 |
3 |
|
T11 |
16 |
|
T12 |
4 |
| auto[1] |
auto[1] |
auto[1] |
591910 |
1 |
|
|
T72 |
1 |
|
T87 |
3 |
|
T38 |
8962 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11106055 |
1 |
|
|
T22 |
1 |
|
T23 |
11 |
|
T24 |
7 |
| auto[1] |
9017405 |
1 |
|
|
T23 |
19 |
|
T24 |
14 |
|
T25 |
11 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
18940380 |
1 |
|
|
T22 |
1 |
|
T23 |
30 |
|
T24 |
21 |
| auto[1] |
1183080 |
1 |
|
|
T27 |
1 |
|
T11 |
1 |
|
T87 |
2 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11043458 |
1 |
|
|
T22 |
1 |
|
T23 |
30 |
|
T24 |
21 |
| auto[1] |
9080002 |
1 |
|
|
T25 |
10 |
|
T27 |
4 |
|
T11 |
9 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
3950254 |
1 |
|
|
T25 |
7 |
|
T11 |
4 |
|
T12 |
9 |
| auto[1] |
auto[0] |
auto[1] |
592880 |
1 |
|
|
T11 |
1 |
|
T38 |
9124 |
|
T96 |
14 |
| auto[1] |
auto[1] |
auto[0] |
3946668 |
1 |
|
|
T25 |
3 |
|
T27 |
3 |
|
T11 |
4 |
| auto[1] |
auto[1] |
auto[1] |
590200 |
1 |
|
|
T27 |
1 |
|
T87 |
2 |
|
T73 |
1 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11118043 |
1 |
|
|
T22 |
1 |
|
T23 |
21 |
|
T24 |
17 |
| auto[1] |
9005417 |
1 |
|
|
T23 |
9 |
|
T24 |
4 |
|
T25 |
12 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
18946850 |
1 |
|
|
T22 |
1 |
|
T23 |
30 |
|
T24 |
21 |
| auto[1] |
1176610 |
1 |
|
|
T38 |
17227 |
|
T96 |
16 |
|
T97 |
37 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11101342 |
1 |
|
|
T22 |
1 |
|
T23 |
30 |
|
T24 |
21 |
| auto[1] |
9022118 |
1 |
|
|
T25 |
10 |
|
T27 |
4 |
|
T1 |
1 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
3932816 |
1 |
|
|
T25 |
4 |
|
T1 |
1 |
|
T11 |
20 |
| auto[1] |
auto[0] |
auto[1] |
588402 |
1 |
|
|
T38 |
8026 |
|
T96 |
3 |
|
T97 |
13 |
| auto[1] |
auto[1] |
auto[0] |
3912692 |
1 |
|
|
T25 |
6 |
|
T27 |
4 |
|
T12 |
3 |
| auto[1] |
auto[1] |
auto[1] |
588208 |
1 |
|
|
T38 |
9201 |
|
T96 |
13 |
|
T97 |
24 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11101235 |
1 |
|
|
T22 |
1 |
|
T23 |
15 |
|
T24 |
12 |
| auto[1] |
9022225 |
1 |
|
|
T23 |
15 |
|
T24 |
9 |
|
T25 |
10 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
18945824 |
1 |
|
|
T22 |
1 |
|
T23 |
30 |
|
T24 |
21 |
| auto[1] |
1177636 |
1 |
|
|
T11 |
7 |
|
T72 |
1 |
|
T89 |
1 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11092843 |
1 |
|
|
T22 |
1 |
|
T23 |
30 |
|
T24 |
21 |
| auto[1] |
9030617 |
1 |
|
|
T25 |
6 |
|
T27 |
4 |
|
T11 |
24 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
3917114 |
1 |
|
|
T25 |
5 |
|
T27 |
4 |
|
T11 |
12 |
| auto[1] |
auto[0] |
auto[1] |
586949 |
1 |
|
|
T11 |
5 |
|
T89 |
1 |
|
T38 |
9190 |
| auto[1] |
auto[1] |
auto[0] |
3935867 |
1 |
|
|
T25 |
1 |
|
T11 |
5 |
|
T12 |
6 |
| auto[1] |
auto[1] |
auto[1] |
590687 |
1 |
|
|
T11 |
2 |
|
T72 |
1 |
|
T38 |
7614 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11082695 |
1 |
|
|
T22 |
1 |
|
T23 |
7 |
|
T24 |
12 |
| auto[1] |
9040765 |
1 |
|
|
T23 |
23 |
|
T24 |
9 |
|
T25 |
13 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
18947681 |
1 |
|
|
T22 |
1 |
|
T23 |
30 |
|
T24 |
21 |
| auto[1] |
1175779 |
1 |
|
|
T11 |
4 |
|
T87 |
3 |
|
T101 |
1 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11105978 |
1 |
|
|
T22 |
1 |
|
T23 |
30 |
|
T24 |
21 |
| auto[1] |
9017482 |
1 |
|
|
T25 |
10 |
|
T1 |
1 |
|
T11 |
24 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
3925667 |
1 |
|
|
T25 |
3 |
|
T1 |
1 |
|
T11 |
20 |
| auto[1] |
auto[0] |
auto[1] |
588958 |
1 |
|
|
T11 |
4 |
|
T101 |
1 |
|
T38 |
8528 |
| auto[1] |
auto[1] |
auto[0] |
3916036 |
1 |
|
|
T25 |
7 |
|
T12 |
3 |
|
T14 |
5 |
| auto[1] |
auto[1] |
auto[1] |
586821 |
1 |
|
|
T87 |
3 |
|
T89 |
6 |
|
T38 |
8514 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11109434 |
1 |
|
|
T22 |
1 |
|
T23 |
19 |
|
T24 |
15 |
| auto[1] |
9014026 |
1 |
|
|
T23 |
11 |
|
T24 |
6 |
|
T25 |
12 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
18949481 |
1 |
|
|
T22 |
1 |
|
T23 |
30 |
|
T24 |
21 |
| auto[1] |
1173979 |
1 |
|
|
T11 |
2 |
|
T88 |
2 |
|
T89 |
1 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11111867 |
1 |
|
|
T22 |
1 |
|
T23 |
30 |
|
T24 |
21 |
| auto[1] |
9011593 |
1 |
|
|
T25 |
12 |
|
T11 |
9 |
|
T12 |
11 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
3929188 |
1 |
|
|
T25 |
6 |
|
T11 |
7 |
|
T12 |
6 |
| auto[1] |
auto[0] |
auto[1] |
590510 |
1 |
|
|
T11 |
2 |
|
T88 |
2 |
|
T73 |
1 |
| auto[1] |
auto[1] |
auto[0] |
3908426 |
1 |
|
|
T25 |
6 |
|
T12 |
5 |
|
T14 |
2 |
| auto[1] |
auto[1] |
auto[1] |
583469 |
1 |
|
|
T89 |
1 |
|
T38 |
8382 |
|
T96 |
16 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11080939 |
1 |
|
|
T22 |
1 |
|
T23 |
8 |
|
T24 |
13 |
| auto[1] |
9042521 |
1 |
|
|
T23 |
22 |
|
T24 |
8 |
|
T25 |
11 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
18957788 |
1 |
|
|
T22 |
1 |
|
T23 |
30 |
|
T24 |
21 |
| auto[1] |
1165672 |
1 |
|
|
T11 |
1 |
|
T4 |
1 |
|
T87 |
2 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11179797 |
1 |
|
|
T22 |
1 |
|
T23 |
30 |
|
T24 |
21 |
| auto[1] |
8943663 |
1 |
|
|
T25 |
10 |
|
T1 |
1 |
|
T11 |
25 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
3877116 |
1 |
|
|
T25 |
5 |
|
T1 |
1 |
|
T11 |
13 |
| auto[1] |
auto[0] |
auto[1] |
581018 |
1 |
|
|
T87 |
2 |
|
T38 |
8947 |
|
T96 |
13 |
| auto[1] |
auto[1] |
auto[0] |
3900875 |
1 |
|
|
T25 |
5 |
|
T11 |
11 |
|
T12 |
2 |
| auto[1] |
auto[1] |
auto[1] |
584654 |
1 |
|
|
T11 |
1 |
|
T4 |
1 |
|
T88 |
1 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11080642 |
1 |
|
|
T22 |
1 |
|
T23 |
18 |
|
T24 |
1 |
| auto[1] |
9042818 |
1 |
|
|
T23 |
12 |
|
T24 |
20 |
|
T25 |
11 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
18951358 |
1 |
|
|
T22 |
1 |
|
T23 |
30 |
|
T24 |
21 |
| auto[1] |
1172102 |
1 |
|
|
T11 |
2 |
|
T4 |
2 |
|
T87 |
4 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11111863 |
1 |
|
|
T22 |
1 |
|
T23 |
30 |
|
T24 |
21 |
| auto[1] |
9011597 |
1 |
|
|
T25 |
10 |
|
T1 |
1 |
|
T11 |
24 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
3920812 |
1 |
|
|
T25 |
7 |
|
T11 |
22 |
|
T12 |
4 |
| auto[1] |
auto[0] |
auto[1] |
584528 |
1 |
|
|
T11 |
2 |
|
T4 |
1 |
|
T8 |
1 |
| auto[1] |
auto[1] |
auto[0] |
3918683 |
1 |
|
|
T25 |
3 |
|
T1 |
1 |
|
T12 |
3 |
| auto[1] |
auto[1] |
auto[1] |
587574 |
1 |
|
|
T4 |
1 |
|
T87 |
4 |
|
T38 |
7820 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11095646 |
1 |
|
|
T22 |
1 |
|
T23 |
3 |
|
T24 |
4 |
| auto[1] |
9027814 |
1 |
|
|
T23 |
27 |
|
T24 |
17 |
|
T25 |
9 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
18946283 |
1 |
|
|
T22 |
1 |
|
T23 |
30 |
|
T24 |
21 |
| auto[1] |
1177177 |
1 |
|
|
T11 |
5 |
|
T87 |
1 |
|
T101 |
1 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11099840 |
1 |
|
|
T22 |
1 |
|
T23 |
30 |
|
T24 |
21 |
| auto[1] |
9023620 |
1 |
|
|
T25 |
9 |
|
T27 |
4 |
|
T11 |
25 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
3942616 |
1 |
|
|
T25 |
7 |
|
T11 |
20 |
|
T12 |
2 |
| auto[1] |
auto[0] |
auto[1] |
592190 |
1 |
|
|
T11 |
5 |
|
T87 |
1 |
|
T74 |
1 |
| auto[1] |
auto[1] |
auto[0] |
3903827 |
1 |
|
|
T25 |
2 |
|
T27 |
4 |
|
T12 |
3 |
| auto[1] |
auto[1] |
auto[1] |
584987 |
1 |
|
|
T101 |
1 |
|
T38 |
7885 |
|
T96 |
11 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11111472 |
1 |
|
|
T22 |
1 |
|
T23 |
19 |
|
T24 |
1 |
| auto[1] |
9011988 |
1 |
|
|
T23 |
11 |
|
T24 |
20 |
|
T25 |
12 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
18947483 |
1 |
|
|
T22 |
1 |
|
T23 |
30 |
|
T24 |
21 |
| auto[1] |
1175977 |
1 |
|
|
T88 |
3 |
|
T89 |
3 |
|
T73 |
1 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11101020 |
1 |
|
|
T22 |
1 |
|
T23 |
30 |
|
T24 |
21 |
| auto[1] |
9022440 |
1 |
|
|
T25 |
9 |
|
T12 |
7 |
|
T14 |
5 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
3922183 |
1 |
|
|
T25 |
4 |
|
T12 |
6 |
|
T14 |
3 |
| auto[1] |
auto[0] |
auto[1] |
586414 |
1 |
|
|
T88 |
3 |
|
T73 |
1 |
|
T38 |
8344 |
| auto[1] |
auto[1] |
auto[0] |
3924280 |
1 |
|
|
T25 |
5 |
|
T12 |
1 |
|
T14 |
2 |
| auto[1] |
auto[1] |
auto[1] |
589563 |
1 |
|
|
T89 |
3 |
|
T38 |
7787 |
|
T96 |
9 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11079649 |
1 |
|
|
T22 |
1 |
|
T23 |
11 |
|
T24 |
7 |
| auto[1] |
9043811 |
1 |
|
|
T23 |
19 |
|
T24 |
14 |
|
T25 |
13 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
18937594 |
1 |
|
|
T22 |
1 |
|
T23 |
30 |
|
T24 |
21 |
| auto[1] |
1185866 |
1 |
|
|
T87 |
1 |
|
T38 |
16552 |
|
T96 |
22 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11032072 |
1 |
|
|
T22 |
1 |
|
T23 |
30 |
|
T24 |
21 |
| auto[1] |
9091388 |
1 |
|
|
T25 |
10 |
|
T12 |
11 |
|
T14 |
8 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
3936934 |
1 |
|
|
T25 |
6 |
|
T12 |
6 |
|
T14 |
3 |
| auto[1] |
auto[0] |
auto[1] |
590706 |
1 |
|
|
T87 |
1 |
|
T38 |
8113 |
|
T96 |
13 |
| auto[1] |
auto[1] |
auto[0] |
3968588 |
1 |
|
|
T25 |
4 |
|
T12 |
5 |
|
T14 |
5 |
| auto[1] |
auto[1] |
auto[1] |
595160 |
1 |
|
|
T38 |
8439 |
|
T96 |
9 |
|
T97 |
17 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11127961 |
1 |
|
|
T22 |
1 |
|
T23 |
16 |
|
T24 |
11 |
| auto[1] |
8995499 |
1 |
|
|
T23 |
14 |
|
T24 |
10 |
|
T25 |
9 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
18948216 |
1 |
|
|
T22 |
1 |
|
T23 |
30 |
|
T24 |
21 |
| auto[1] |
1175244 |
1 |
|
|
T8 |
2 |
|
T38 |
15247 |
|
T96 |
27 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11111228 |
1 |
|
|
T22 |
1 |
|
T23 |
30 |
|
T24 |
21 |
| auto[1] |
9012232 |
1 |
|
|
T25 |
9 |
|
T27 |
4 |
|
T11 |
20 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
3925233 |
1 |
|
|
T25 |
4 |
|
T11 |
20 |
|
T12 |
5 |
| auto[1] |
auto[0] |
auto[1] |
590228 |
1 |
|
|
T8 |
2 |
|
T38 |
7676 |
|
T96 |
14 |
| auto[1] |
auto[1] |
auto[0] |
3911755 |
1 |
|
|
T25 |
5 |
|
T27 |
4 |
|
T12 |
5 |
| auto[1] |
auto[1] |
auto[1] |
585016 |
1 |
|
|
T38 |
7571 |
|
T96 |
13 |
|
T97 |
8 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11107385 |
1 |
|
|
T22 |
1 |
|
T23 |
8 |
|
T24 |
8 |
| auto[1] |
9016075 |
1 |
|
|
T23 |
22 |
|
T24 |
13 |
|
T25 |
10 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
18947068 |
1 |
|
|
T22 |
1 |
|
T23 |
30 |
|
T24 |
21 |
| auto[1] |
1176392 |
1 |
|
|
T27 |
1 |
|
T11 |
3 |
|
T87 |
5 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11101809 |
1 |
|
|
T22 |
1 |
|
T23 |
30 |
|
T24 |
21 |
| auto[1] |
9021651 |
1 |
|
|
T25 |
4 |
|
T27 |
4 |
|
T1 |
1 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
3934033 |
1 |
|
|
T25 |
3 |
|
T27 |
3 |
|
T11 |
11 |
| auto[1] |
auto[0] |
auto[1] |
590177 |
1 |
|
|
T27 |
1 |
|
T11 |
2 |
|
T101 |
1 |
| auto[1] |
auto[1] |
auto[0] |
3911226 |
1 |
|
|
T25 |
1 |
|
T1 |
1 |
|
T11 |
6 |
| auto[1] |
auto[1] |
auto[1] |
586215 |
1 |
|
|
T11 |
1 |
|
T87 |
5 |
|
T89 |
4 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11093064 |
1 |
|
|
T22 |
1 |
|
T23 |
15 |
|
T24 |
14 |
| auto[1] |
9030396 |
1 |
|
|
T23 |
15 |
|
T24 |
7 |
|
T25 |
11 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
18944374 |
1 |
|
|
T22 |
1 |
|
T23 |
30 |
|
T24 |
21 |
| auto[1] |
1179086 |
1 |
|
|
T11 |
5 |
|
T4 |
1 |
|
T72 |
1 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11080362 |
1 |
|
|
T22 |
1 |
|
T23 |
30 |
|
T24 |
21 |
| auto[1] |
9043098 |
1 |
|
|
T25 |
7 |
|
T27 |
4 |
|
T1 |
1 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
3925065 |
1 |
|
|
T25 |
3 |
|
T1 |
1 |
|
T11 |
14 |
| auto[1] |
auto[0] |
auto[1] |
587189 |
1 |
|
|
T11 |
3 |
|
T72 |
1 |
|
T87 |
3 |
| auto[1] |
auto[1] |
auto[0] |
3938947 |
1 |
|
|
T25 |
4 |
|
T27 |
4 |
|
T11 |
5 |
| auto[1] |
auto[1] |
auto[1] |
591897 |
1 |
|
|
T11 |
2 |
|
T4 |
1 |
|
T87 |
2 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11098591 |
1 |
|
|
T22 |
1 |
|
T23 |
14 |
|
T24 |
10 |
| auto[1] |
9024869 |
1 |
|
|
T23 |
16 |
|
T24 |
11 |
|
T25 |
9 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
18946789 |
1 |
|
|
T22 |
1 |
|
T23 |
30 |
|
T24 |
21 |
| auto[1] |
1176671 |
1 |
|
|
T11 |
6 |
|
T8 |
2 |
|
T89 |
2 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11104581 |
1 |
|
|
T22 |
1 |
|
T23 |
30 |
|
T24 |
21 |
| auto[1] |
9018879 |
1 |
|
|
T25 |
10 |
|
T27 |
4 |
|
T1 |
1 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
3924636 |
1 |
|
|
T25 |
7 |
|
T27 |
4 |
|
T11 |
10 |
| auto[1] |
auto[0] |
auto[1] |
589566 |
1 |
|
|
T11 |
3 |
|
T8 |
1 |
|
T89 |
2 |
| auto[1] |
auto[1] |
auto[0] |
3917572 |
1 |
|
|
T25 |
3 |
|
T1 |
1 |
|
T11 |
8 |
| auto[1] |
auto[1] |
auto[1] |
587105 |
1 |
|
|
T11 |
3 |
|
T8 |
1 |
|
T38 |
8401 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11103229 |
1 |
|
|
T22 |
1 |
|
T23 |
23 |
|
T24 |
9 |
| auto[1] |
9020231 |
1 |
|
|
T23 |
7 |
|
T24 |
12 |
|
T25 |
12 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
18951640 |
1 |
|
|
T22 |
1 |
|
T23 |
30 |
|
T24 |
21 |
| auto[1] |
1171820 |
1 |
|
|
T72 |
1 |
|
T88 |
1 |
|
T8 |
1 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11127089 |
1 |
|
|
T22 |
1 |
|
T23 |
30 |
|
T24 |
21 |
| auto[1] |
8996371 |
1 |
|
|
T25 |
8 |
|
T1 |
1 |
|
T12 |
6 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
3920733 |
1 |
|
|
T25 |
3 |
|
T12 |
4 |
|
T14 |
1 |
| auto[1] |
auto[0] |
auto[1] |
585701 |
1 |
|
|
T8 |
1 |
|
T38 |
7628 |
|
T96 |
11 |
| auto[1] |
auto[1] |
auto[0] |
3903818 |
1 |
|
|
T25 |
5 |
|
T1 |
1 |
|
T12 |
2 |
| auto[1] |
auto[1] |
auto[1] |
586119 |
1 |
|
|
T72 |
1 |
|
T88 |
1 |
|
T89 |
1 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11151830 |
1 |
|
|
T22 |
1 |
|
T23 |
22 |
|
T24 |
8 |
| auto[1] |
8971630 |
1 |
|
|
T23 |
8 |
|
T24 |
13 |
|
T25 |
12 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
18947792 |
1 |
|
|
T22 |
1 |
|
T23 |
30 |
|
T24 |
21 |
| auto[1] |
1175668 |
1 |
|
|
T27 |
1 |
|
T4 |
1 |
|
T89 |
4 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11102630 |
1 |
|
|
T22 |
1 |
|
T23 |
30 |
|
T24 |
21 |
| auto[1] |
9020830 |
1 |
|
|
T25 |
8 |
|
T27 |
4 |
|
T12 |
9 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
3944279 |
1 |
|
|
T25 |
3 |
|
T27 |
3 |
|
T12 |
4 |
| auto[1] |
auto[0] |
auto[1] |
591860 |
1 |
|
|
T27 |
1 |
|
T89 |
4 |
|
T38 |
7893 |
| auto[1] |
auto[1] |
auto[0] |
3900883 |
1 |
|
|
T25 |
5 |
|
T12 |
5 |
|
T14 |
3 |
| auto[1] |
auto[1] |
auto[1] |
583808 |
1 |
|
|
T4 |
1 |
|
T38 |
8631 |
|
T96 |
11 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11124349 |
1 |
|
|
T22 |
1 |
|
T23 |
20 |
|
T24 |
12 |
| auto[1] |
8999111 |
1 |
|
|
T23 |
10 |
|
T24 |
9 |
|
T25 |
6 |