Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11106682 |
1 |
|
|
T22 |
1 |
|
T23 |
22 |
|
T24 |
8 |
| auto[1] |
9016778 |
1 |
|
|
T23 |
8 |
|
T24 |
13 |
|
T25 |
6 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
18940953 |
1 |
|
|
T22 |
1 |
|
T23 |
30 |
|
T24 |
21 |
| auto[1] |
1182507 |
1 |
|
|
T89 |
4 |
|
T74 |
3 |
|
T38 |
16518 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11065667 |
1 |
|
|
T22 |
1 |
|
T23 |
30 |
|
T24 |
21 |
| auto[1] |
9057793 |
1 |
|
|
T25 |
11 |
|
T11 |
5 |
|
T12 |
7 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
3937626 |
1 |
|
|
T25 |
8 |
|
T11 |
5 |
|
T12 |
3 |
| auto[1] |
auto[0] |
auto[1] |
591599 |
1 |
|
|
T89 |
4 |
|
T74 |
3 |
|
T38 |
8568 |
| auto[1] |
auto[1] |
auto[0] |
3937660 |
1 |
|
|
T25 |
3 |
|
T12 |
4 |
|
T14 |
2 |
| auto[1] |
auto[1] |
auto[1] |
590908 |
1 |
|
|
T38 |
7950 |
|
T96 |
15 |
|
T97 |
28 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |