Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11137433 |
1 |
|
|
T22 |
1 |
|
T23 |
22 |
|
T24 |
13 |
| auto[1] |
8986027 |
1 |
|
|
T23 |
8 |
|
T24 |
8 |
|
T25 |
15 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
18944417 |
1 |
|
|
T22 |
1 |
|
T23 |
30 |
|
T24 |
21 |
| auto[1] |
1179043 |
1 |
|
|
T27 |
1 |
|
T11 |
3 |
|
T72 |
1 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11079479 |
1 |
|
|
T22 |
1 |
|
T23 |
30 |
|
T24 |
21 |
| auto[1] |
9043981 |
1 |
|
|
T25 |
4 |
|
T27 |
4 |
|
T1 |
1 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
3958101 |
1 |
|
|
T27 |
3 |
|
T11 |
12 |
|
T12 |
5 |
| auto[1] |
auto[0] |
auto[1] |
593711 |
1 |
|
|
T27 |
1 |
|
T11 |
1 |
|
T38 |
7703 |
| auto[1] |
auto[1] |
auto[0] |
3906837 |
1 |
|
|
T25 |
4 |
|
T1 |
1 |
|
T11 |
5 |
| auto[1] |
auto[1] |
auto[1] |
585332 |
1 |
|
|
T11 |
2 |
|
T72 |
1 |
|
T38 |
8501 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |