Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
99.61 99.06 99.10 100.00 99.80 99.68 100.00


Total test records in report: 946
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T772 /workspace/coverage/default/4.gpio_random_long_reg_writes_reg_reads.1029035898 Dec 20 12:29:20 PM PST 23 Dec 20 12:29:47 PM PST 23 39979505 ps
T773 /workspace/coverage/default/46.gpio_intr_rand_pgm.2285958900 Dec 20 12:30:24 PM PST 23 Dec 20 12:31:20 PM PST 23 35831644 ps
T774 /workspace/coverage/default/36.gpio_stress_all_with_rand_reset.2848593094 Dec 20 12:30:02 PM PST 23 Dec 20 12:34:36 PM PST 23 34984564629 ps
T775 /workspace/coverage/default/25.gpio_stress_all.1408924856 Dec 20 12:29:46 PM PST 23 Dec 20 12:31:48 PM PST 23 34334493658 ps
T776 /workspace/coverage/default/14.gpio_smoke_no_pullup_pulldown.2524403408 Dec 20 12:29:12 PM PST 23 Dec 20 12:29:40 PM PST 23 222101047 ps
T777 /workspace/coverage/default/11.gpio_smoke_no_pullup_pulldown.3606740661 Dec 20 12:29:13 PM PST 23 Dec 20 12:29:41 PM PST 23 167317549 ps
T778 /workspace/coverage/default/21.gpio_rand_intr_trigger.1824719834 Dec 20 12:29:54 PM PST 23 Dec 20 12:30:15 PM PST 23 53180692 ps
T779 /workspace/coverage/default/15.gpio_alert_test.2836374766 Dec 20 12:28:58 PM PST 23 Dec 20 12:29:32 PM PST 23 13747361 ps
T780 /workspace/coverage/default/10.gpio_alert_test.1866688165 Dec 20 12:28:51 PM PST 23 Dec 20 12:29:26 PM PST 23 85831198 ps
T781 /workspace/coverage/default/49.gpio_smoke_no_pullup_pulldown.3440891699 Dec 20 12:30:44 PM PST 23 Dec 20 12:31:23 PM PST 23 618234777 ps
T782 /workspace/coverage/default/40.gpio_smoke_no_pullup_pulldown.2309020446 Dec 20 12:30:54 PM PST 23 Dec 20 12:31:36 PM PST 23 41025514 ps
T783 /workspace/coverage/default/43.gpio_filter_stress.1090030281 Dec 20 12:30:37 PM PST 23 Dec 20 12:31:41 PM PST 23 3522268951 ps
T784 /workspace/coverage/default/48.gpio_full_random.2169552595 Dec 20 12:30:37 PM PST 23 Dec 20 12:31:16 PM PST 23 102526431 ps
T785 /workspace/coverage/default/30.gpio_rand_intr_trigger.1472941651 Dec 20 12:30:01 PM PST 23 Dec 20 12:30:49 PM PST 23 88008627 ps
T786 /workspace/coverage/default/20.gpio_full_random.564460831 Dec 20 12:29:52 PM PST 23 Dec 20 12:30:13 PM PST 23 130824835 ps
T787 /workspace/coverage/default/12.gpio_smoke.2199555152 Dec 20 12:29:25 PM PST 23 Dec 20 12:29:49 PM PST 23 68968048 ps
T788 /workspace/coverage/default/8.gpio_random_long_reg_writes_reg_reads.2207345718 Dec 20 12:28:50 PM PST 23 Dec 20 12:29:27 PM PST 23 893930527 ps
T789 /workspace/coverage/default/38.gpio_random_dout_din.409895133 Dec 20 12:30:13 PM PST 23 Dec 20 12:31:09 PM PST 23 67214754 ps
T790 /workspace/coverage/default/32.gpio_random_dout_din.3599765808 Dec 20 12:30:31 PM PST 23 Dec 20 12:31:16 PM PST 23 61074915 ps
T791 /workspace/coverage/default/41.gpio_dout_din_regs_random_rw.2240247508 Dec 20 12:30:30 PM PST 23 Dec 20 12:31:23 PM PST 23 18141820 ps
T792 /workspace/coverage/default/8.gpio_stress_all_with_rand_reset.3715247406 Dec 20 12:28:50 PM PST 23 Dec 20 12:46:52 PM PST 23 174828792959 ps
T793 /workspace/coverage/default/23.gpio_dout_din_regs_random_rw.3463729467 Dec 20 12:29:59 PM PST 23 Dec 20 12:30:45 PM PST 23 46568043 ps
T794 /workspace/coverage/default/10.gpio_smoke.3665752570 Dec 20 12:28:48 PM PST 23 Dec 20 12:29:23 PM PST 23 363495368 ps
T795 /workspace/coverage/default/15.gpio_random_dout_din.345760707 Dec 20 12:28:57 PM PST 23 Dec 20 12:29:32 PM PST 23 244301932 ps
T796 /workspace/coverage/default/39.gpio_alert_test.233423084 Dec 20 12:30:48 PM PST 23 Dec 20 12:31:25 PM PST 23 11400769 ps
T797 /workspace/coverage/default/26.gpio_random_long_reg_writes_reg_reads.2508559159 Dec 20 12:30:10 PM PST 23 Dec 20 12:31:06 PM PST 23 125072491 ps
T798 /workspace/coverage/default/7.gpio_stress_all.2159118697 Dec 20 12:28:49 PM PST 23 Dec 20 12:31:59 PM PST 23 6258144429 ps
T799 /workspace/coverage/default/8.gpio_stress_all.1778090200 Dec 20 12:29:40 PM PST 23 Dec 20 12:30:54 PM PST 23 3989613089 ps
T800 /workspace/coverage/default/41.gpio_stress_all_with_rand_reset.2581515103 Dec 20 12:30:31 PM PST 23 Dec 20 12:55:35 PM PST 23 463205222410 ps
T801 /workspace/coverage/default/49.gpio_filter_stress.3328609292 Dec 20 12:30:31 PM PST 23 Dec 20 12:31:48 PM PST 23 932139560 ps
T802 /workspace/coverage/default/4.gpio_rand_intr_trigger.188409669 Dec 20 12:28:45 PM PST 23 Dec 20 12:29:19 PM PST 23 118630858 ps
T803 /workspace/coverage/default/9.gpio_smoke.2568119576 Dec 20 12:28:50 PM PST 23 Dec 20 12:29:26 PM PST 23 129704181 ps
T804 /workspace/coverage/default/25.gpio_rand_intr_trigger.2594826106 Dec 20 12:29:53 PM PST 23 Dec 20 12:30:15 PM PST 23 212007833 ps
T805 /workspace/coverage/default/22.gpio_smoke_no_pullup_pulldown.3326829704 Dec 20 12:30:29 PM PST 23 Dec 20 12:31:17 PM PST 23 52122053 ps
T806 /workspace/coverage/default/9.gpio_stress_all_with_rand_reset.2852680774 Dec 20 12:28:52 PM PST 23 Dec 20 12:44:26 PM PST 23 633136746577 ps
T807 /workspace/coverage/default/46.gpio_alert_test.2349354667 Dec 20 12:30:50 PM PST 23 Dec 20 12:31:29 PM PST 23 11826415 ps
T808 /workspace/coverage/default/32.gpio_smoke_no_pullup_pulldown.3118110571 Dec 20 12:30:07 PM PST 23 Dec 20 12:31:02 PM PST 23 79154970 ps
T59 /workspace/coverage/default/0.gpio_sec_cm.2786617062 Dec 20 12:28:38 PM PST 23 Dec 20 12:29:11 PM PST 23 89070543 ps
T809 /workspace/coverage/default/47.gpio_intr_with_filter_rand_intr_event.3324532190 Dec 20 12:31:10 PM PST 23 Dec 20 12:32:02 PM PST 23 405940119 ps
T810 /workspace/coverage/default/31.gpio_random_dout_din.399160192 Dec 20 12:30:06 PM PST 23 Dec 20 12:31:05 PM PST 23 186199115 ps
T811 /workspace/coverage/default/47.gpio_stress_all.4197611733 Dec 20 12:30:56 PM PST 23 Dec 20 12:33:27 PM PST 23 17642806440 ps
T812 /workspace/coverage/default/15.gpio_full_random.4233635553 Dec 20 12:28:59 PM PST 23 Dec 20 12:29:33 PM PST 23 46037598 ps
T60 /workspace/coverage/default/4.gpio_sec_cm.2021214542 Dec 20 12:28:35 PM PST 23 Dec 20 12:29:07 PM PST 23 351431502 ps
T813 /workspace/coverage/default/13.gpio_random_dout_din_no_pullup_pulldown.2868716616 Dec 20 12:29:01 PM PST 23 Dec 20 12:29:34 PM PST 23 48441228 ps
T814 /workspace/coverage/default/1.gpio_full_random.1872021580 Dec 20 12:28:34 PM PST 23 Dec 20 12:29:07 PM PST 23 359072850 ps
T815 /workspace/coverage/default/16.gpio_stress_all_with_rand_reset.1698647250 Dec 20 12:28:58 PM PST 23 Dec 20 12:33:41 PM PST 23 15959470467 ps
T816 /workspace/coverage/default/24.gpio_random_dout_din.4078172664 Dec 20 12:30:05 PM PST 23 Dec 20 12:30:54 PM PST 23 41737485 ps
T817 /workspace/coverage/default/19.gpio_alert_test.3684882267 Dec 20 12:29:08 PM PST 23 Dec 20 12:29:37 PM PST 23 13060621 ps
T818 /workspace/coverage/default/13.gpio_rand_intr_trigger.2774465833 Dec 20 12:29:09 PM PST 23 Dec 20 12:29:39 PM PST 23 166287951 ps
T819 /workspace/coverage/default/10.gpio_stress_all_with_rand_reset.1801770021 Dec 20 12:28:52 PM PST 23 Dec 20 12:35:46 PM PST 23 27492081321 ps
T820 /workspace/coverage/default/31.gpio_rand_intr_trigger.41382215 Dec 20 12:30:20 PM PST 23 Dec 20 12:31:22 PM PST 23 1684655319 ps
T821 /workspace/coverage/default/19.gpio_dout_din_regs_random_rw.3846586967 Dec 20 12:29:33 PM PST 23 Dec 20 12:29:55 PM PST 23 32798535 ps
T822 /workspace/coverage/default/27.gpio_smoke.2464935745 Dec 20 12:29:54 PM PST 23 Dec 20 12:30:15 PM PST 23 203392360 ps
T823 /workspace/coverage/default/49.gpio_random_long_reg_writes_reg_reads.2411856816 Dec 20 12:30:41 PM PST 23 Dec 20 12:31:29 PM PST 23 478183236 ps
T824 /workspace/coverage/default/34.gpio_smoke.3987816310 Dec 20 12:30:11 PM PST 23 Dec 20 12:31:06 PM PST 23 91723954 ps
T825 /workspace/coverage/default/39.gpio_smoke.903111386 Dec 20 12:30:27 PM PST 23 Dec 20 12:31:17 PM PST 23 44531194 ps
T826 /workspace/coverage/default/49.gpio_intr_with_filter_rand_intr_event.800896013 Dec 20 12:31:00 PM PST 23 Dec 20 12:31:47 PM PST 23 353987429 ps
T827 /workspace/coverage/default/12.gpio_smoke_no_pullup_pulldown.2672969906 Dec 20 12:28:51 PM PST 23 Dec 20 12:29:27 PM PST 23 134181441 ps
T828 /workspace/coverage/default/41.gpio_intr_rand_pgm.1479176315 Dec 20 12:30:14 PM PST 23 Dec 20 12:31:17 PM PST 23 156734950 ps
T829 /workspace/coverage/default/6.gpio_random_dout_din_no_pullup_pulldown.391954294 Dec 20 12:28:29 PM PST 23 Dec 20 12:29:03 PM PST 23 429125526 ps
T830 /workspace/coverage/default/40.gpio_filter_stress.3516824025 Dec 20 12:30:33 PM PST 23 Dec 20 12:31:41 PM PST 23 706402702 ps
T831 /workspace/coverage/default/45.gpio_intr_with_filter_rand_intr_event.854436067 Dec 20 12:31:08 PM PST 23 Dec 20 12:31:58 PM PST 23 38406101 ps
T832 /workspace/coverage/default/22.gpio_dout_din_regs_random_rw.2775092696 Dec 20 12:30:22 PM PST 23 Dec 20 12:31:27 PM PST 23 36853978 ps
T833 /workspace/coverage/default/44.gpio_smoke_no_pullup_pulldown.1247861973 Dec 20 12:30:31 PM PST 23 Dec 20 12:31:16 PM PST 23 441483751 ps
T834 /workspace/coverage/default/41.gpio_filter_stress.172480545 Dec 20 12:30:31 PM PST 23 Dec 20 12:31:52 PM PST 23 1680637779 ps
T835 /workspace/coverage/default/9.gpio_stress_all.3400839577 Dec 20 12:28:54 PM PST 23 Dec 20 12:31:31 PM PST 23 4688262172 ps
T836 /workspace/coverage/default/14.gpio_stress_all.3444412979 Dec 20 12:29:07 PM PST 23 Dec 20 12:31:37 PM PST 23 5661366036 ps
T837 /workspace/coverage/default/11.gpio_rand_intr_trigger.1046453222 Dec 20 12:28:55 PM PST 23 Dec 20 12:29:32 PM PST 23 157348056 ps
T838 /workspace/coverage/default/18.gpio_smoke_no_pullup_pulldown.2844617505 Dec 20 12:29:08 PM PST 23 Dec 20 12:29:39 PM PST 23 233826393 ps
T839 /workspace/coverage/default/23.gpio_full_random.45509865 Dec 20 12:30:05 PM PST 23 Dec 20 12:30:55 PM PST 23 236751997 ps
T840 /workspace/coverage/default/23.gpio_smoke.3616489745 Dec 20 12:29:54 PM PST 23 Dec 20 12:30:17 PM PST 23 41245022 ps
T841 /workspace/coverage/default/16.gpio_intr_with_filter_rand_intr_event.2361400878 Dec 20 12:29:11 PM PST 23 Dec 20 12:29:42 PM PST 23 85340953 ps
T842 /workspace/coverage/default/0.gpio_filter_stress.3201143021 Dec 20 12:28:32 PM PST 23 Dec 20 12:29:10 PM PST 23 217220043 ps
T843 /workspace/coverage/default/6.gpio_random_dout_din.243627914 Dec 20 12:28:41 PM PST 23 Dec 20 12:29:14 PM PST 23 28773129 ps
T844 /workspace/coverage/default/0.gpio_random_dout_din_no_pullup_pulldown.3943076423 Dec 20 12:28:35 PM PST 23 Dec 20 12:29:08 PM PST 23 40791327 ps
T845 /workspace/coverage/default/23.gpio_intr_with_filter_rand_intr_event.2366342562 Dec 20 12:30:09 PM PST 23 Dec 20 12:31:06 PM PST 23 209989316 ps
T846 /workspace/coverage/default/32.gpio_random_long_reg_writes_reg_reads.1029923299 Dec 20 12:30:26 PM PST 23 Dec 20 12:31:20 PM PST 23 658636150 ps
T847 /workspace/coverage/cover_reg_top/12.gpio_tl_intg_err.3708158936 Dec 20 12:27:13 PM PST 23 Dec 20 12:27:50 PM PST 23 143581678 ps
T35 /workspace/coverage/cover_reg_top/16.gpio_tl_intg_err.272647530 Dec 20 12:27:37 PM PST 23 Dec 20 12:28:13 PM PST 23 123017740 ps
T77 /workspace/coverage/cover_reg_top/4.gpio_csr_aliasing.2684145309 Dec 20 12:27:26 PM PST 23 Dec 20 12:28:06 PM PST 23 97550038 ps
T36 /workspace/coverage/cover_reg_top/2.gpio_tl_intg_err.1654774202 Dec 20 12:29:17 PM PST 23 Dec 20 12:29:43 PM PST 23 135341656 ps
T32 /workspace/coverage/cover_reg_top/8.gpio_tl_intg_err.3313330063 Dec 20 12:27:34 PM PST 23 Dec 20 12:28:11 PM PST 23 237688637 ps
T848 /workspace/coverage/cover_reg_top/15.gpio_tl_intg_err.3277821530 Dec 20 12:27:23 PM PST 23 Dec 20 12:28:03 PM PST 23 46136735 ps
T849 /workspace/coverage/cover_reg_top/35.gpio_intr_test.3127313561 Dec 20 12:27:52 PM PST 23 Dec 20 12:28:28 PM PST 23 26763113 ps
T850 /workspace/coverage/cover_reg_top/15.gpio_csr_rw.3624458398 Dec 20 12:27:23 PM PST 23 Dec 20 12:28:03 PM PST 23 11522335 ps
T851 /workspace/coverage/cover_reg_top/3.gpio_csr_rw.2840057391 Dec 20 12:27:13 PM PST 23 Dec 20 12:27:50 PM PST 23 52481115 ps
T852 /workspace/coverage/cover_reg_top/3.gpio_csr_aliasing.2608120260 Dec 20 12:27:10 PM PST 23 Dec 20 12:27:45 PM PST 23 20227978 ps
T853 /workspace/coverage/cover_reg_top/18.gpio_intr_test.4454617 Dec 20 12:27:49 PM PST 23 Dec 20 12:28:30 PM PST 23 15059990 ps
T854 /workspace/coverage/cover_reg_top/1.gpio_csr_hw_reset.1488666696 Dec 20 12:27:15 PM PST 23 Dec 20 12:27:52 PM PST 23 163373590 ps
T855 /workspace/coverage/cover_reg_top/4.gpio_csr_hw_reset.3162154617 Dec 20 12:27:10 PM PST 23 Dec 20 12:27:43 PM PST 23 34731067 ps
T856 /workspace/coverage/cover_reg_top/11.gpio_csr_rw.1724663736 Dec 20 12:27:11 PM PST 23 Dec 20 12:27:46 PM PST 23 18988298 ps
T857 /workspace/coverage/cover_reg_top/4.gpio_csr_bit_bash.3613967704 Dec 20 12:29:01 PM PST 23 Dec 20 12:29:36 PM PST 23 160453361 ps
T858 /workspace/coverage/cover_reg_top/16.gpio_csr_mem_rw_with_rand_reset.2590973647 Dec 20 12:27:42 PM PST 23 Dec 20 12:28:17 PM PST 23 149252472 ps
T90 /workspace/coverage/cover_reg_top/11.gpio_same_csr_outstanding.1887101868 Dec 20 12:27:16 PM PST 23 Dec 20 12:27:54 PM PST 23 43585159 ps
T859 /workspace/coverage/cover_reg_top/1.gpio_intr_test.3396030180 Dec 20 12:29:13 PM PST 23 Dec 20 12:29:40 PM PST 23 14527807 ps
T91 /workspace/coverage/cover_reg_top/6.gpio_same_csr_outstanding.4002470436 Dec 20 12:27:17 PM PST 23 Dec 20 12:27:56 PM PST 23 73501176 ps
T860 /workspace/coverage/cover_reg_top/2.gpio_intr_test.1615426443 Dec 20 12:27:08 PM PST 23 Dec 20 12:27:39 PM PST 23 14677605 ps
T861 /workspace/coverage/cover_reg_top/0.gpio_csr_hw_reset.180269137 Dec 20 12:27:21 PM PST 23 Dec 20 12:28:01 PM PST 23 27800958 ps
T98 /workspace/coverage/cover_reg_top/18.gpio_tl_intg_err.3573603377 Dec 20 12:27:49 PM PST 23 Dec 20 12:28:24 PM PST 23 99882785 ps
T862 /workspace/coverage/cover_reg_top/13.gpio_csr_rw.1528512798 Dec 20 12:27:15 PM PST 23 Dec 20 12:27:52 PM PST 23 40534380 ps
T863 /workspace/coverage/cover_reg_top/1.gpio_csr_mem_rw_with_rand_reset.4094287022 Dec 20 12:28:55 PM PST 23 Dec 20 12:29:31 PM PST 23 18836892 ps
T864 /workspace/coverage/cover_reg_top/4.gpio_csr_mem_rw_with_rand_reset.3979332848 Dec 20 12:29:15 PM PST 23 Dec 20 12:29:42 PM PST 23 45601194 ps
T33 /workspace/coverage/cover_reg_top/17.gpio_tl_intg_err.575559401 Dec 20 12:27:39 PM PST 23 Dec 20 12:28:14 PM PST 23 186107362 ps
T865 /workspace/coverage/cover_reg_top/26.gpio_intr_test.3133028415 Dec 20 12:28:00 PM PST 23 Dec 20 12:28:39 PM PST 23 17937197 ps
T866 /workspace/coverage/cover_reg_top/13.gpio_intr_test.2146568938 Dec 20 12:27:15 PM PST 23 Dec 20 12:27:53 PM PST 23 33398118 ps
T867 /workspace/coverage/cover_reg_top/9.gpio_tl_intg_err.1224903910 Dec 20 12:27:40 PM PST 23 Dec 20 12:28:15 PM PST 23 47285159 ps
T868 /workspace/coverage/cover_reg_top/12.gpio_tl_errors.439762411 Dec 20 12:27:16 PM PST 23 Dec 20 12:27:56 PM PST 23 140106030 ps
T42 /workspace/coverage/cover_reg_top/11.gpio_tl_intg_err.2110116048 Dec 20 12:27:43 PM PST 23 Dec 20 12:28:18 PM PST 23 82499754 ps
T869 /workspace/coverage/cover_reg_top/1.gpio_tl_errors.76568346 Dec 20 12:27:41 PM PST 23 Dec 20 12:28:17 PM PST 23 170314095 ps
T870 /workspace/coverage/cover_reg_top/4.gpio_csr_rw.227617705 Dec 20 12:27:25 PM PST 23 Dec 20 12:28:05 PM PST 23 50141168 ps
T871 /workspace/coverage/cover_reg_top/7.gpio_intr_test.4163551994 Dec 20 12:29:38 PM PST 23 Dec 20 12:29:58 PM PST 23 52957520 ps
T872 /workspace/coverage/cover_reg_top/0.gpio_csr_mem_rw_with_rand_reset.544634644 Dec 20 12:28:50 PM PST 23 Dec 20 12:29:25 PM PST 23 19372771 ps
T873 /workspace/coverage/cover_reg_top/31.gpio_intr_test.963241809 Dec 20 12:27:47 PM PST 23 Dec 20 12:28:22 PM PST 23 88886598 ps
T874 /workspace/coverage/cover_reg_top/37.gpio_intr_test.4213278830 Dec 20 12:28:20 PM PST 23 Dec 20 12:28:56 PM PST 23 24135655 ps
T875 /workspace/coverage/cover_reg_top/16.gpio_intr_test.1846527832 Dec 20 12:27:28 PM PST 23 Dec 20 12:28:07 PM PST 23 15357740 ps
T876 /workspace/coverage/cover_reg_top/45.gpio_intr_test.2286805578 Dec 20 12:27:52 PM PST 23 Dec 20 12:28:28 PM PST 23 38508840 ps
T877 /workspace/coverage/cover_reg_top/4.gpio_intr_test.2502728654 Dec 20 12:29:22 PM PST 23 Dec 20 12:29:46 PM PST 23 21054899 ps
T92 /workspace/coverage/cover_reg_top/13.gpio_same_csr_outstanding.294918254 Dec 20 12:27:29 PM PST 23 Dec 20 12:28:08 PM PST 23 41074437 ps
T878 /workspace/coverage/cover_reg_top/3.gpio_tl_intg_err.2577159149 Dec 20 12:27:29 PM PST 23 Dec 20 12:28:08 PM PST 23 323886809 ps
T879 /workspace/coverage/cover_reg_top/8.gpio_intr_test.932697605 Dec 20 12:27:08 PM PST 23 Dec 20 12:27:40 PM PST 23 21822824 ps
T880 /workspace/coverage/cover_reg_top/2.gpio_same_csr_outstanding.2230323025 Dec 20 12:29:16 PM PST 23 Dec 20 12:29:42 PM PST 23 407126105 ps
T881 /workspace/coverage/cover_reg_top/14.gpio_intr_test.758270549 Dec 20 12:27:33 PM PST 23 Dec 20 12:28:10 PM PST 23 22170404 ps
T78 /workspace/coverage/cover_reg_top/6.gpio_csr_rw.3099719173 Dec 20 12:27:18 PM PST 23 Dec 20 12:27:58 PM PST 23 11902081 ps
T882 /workspace/coverage/cover_reg_top/19.gpio_tl_intg_err.2193260087 Dec 20 12:27:51 PM PST 23 Dec 20 12:28:27 PM PST 23 113008194 ps
T883 /workspace/coverage/cover_reg_top/41.gpio_intr_test.140819410 Dec 20 12:27:48 PM PST 23 Dec 20 12:28:23 PM PST 23 10448717 ps
T80 /workspace/coverage/cover_reg_top/0.gpio_csr_bit_bash.165786441 Dec 20 12:27:05 PM PST 23 Dec 20 12:27:38 PM PST 23 156755260 ps
T884 /workspace/coverage/cover_reg_top/18.gpio_csr_rw.4024916794 Dec 20 12:27:41 PM PST 23 Dec 20 12:28:16 PM PST 23 54800121 ps
T885 /workspace/coverage/cover_reg_top/19.gpio_tl_errors.3973757336 Dec 20 12:27:51 PM PST 23 Dec 20 12:28:28 PM PST 23 219916204 ps
T886 /workspace/coverage/cover_reg_top/6.gpio_tl_errors.101011646 Dec 20 12:29:12 PM PST 23 Dec 20 12:29:42 PM PST 23 256607551 ps
T81 /workspace/coverage/cover_reg_top/2.gpio_csr_rw.1348744731 Dec 20 12:29:32 PM PST 23 Dec 20 12:29:53 PM PST 23 17911496 ps
T887 /workspace/coverage/cover_reg_top/25.gpio_intr_test.2476550747 Dec 20 12:27:44 PM PST 23 Dec 20 12:28:18 PM PST 23 67611265 ps
T888 /workspace/coverage/cover_reg_top/13.gpio_tl_intg_err.2985850815 Dec 20 12:27:39 PM PST 23 Dec 20 12:28:14 PM PST 23 140218022 ps
T889 /workspace/coverage/cover_reg_top/13.gpio_csr_mem_rw_with_rand_reset.2797414395 Dec 20 12:27:12 PM PST 23 Dec 20 12:27:49 PM PST 23 20487087 ps
T890 /workspace/coverage/cover_reg_top/0.gpio_intr_test.2047335915 Dec 20 12:29:16 PM PST 23 Dec 20 12:29:41 PM PST 23 39334523 ps
T891 /workspace/coverage/cover_reg_top/11.gpio_intr_test.1264492323 Dec 20 12:27:36 PM PST 23 Dec 20 12:28:11 PM PST 23 38815301 ps
T892 /workspace/coverage/cover_reg_top/48.gpio_intr_test.2495963056 Dec 20 12:27:50 PM PST 23 Dec 20 12:28:26 PM PST 23 26318999 ps
T893 /workspace/coverage/cover_reg_top/10.gpio_csr_mem_rw_with_rand_reset.232322138 Dec 20 12:27:45 PM PST 23 Dec 20 12:28:20 PM PST 23 24659225 ps
T894 /workspace/coverage/cover_reg_top/3.gpio_csr_bit_bash.2024820634 Dec 20 12:27:13 PM PST 23 Dec 20 12:27:51 PM PST 23 92605978 ps
T895 /workspace/coverage/cover_reg_top/18.gpio_csr_mem_rw_with_rand_reset.1286952752 Dec 20 12:27:58 PM PST 23 Dec 20 12:28:36 PM PST 23 88494628 ps
T896 /workspace/coverage/cover_reg_top/12.gpio_same_csr_outstanding.1564159606 Dec 20 12:27:39 PM PST 23 Dec 20 12:28:14 PM PST 23 152824123 ps
T897 /workspace/coverage/cover_reg_top/10.gpio_same_csr_outstanding.1705842834 Dec 20 12:27:43 PM PST 23 Dec 20 12:28:18 PM PST 23 26703800 ps
T898 /workspace/coverage/cover_reg_top/16.gpio_tl_errors.2606045519 Dec 20 12:27:25 PM PST 23 Dec 20 12:28:06 PM PST 23 280074107 ps
T899 /workspace/coverage/cover_reg_top/10.gpio_intr_test.2500374297 Dec 20 12:27:49 PM PST 23 Dec 20 12:28:24 PM PST 23 17727946 ps
T900 /workspace/coverage/cover_reg_top/7.gpio_csr_mem_rw_with_rand_reset.3825747469 Dec 20 12:29:01 PM PST 23 Dec 20 12:29:34 PM PST 23 346365357 ps
T901 /workspace/coverage/cover_reg_top/34.gpio_intr_test.2759836870 Dec 20 12:27:43 PM PST 23 Dec 20 12:28:17 PM PST 23 52351131 ps
T902 /workspace/coverage/cover_reg_top/2.gpio_csr_hw_reset.308776150 Dec 20 12:27:08 PM PST 23 Dec 20 12:27:39 PM PST 23 15672986 ps
T903 /workspace/coverage/cover_reg_top/20.gpio_intr_test.1287354575 Dec 20 12:27:50 PM PST 23 Dec 20 12:28:25 PM PST 23 53214492 ps
T904 /workspace/coverage/cover_reg_top/4.gpio_tl_errors.1975912073 Dec 20 12:27:20 PM PST 23 Dec 20 12:28:01 PM PST 23 344541967 ps
T905 /workspace/coverage/cover_reg_top/28.gpio_intr_test.3559157766 Dec 20 12:28:11 PM PST 23 Dec 20 12:28:52 PM PST 23 25989663 ps
T906 /workspace/coverage/cover_reg_top/1.gpio_tl_intg_err.1011197862 Dec 20 12:29:12 PM PST 23 Dec 20 12:29:40 PM PST 23 80608177 ps
T907 /workspace/coverage/cover_reg_top/36.gpio_intr_test.2868953956 Dec 20 12:27:51 PM PST 23 Dec 20 12:28:27 PM PST 23 11671063 ps
T908 /workspace/coverage/cover_reg_top/1.gpio_same_csr_outstanding.120749803 Dec 20 12:28:45 PM PST 23 Dec 20 12:29:19 PM PST 23 19025876 ps
T82 /workspace/coverage/cover_reg_top/0.gpio_csr_rw.3975405469 Dec 20 12:27:21 PM PST 23 Dec 20 12:28:01 PM PST 23 12733771 ps
T909 /workspace/coverage/cover_reg_top/46.gpio_intr_test.1915385687 Dec 20 12:27:43 PM PST 23 Dec 20 12:28:18 PM PST 23 14959301 ps
T910 /workspace/coverage/cover_reg_top/3.gpio_intr_test.3975090989 Dec 20 12:27:10 PM PST 23 Dec 20 12:27:53 PM PST 23 15076528 ps
T911 /workspace/coverage/cover_reg_top/17.gpio_intr_test.491418280 Dec 20 12:27:51 PM PST 23 Dec 20 12:28:27 PM PST 23 14526936 ps
T912 /workspace/coverage/cover_reg_top/15.gpio_intr_test.1977027719 Dec 20 12:27:44 PM PST 23 Dec 20 12:28:18 PM PST 23 45297400 ps
T913 /workspace/coverage/cover_reg_top/18.gpio_same_csr_outstanding.2659875372 Dec 20 12:27:41 PM PST 23 Dec 20 12:28:15 PM PST 23 18336232 ps
T914 /workspace/coverage/cover_reg_top/4.gpio_tl_intg_err.1303481002 Dec 20 12:27:07 PM PST 23 Dec 20 12:27:39 PM PST 23 339313123 ps
T915 /workspace/coverage/cover_reg_top/11.gpio_csr_mem_rw_with_rand_reset.3829976912 Dec 20 12:27:33 PM PST 23 Dec 20 12:28:10 PM PST 23 31257472 ps
T916 /workspace/coverage/cover_reg_top/17.gpio_tl_errors.2988499355 Dec 20 12:27:19 PM PST 23 Dec 20 12:28:00 PM PST 23 67615628 ps
T83 /workspace/coverage/cover_reg_top/19.gpio_csr_rw.4291650917 Dec 20 12:27:47 PM PST 23 Dec 20 12:28:22 PM PST 23 11754677 ps
T917 /workspace/coverage/cover_reg_top/33.gpio_intr_test.2756569226 Dec 20 12:28:13 PM PST 23 Dec 20 12:28:53 PM PST 23 15549907 ps
T918 /workspace/coverage/cover_reg_top/23.gpio_intr_test.2099288911 Dec 20 12:27:51 PM PST 23 Dec 20 12:28:27 PM PST 23 14455788 ps
T919 /workspace/coverage/cover_reg_top/5.gpio_intr_test.901139331 Dec 20 12:29:00 PM PST 23 Dec 20 12:29:33 PM PST 23 40712769 ps
T920 /workspace/coverage/cover_reg_top/10.gpio_tl_errors.2060731846 Dec 20 12:27:45 PM PST 23 Dec 20 12:28:20 PM PST 23 189638902 ps
T85 /workspace/coverage/cover_reg_top/1.gpio_csr_rw.1054925185 Dec 20 12:27:08 PM PST 23 Dec 20 12:27:40 PM PST 23 36234469 ps
T921 /workspace/coverage/cover_reg_top/16.gpio_same_csr_outstanding.3622657981 Dec 20 12:27:43 PM PST 23 Dec 20 12:28:17 PM PST 23 119838395 ps
T922 /workspace/coverage/cover_reg_top/29.gpio_intr_test.1205218036 Dec 20 12:27:46 PM PST 23 Dec 20 12:28:21 PM PST 23 19119075 ps
T923 /workspace/coverage/cover_reg_top/7.gpio_same_csr_outstanding.955308030 Dec 20 12:27:30 PM PST 23 Dec 20 12:28:08 PM PST 23 25709780 ps
T924 /workspace/coverage/cover_reg_top/15.gpio_same_csr_outstanding.342850145 Dec 20 12:27:47 PM PST 23 Dec 20 12:28:30 PM PST 23 134006391 ps
T925 /workspace/coverage/cover_reg_top/14.gpio_same_csr_outstanding.3035824660 Dec 20 12:27:47 PM PST 23 Dec 20 12:28:22 PM PST 23 30368351 ps
T926 /workspace/coverage/cover_reg_top/8.gpio_csr_rw.1255213823 Dec 20 12:29:06 PM PST 23 Dec 20 12:29:36 PM PST 23 15251727 ps
T927 /workspace/coverage/cover_reg_top/2.gpio_tl_errors.2430148286 Dec 20 12:27:27 PM PST 23 Dec 20 12:28:08 PM PST 23 132422106 ps
T86 /workspace/coverage/cover_reg_top/0.gpio_csr_aliasing.3467621685 Dec 20 12:28:59 PM PST 23 Dec 20 12:29:33 PM PST 23 34036756 ps
T928 /workspace/coverage/cover_reg_top/15.gpio_tl_errors.1191049740 Dec 20 12:27:41 PM PST 23 Dec 20 12:28:17 PM PST 23 413867555 ps
T929 /workspace/coverage/cover_reg_top/19.gpio_csr_mem_rw_with_rand_reset.3405644182 Dec 20 12:27:38 PM PST 23 Dec 20 12:28:13 PM PST 23 98792445 ps
T930 /workspace/coverage/cover_reg_top/30.gpio_intr_test.851231901 Dec 20 12:27:49 PM PST 23 Dec 20 12:28:24 PM PST 23 16465705 ps
T931 /workspace/coverage/cover_reg_top/6.gpio_tl_intg_err.3116269141 Dec 20 12:29:01 PM PST 23 Dec 20 12:29:34 PM PST 23 164547184 ps
T932 /workspace/coverage/cover_reg_top/24.gpio_intr_test.2363909795 Dec 20 12:27:41 PM PST 23 Dec 20 12:28:15 PM PST 23 34549210 ps
T79 /workspace/coverage/cover_reg_top/16.gpio_csr_rw.3890337268 Dec 20 12:27:41 PM PST 23 Dec 20 12:28:16 PM PST 23 71505137 ps
T933 /workspace/coverage/cover_reg_top/9.gpio_csr_mem_rw_with_rand_reset.1360671020 Dec 20 12:27:16 PM PST 23 Dec 20 12:27:54 PM PST 23 66765193 ps
T934 /workspace/coverage/cover_reg_top/27.gpio_intr_test.4160444132 Dec 20 12:27:45 PM PST 23 Dec 20 12:28:20 PM PST 23 53468284 ps
T935 /workspace/coverage/cover_reg_top/9.gpio_intr_test.3416429641 Dec 20 12:27:46 PM PST 23 Dec 20 12:28:20 PM PST 23 12513012 ps
T936 /workspace/coverage/cover_reg_top/38.gpio_intr_test.928042235 Dec 20 12:27:45 PM PST 23 Dec 20 12:28:19 PM PST 23 12998497 ps
T937 /workspace/coverage/cover_reg_top/13.gpio_tl_errors.316206416 Dec 20 12:27:16 PM PST 23 Dec 20 12:27:56 PM PST 23 39311542 ps
T938 /workspace/coverage/cover_reg_top/19.gpio_intr_test.2173237506 Dec 20 12:27:49 PM PST 23 Dec 20 12:28:25 PM PST 23 20048808 ps
T84 /workspace/coverage/cover_reg_top/3.gpio_csr_hw_reset.3886570660 Dec 20 12:27:12 PM PST 23 Dec 20 12:27:48 PM PST 23 20514584 ps
T939 /workspace/coverage/cover_reg_top/39.gpio_intr_test.3996753397 Dec 20 12:27:55 PM PST 23 Dec 20 12:28:33 PM PST 23 25105486 ps
T940 /workspace/coverage/cover_reg_top/5.gpio_tl_errors.3780628293 Dec 20 12:27:09 PM PST 23 Dec 20 12:27:41 PM PST 23 37239856 ps
T941 /workspace/coverage/cover_reg_top/6.gpio_csr_mem_rw_with_rand_reset.4688302 Dec 20 12:29:02 PM PST 23 Dec 20 12:29:35 PM PST 23 23503775 ps
T942 /workspace/coverage/cover_reg_top/3.gpio_tl_errors.4261693512 Dec 20 12:27:36 PM PST 23 Dec 20 12:28:13 PM PST 23 480495707 ps
T943 /workspace/coverage/cover_reg_top/18.gpio_tl_errors.780542354 Dec 20 12:27:53 PM PST 23 Dec 20 12:28:31 PM PST 23 117443672 ps
T944 /workspace/coverage/cover_reg_top/0.gpio_same_csr_outstanding.94197430 Dec 20 12:27:10 PM PST 23 Dec 20 12:27:45 PM PST 23 127612936 ps
T945 /workspace/coverage/cover_reg_top/17.gpio_csr_mem_rw_with_rand_reset.2328941925 Dec 20 12:27:39 PM PST 23 Dec 20 12:28:13 PM PST 23 19263488 ps
T946 /workspace/coverage/cover_reg_top/11.gpio_tl_errors.2043556254 Dec 20 12:27:30 PM PST 23 Dec 20 12:28:09 PM PST 23 315764644 ps

Test location /workspace/coverage/cover_reg_top/14.gpio_tl_intg_err.4241191715
Short name T12
Test name
Test status
Simulation time 341230556 ps
CPU time 1.37 seconds
Started Dec 20 12:27:34 PM PST 23
Finished Dec 20 12:28:11 PM PST 23
Peak memory 198476 kb
Host smart-9aef6848-603a-4319-b2a6-857b5f9eb40c
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4241191715 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 14.gpio_tl_intg_err.4241191715
Directory /workspace/14.gpio_tl_intg_err/latest

Test location /workspace/coverage/en_cdc_prims/44.gpio_smoke_no_pullup_pulldown_en_cdc_prim.86751982
Short name T55
Test name
Test status
Simulation time 78535238 ps
CPU time 1.21 seconds
Started Dec 20 12:20:25 PM PST 23
Finished Dec 20 12:20:31 PM PST 23
Peak memory 197680 kb
Host smart-b3d51eda-a986-47f1-b492-66c8f0bd6061
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=86751982 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 44.gpio_smoke_no_pullup_pulldown_e
n_cdc_prim.86751982
Directory /workspace/44.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/default/5.gpio_intr_with_filter_rand_intr_event.1713154093
Short name T47
Test name
Test status
Simulation time 113470043 ps
CPU time 1.3 seconds
Started Dec 20 12:28:37 PM PST 23
Finished Dec 20 12:29:10 PM PST 23
Peak memory 198300 kb
Host smart-02118cf5-3696-4011-971f-ff0d12af1845
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1713154093 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 5.gpio_intr_with_filter_rand_intr_event.1713154093
Directory /workspace/5.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/43.gpio_stress_all_with_rand_reset.2991393916
Short name T38
Test name
Test status
Simulation time 150472643181 ps
CPU time 969.46 seconds
Started Dec 20 12:30:38 PM PST 23
Finished Dec 20 12:47:25 PM PST 23
Peak memory 198392 kb
Host smart-230fcd36-d431-464c-86a5-3662d4de8764
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=2991393916 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_stress_all_with_rand_reset.2991393916
Directory /workspace/43.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.gpio_tl_errors.8298203
Short name T26
Test name
Test status
Simulation time 395181841 ps
CPU time 2.22 seconds
Started Dec 20 12:27:34 PM PST 23
Finished Dec 20 12:28:12 PM PST 23
Peak memory 198536 kb
Host smart-c2f8d349-d753-4727-a073-5f9ea1d80d1e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=8298203 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.gpio_tl_errors.8298203
Directory /workspace/14.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.gpio_csr_rw.227709744
Short name T4
Test name
Test status
Simulation time 44277215 ps
CPU time 0.61 seconds
Started Dec 20 12:27:21 PM PST 23
Finished Dec 20 12:28:01 PM PST 23
Peak memory 195184 kb
Host smart-ccb35710-a8cd-4894-910d-9032a1426b84
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=227709744 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_S
EQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.gpio
_csr_rw.227709744
Directory /workspace/12.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/43.gpio_intr_test.3602963879
Short name T107
Test name
Test status
Simulation time 21287828 ps
CPU time 0.57 seconds
Started Dec 20 12:27:45 PM PST 23
Finished Dec 20 12:28:20 PM PST 23
Peak memory 193992 kb
Host smart-047f6974-e540-4392-b77f-e91995c2321c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3602963879 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.gpio_intr_test.3602963879
Directory /workspace/43.gpio_intr_test/latest

Test location /workspace/coverage/default/2.gpio_sec_cm.3912396785
Short name T28
Test name
Test status
Simulation time 33853171 ps
CPU time 0.76 seconds
Started Dec 20 12:28:46 PM PST 23
Finished Dec 20 12:29:19 PM PST 23
Peak memory 213552 kb
Host smart-68aeec00-4afa-40af-8c46-6b2e776ccd9b
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3912396785 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_sec_cm.3912396785
Directory /workspace/2.gpio_sec_cm/latest

Test location /workspace/coverage/cover_reg_top/2.gpio_csr_bit_bash.784237383
Short name T22
Test name
Test status
Simulation time 221601996 ps
CPU time 2.03 seconds
Started Dec 20 12:27:09 PM PST 23
Finished Dec 20 12:27:42 PM PST 23
Peak memory 197220 kb
Host smart-372e3d04-0f25-47a5-ae54-67193ef7d7eb
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=784237383 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.gpio_csr_bit_bash.784237383
Directory /workspace/2.gpio_csr_bit_bash/latest

Test location /workspace/coverage/en_cdc_prims/23.gpio_smoke_en_cdc_prim.1349013282
Short name T45
Test name
Test status
Simulation time 36140466 ps
CPU time 0.71 seconds
Started Dec 20 12:20:23 PM PST 23
Finished Dec 20 12:20:27 PM PST 23
Peak memory 195132 kb
Host smart-6cb4e11c-2552-47ad-ac47-30d61153935e
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1349013282 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 23.gpio_smoke_en_cdc_prim.1349013282
Directory /workspace/23.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/cover_reg_top/3.gpio_same_csr_outstanding.3095800991
Short name T87
Test name
Test status
Simulation time 18241069 ps
CPU time 0.89 seconds
Started Dec 20 12:28:49 PM PST 23
Finished Dec 20 12:29:26 PM PST 23
Peak memory 195376 kb
Host smart-82e18597-6dcb-4279-a4f9-b5008d009ae3
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3095800991 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 3.gpio_same_csr_outstanding.3095800991
Directory /workspace/3.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.gpio_tl_intg_err.2110116048
Short name T42
Test name
Test status
Simulation time 82499754 ps
CPU time 1.19 seconds
Started Dec 20 12:27:43 PM PST 23
Finished Dec 20 12:28:18 PM PST 23
Peak memory 198424 kb
Host smart-05ee54cf-f56a-4b7b-8943-68d288ebe03e
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2110116048 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 11.gpio_tl_intg_err.2110116048
Directory /workspace/11.gpio_tl_intg_err/latest

Test location /workspace/coverage/default/1.gpio_alert_test.1345635500
Short name T253
Test name
Test status
Simulation time 79503646 ps
CPU time 0.57 seconds
Started Dec 20 12:28:36 PM PST 23
Finished Dec 20 12:29:08 PM PST 23
Peak memory 194072 kb
Host smart-fc154c6a-3a13-4eb2-9d72-76ce7c848019
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1345635500 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_alert_test.1345635500
Directory /workspace/1.gpio_alert_test/latest

Test location /workspace/coverage/cover_reg_top/0.gpio_tl_intg_err.2099393373
Short name T14
Test name
Test status
Simulation time 246000841 ps
CPU time 1.08 seconds
Started Dec 20 12:27:18 PM PST 23
Finished Dec 20 12:27:59 PM PST 23
Peak memory 198440 kb
Host smart-1c6b8f89-93f1-44e9-8921-637821081466
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2099393373 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 0.gpio_tl_intg_err.2099393373
Directory /workspace/0.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/0.gpio_csr_aliasing.3467621685
Short name T86
Test name
Test status
Simulation time 34036756 ps
CPU time 0.79 seconds
Started Dec 20 12:28:59 PM PST 23
Finished Dec 20 12:29:33 PM PST 23
Peak memory 196368 kb
Host smart-6e269b6f-155d-46a9-a708-46bdea3ca590
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3467621685 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM
_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name
0.gpio_csr_aliasing.3467621685
Directory /workspace/0.gpio_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.gpio_csr_bit_bash.165786441
Short name T80
Test name
Test status
Simulation time 156755260 ps
CPU time 2.86 seconds
Started Dec 20 12:27:05 PM PST 23
Finished Dec 20 12:27:38 PM PST 23
Peak memory 198320 kb
Host smart-573fa7b7-b014-412c-902b-07452775acbf
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=165786441 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.gpio_csr_bit_bash.165786441
Directory /workspace/0.gpio_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.gpio_csr_hw_reset.180269137
Short name T861
Test name
Test status
Simulation time 27800958 ps
CPU time 0.66 seconds
Started Dec 20 12:27:21 PM PST 23
Finished Dec 20 12:28:01 PM PST 23
Peak memory 195156 kb
Host smart-93c3b536-4435-46f6-8626-6e4b7c325335
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=180269137 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.gpio_csr_hw_reset.180269137
Directory /workspace/0.gpio_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.gpio_csr_mem_rw_with_rand_reset.544634644
Short name T872
Test name
Test status
Simulation time 19372771 ps
CPU time 0.63 seconds
Started Dec 20 12:28:50 PM PST 23
Finished Dec 20 12:29:25 PM PST 23
Peak memory 195740 kb
Host smart-65f8831a-53b0-4bb5-bb86-af0a93330837
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=544634644 -asser
t nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage
/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.gpio_csr_mem_rw_with_rand_reset.544634644
Directory /workspace/0.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.gpio_csr_rw.3975405469
Short name T82
Test name
Test status
Simulation time 12733771 ps
CPU time 0.6 seconds
Started Dec 20 12:27:21 PM PST 23
Finished Dec 20 12:28:01 PM PST 23
Peak memory 195104 kb
Host smart-bbecbc6d-0866-4eef-a7b7-576f70b3de6c
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3975405469 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.gpio
_csr_rw.3975405469
Directory /workspace/0.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.gpio_intr_test.2047335915
Short name T890
Test name
Test status
Simulation time 39334523 ps
CPU time 0.55 seconds
Started Dec 20 12:29:16 PM PST 23
Finished Dec 20 12:29:41 PM PST 23
Peak memory 194264 kb
Host smart-4dd3f735-cc5f-4bdf-acdb-07e75a4899fd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2047335915 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.gpio_intr_test.2047335915
Directory /workspace/0.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.gpio_same_csr_outstanding.94197430
Short name T944
Test name
Test status
Simulation time 127612936 ps
CPU time 0.89 seconds
Started Dec 20 12:27:10 PM PST 23
Finished Dec 20 12:27:45 PM PST 23
Peak memory 196512 kb
Host smart-ada31c4f-2fa1-4039-8d75-ce46030447f6
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=94197430 -assert nopostproc +UVM_TESTNAME=gpio_base
_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 0.gpio_same_csr_outstanding.94197430
Directory /workspace/0.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.gpio_tl_errors.3103924712
Short name T7
Test name
Test status
Simulation time 48008804 ps
CPU time 1.25 seconds
Started Dec 20 12:29:12 PM PST 23
Finished Dec 20 12:29:40 PM PST 23
Peak memory 195944 kb
Host smart-91bbc30a-363a-43ec-b46f-57ff38b66792
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3103924712 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.gpio_tl_errors.3103924712
Directory /workspace/0.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.gpio_csr_aliasing.1793252879
Short name T15
Test name
Test status
Simulation time 68052451 ps
CPU time 0.63 seconds
Started Dec 20 12:29:00 PM PST 23
Finished Dec 20 12:29:33 PM PST 23
Peak memory 194124 kb
Host smart-d6943d06-60ee-4aee-86ca-c579ce64dd79
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1793252879 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM
_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name
1.gpio_csr_aliasing.1793252879
Directory /workspace/1.gpio_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.gpio_csr_bit_bash.2713181391
Short name T2
Test name
Test status
Simulation time 376188494 ps
CPU time 3.35 seconds
Started Dec 20 12:27:08 PM PST 23
Finished Dec 20 12:27:42 PM PST 23
Peak memory 196976 kb
Host smart-4d3c6186-a79b-47c7-91d0-c1e2f8a3b0cd
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2713181391 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.gpio_csr_bit_bash.2713181391
Directory /workspace/1.gpio_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.gpio_csr_hw_reset.1488666696
Short name T854
Test name
Test status
Simulation time 163373590 ps
CPU time 0.57 seconds
Started Dec 20 12:27:15 PM PST 23
Finished Dec 20 12:27:52 PM PST 23
Peak memory 194604 kb
Host smart-a788f110-74b0-48d7-8e61-159e0328aa56
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1488666696 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.gpio_csr_hw_reset.1488666696
Directory /workspace/1.gpio_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.gpio_csr_mem_rw_with_rand_reset.4094287022
Short name T863
Test name
Test status
Simulation time 18836892 ps
CPU time 1.03 seconds
Started Dec 20 12:28:55 PM PST 23
Finished Dec 20 12:29:31 PM PST 23
Peak memory 197196 kb
Host smart-62ad1f62-aacc-4e30-81ea-49e6ac26063b
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4094287022 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.gpio_csr_mem_rw_with_rand_reset.4094287022
Directory /workspace/1.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.gpio_csr_rw.1054925185
Short name T85
Test name
Test status
Simulation time 36234469 ps
CPU time 0.62 seconds
Started Dec 20 12:27:08 PM PST 23
Finished Dec 20 12:27:40 PM PST 23
Peak memory 195288 kb
Host smart-f2fbdddd-a56b-48be-85c0-f9868367da6b
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1054925185 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.gpio
_csr_rw.1054925185
Directory /workspace/1.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.gpio_intr_test.3396030180
Short name T859
Test name
Test status
Simulation time 14527807 ps
CPU time 0.7 seconds
Started Dec 20 12:29:13 PM PST 23
Finished Dec 20 12:29:40 PM PST 23
Peak memory 192764 kb
Host smart-52c38460-2efb-49bb-b0ec-69a51a69ce49
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3396030180 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.gpio_intr_test.3396030180
Directory /workspace/1.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.gpio_same_csr_outstanding.120749803
Short name T908
Test name
Test status
Simulation time 19025876 ps
CPU time 0.72 seconds
Started Dec 20 12:28:45 PM PST 23
Finished Dec 20 12:29:19 PM PST 23
Peak memory 194048 kb
Host smart-3f392d3f-9f67-4372-92f6-7616e7b5ee46
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=120749803 -assert nopostproc +UVM_TESTNAME=gpio_bas
e_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul
l -cm_name 1.gpio_same_csr_outstanding.120749803
Directory /workspace/1.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.gpio_tl_errors.76568346
Short name T869
Test name
Test status
Simulation time 170314095 ps
CPU time 2.17 seconds
Started Dec 20 12:27:41 PM PST 23
Finished Dec 20 12:28:17 PM PST 23
Peak memory 198344 kb
Host smart-7f859640-0b6f-4d0f-a7b6-5020490aab9a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=76568346 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.gpio_tl_errors.76568346
Directory /workspace/1.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.gpio_tl_intg_err.1011197862
Short name T906
Test name
Test status
Simulation time 80608177 ps
CPU time 0.97 seconds
Started Dec 20 12:29:12 PM PST 23
Finished Dec 20 12:29:40 PM PST 23
Peak memory 195168 kb
Host smart-4ad10ce9-8968-46f3-991c-3462b8767249
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1011197862 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 1.gpio_tl_intg_err.1011197862
Directory /workspace/1.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.gpio_csr_mem_rw_with_rand_reset.232322138
Short name T893
Test name
Test status
Simulation time 24659225 ps
CPU time 0.87 seconds
Started Dec 20 12:27:45 PM PST 23
Finished Dec 20 12:28:20 PM PST 23
Peak memory 198332 kb
Host smart-2c517ce4-06f4-4ce9-b83d-8e5872699de7
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=232322138 -asser
t nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage
/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.gpio_csr_mem_rw_with_rand_reset.232322138
Directory /workspace/10.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.gpio_csr_rw.1992608705
Short name T101
Test name
Test status
Simulation time 14301272 ps
CPU time 0.6 seconds
Started Dec 20 12:27:13 PM PST 23
Finished Dec 20 12:27:50 PM PST 23
Peak memory 195708 kb
Host smart-a282dd59-9951-421d-91c5-268312d6cab0
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1992608705 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.gpi
o_csr_rw.1992608705
Directory /workspace/10.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.gpio_intr_test.2500374297
Short name T899
Test name
Test status
Simulation time 17727946 ps
CPU time 0.57 seconds
Started Dec 20 12:27:49 PM PST 23
Finished Dec 20 12:28:24 PM PST 23
Peak memory 194044 kb
Host smart-9d356eda-3b27-4353-839f-af280c8a5122
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2500374297 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.gpio_intr_test.2500374297
Directory /workspace/10.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.gpio_same_csr_outstanding.1705842834
Short name T897
Test name
Test status
Simulation time 26703800 ps
CPU time 0.64 seconds
Started Dec 20 12:27:43 PM PST 23
Finished Dec 20 12:28:18 PM PST 23
Peak memory 195300 kb
Host smart-8896cd22-a18b-4cc7-ad43-c687ff77d4db
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1705842834 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 10.gpio_same_csr_outstanding.1705842834
Directory /workspace/10.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.gpio_tl_errors.2060731846
Short name T920
Test name
Test status
Simulation time 189638902 ps
CPU time 1.24 seconds
Started Dec 20 12:27:45 PM PST 23
Finished Dec 20 12:28:20 PM PST 23
Peak memory 198328 kb
Host smart-43bcbd4a-a04a-4047-8ec6-69f42a3f2402
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2060731846 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.gpio_tl_errors.2060731846
Directory /workspace/10.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.gpio_tl_intg_err.2208408522
Short name T41
Test name
Test status
Simulation time 47429250 ps
CPU time 0.86 seconds
Started Dec 20 12:27:24 PM PST 23
Finished Dec 20 12:28:04 PM PST 23
Peak memory 197496 kb
Host smart-1e738e24-0980-43ec-a403-c9471003507a
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2208408522 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 10.gpio_tl_intg_err.2208408522
Directory /workspace/10.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.gpio_csr_mem_rw_with_rand_reset.3829976912
Short name T915
Test name
Test status
Simulation time 31257472 ps
CPU time 0.9 seconds
Started Dec 20 12:27:33 PM PST 23
Finished Dec 20 12:28:10 PM PST 23
Peak memory 198296 kb
Host smart-6d42137f-0437-400c-95b8-9fa76507d9af
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3829976912 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.gpio_csr_mem_rw_with_rand_reset.3829976912
Directory /workspace/11.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.gpio_csr_rw.1724663736
Short name T856
Test name
Test status
Simulation time 18988298 ps
CPU time 0.58 seconds
Started Dec 20 12:27:11 PM PST 23
Finished Dec 20 12:27:46 PM PST 23
Peak memory 195008 kb
Host smart-b758844a-e4a5-4998-b47d-b97dfb6f8cd8
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1724663736 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.gpi
o_csr_rw.1724663736
Directory /workspace/11.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.gpio_intr_test.1264492323
Short name T891
Test name
Test status
Simulation time 38815301 ps
CPU time 0.59 seconds
Started Dec 20 12:27:36 PM PST 23
Finished Dec 20 12:28:11 PM PST 23
Peak memory 194116 kb
Host smart-c9bb287b-f79b-43cc-a5d2-176dc86e70a7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1264492323 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.gpio_intr_test.1264492323
Directory /workspace/11.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.gpio_same_csr_outstanding.1887101868
Short name T90
Test name
Test status
Simulation time 43585159 ps
CPU time 1.01 seconds
Started Dec 20 12:27:16 PM PST 23
Finished Dec 20 12:27:54 PM PST 23
Peak memory 196824 kb
Host smart-7be5be5e-5390-4b71-9009-27823a063e98
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1887101868 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 11.gpio_same_csr_outstanding.1887101868
Directory /workspace/11.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.gpio_tl_errors.2043556254
Short name T946
Test name
Test status
Simulation time 315764644 ps
CPU time 1.8 seconds
Started Dec 20 12:27:30 PM PST 23
Finished Dec 20 12:28:09 PM PST 23
Peak memory 198468 kb
Host smart-b0fa51c2-e7fb-4adb-bf0a-fb075ee9f61c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2043556254 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.gpio_tl_errors.2043556254
Directory /workspace/11.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.gpio_csr_mem_rw_with_rand_reset.1489656030
Short name T17
Test name
Test status
Simulation time 30443957 ps
CPU time 0.91 seconds
Started Dec 20 12:27:29 PM PST 23
Finished Dec 20 12:28:08 PM PST 23
Peak memory 198360 kb
Host smart-f6e31916-8e37-4b75-8edb-6e5983477a4d
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1489656030 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.gpio_csr_mem_rw_with_rand_reset.1489656030
Directory /workspace/12.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.gpio_intr_test.2297263259
Short name T23
Test name
Test status
Simulation time 18032254 ps
CPU time 0.59 seconds
Started Dec 20 12:27:16 PM PST 23
Finished Dec 20 12:27:54 PM PST 23
Peak memory 194148 kb
Host smart-903eade3-5077-4c33-abca-4cfcaaa6ab1d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2297263259 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.gpio_intr_test.2297263259
Directory /workspace/12.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.gpio_same_csr_outstanding.1564159606
Short name T896
Test name
Test status
Simulation time 152824123 ps
CPU time 0.77 seconds
Started Dec 20 12:27:39 PM PST 23
Finished Dec 20 12:28:14 PM PST 23
Peak memory 196580 kb
Host smart-3d22801b-5b2e-4a54-8502-66c08a298d63
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1564159606 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 12.gpio_same_csr_outstanding.1564159606
Directory /workspace/12.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.gpio_tl_errors.439762411
Short name T868
Test name
Test status
Simulation time 140106030 ps
CPU time 2.84 seconds
Started Dec 20 12:27:16 PM PST 23
Finished Dec 20 12:27:56 PM PST 23
Peak memory 198436 kb
Host smart-e7f5e51e-109f-472f-87b2-fa79fc998fe8
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=439762411 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.gpio_tl_errors.439762411
Directory /workspace/12.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.gpio_tl_intg_err.3708158936
Short name T847
Test name
Test status
Simulation time 143581678 ps
CPU time 0.82 seconds
Started Dec 20 12:27:13 PM PST 23
Finished Dec 20 12:27:50 PM PST 23
Peak memory 197600 kb
Host smart-9f5326fa-8726-487e-aa29-bc0a41ac5ac5
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3708158936 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 12.gpio_tl_intg_err.3708158936
Directory /workspace/12.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.gpio_csr_mem_rw_with_rand_reset.2797414395
Short name T889
Test name
Test status
Simulation time 20487087 ps
CPU time 1.16 seconds
Started Dec 20 12:27:12 PM PST 23
Finished Dec 20 12:27:49 PM PST 23
Peak memory 198488 kb
Host smart-4e9e7999-d7e6-4adf-b075-b06381283ff8
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2797414395 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.gpio_csr_mem_rw_with_rand_reset.2797414395
Directory /workspace/13.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.gpio_csr_rw.1528512798
Short name T862
Test name
Test status
Simulation time 40534380 ps
CPU time 0.61 seconds
Started Dec 20 12:27:15 PM PST 23
Finished Dec 20 12:27:52 PM PST 23
Peak memory 195628 kb
Host smart-8feff51f-522e-4eb6-8215-40e7554c694f
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1528512798 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.gpi
o_csr_rw.1528512798
Directory /workspace/13.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.gpio_intr_test.2146568938
Short name T866
Test name
Test status
Simulation time 33398118 ps
CPU time 0.6 seconds
Started Dec 20 12:27:15 PM PST 23
Finished Dec 20 12:27:53 PM PST 23
Peak memory 194652 kb
Host smart-4b026fe0-bbee-468d-ac76-fff91658b8d2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2146568938 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.gpio_intr_test.2146568938
Directory /workspace/13.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.gpio_same_csr_outstanding.294918254
Short name T92
Test name
Test status
Simulation time 41074437 ps
CPU time 0.65 seconds
Started Dec 20 12:27:29 PM PST 23
Finished Dec 20 12:28:08 PM PST 23
Peak memory 195204 kb
Host smart-cf65c42f-0dfb-45b4-82eb-d547652c2b18
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=294918254 -assert nopostproc +UVM_TESTNAME=gpio_bas
e_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul
l -cm_name 13.gpio_same_csr_outstanding.294918254
Directory /workspace/13.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.gpio_tl_errors.316206416
Short name T937
Test name
Test status
Simulation time 39311542 ps
CPU time 2.13 seconds
Started Dec 20 12:27:16 PM PST 23
Finished Dec 20 12:27:56 PM PST 23
Peak memory 198512 kb
Host smart-94e6053b-6ef6-4a10-b18f-1b5e041f30c3
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=316206416 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.gpio_tl_errors.316206416
Directory /workspace/13.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.gpio_tl_intg_err.2985850815
Short name T888
Test name
Test status
Simulation time 140218022 ps
CPU time 1.38 seconds
Started Dec 20 12:27:39 PM PST 23
Finished Dec 20 12:28:14 PM PST 23
Peak memory 198188 kb
Host smart-5fdf7d40-11a8-46ca-8f35-9161a4d3baf2
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2985850815 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 13.gpio_tl_intg_err.2985850815
Directory /workspace/13.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.gpio_csr_mem_rw_with_rand_reset.4245767015
Short name T103
Test name
Test status
Simulation time 44789831 ps
CPU time 0.64 seconds
Started Dec 20 12:27:41 PM PST 23
Finished Dec 20 12:28:16 PM PST 23
Peak memory 197468 kb
Host smart-d319c0a1-40c1-4f65-8363-c922bde7eb63
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4245767015 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.gpio_csr_mem_rw_with_rand_reset.4245767015
Directory /workspace/14.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.gpio_csr_rw.13006652
Short name T6
Test name
Test status
Simulation time 56723198 ps
CPU time 0.56 seconds
Started Dec 20 12:27:10 PM PST 23
Finished Dec 20 12:27:44 PM PST 23
Peak memory 193624 kb
Host smart-a6c62e76-dd5a-4c24-946f-090f5ae5ae19
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13006652 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SE
Q=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.gpio_
csr_rw.13006652
Directory /workspace/14.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.gpio_intr_test.758270549
Short name T881
Test name
Test status
Simulation time 22170404 ps
CPU time 0.57 seconds
Started Dec 20 12:27:33 PM PST 23
Finished Dec 20 12:28:10 PM PST 23
Peak memory 194048 kb
Host smart-d4e4d521-733e-4a32-96cc-dd0fb332be8b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=758270549 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.gpio_intr_test.758270549
Directory /workspace/14.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.gpio_same_csr_outstanding.3035824660
Short name T925
Test name
Test status
Simulation time 30368351 ps
CPU time 0.64 seconds
Started Dec 20 12:27:47 PM PST 23
Finished Dec 20 12:28:22 PM PST 23
Peak memory 195520 kb
Host smart-3905fe9d-ec3a-46cf-b3ce-0319bf7e59c2
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3035824660 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 14.gpio_same_csr_outstanding.3035824660
Directory /workspace/14.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.gpio_csr_mem_rw_with_rand_reset.3520590826
Short name T9
Test name
Test status
Simulation time 44687496 ps
CPU time 0.8 seconds
Started Dec 20 12:27:47 PM PST 23
Finished Dec 20 12:28:23 PM PST 23
Peak memory 198312 kb
Host smart-6daf55c3-6249-48c6-a465-cd48b627ff98
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3520590826 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.gpio_csr_mem_rw_with_rand_reset.3520590826
Directory /workspace/15.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.gpio_csr_rw.3624458398
Short name T850
Test name
Test status
Simulation time 11522335 ps
CPU time 0.6 seconds
Started Dec 20 12:27:23 PM PST 23
Finished Dec 20 12:28:03 PM PST 23
Peak memory 195572 kb
Host smart-e150f0db-b1b7-4c02-b427-ea5731b8aae5
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3624458398 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.gpi
o_csr_rw.3624458398
Directory /workspace/15.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.gpio_intr_test.1977027719
Short name T912
Test name
Test status
Simulation time 45297400 ps
CPU time 0.61 seconds
Started Dec 20 12:27:44 PM PST 23
Finished Dec 20 12:28:18 PM PST 23
Peak memory 194192 kb
Host smart-ceb16fe8-26b9-47a2-9be2-fc9b6318716f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1977027719 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.gpio_intr_test.1977027719
Directory /workspace/15.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.gpio_same_csr_outstanding.342850145
Short name T924
Test name
Test status
Simulation time 134006391 ps
CPU time 0.62 seconds
Started Dec 20 12:27:47 PM PST 23
Finished Dec 20 12:28:30 PM PST 23
Peak memory 195048 kb
Host smart-7039b751-89d1-4e2b-b854-2cd863ceda7a
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=342850145 -assert nopostproc +UVM_TESTNAME=gpio_bas
e_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul
l -cm_name 15.gpio_same_csr_outstanding.342850145
Directory /workspace/15.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.gpio_tl_errors.1191049740
Short name T928
Test name
Test status
Simulation time 413867555 ps
CPU time 2.02 seconds
Started Dec 20 12:27:41 PM PST 23
Finished Dec 20 12:28:17 PM PST 23
Peak memory 198340 kb
Host smart-08cc49dc-fd09-48af-a6e8-b2d98f4926d8
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1191049740 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.gpio_tl_errors.1191049740
Directory /workspace/15.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.gpio_tl_intg_err.3277821530
Short name T848
Test name
Test status
Simulation time 46136735 ps
CPU time 0.88 seconds
Started Dec 20 12:27:23 PM PST 23
Finished Dec 20 12:28:03 PM PST 23
Peak memory 197768 kb
Host smart-779e0650-893a-45ca-9257-6b2e0aa0f098
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3277821530 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 15.gpio_tl_intg_err.3277821530
Directory /workspace/15.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.gpio_csr_mem_rw_with_rand_reset.2590973647
Short name T858
Test name
Test status
Simulation time 149252472 ps
CPU time 1.01 seconds
Started Dec 20 12:27:42 PM PST 23
Finished Dec 20 12:28:17 PM PST 23
Peak memory 198360 kb
Host smart-42d37a6e-f236-4015-9486-0f53c57d48f9
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2590973647 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.gpio_csr_mem_rw_with_rand_reset.2590973647
Directory /workspace/16.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.gpio_csr_rw.3890337268
Short name T79
Test name
Test status
Simulation time 71505137 ps
CPU time 0.56 seconds
Started Dec 20 12:27:41 PM PST 23
Finished Dec 20 12:28:16 PM PST 23
Peak memory 193612 kb
Host smart-62f48ed7-3cd9-4afe-98c8-d777e90300fc
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3890337268 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.gpi
o_csr_rw.3890337268
Directory /workspace/16.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.gpio_intr_test.1846527832
Short name T875
Test name
Test status
Simulation time 15357740 ps
CPU time 0.64 seconds
Started Dec 20 12:27:28 PM PST 23
Finished Dec 20 12:28:07 PM PST 23
Peak memory 194152 kb
Host smart-452de105-d6a3-4352-b3d8-ba8176e1c410
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1846527832 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.gpio_intr_test.1846527832
Directory /workspace/16.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.gpio_same_csr_outstanding.3622657981
Short name T921
Test name
Test status
Simulation time 119838395 ps
CPU time 0.81 seconds
Started Dec 20 12:27:43 PM PST 23
Finished Dec 20 12:28:17 PM PST 23
Peak memory 197384 kb
Host smart-c2ae0055-ae03-47d2-b030-70195f1c2dbc
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3622657981 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 16.gpio_same_csr_outstanding.3622657981
Directory /workspace/16.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.gpio_tl_errors.2606045519
Short name T898
Test name
Test status
Simulation time 280074107 ps
CPU time 2.49 seconds
Started Dec 20 12:27:25 PM PST 23
Finished Dec 20 12:28:06 PM PST 23
Peak memory 198452 kb
Host smart-3c0f4439-1241-4826-8891-6b1141b4cde6
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2606045519 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.gpio_tl_errors.2606045519
Directory /workspace/16.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.gpio_tl_intg_err.272647530
Short name T35
Test name
Test status
Simulation time 123017740 ps
CPU time 1.09 seconds
Started Dec 20 12:27:37 PM PST 23
Finished Dec 20 12:28:13 PM PST 23
Peak memory 198312 kb
Host smart-fef7ff2f-3044-4b8b-823b-23a6ad9b01c4
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=272647530 -assert nopostproc +UVM_TESTNAME=gpio_base_test +U
VM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam
e 16.gpio_tl_intg_err.272647530
Directory /workspace/16.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.gpio_csr_mem_rw_with_rand_reset.2328941925
Short name T945
Test name
Test status
Simulation time 19263488 ps
CPU time 0.71 seconds
Started Dec 20 12:27:39 PM PST 23
Finished Dec 20 12:28:13 PM PST 23
Peak memory 198248 kb
Host smart-82b23bff-9f47-4bf9-a758-e807884c8535
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2328941925 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.gpio_csr_mem_rw_with_rand_reset.2328941925
Directory /workspace/17.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.gpio_csr_rw.2917291418
Short name T1
Test name
Test status
Simulation time 14383449 ps
CPU time 0.58 seconds
Started Dec 20 12:27:17 PM PST 23
Finished Dec 20 12:27:55 PM PST 23
Peak memory 194968 kb
Host smart-347a2ec3-7939-4c16-9c2d-539d6f6bd07b
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2917291418 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.gpi
o_csr_rw.2917291418
Directory /workspace/17.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.gpio_intr_test.491418280
Short name T911
Test name
Test status
Simulation time 14526936 ps
CPU time 0.58 seconds
Started Dec 20 12:27:51 PM PST 23
Finished Dec 20 12:28:27 PM PST 23
Peak memory 194136 kb
Host smart-cb3d0565-de34-4b2c-8b18-1dd853a43da4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=491418280 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.gpio_intr_test.491418280
Directory /workspace/17.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.gpio_same_csr_outstanding.3784169646
Short name T88
Test name
Test status
Simulation time 26367160 ps
CPU time 0.69 seconds
Started Dec 20 12:27:42 PM PST 23
Finished Dec 20 12:28:16 PM PST 23
Peak memory 196232 kb
Host smart-047dd635-eb00-4712-b1fe-6af1b0ea6047
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3784169646 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 17.gpio_same_csr_outstanding.3784169646
Directory /workspace/17.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.gpio_tl_errors.2988499355
Short name T916
Test name
Test status
Simulation time 67615628 ps
CPU time 1.58 seconds
Started Dec 20 12:27:19 PM PST 23
Finished Dec 20 12:28:00 PM PST 23
Peak memory 198424 kb
Host smart-5aa36313-7715-414d-9cd9-1bce66b39bbc
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2988499355 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.gpio_tl_errors.2988499355
Directory /workspace/17.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.gpio_tl_intg_err.575559401
Short name T33
Test name
Test status
Simulation time 186107362 ps
CPU time 1.36 seconds
Started Dec 20 12:27:39 PM PST 23
Finished Dec 20 12:28:14 PM PST 23
Peak memory 198484 kb
Host smart-728aa076-b63e-431d-b53f-95a450ace660
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=575559401 -assert nopostproc +UVM_TESTNAME=gpio_base_test +U
VM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam
e 17.gpio_tl_intg_err.575559401
Directory /workspace/17.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.gpio_csr_mem_rw_with_rand_reset.1286952752
Short name T895
Test name
Test status
Simulation time 88494628 ps
CPU time 0.77 seconds
Started Dec 20 12:27:58 PM PST 23
Finished Dec 20 12:28:36 PM PST 23
Peak memory 198360 kb
Host smart-96b7bd7e-00cf-4533-a657-4c48f7966cf4
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1286952752 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.gpio_csr_mem_rw_with_rand_reset.1286952752
Directory /workspace/18.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.gpio_csr_rw.4024916794
Short name T884
Test name
Test status
Simulation time 54800121 ps
CPU time 0.59 seconds
Started Dec 20 12:27:41 PM PST 23
Finished Dec 20 12:28:16 PM PST 23
Peak memory 194976 kb
Host smart-a75a128e-67e5-4d7f-ae5e-76c0f98d6b40
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4024916794 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.gpi
o_csr_rw.4024916794
Directory /workspace/18.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.gpio_intr_test.4454617
Short name T853
Test name
Test status
Simulation time 15059990 ps
CPU time 0.61 seconds
Started Dec 20 12:27:49 PM PST 23
Finished Dec 20 12:28:30 PM PST 23
Peak memory 194080 kb
Host smart-6ddf367f-898a-46db-b596-5da374f2a2fe
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4454617 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.gpio_intr_test.4454617
Directory /workspace/18.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.gpio_same_csr_outstanding.2659875372
Short name T913
Test name
Test status
Simulation time 18336232 ps
CPU time 0.73 seconds
Started Dec 20 12:27:41 PM PST 23
Finished Dec 20 12:28:15 PM PST 23
Peak memory 195808 kb
Host smart-79a3dd79-5142-4c5a-b41d-a0d2c0c08376
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2659875372 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 18.gpio_same_csr_outstanding.2659875372
Directory /workspace/18.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.gpio_tl_errors.780542354
Short name T943
Test name
Test status
Simulation time 117443672 ps
CPU time 2.63 seconds
Started Dec 20 12:27:53 PM PST 23
Finished Dec 20 12:28:31 PM PST 23
Peak memory 198524 kb
Host smart-ae3b83f2-1251-4560-9594-808e7a1cc175
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=780542354 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.gpio_tl_errors.780542354
Directory /workspace/18.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.gpio_tl_intg_err.3573603377
Short name T98
Test name
Test status
Simulation time 99882785 ps
CPU time 0.84 seconds
Started Dec 20 12:27:49 PM PST 23
Finished Dec 20 12:28:24 PM PST 23
Peak memory 197696 kb
Host smart-04a887cb-8f92-4537-92aa-22da8e522b7e
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3573603377 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 18.gpio_tl_intg_err.3573603377
Directory /workspace/18.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.gpio_csr_mem_rw_with_rand_reset.3405644182
Short name T929
Test name
Test status
Simulation time 98792445 ps
CPU time 0.79 seconds
Started Dec 20 12:27:38 PM PST 23
Finished Dec 20 12:28:13 PM PST 23
Peak memory 198336 kb
Host smart-3ea6a970-172f-4dc9-a2f5-3840af61fa6f
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3405644182 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.gpio_csr_mem_rw_with_rand_reset.3405644182
Directory /workspace/19.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.gpio_csr_rw.4291650917
Short name T83
Test name
Test status
Simulation time 11754677 ps
CPU time 0.61 seconds
Started Dec 20 12:27:47 PM PST 23
Finished Dec 20 12:28:22 PM PST 23
Peak memory 194788 kb
Host smart-3392554e-0271-4740-81ce-dca9eabfcbf4
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4291650917 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.gpi
o_csr_rw.4291650917
Directory /workspace/19.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.gpio_intr_test.2173237506
Short name T938
Test name
Test status
Simulation time 20048808 ps
CPU time 0.57 seconds
Started Dec 20 12:27:49 PM PST 23
Finished Dec 20 12:28:25 PM PST 23
Peak memory 194696 kb
Host smart-b5b509d1-20fe-48e7-a275-345724e540f6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2173237506 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.gpio_intr_test.2173237506
Directory /workspace/19.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.gpio_same_csr_outstanding.2534634684
Short name T74
Test name
Test status
Simulation time 90757126 ps
CPU time 0.66 seconds
Started Dec 20 12:28:00 PM PST 23
Finished Dec 20 12:28:39 PM PST 23
Peak memory 195056 kb
Host smart-15767a77-3d5d-466d-bd72-8c8c6ee02bfc
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2534634684 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 19.gpio_same_csr_outstanding.2534634684
Directory /workspace/19.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.gpio_tl_errors.3973757336
Short name T885
Test name
Test status
Simulation time 219916204 ps
CPU time 2.07 seconds
Started Dec 20 12:27:51 PM PST 23
Finished Dec 20 12:28:28 PM PST 23
Peak memory 198536 kb
Host smart-ec96b420-476e-47e2-a5fd-881cbccd7208
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3973757336 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.gpio_tl_errors.3973757336
Directory /workspace/19.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.gpio_tl_intg_err.2193260087
Short name T882
Test name
Test status
Simulation time 113008194 ps
CPU time 1.35 seconds
Started Dec 20 12:27:51 PM PST 23
Finished Dec 20 12:28:27 PM PST 23
Peak memory 198312 kb
Host smart-88f04834-31a4-468d-962a-3c44a9d216d5
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2193260087 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 19.gpio_tl_intg_err.2193260087
Directory /workspace/19.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.gpio_csr_aliasing.2939974060
Short name T72
Test name
Test status
Simulation time 130756826 ps
CPU time 0.85 seconds
Started Dec 20 12:27:07 PM PST 23
Finished Dec 20 12:27:38 PM PST 23
Peak memory 197044 kb
Host smart-2de534c0-fd4f-425c-b59c-c8bd9d63c08f
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2939974060 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM
_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name
2.gpio_csr_aliasing.2939974060
Directory /workspace/2.gpio_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.gpio_csr_hw_reset.308776150
Short name T902
Test name
Test status
Simulation time 15672986 ps
CPU time 0.64 seconds
Started Dec 20 12:27:08 PM PST 23
Finished Dec 20 12:27:39 PM PST 23
Peak memory 194984 kb
Host smart-2cbf494d-4934-441c-a6da-b95db8b9ab3b
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=308776150 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.gpio_csr_hw_reset.308776150
Directory /workspace/2.gpio_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.gpio_csr_mem_rw_with_rand_reset.2874022484
Short name T34
Test name
Test status
Simulation time 30837794 ps
CPU time 1.53 seconds
Started Dec 20 12:29:34 PM PST 23
Finished Dec 20 12:29:56 PM PST 23
Peak memory 198252 kb
Host smart-8f1f4c2d-1569-4b68-b2ae-8d6322b32192
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2874022484 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.gpio_csr_mem_rw_with_rand_reset.2874022484
Directory /workspace/2.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.gpio_csr_rw.1348744731
Short name T81
Test name
Test status
Simulation time 17911496 ps
CPU time 0.6 seconds
Started Dec 20 12:29:32 PM PST 23
Finished Dec 20 12:29:53 PM PST 23
Peak memory 194724 kb
Host smart-d4990f2c-9b77-48f1-a8bc-b0ae51207b66
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1348744731 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.gpio
_csr_rw.1348744731
Directory /workspace/2.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.gpio_intr_test.1615426443
Short name T860
Test name
Test status
Simulation time 14677605 ps
CPU time 0.6 seconds
Started Dec 20 12:27:08 PM PST 23
Finished Dec 20 12:27:39 PM PST 23
Peak memory 194152 kb
Host smart-e4a81d39-fbbd-4d61-81e1-34dffd2812ce
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1615426443 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.gpio_intr_test.1615426443
Directory /workspace/2.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.gpio_same_csr_outstanding.2230323025
Short name T880
Test name
Test status
Simulation time 407126105 ps
CPU time 0.78 seconds
Started Dec 20 12:29:16 PM PST 23
Finished Dec 20 12:29:42 PM PST 23
Peak memory 196756 kb
Host smart-7c173d1f-5a84-455d-a0a6-0b95b30e4f7c
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2230323025 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 2.gpio_same_csr_outstanding.2230323025
Directory /workspace/2.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.gpio_tl_errors.2430148286
Short name T927
Test name
Test status
Simulation time 132422106 ps
CPU time 3.07 seconds
Started Dec 20 12:27:27 PM PST 23
Finished Dec 20 12:28:08 PM PST 23
Peak memory 198440 kb
Host smart-3040b26c-9306-456c-aac2-0018ecf0cfd8
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2430148286 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.gpio_tl_errors.2430148286
Directory /workspace/2.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.gpio_tl_intg_err.1654774202
Short name T36
Test name
Test status
Simulation time 135341656 ps
CPU time 1.3 seconds
Started Dec 20 12:29:17 PM PST 23
Finished Dec 20 12:29:43 PM PST 23
Peak memory 197868 kb
Host smart-f17eea08-9dd7-4675-b1d2-38e1c8119f6a
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1654774202 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 2.gpio_tl_intg_err.1654774202
Directory /workspace/2.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.gpio_intr_test.1287354575
Short name T903
Test name
Test status
Simulation time 53214492 ps
CPU time 0.58 seconds
Started Dec 20 12:27:50 PM PST 23
Finished Dec 20 12:28:25 PM PST 23
Peak memory 194152 kb
Host smart-82c28896-ed5b-4202-8594-962e36aca6ec
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1287354575 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.gpio_intr_test.1287354575
Directory /workspace/20.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.gpio_intr_test.2921479690
Short name T31
Test name
Test status
Simulation time 13495820 ps
CPU time 0.59 seconds
Started Dec 20 12:28:09 PM PST 23
Finished Dec 20 12:28:50 PM PST 23
Peak memory 194072 kb
Host smart-c4a70b7a-11cc-4dc6-ab44-27cfb43921ab
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2921479690 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.gpio_intr_test.2921479690
Directory /workspace/21.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.gpio_intr_test.1779536887
Short name T94
Test name
Test status
Simulation time 150192914 ps
CPU time 0.61 seconds
Started Dec 20 12:27:49 PM PST 23
Finished Dec 20 12:28:24 PM PST 23
Peak memory 194140 kb
Host smart-ad1e21e7-d821-4a73-905c-fd6189492c5c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1779536887 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.gpio_intr_test.1779536887
Directory /workspace/22.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.gpio_intr_test.2099288911
Short name T918
Test name
Test status
Simulation time 14455788 ps
CPU time 0.6 seconds
Started Dec 20 12:27:51 PM PST 23
Finished Dec 20 12:28:27 PM PST 23
Peak memory 194156 kb
Host smart-0791c329-ccff-491d-b197-5d213ced9218
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2099288911 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.gpio_intr_test.2099288911
Directory /workspace/23.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.gpio_intr_test.2363909795
Short name T932
Test name
Test status
Simulation time 34549210 ps
CPU time 0.6 seconds
Started Dec 20 12:27:41 PM PST 23
Finished Dec 20 12:28:15 PM PST 23
Peak memory 194796 kb
Host smart-5807b4d5-a29b-4871-9fe1-7410647b7389
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2363909795 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.gpio_intr_test.2363909795
Directory /workspace/24.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.gpio_intr_test.2476550747
Short name T887
Test name
Test status
Simulation time 67611265 ps
CPU time 0.6 seconds
Started Dec 20 12:27:44 PM PST 23
Finished Dec 20 12:28:18 PM PST 23
Peak memory 194148 kb
Host smart-8441ee83-06dd-433a-93bf-4c4858da82ab
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2476550747 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.gpio_intr_test.2476550747
Directory /workspace/25.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.gpio_intr_test.3133028415
Short name T865
Test name
Test status
Simulation time 17937197 ps
CPU time 0.63 seconds
Started Dec 20 12:28:00 PM PST 23
Finished Dec 20 12:28:39 PM PST 23
Peak memory 194772 kb
Host smart-2ce88ddf-887a-46c8-9566-200c25152597
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3133028415 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.gpio_intr_test.3133028415
Directory /workspace/26.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.gpio_intr_test.4160444132
Short name T934
Test name
Test status
Simulation time 53468284 ps
CPU time 0.61 seconds
Started Dec 20 12:27:45 PM PST 23
Finished Dec 20 12:28:20 PM PST 23
Peak memory 194100 kb
Host smart-b3fc8023-27e1-49bf-a67f-d5ff560b3de2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4160444132 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.gpio_intr_test.4160444132
Directory /workspace/27.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.gpio_intr_test.3559157766
Short name T905
Test name
Test status
Simulation time 25989663 ps
CPU time 0.58 seconds
Started Dec 20 12:28:11 PM PST 23
Finished Dec 20 12:28:52 PM PST 23
Peak memory 193940 kb
Host smart-77235af9-a3e5-4302-bd69-a6ea932e7cd2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3559157766 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.gpio_intr_test.3559157766
Directory /workspace/28.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.gpio_intr_test.1205218036
Short name T922
Test name
Test status
Simulation time 19119075 ps
CPU time 0.63 seconds
Started Dec 20 12:27:46 PM PST 23
Finished Dec 20 12:28:21 PM PST 23
Peak memory 194252 kb
Host smart-1d6b34f7-b28c-4b20-b990-e49764e1aedb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1205218036 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.gpio_intr_test.1205218036
Directory /workspace/29.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.gpio_csr_aliasing.2608120260
Short name T852
Test name
Test status
Simulation time 20227978 ps
CPU time 0.79 seconds
Started Dec 20 12:27:10 PM PST 23
Finished Dec 20 12:27:45 PM PST 23
Peak memory 196168 kb
Host smart-3fb93436-8b45-4274-b72d-ff0c54896a22
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2608120260 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM
_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name
3.gpio_csr_aliasing.2608120260
Directory /workspace/3.gpio_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.gpio_csr_bit_bash.2024820634
Short name T894
Test name
Test status
Simulation time 92605978 ps
CPU time 1.42 seconds
Started Dec 20 12:27:13 PM PST 23
Finished Dec 20 12:27:51 PM PST 23
Peak memory 197124 kb
Host smart-7f783031-9910-4b27-9dc1-653a23680b67
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2024820634 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.gpio_csr_bit_bash.2024820634
Directory /workspace/3.gpio_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.gpio_csr_hw_reset.3886570660
Short name T84
Test name
Test status
Simulation time 20514584 ps
CPU time 0.65 seconds
Started Dec 20 12:27:12 PM PST 23
Finished Dec 20 12:27:48 PM PST 23
Peak memory 195656 kb
Host smart-59e29c40-71a5-4902-90de-9660b9463cce
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3886570660 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.gpio_csr_hw_reset.3886570660
Directory /workspace/3.gpio_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.gpio_csr_mem_rw_with_rand_reset.3013276
Short name T10
Test name
Test status
Simulation time 52902978 ps
CPU time 0.87 seconds
Started Dec 20 12:27:18 PM PST 23
Finished Dec 20 12:28:03 PM PST 23
Peak memory 198308 kb
Host smart-5d36ba42-223a-4ad1-8ef0-fb6dcf331366
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3013276 -assert
nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/c
over_reg_top.vdb -cm_log /dev/null -cm_name 3.gpio_csr_mem_rw_with_rand_reset.3013276
Directory /workspace/3.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.gpio_csr_rw.2840057391
Short name T851
Test name
Test status
Simulation time 52481115 ps
CPU time 0.58 seconds
Started Dec 20 12:27:13 PM PST 23
Finished Dec 20 12:27:50 PM PST 23
Peak memory 193680 kb
Host smart-01e11393-7496-4036-947a-6da8a58e8565
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2840057391 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.gpio
_csr_rw.2840057391
Directory /workspace/3.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.gpio_intr_test.3975090989
Short name T910
Test name
Test status
Simulation time 15076528 ps
CPU time 0.62 seconds
Started Dec 20 12:27:10 PM PST 23
Finished Dec 20 12:27:53 PM PST 23
Peak memory 194220 kb
Host smart-ff54fc22-f631-423c-833f-cbbed12340b8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3975090989 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.gpio_intr_test.3975090989
Directory /workspace/3.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.gpio_tl_errors.4261693512
Short name T942
Test name
Test status
Simulation time 480495707 ps
CPU time 2.49 seconds
Started Dec 20 12:27:36 PM PST 23
Finished Dec 20 12:28:13 PM PST 23
Peak memory 198376 kb
Host smart-daed461e-a64c-4186-8376-1a20ac3a5248
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4261693512 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.gpio_tl_errors.4261693512
Directory /workspace/3.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.gpio_tl_intg_err.2577159149
Short name T878
Test name
Test status
Simulation time 323886809 ps
CPU time 1.4 seconds
Started Dec 20 12:27:29 PM PST 23
Finished Dec 20 12:28:08 PM PST 23
Peak memory 198460 kb
Host smart-b313507b-91af-48e4-a265-437280fc7583
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2577159149 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 3.gpio_tl_intg_err.2577159149
Directory /workspace/3.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.gpio_intr_test.851231901
Short name T930
Test name
Test status
Simulation time 16465705 ps
CPU time 0.55 seconds
Started Dec 20 12:27:49 PM PST 23
Finished Dec 20 12:28:24 PM PST 23
Peak memory 194156 kb
Host smart-629a333a-56f4-4028-9562-8466310b81a3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=851231901 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.gpio_intr_test.851231901
Directory /workspace/30.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.gpio_intr_test.963241809
Short name T873
Test name
Test status
Simulation time 88886598 ps
CPU time 0.57 seconds
Started Dec 20 12:27:47 PM PST 23
Finished Dec 20 12:28:22 PM PST 23
Peak memory 194088 kb
Host smart-740b6263-eec0-4d3a-b2d2-d6fc7b604729
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=963241809 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.gpio_intr_test.963241809
Directory /workspace/31.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.gpio_intr_test.4161393938
Short name T24
Test name
Test status
Simulation time 23847577 ps
CPU time 0.57 seconds
Started Dec 20 12:27:53 PM PST 23
Finished Dec 20 12:28:29 PM PST 23
Peak memory 194164 kb
Host smart-c8d42fb2-0ba1-45e9-9c54-b02ff5c3cdf2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4161393938 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.gpio_intr_test.4161393938
Directory /workspace/32.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.gpio_intr_test.2756569226
Short name T917
Test name
Test status
Simulation time 15549907 ps
CPU time 0.56 seconds
Started Dec 20 12:28:13 PM PST 23
Finished Dec 20 12:28:53 PM PST 23
Peak memory 194744 kb
Host smart-57b17c88-f76e-431f-bf04-764c7962ecea
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2756569226 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.gpio_intr_test.2756569226
Directory /workspace/33.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.gpio_intr_test.2759836870
Short name T901
Test name
Test status
Simulation time 52351131 ps
CPU time 0.61 seconds
Started Dec 20 12:27:43 PM PST 23
Finished Dec 20 12:28:17 PM PST 23
Peak memory 194744 kb
Host smart-870737d4-e409-4c6b-8fb3-e313eaa85b5d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2759836870 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.gpio_intr_test.2759836870
Directory /workspace/34.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.gpio_intr_test.3127313561
Short name T849
Test name
Test status
Simulation time 26763113 ps
CPU time 0.6 seconds
Started Dec 20 12:27:52 PM PST 23
Finished Dec 20 12:28:28 PM PST 23
Peak memory 194188 kb
Host smart-ff8b6f71-638f-4614-829e-9cca611d56af
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3127313561 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.gpio_intr_test.3127313561
Directory /workspace/35.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.gpio_intr_test.2868953956
Short name T907
Test name
Test status
Simulation time 11671063 ps
CPU time 0.62 seconds
Started Dec 20 12:27:51 PM PST 23
Finished Dec 20 12:28:27 PM PST 23
Peak memory 194748 kb
Host smart-03e99261-bcf8-46e6-8437-5d1e8f04f9f3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2868953956 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.gpio_intr_test.2868953956
Directory /workspace/36.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.gpio_intr_test.4213278830
Short name T874
Test name
Test status
Simulation time 24135655 ps
CPU time 0.58 seconds
Started Dec 20 12:28:20 PM PST 23
Finished Dec 20 12:28:56 PM PST 23
Peak memory 194724 kb
Host smart-8256f774-80f6-4b76-8dd7-f55667a95fb7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4213278830 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.gpio_intr_test.4213278830
Directory /workspace/37.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.gpio_intr_test.928042235
Short name T936
Test name
Test status
Simulation time 12998497 ps
CPU time 0.61 seconds
Started Dec 20 12:27:45 PM PST 23
Finished Dec 20 12:28:19 PM PST 23
Peak memory 194104 kb
Host smart-8b30c8cb-8033-465b-8482-e6ab73776893
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=928042235 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.gpio_intr_test.928042235
Directory /workspace/38.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.gpio_intr_test.3996753397
Short name T939
Test name
Test status
Simulation time 25105486 ps
CPU time 0.6 seconds
Started Dec 20 12:27:55 PM PST 23
Finished Dec 20 12:28:33 PM PST 23
Peak memory 194080 kb
Host smart-4ee37c48-4d57-4ed8-9710-93a789011adb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3996753397 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.gpio_intr_test.3996753397
Directory /workspace/39.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.gpio_csr_aliasing.2684145309
Short name T77
Test name
Test status
Simulation time 97550038 ps
CPU time 0.75 seconds
Started Dec 20 12:27:26 PM PST 23
Finished Dec 20 12:28:06 PM PST 23
Peak memory 196212 kb
Host smart-639c00a9-0d62-4a85-9696-fddecc8d64f9
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2684145309 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM
_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name
4.gpio_csr_aliasing.2684145309
Directory /workspace/4.gpio_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.gpio_csr_bit_bash.3613967704
Short name T857
Test name
Test status
Simulation time 160453361 ps
CPU time 2.82 seconds
Started Dec 20 12:29:01 PM PST 23
Finished Dec 20 12:29:36 PM PST 23
Peak memory 196996 kb
Host smart-5cf20f4f-8d73-461e-8c5d-61aee2e9b9a5
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3613967704 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.gpio_csr_bit_bash.3613967704
Directory /workspace/4.gpio_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.gpio_csr_hw_reset.3162154617
Short name T855
Test name
Test status
Simulation time 34731067 ps
CPU time 0.63 seconds
Started Dec 20 12:27:10 PM PST 23
Finished Dec 20 12:27:43 PM PST 23
Peak memory 194952 kb
Host smart-d0854f61-db89-4249-918a-9ff2f731a204
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3162154617 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.gpio_csr_hw_reset.3162154617
Directory /workspace/4.gpio_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.gpio_csr_mem_rw_with_rand_reset.3979332848
Short name T864
Test name
Test status
Simulation time 45601194 ps
CPU time 0.7 seconds
Started Dec 20 12:29:15 PM PST 23
Finished Dec 20 12:29:42 PM PST 23
Peak memory 197816 kb
Host smart-d5785e95-7794-4cd8-aa20-ee90c5293080
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3979332848 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.gpio_csr_mem_rw_with_rand_reset.3979332848
Directory /workspace/4.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.gpio_csr_rw.227617705
Short name T870
Test name
Test status
Simulation time 50141168 ps
CPU time 0.61 seconds
Started Dec 20 12:27:25 PM PST 23
Finished Dec 20 12:28:05 PM PST 23
Peak memory 195132 kb
Host smart-8a60df85-ef5a-4b87-a412-21baf57693f3
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=227617705 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_S
EQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.gpio_
csr_rw.227617705
Directory /workspace/4.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.gpio_intr_test.2502728654
Short name T877
Test name
Test status
Simulation time 21054899 ps
CPU time 0.57 seconds
Started Dec 20 12:29:22 PM PST 23
Finished Dec 20 12:29:46 PM PST 23
Peak memory 193688 kb
Host smart-f7e3641c-092d-4a62-a4d9-e80cdba475cd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2502728654 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.gpio_intr_test.2502728654
Directory /workspace/4.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.gpio_same_csr_outstanding.4270129710
Short name T89
Test name
Test status
Simulation time 19179915 ps
CPU time 0.8 seconds
Started Dec 20 12:27:38 PM PST 23
Finished Dec 20 12:28:13 PM PST 23
Peak memory 196404 kb
Host smart-ab62f7d2-a95c-4808-aa2f-badc4233aeb9
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4270129710 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 4.gpio_same_csr_outstanding.4270129710
Directory /workspace/4.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.gpio_tl_errors.1975912073
Short name T904
Test name
Test status
Simulation time 344541967 ps
CPU time 1.85 seconds
Started Dec 20 12:27:20 PM PST 23
Finished Dec 20 12:28:01 PM PST 23
Peak memory 198400 kb
Host smart-e5d226b2-5a7e-446d-a651-03c7fc1b783c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1975912073 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.gpio_tl_errors.1975912073
Directory /workspace/4.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.gpio_tl_intg_err.1303481002
Short name T914
Test name
Test status
Simulation time 339313123 ps
CPU time 1.34 seconds
Started Dec 20 12:27:07 PM PST 23
Finished Dec 20 12:27:39 PM PST 23
Peak memory 198488 kb
Host smart-10a5693c-a67d-4495-a578-4205ca72c7bf
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1303481002 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 4.gpio_tl_intg_err.1303481002
Directory /workspace/4.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.gpio_intr_test.1057472981
Short name T108
Test name
Test status
Simulation time 87084362 ps
CPU time 0.58 seconds
Started Dec 20 12:28:09 PM PST 23
Finished Dec 20 12:28:49 PM PST 23
Peak memory 194072 kb
Host smart-3c8947f6-20ed-48c5-962c-db849cb3c2b8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1057472981 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.gpio_intr_test.1057472981
Directory /workspace/40.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.gpio_intr_test.140819410
Short name T883
Test name
Test status
Simulation time 10448717 ps
CPU time 0.57 seconds
Started Dec 20 12:27:48 PM PST 23
Finished Dec 20 12:28:23 PM PST 23
Peak memory 194096 kb
Host smart-91df643a-ab22-41e0-98b0-63a838cc176d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=140819410 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.gpio_intr_test.140819410
Directory /workspace/41.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.gpio_intr_test.419263655
Short name T19
Test name
Test status
Simulation time 57648263 ps
CPU time 0.59 seconds
Started Dec 20 12:27:45 PM PST 23
Finished Dec 20 12:28:19 PM PST 23
Peak memory 194136 kb
Host smart-e26b098a-7b8d-4ad1-911c-3a1b0571255d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=419263655 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.gpio_intr_test.419263655
Directory /workspace/42.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.gpio_intr_test.1948654061
Short name T106
Test name
Test status
Simulation time 56365597 ps
CPU time 0.59 seconds
Started Dec 20 12:27:53 PM PST 23
Finished Dec 20 12:28:28 PM PST 23
Peak memory 194052 kb
Host smart-d6064922-fedb-4267-937a-4d226ec5bbba
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1948654061 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.gpio_intr_test.1948654061
Directory /workspace/44.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.gpio_intr_test.2286805578
Short name T876
Test name
Test status
Simulation time 38508840 ps
CPU time 0.57 seconds
Started Dec 20 12:27:52 PM PST 23
Finished Dec 20 12:28:28 PM PST 23
Peak memory 194812 kb
Host smart-77bd81d1-6356-4fb0-9889-31b8ac8f2523
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2286805578 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.gpio_intr_test.2286805578
Directory /workspace/45.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.gpio_intr_test.1915385687
Short name T909
Test name
Test status
Simulation time 14959301 ps
CPU time 0.61 seconds
Started Dec 20 12:27:43 PM PST 23
Finished Dec 20 12:28:18 PM PST 23
Peak memory 194860 kb
Host smart-558e8008-684f-434d-aed4-7ba0b9643731
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1915385687 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.gpio_intr_test.1915385687
Directory /workspace/46.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.gpio_intr_test.3367923870
Short name T18
Test name
Test status
Simulation time 75097280 ps
CPU time 0.57 seconds
Started Dec 20 12:27:44 PM PST 23
Finished Dec 20 12:28:18 PM PST 23
Peak memory 194072 kb
Host smart-27198192-a6d7-42dd-a9bc-458949192afc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3367923870 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.gpio_intr_test.3367923870
Directory /workspace/47.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.gpio_intr_test.2495963056
Short name T892
Test name
Test status
Simulation time 26318999 ps
CPU time 0.59 seconds
Started Dec 20 12:27:50 PM PST 23
Finished Dec 20 12:28:26 PM PST 23
Peak memory 194124 kb
Host smart-cbaea8e6-8e47-4695-94fa-dcdd00b0d386
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2495963056 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.gpio_intr_test.2495963056
Directory /workspace/48.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.gpio_intr_test.2995806007
Short name T20
Test name
Test status
Simulation time 12501075 ps
CPU time 0.57 seconds
Started Dec 20 12:27:56 PM PST 23
Finished Dec 20 12:28:34 PM PST 23
Peak memory 194180 kb
Host smart-e5b7b807-c1b2-4b14-a1b9-65fb2097d6a0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2995806007 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.gpio_intr_test.2995806007
Directory /workspace/49.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.gpio_csr_mem_rw_with_rand_reset.754493700
Short name T13
Test name
Test status
Simulation time 76486379 ps
CPU time 1.26 seconds
Started Dec 20 12:29:12 PM PST 23
Finished Dec 20 12:29:41 PM PST 23
Peak memory 195972 kb
Host smart-ce1c0a94-6009-460f-8cf5-b82beeb348e2
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=754493700 -asser
t nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage
/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.gpio_csr_mem_rw_with_rand_reset.754493700
Directory /workspace/5.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.gpio_csr_rw.586564777
Short name T93
Test name
Test status
Simulation time 14473182 ps
CPU time 0.58 seconds
Started Dec 20 12:27:12 PM PST 23
Finished Dec 20 12:27:48 PM PST 23
Peak memory 195524 kb
Host smart-64429b13-d261-4376-ba0b-b2f4d8c0efb3
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=586564777 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_S
EQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.gpio_
csr_rw.586564777
Directory /workspace/5.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.gpio_intr_test.901139331
Short name T919
Test name
Test status
Simulation time 40712769 ps
CPU time 0.55 seconds
Started Dec 20 12:29:00 PM PST 23
Finished Dec 20 12:29:33 PM PST 23
Peak memory 193552 kb
Host smart-2b940733-50e2-45a9-b016-41c536b220a1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=901139331 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.gpio_intr_test.901139331
Directory /workspace/5.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.gpio_same_csr_outstanding.4145682342
Short name T11
Test name
Test status
Simulation time 70761529 ps
CPU time 0.83 seconds
Started Dec 20 12:27:18 PM PST 23
Finished Dec 20 12:27:58 PM PST 23
Peak memory 196880 kb
Host smart-fb89f003-b2db-4f73-a471-511e0fae9067
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4145682342 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 5.gpio_same_csr_outstanding.4145682342
Directory /workspace/5.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.gpio_tl_errors.3780628293
Short name T940
Test name
Test status
Simulation time 37239856 ps
CPU time 1.83 seconds
Started Dec 20 12:27:09 PM PST 23
Finished Dec 20 12:27:41 PM PST 23
Peak memory 198456 kb
Host smart-c722c800-a581-44ea-98f9-c06ab6c829f0
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3780628293 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.gpio_tl_errors.3780628293
Directory /workspace/5.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.gpio_tl_intg_err.2375211038
Short name T25
Test name
Test status
Simulation time 178138815 ps
CPU time 1.38 seconds
Started Dec 20 12:27:21 PM PST 23
Finished Dec 20 12:28:02 PM PST 23
Peak memory 198448 kb
Host smart-bea86507-ba37-442a-ad07-64f6bb941848
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2375211038 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 5.gpio_tl_intg_err.2375211038
Directory /workspace/5.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.gpio_csr_mem_rw_with_rand_reset.4688302
Short name T941
Test name
Test status
Simulation time 23503775 ps
CPU time 0.69 seconds
Started Dec 20 12:29:02 PM PST 23
Finished Dec 20 12:29:35 PM PST 23
Peak memory 197592 kb
Host smart-741f7e4e-c6b7-47f7-a112-67b38ee99714
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4688302 -assert
nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/c
over_reg_top.vdb -cm_log /dev/null -cm_name 6.gpio_csr_mem_rw_with_rand_reset.4688302
Directory /workspace/6.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.gpio_csr_rw.3099719173
Short name T78
Test name
Test status
Simulation time 11902081 ps
CPU time 0.64 seconds
Started Dec 20 12:27:18 PM PST 23
Finished Dec 20 12:27:58 PM PST 23
Peak memory 195248 kb
Host smart-0d8d4095-0936-44e5-9aab-3b3962cf14ed
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3099719173 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.gpio
_csr_rw.3099719173
Directory /workspace/6.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.gpio_intr_test.1810561350
Short name T21
Test name
Test status
Simulation time 29853140 ps
CPU time 0.61 seconds
Started Dec 20 12:29:45 PM PST 23
Finished Dec 20 12:30:04 PM PST 23
Peak memory 193832 kb
Host smart-c353a7e0-dbb0-458e-a87b-c7cc73f7a435
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1810561350 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.gpio_intr_test.1810561350
Directory /workspace/6.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.gpio_same_csr_outstanding.4002470436
Short name T91
Test name
Test status
Simulation time 73501176 ps
CPU time 0.8 seconds
Started Dec 20 12:27:17 PM PST 23
Finished Dec 20 12:27:56 PM PST 23
Peak memory 196584 kb
Host smart-d4e8beb4-f56b-4996-b658-e4bfd8e4c6f4
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4002470436 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 6.gpio_same_csr_outstanding.4002470436
Directory /workspace/6.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.gpio_tl_errors.101011646
Short name T886
Test name
Test status
Simulation time 256607551 ps
CPU time 2.45 seconds
Started Dec 20 12:29:12 PM PST 23
Finished Dec 20 12:29:42 PM PST 23
Peak memory 195792 kb
Host smart-0589d4b9-f9f1-42ac-bd5e-f5ee4df8e78f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=101011646 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.gpio_tl_errors.101011646
Directory /workspace/6.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.gpio_tl_intg_err.3116269141
Short name T931
Test name
Test status
Simulation time 164547184 ps
CPU time 1.33 seconds
Started Dec 20 12:29:01 PM PST 23
Finished Dec 20 12:29:34 PM PST 23
Peak memory 197764 kb
Host smart-26e42d73-f311-489f-b3bd-110592e22846
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3116269141 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 6.gpio_tl_intg_err.3116269141
Directory /workspace/6.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.gpio_csr_mem_rw_with_rand_reset.3825747469
Short name T900
Test name
Test status
Simulation time 346365357 ps
CPU time 0.73 seconds
Started Dec 20 12:29:01 PM PST 23
Finished Dec 20 12:29:34 PM PST 23
Peak memory 197784 kb
Host smart-d1fdefcf-ee7b-4f53-af35-ab42c70142c8
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3825747469 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.gpio_csr_mem_rw_with_rand_reset.3825747469
Directory /workspace/7.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.gpio_csr_rw.3452131714
Short name T102
Test name
Test status
Simulation time 52100368 ps
CPU time 0.6 seconds
Started Dec 20 12:27:14 PM PST 23
Finished Dec 20 12:27:51 PM PST 23
Peak memory 194968 kb
Host smart-4259c9d3-39f8-4483-9965-fee2a5dffced
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3452131714 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.gpio
_csr_rw.3452131714
Directory /workspace/7.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.gpio_intr_test.4163551994
Short name T871
Test name
Test status
Simulation time 52957520 ps
CPU time 0.58 seconds
Started Dec 20 12:29:38 PM PST 23
Finished Dec 20 12:29:58 PM PST 23
Peak memory 193900 kb
Host smart-0462198b-ca5a-483a-aec1-d7d12205251e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4163551994 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.gpio_intr_test.4163551994
Directory /workspace/7.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.gpio_same_csr_outstanding.955308030
Short name T923
Test name
Test status
Simulation time 25709780 ps
CPU time 0.7 seconds
Started Dec 20 12:27:30 PM PST 23
Finished Dec 20 12:28:08 PM PST 23
Peak memory 196256 kb
Host smart-7637a5a7-f6e7-4173-bb7e-fc612da101aa
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=955308030 -assert nopostproc +UVM_TESTNAME=gpio_bas
e_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul
l -cm_name 7.gpio_same_csr_outstanding.955308030
Directory /workspace/7.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.gpio_tl_errors.1257633568
Short name T5
Test name
Test status
Simulation time 562547418 ps
CPU time 2.77 seconds
Started Dec 20 12:28:50 PM PST 23
Finished Dec 20 12:29:27 PM PST 23
Peak memory 197028 kb
Host smart-d22a5542-2c29-4635-b89a-ec27e32f302e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1257633568 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.gpio_tl_errors.1257633568
Directory /workspace/7.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.gpio_tl_intg_err.2858493333
Short name T3
Test name
Test status
Simulation time 231181016 ps
CPU time 1.1 seconds
Started Dec 20 12:27:17 PM PST 23
Finished Dec 20 12:27:56 PM PST 23
Peak memory 198340 kb
Host smart-ea67cfd7-4772-40d6-be1d-978a0b237da6
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2858493333 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 7.gpio_tl_intg_err.2858493333
Directory /workspace/7.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.gpio_csr_mem_rw_with_rand_reset.1658340309
Short name T37
Test name
Test status
Simulation time 16935088 ps
CPU time 0.64 seconds
Started Dec 20 12:27:30 PM PST 23
Finished Dec 20 12:28:08 PM PST 23
Peak memory 197332 kb
Host smart-cd200a8a-d467-4acc-bf3d-7947ae450bcd
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1658340309 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.gpio_csr_mem_rw_with_rand_reset.1658340309
Directory /workspace/8.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.gpio_csr_rw.1255213823
Short name T926
Test name
Test status
Simulation time 15251727 ps
CPU time 0.56 seconds
Started Dec 20 12:29:06 PM PST 23
Finished Dec 20 12:29:36 PM PST 23
Peak memory 193080 kb
Host smart-885dce7b-64d3-4464-b5fc-2551c7ccf222
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1255213823 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.gpio
_csr_rw.1255213823
Directory /workspace/8.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.gpio_intr_test.932697605
Short name T879
Test name
Test status
Simulation time 21822824 ps
CPU time 0.59 seconds
Started Dec 20 12:27:08 PM PST 23
Finished Dec 20 12:27:40 PM PST 23
Peak memory 194172 kb
Host smart-25a96b28-f60d-430b-8704-34594bde5a24
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=932697605 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.gpio_intr_test.932697605
Directory /workspace/8.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.gpio_same_csr_outstanding.1460773675
Short name T27
Test name
Test status
Simulation time 17061558 ps
CPU time 0.65 seconds
Started Dec 20 12:27:08 PM PST 23
Finished Dec 20 12:27:39 PM PST 23
Peak memory 195696 kb
Host smart-46ed4e91-87e5-4afe-b28a-7d047ff2192a
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1460773675 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 8.gpio_same_csr_outstanding.1460773675
Directory /workspace/8.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.gpio_tl_errors.544027299
Short name T71
Test name
Test status
Simulation time 593739008 ps
CPU time 1.52 seconds
Started Dec 20 12:27:46 PM PST 23
Finished Dec 20 12:28:21 PM PST 23
Peak memory 198408 kb
Host smart-735d937b-a1a1-4d2a-8496-79a1dba20bc8
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=544027299 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.gpio_tl_errors.544027299
Directory /workspace/8.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.gpio_tl_intg_err.3313330063
Short name T32
Test name
Test status
Simulation time 237688637 ps
CPU time 1.42 seconds
Started Dec 20 12:27:34 PM PST 23
Finished Dec 20 12:28:11 PM PST 23
Peak memory 198144 kb
Host smart-31709ffa-2429-46a3-a2e8-1d5f790935d9
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3313330063 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 8.gpio_tl_intg_err.3313330063
Directory /workspace/8.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.gpio_csr_mem_rw_with_rand_reset.1360671020
Short name T933
Test name
Test status
Simulation time 66765193 ps
CPU time 0.7 seconds
Started Dec 20 12:27:16 PM PST 23
Finished Dec 20 12:27:54 PM PST 23
Peak memory 198068 kb
Host smart-de085030-d1b2-4f07-836a-c7072073e06a
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1360671020 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.gpio_csr_mem_rw_with_rand_reset.1360671020
Directory /workspace/9.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.gpio_csr_rw.1869899587
Short name T73
Test name
Test status
Simulation time 44922642 ps
CPU time 0.6 seconds
Started Dec 20 12:27:12 PM PST 23
Finished Dec 20 12:27:48 PM PST 23
Peak memory 194832 kb
Host smart-ac3ef6a4-65a9-44be-9746-ddac5fe57471
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1869899587 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.gpio
_csr_rw.1869899587
Directory /workspace/9.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.gpio_intr_test.3416429641
Short name T935
Test name
Test status
Simulation time 12513012 ps
CPU time 0.58 seconds
Started Dec 20 12:27:46 PM PST 23
Finished Dec 20 12:28:20 PM PST 23
Peak memory 193840 kb
Host smart-a68a4d0d-a0ee-463b-87ad-640569ed4392
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3416429641 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.gpio_intr_test.3416429641
Directory /workspace/9.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.gpio_same_csr_outstanding.3239784393
Short name T8
Test name
Test status
Simulation time 87019115 ps
CPU time 0.72 seconds
Started Dec 20 12:27:30 PM PST 23
Finished Dec 20 12:28:08 PM PST 23
Peak memory 195212 kb
Host smart-e5f2db3e-e25e-4317-8b5f-2360195e2c4a
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3239784393 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 9.gpio_same_csr_outstanding.3239784393
Directory /workspace/9.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.gpio_tl_errors.3411760516
Short name T16
Test name
Test status
Simulation time 32289602 ps
CPU time 1.47 seconds
Started Dec 20 12:27:36 PM PST 23
Finished Dec 20 12:28:12 PM PST 23
Peak memory 198420 kb
Host smart-2334b3f9-f73f-4ddc-9ba7-fde27c914f83
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3411760516 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.gpio_tl_errors.3411760516
Directory /workspace/9.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.gpio_tl_intg_err.1224903910
Short name T867
Test name
Test status
Simulation time 47285159 ps
CPU time 0.84 seconds
Started Dec 20 12:27:40 PM PST 23
Finished Dec 20 12:28:15 PM PST 23
Peak memory 197540 kb
Host smart-addfc0c2-26d3-416e-bba6-b3a48717186f
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1224903910 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 9.gpio_tl_intg_err.1224903910
Directory /workspace/9.gpio_tl_intg_err/latest

Test location /workspace/coverage/default/0.gpio_alert_test.1565991895
Short name T440
Test name
Test status
Simulation time 92115864 ps
CPU time 0.56 seconds
Started Dec 20 12:28:38 PM PST 23
Finished Dec 20 12:29:11 PM PST 23
Peak memory 194184 kb
Host smart-68defbed-600f-496d-918c-b7f8bbfac3be
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1565991895 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_alert_test.1565991895
Directory /workspace/0.gpio_alert_test/latest

Test location /workspace/coverage/default/0.gpio_dout_din_regs_random_rw.1634946081
Short name T691
Test name
Test status
Simulation time 33385108 ps
CPU time 0.8 seconds
Started Dec 20 12:28:39 PM PST 23
Finished Dec 20 12:29:11 PM PST 23
Peak memory 196392 kb
Host smart-65d56dc9-1b7a-419d-85fe-fd770979b2dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1634946081 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_dout_din_regs_random_rw.1634946081
Directory /workspace/0.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/0.gpio_filter_stress.3201143021
Short name T842
Test name
Test status
Simulation time 217220043 ps
CPU time 5.35 seconds
Started Dec 20 12:28:32 PM PST 23
Finished Dec 20 12:29:10 PM PST 23
Peak memory 198132 kb
Host smart-3302d13d-9cbf-45de-8c7e-9ed4b4f4e0e4
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3201143021 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_filter_stres
s.3201143021
Directory /workspace/0.gpio_filter_stress/latest

Test location /workspace/coverage/default/0.gpio_full_random.376212203
Short name T295
Test name
Test status
Simulation time 118834768 ps
CPU time 0.9 seconds
Started Dec 20 12:28:42 PM PST 23
Finished Dec 20 12:29:15 PM PST 23
Peak memory 197032 kb
Host smart-6d8c6179-aa18-4ca7-b9e5-693172adf922
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=376212203 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_full_random.376212203
Directory /workspace/0.gpio_full_random/latest

Test location /workspace/coverage/default/0.gpio_intr_rand_pgm.1851324314
Short name T522
Test name
Test status
Simulation time 109334073 ps
CPU time 1.35 seconds
Started Dec 20 12:28:41 PM PST 23
Finished Dec 20 12:29:15 PM PST 23
Peak memory 196644 kb
Host smart-bd48321e-1050-4d31-be34-1acca29dead1
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1851324314 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_intr_rand_pgm.1851324314
Directory /workspace/0.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/0.gpio_intr_with_filter_rand_intr_event.1554618965
Short name T404
Test name
Test status
Simulation time 81291030 ps
CPU time 1.7 seconds
Started Dec 20 12:28:37 PM PST 23
Finished Dec 20 12:29:10 PM PST 23
Peak memory 197324 kb
Host smart-8b7e5d14-fbc1-4b33-952e-a56dd224310b
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1554618965 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 0.gpio_intr_with_filter_rand_intr_event.1554618965
Directory /workspace/0.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/0.gpio_rand_intr_trigger.3750738671
Short name T545
Test name
Test status
Simulation time 1924899045 ps
CPU time 3.17 seconds
Started Dec 20 12:28:36 PM PST 23
Finished Dec 20 12:29:10 PM PST 23
Peak memory 198196 kb
Host smart-d2422780-47cb-415c-b4a7-0afe3a98baac
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3750738671 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_rand_intr_trigger.
3750738671
Directory /workspace/0.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/0.gpio_random_dout_din.2162689794
Short name T643
Test name
Test status
Simulation time 38218626 ps
CPU time 0.63 seconds
Started Dec 20 12:28:43 PM PST 23
Finished Dec 20 12:29:16 PM PST 23
Peak memory 194384 kb
Host smart-7aecd1fa-d982-4921-a048-ed2c17b43253
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2162689794 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_random_dout_din.2162689794
Directory /workspace/0.gpio_random_dout_din/latest

Test location /workspace/coverage/default/0.gpio_random_dout_din_no_pullup_pulldown.3943076423
Short name T844
Test name
Test status
Simulation time 40791327 ps
CPU time 1.13 seconds
Started Dec 20 12:28:35 PM PST 23
Finished Dec 20 12:29:08 PM PST 23
Peak memory 197168 kb
Host smart-7d19b359-65bd-4749-83a9-7707a45eb6e7
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3943076423 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_random_dout_din_no_pullup
_pulldown.3943076423
Directory /workspace/0.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/0.gpio_random_long_reg_writes_reg_reads.2154968841
Short name T321
Test name
Test status
Simulation time 574193326 ps
CPU time 3.6 seconds
Started Dec 20 12:28:41 PM PST 23
Finished Dec 20 12:29:16 PM PST 23
Peak memory 198124 kb
Host smart-cdab48d5-8bc3-4c69-a824-a857c7e40a41
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2154968841 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_ran
dom_long_reg_writes_reg_reads.2154968841
Directory /workspace/0.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/0.gpio_sec_cm.2786617062
Short name T59
Test name
Test status
Simulation time 89070543 ps
CPU time 0.92 seconds
Started Dec 20 12:28:38 PM PST 23
Finished Dec 20 12:29:11 PM PST 23
Peak memory 214672 kb
Host smart-077e84ba-4d24-4cb8-9ef3-4cc12b8d600d
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2786617062 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_sec_cm.2786617062
Directory /workspace/0.gpio_sec_cm/latest

Test location /workspace/coverage/default/0.gpio_smoke.393392087
Short name T198
Test name
Test status
Simulation time 28570059 ps
CPU time 0.9 seconds
Started Dec 20 12:28:44 PM PST 23
Finished Dec 20 12:29:17 PM PST 23
Peak memory 195844 kb
Host smart-ce374dde-837b-44e5-b49d-b380ef31f705
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=393392087 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_smoke.393392087
Directory /workspace/0.gpio_smoke/latest

Test location /workspace/coverage/default/0.gpio_smoke_no_pullup_pulldown.2997316504
Short name T256
Test name
Test status
Simulation time 283572190 ps
CPU time 1.24 seconds
Started Dec 20 12:28:42 PM PST 23
Finished Dec 20 12:29:15 PM PST 23
Peak memory 196316 kb
Host smart-83f11eb0-dc44-4094-8404-9948b2202188
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2997316504 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_smoke_no_pullup_pulldown.2997316504
Directory /workspace/0.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/0.gpio_stress_all.3823571725
Short name T61
Test name
Test status
Simulation time 10556402696 ps
CPU time 96.46 seconds
Started Dec 20 12:28:43 PM PST 23
Finished Dec 20 12:30:52 PM PST 23
Peak memory 198292 kb
Host smart-f5383330-78a4-424e-9b85-d0fc522d1260
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3823571725 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.g
pio_stress_all.3823571725
Directory /workspace/0.gpio_stress_all/latest

Test location /workspace/coverage/default/0.gpio_stress_all_with_rand_reset.282926111
Short name T569
Test name
Test status
Simulation time 148222719870 ps
CPU time 854.06 seconds
Started Dec 20 12:28:39 PM PST 23
Finished Dec 20 12:43:25 PM PST 23
Peak memory 198232 kb
Host smart-cb0d722f-f49d-4a4b-a0a1-4f6818fa8686
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=282926111 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_stress_all_with_rand_reset.282926111
Directory /workspace/0.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/1.gpio_dout_din_regs_random_rw.3471570760
Short name T201
Test name
Test status
Simulation time 26554500 ps
CPU time 0.82 seconds
Started Dec 20 12:28:42 PM PST 23
Finished Dec 20 12:29:14 PM PST 23
Peak memory 195424 kb
Host smart-732bba72-8c92-458d-819b-f4a2520e7b8a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3471570760 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_dout_din_regs_random_rw.3471570760
Directory /workspace/1.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/1.gpio_filter_stress.1120442116
Short name T730
Test name
Test status
Simulation time 2207324330 ps
CPU time 15.11 seconds
Started Dec 20 12:28:40 PM PST 23
Finished Dec 20 12:29:27 PM PST 23
Peak memory 196592 kb
Host smart-b2be6724-5c5a-4313-9c6b-77856adb8229
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1120442116 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_filter_stres
s.1120442116
Directory /workspace/1.gpio_filter_stress/latest

Test location /workspace/coverage/default/1.gpio_full_random.1872021580
Short name T814
Test name
Test status
Simulation time 359072850 ps
CPU time 1.04 seconds
Started Dec 20 12:28:34 PM PST 23
Finished Dec 20 12:29:07 PM PST 23
Peak memory 197988 kb
Host smart-d7116aa1-4b8d-460e-903f-0f7ecded48bc
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1872021580 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_full_random.1872021580
Directory /workspace/1.gpio_full_random/latest

Test location /workspace/coverage/default/1.gpio_intr_rand_pgm.3866354968
Short name T592
Test name
Test status
Simulation time 52959759 ps
CPU time 1.19 seconds
Started Dec 20 12:28:43 PM PST 23
Finished Dec 20 12:29:16 PM PST 23
Peak memory 197120 kb
Host smart-d5cfc4af-13e5-4c39-8b74-f7e4af434491
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3866354968 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_intr_rand_pgm.3866354968
Directory /workspace/1.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/1.gpio_intr_with_filter_rand_intr_event.2061414888
Short name T348
Test name
Test status
Simulation time 68682788 ps
CPU time 2.35 seconds
Started Dec 20 12:28:38 PM PST 23
Finished Dec 20 12:29:12 PM PST 23
Peak memory 196680 kb
Host smart-8704ea1c-a212-4f80-822d-cfd8f891fb9f
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2061414888 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 1.gpio_intr_with_filter_rand_intr_event.2061414888
Directory /workspace/1.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/1.gpio_rand_intr_trigger.3172153225
Short name T282
Test name
Test status
Simulation time 82112933 ps
CPU time 2.09 seconds
Started Dec 20 12:28:41 PM PST 23
Finished Dec 20 12:29:15 PM PST 23
Peak memory 197868 kb
Host smart-c10be0ec-e640-4c9c-8665-4efcf50c089f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3172153225 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_rand_intr_trigger.
3172153225
Directory /workspace/1.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/1.gpio_random_dout_din.3341617133
Short name T224
Test name
Test status
Simulation time 40171829 ps
CPU time 0.95 seconds
Started Dec 20 12:28:31 PM PST 23
Finished Dec 20 12:29:05 PM PST 23
Peak memory 196812 kb
Host smart-a470fd7d-7619-472d-ae84-0583c957fd00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3341617133 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_random_dout_din.3341617133
Directory /workspace/1.gpio_random_dout_din/latest

Test location /workspace/coverage/default/1.gpio_random_dout_din_no_pullup_pulldown.3236854385
Short name T728
Test name
Test status
Simulation time 207163956 ps
CPU time 1.2 seconds
Started Dec 20 12:28:35 PM PST 23
Finished Dec 20 12:29:08 PM PST 23
Peak memory 197140 kb
Host smart-1087fab2-00f7-4484-8c0a-fcaa0b682f11
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3236854385 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_random_dout_din_no_pullup
_pulldown.3236854385
Directory /workspace/1.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/1.gpio_random_long_reg_writes_reg_reads.3260060053
Short name T468
Test name
Test status
Simulation time 68784159 ps
CPU time 3.05 seconds
Started Dec 20 12:28:42 PM PST 23
Finished Dec 20 12:29:17 PM PST 23
Peak memory 198180 kb
Host smart-e12ba9fb-d639-45c4-9d21-1eed1ce84146
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3260060053 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_ran
dom_long_reg_writes_reg_reads.3260060053
Directory /workspace/1.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/1.gpio_sec_cm.3487686144
Short name T30
Test name
Test status
Simulation time 227455211 ps
CPU time 0.78 seconds
Started Dec 20 12:28:47 PM PST 23
Finished Dec 20 12:29:21 PM PST 23
Peak memory 212740 kb
Host smart-5dc73721-fea4-45dd-add9-9305f03c0099
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3487686144 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_sec_cm.3487686144
Directory /workspace/1.gpio_sec_cm/latest

Test location /workspace/coverage/default/1.gpio_smoke.174196850
Short name T377
Test name
Test status
Simulation time 51691690 ps
CPU time 0.84 seconds
Started Dec 20 12:28:38 PM PST 23
Finished Dec 20 12:29:11 PM PST 23
Peak memory 196168 kb
Host smart-554ef0e0-59e5-4ba1-b887-d47da6ea1b74
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=174196850 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_smoke.174196850
Directory /workspace/1.gpio_smoke/latest

Test location /workspace/coverage/default/1.gpio_smoke_no_pullup_pulldown.616822896
Short name T227
Test name
Test status
Simulation time 667305263 ps
CPU time 1.31 seconds
Started Dec 20 12:28:34 PM PST 23
Finished Dec 20 12:29:07 PM PST 23
Peak memory 196600 kb
Host smart-ea617d56-4361-4124-adc9-02b5b9053477
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=616822896 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_smoke_no_pullup_pulldown.616822896
Directory /workspace/1.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/1.gpio_stress_all.1497751208
Short name T655
Test name
Test status
Simulation time 12362153734 ps
CPU time 64.46 seconds
Started Dec 20 12:28:38 PM PST 23
Finished Dec 20 12:30:14 PM PST 23
Peak memory 198076 kb
Host smart-95136efe-e0ce-4bfb-9311-86ee99260e14
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1497751208 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.g
pio_stress_all.1497751208
Directory /workspace/1.gpio_stress_all/latest

Test location /workspace/coverage/default/1.gpio_stress_all_with_rand_reset.435920999
Short name T616
Test name
Test status
Simulation time 289062652794 ps
CPU time 874.29 seconds
Started Dec 20 12:28:33 PM PST 23
Finished Dec 20 12:43:39 PM PST 23
Peak memory 198432 kb
Host smart-d5255c59-eba6-4818-904a-98f86c808d09
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=435920999 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_stress_all_with_rand_reset.435920999
Directory /workspace/1.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/10.gpio_alert_test.1866688165
Short name T780
Test name
Test status
Simulation time 85831198 ps
CPU time 0.59 seconds
Started Dec 20 12:28:51 PM PST 23
Finished Dec 20 12:29:26 PM PST 23
Peak memory 194968 kb
Host smart-c554caf4-dd4e-4913-95be-126c49a45143
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1866688165 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_alert_test.1866688165
Directory /workspace/10.gpio_alert_test/latest

Test location /workspace/coverage/default/10.gpio_dout_din_regs_random_rw.1839056704
Short name T498
Test name
Test status
Simulation time 90417215 ps
CPU time 0.69 seconds
Started Dec 20 12:29:38 PM PST 23
Finished Dec 20 12:29:58 PM PST 23
Peak memory 195056 kb
Host smart-ef4b864f-7a4d-40d7-be5e-f55d5c150ed1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1839056704 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_dout_din_regs_random_rw.1839056704
Directory /workspace/10.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/10.gpio_filter_stress.3289999892
Short name T388
Test name
Test status
Simulation time 1825031727 ps
CPU time 7.33 seconds
Started Dec 20 12:29:17 PM PST 23
Finished Dec 20 12:29:49 PM PST 23
Peak memory 196952 kb
Host smart-23e7b780-ebeb-44b1-818f-06b860bb2585
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3289999892 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_filter_stre
ss.3289999892
Directory /workspace/10.gpio_filter_stress/latest

Test location /workspace/coverage/default/10.gpio_full_random.3798045995
Short name T418
Test name
Test status
Simulation time 474944488 ps
CPU time 0.76 seconds
Started Dec 20 12:28:53 PM PST 23
Finished Dec 20 12:29:28 PM PST 23
Peak memory 195816 kb
Host smart-18efa346-bd1d-478a-92dc-5d64a2ce5b75
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3798045995 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_full_random.3798045995
Directory /workspace/10.gpio_full_random/latest

Test location /workspace/coverage/default/10.gpio_intr_rand_pgm.2531030401
Short name T496
Test name
Test status
Simulation time 31143629 ps
CPU time 0.8 seconds
Started Dec 20 12:28:58 PM PST 23
Finished Dec 20 12:29:32 PM PST 23
Peak memory 196436 kb
Host smart-35c2aec0-4be3-4fd8-a0f8-4eb657f9fba5
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2531030401 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_intr_rand_pgm.2531030401
Directory /workspace/10.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/10.gpio_intr_with_filter_rand_intr_event.1962423538
Short name T349
Test name
Test status
Simulation time 293491695 ps
CPU time 2.74 seconds
Started Dec 20 12:29:21 PM PST 23
Finished Dec 20 12:29:48 PM PST 23
Peak memory 196328 kb
Host smart-8c975ed6-f291-4b18-9f0c-0efefac49338
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1962423538 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 10.gpio_intr_with_filter_rand_intr_event.1962423538
Directory /workspace/10.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/10.gpio_rand_intr_trigger.1786154649
Short name T242
Test name
Test status
Simulation time 40670897 ps
CPU time 1.1 seconds
Started Dec 20 12:29:33 PM PST 23
Finished Dec 20 12:29:55 PM PST 23
Peak memory 196604 kb
Host smart-6f2d120e-35e8-4afb-b597-7541d8b2d4be
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1786154649 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_rand_intr_trigger
.1786154649
Directory /workspace/10.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/10.gpio_random_dout_din.345647678
Short name T437
Test name
Test status
Simulation time 41941579 ps
CPU time 0.7 seconds
Started Dec 20 12:28:49 PM PST 23
Finished Dec 20 12:29:24 PM PST 23
Peak memory 195488 kb
Host smart-504d2b2a-d787-484d-ba86-5458167f2f77
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=345647678 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_random_dout_din.345647678
Directory /workspace/10.gpio_random_dout_din/latest

Test location /workspace/coverage/default/10.gpio_random_dout_din_no_pullup_pulldown.2665234076
Short name T230
Test name
Test status
Simulation time 125189962 ps
CPU time 1.16 seconds
Started Dec 20 12:28:48 PM PST 23
Finished Dec 20 12:29:22 PM PST 23
Peak memory 196032 kb
Host smart-1839ba78-4245-4a6d-bfae-11ccb3cd84da
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2665234076 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_random_dout_din_no_pullu
p_pulldown.2665234076
Directory /workspace/10.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/10.gpio_random_long_reg_writes_reg_reads.1243671897
Short name T96
Test name
Test status
Simulation time 1215935387 ps
CPU time 3.38 seconds
Started Dec 20 12:28:57 PM PST 23
Finished Dec 20 12:29:34 PM PST 23
Peak memory 198112 kb
Host smart-eff4c98d-c0b7-492c-a0d2-d06a669d19ec
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1243671897 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_ra
ndom_long_reg_writes_reg_reads.1243671897
Directory /workspace/10.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/10.gpio_smoke.3665752570
Short name T794
Test name
Test status
Simulation time 363495368 ps
CPU time 0.93 seconds
Started Dec 20 12:28:48 PM PST 23
Finished Dec 20 12:29:23 PM PST 23
Peak memory 195988 kb
Host smart-28579923-8cae-4135-80a3-975dd24ae2af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3665752570 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_smoke.3665752570
Directory /workspace/10.gpio_smoke/latest

Test location /workspace/coverage/default/10.gpio_smoke_no_pullup_pulldown.127990818
Short name T415
Test name
Test status
Simulation time 171618908 ps
CPU time 0.82 seconds
Started Dec 20 12:29:15 PM PST 23
Finished Dec 20 12:29:41 PM PST 23
Peak memory 195448 kb
Host smart-b3c89c24-4360-4a86-aca5-167f6e265674
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=127990818 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_smoke_no_pullup_pulldown.127990818
Directory /workspace/10.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/10.gpio_stress_all.3547066655
Short name T241
Test name
Test status
Simulation time 42708383552 ps
CPU time 102.42 seconds
Started Dec 20 12:29:29 PM PST 23
Finished Dec 20 12:31:34 PM PST 23
Peak memory 198320 kb
Host smart-06b54124-c4dc-41ac-af56-39eeb838da22
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3547066655 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.
gpio_stress_all.3547066655
Directory /workspace/10.gpio_stress_all/latest

Test location /workspace/coverage/default/10.gpio_stress_all_with_rand_reset.1801770021
Short name T819
Test name
Test status
Simulation time 27492081321 ps
CPU time 379.42 seconds
Started Dec 20 12:28:52 PM PST 23
Finished Dec 20 12:35:46 PM PST 23
Peak memory 198380 kb
Host smart-c2a4bdfb-a165-4e7a-9c41-13a26317f56f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=1801770021 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_stress_all_with_rand_reset.1801770021
Directory /workspace/10.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/11.gpio_alert_test.2859299873
Short name T762
Test name
Test status
Simulation time 21405505 ps
CPU time 0.57 seconds
Started Dec 20 12:29:21 PM PST 23
Finished Dec 20 12:29:45 PM PST 23
Peak memory 194116 kb
Host smart-dc5ad158-d325-48c0-bae2-2357c598219e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2859299873 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_alert_test.2859299873
Directory /workspace/11.gpio_alert_test/latest

Test location /workspace/coverage/default/11.gpio_dout_din_regs_random_rw.974118776
Short name T666
Test name
Test status
Simulation time 99198865 ps
CPU time 0.73 seconds
Started Dec 20 12:29:09 PM PST 23
Finished Dec 20 12:29:38 PM PST 23
Peak memory 195100 kb
Host smart-4f3fc265-e8bc-4b8f-8f56-88a655343c62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=974118776 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_dout_din_regs_random_rw.974118776
Directory /workspace/11.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/11.gpio_filter_stress.2137660863
Short name T411
Test name
Test status
Simulation time 539791571 ps
CPU time 7.27 seconds
Started Dec 20 12:29:34 PM PST 23
Finished Dec 20 12:30:02 PM PST 23
Peak memory 197096 kb
Host smart-bf0c405c-0529-4e85-8dd8-8089f761606c
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2137660863 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_filter_stre
ss.2137660863
Directory /workspace/11.gpio_filter_stress/latest

Test location /workspace/coverage/default/11.gpio_full_random.2829252930
Short name T398
Test name
Test status
Simulation time 71031207 ps
CPU time 0.71 seconds
Started Dec 20 12:28:59 PM PST 23
Finished Dec 20 12:29:33 PM PST 23
Peak memory 194824 kb
Host smart-6720631f-ebe0-42c5-948b-3d538ee0fca6
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2829252930 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_full_random.2829252930
Directory /workspace/11.gpio_full_random/latest

Test location /workspace/coverage/default/11.gpio_intr_rand_pgm.371864981
Short name T424
Test name
Test status
Simulation time 16515896 ps
CPU time 0.66 seconds
Started Dec 20 12:28:52 PM PST 23
Finished Dec 20 12:29:27 PM PST 23
Peak memory 195168 kb
Host smart-905c47e8-2658-4e64-80c2-a82c0ba22013
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=371864981 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_intr_rand_pgm.371864981
Directory /workspace/11.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/11.gpio_intr_with_filter_rand_intr_event.2474836410
Short name T300
Test name
Test status
Simulation time 57891270 ps
CPU time 2.12 seconds
Started Dec 20 12:28:53 PM PST 23
Finished Dec 20 12:29:30 PM PST 23
Peak memory 198284 kb
Host smart-a7f43bf7-5ce4-4f4e-a7c6-d8faeecb4798
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2474836410 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 11.gpio_intr_with_filter_rand_intr_event.2474836410
Directory /workspace/11.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/11.gpio_rand_intr_trigger.1046453222
Short name T837
Test name
Test status
Simulation time 157348056 ps
CPU time 3.05 seconds
Started Dec 20 12:28:55 PM PST 23
Finished Dec 20 12:29:32 PM PST 23
Peak memory 197308 kb
Host smart-8b6c89ec-9726-4da5-8be7-515e05e98309
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1046453222 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_rand_intr_trigger
.1046453222
Directory /workspace/11.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/11.gpio_random_dout_din.2254117344
Short name T741
Test name
Test status
Simulation time 72746265 ps
CPU time 1 seconds
Started Dec 20 12:29:02 PM PST 23
Finished Dec 20 12:29:35 PM PST 23
Peak memory 196828 kb
Host smart-62c01a2b-3801-4d61-bbdb-e134323811b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2254117344 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_random_dout_din.2254117344
Directory /workspace/11.gpio_random_dout_din/latest

Test location /workspace/coverage/default/11.gpio_random_dout_din_no_pullup_pulldown.845111493
Short name T632
Test name
Test status
Simulation time 26059135 ps
CPU time 0.7 seconds
Started Dec 20 12:28:50 PM PST 23
Finished Dec 20 12:29:25 PM PST 23
Peak memory 195444 kb
Host smart-d533bc42-b090-4f9f-b64a-314f306ad9a1
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=845111493 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_random_dout_din_no_pullup
_pulldown.845111493
Directory /workspace/11.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/11.gpio_random_long_reg_writes_reg_reads.2468157779
Short name T399
Test name
Test status
Simulation time 309378197 ps
CPU time 3.58 seconds
Started Dec 20 12:28:52 PM PST 23
Finished Dec 20 12:29:30 PM PST 23
Peak memory 198232 kb
Host smart-3123c867-fa67-4a6f-8d77-5804caad96be
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2468157779 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_ra
ndom_long_reg_writes_reg_reads.2468157779
Directory /workspace/11.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/11.gpio_smoke.3120647595
Short name T686
Test name
Test status
Simulation time 50168213 ps
CPU time 0.97 seconds
Started Dec 20 12:28:52 PM PST 23
Finished Dec 20 12:29:27 PM PST 23
Peak memory 196508 kb
Host smart-69afd71e-2a9c-4a64-a0cf-4c2306618558
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3120647595 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_smoke.3120647595
Directory /workspace/11.gpio_smoke/latest

Test location /workspace/coverage/default/11.gpio_smoke_no_pullup_pulldown.3606740661
Short name T777
Test name
Test status
Simulation time 167317549 ps
CPU time 1.06 seconds
Started Dec 20 12:29:13 PM PST 23
Finished Dec 20 12:29:41 PM PST 23
Peak memory 196428 kb
Host smart-f79c6133-2843-4d86-a61f-6f7b119f161e
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3606740661 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_smoke_no_pullup_pulldown.3606740661
Directory /workspace/11.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/11.gpio_stress_all.282786325
Short name T459
Test name
Test status
Simulation time 6451710994 ps
CPU time 167.52 seconds
Started Dec 20 12:29:38 PM PST 23
Finished Dec 20 12:32:45 PM PST 23
Peak memory 198344 kb
Host smart-fbdf1c81-e3bb-493b-9da0-29fc3b8cbc17
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=282786325 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.g
pio_stress_all.282786325
Directory /workspace/11.gpio_stress_all/latest

Test location /workspace/coverage/default/11.gpio_stress_all_with_rand_reset.4288651962
Short name T548
Test name
Test status
Simulation time 23199210199 ps
CPU time 353.34 seconds
Started Dec 20 12:29:12 PM PST 23
Finished Dec 20 12:35:32 PM PST 23
Peak memory 198444 kb
Host smart-d38b5ebd-f969-4f15-a3fd-8d7e57b690a0
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=4288651962 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_stress_all_with_rand_reset.4288651962
Directory /workspace/11.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/12.gpio_alert_test.724362641
Short name T423
Test name
Test status
Simulation time 21317945 ps
CPU time 0.55 seconds
Started Dec 20 12:28:56 PM PST 23
Finished Dec 20 12:29:31 PM PST 23
Peak memory 194160 kb
Host smart-78ec600d-9a6b-4c46-bd3d-4e74dae0f2b1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=724362641 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_alert_test.724362641
Directory /workspace/12.gpio_alert_test/latest

Test location /workspace/coverage/default/12.gpio_dout_din_regs_random_rw.1884169033
Short name T712
Test name
Test status
Simulation time 153834456 ps
CPU time 0.93 seconds
Started Dec 20 12:29:05 PM PST 23
Finished Dec 20 12:29:36 PM PST 23
Peak memory 196208 kb
Host smart-548d8833-8c1f-4b8c-bfe2-10cf2b2d4204
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1884169033 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_dout_din_regs_random_rw.1884169033
Directory /workspace/12.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/12.gpio_filter_stress.2243931085
Short name T726
Test name
Test status
Simulation time 669488585 ps
CPU time 22.8 seconds
Started Dec 20 12:29:07 PM PST 23
Finished Dec 20 12:29:59 PM PST 23
Peak memory 196696 kb
Host smart-3922e46b-e5cd-4278-a4b8-ea939963c8df
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2243931085 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_filter_stre
ss.2243931085
Directory /workspace/12.gpio_filter_stress/latest

Test location /workspace/coverage/default/12.gpio_full_random.1637591073
Short name T700
Test name
Test status
Simulation time 122258191 ps
CPU time 0.71 seconds
Started Dec 20 12:29:17 PM PST 23
Finished Dec 20 12:29:43 PM PST 23
Peak memory 195472 kb
Host smart-e3f8f8c6-652c-4ba3-917b-86baf3d09d3f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1637591073 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_full_random.1637591073
Directory /workspace/12.gpio_full_random/latest

Test location /workspace/coverage/default/12.gpio_intr_rand_pgm.3292683105
Short name T542
Test name
Test status
Simulation time 83114472 ps
CPU time 0.65 seconds
Started Dec 20 12:29:10 PM PST 23
Finished Dec 20 12:29:40 PM PST 23
Peak memory 194536 kb
Host smart-19b7cdc0-75f0-47e6-b945-4da8b3fc67fe
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3292683105 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_intr_rand_pgm.3292683105
Directory /workspace/12.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/12.gpio_intr_with_filter_rand_intr_event.729865326
Short name T360
Test name
Test status
Simulation time 54523808 ps
CPU time 2.07 seconds
Started Dec 20 12:29:01 PM PST 23
Finished Dec 20 12:29:35 PM PST 23
Peak memory 198236 kb
Host smart-11aab99c-3ab2-4455-a766-3da3f821d2e0
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=729865326 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 12.gpio_intr_with_filter_rand_intr_event.729865326
Directory /workspace/12.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/12.gpio_rand_intr_trigger.4236739334
Short name T721
Test name
Test status
Simulation time 104935921 ps
CPU time 2.89 seconds
Started Dec 20 12:29:24 PM PST 23
Finished Dec 20 12:29:50 PM PST 23
Peak memory 197104 kb
Host smart-4db4076a-8c32-447d-9457-4087d95caf74
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4236739334 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_rand_intr_trigger
.4236739334
Directory /workspace/12.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/12.gpio_random_dout_din.2052162804
Short name T664
Test name
Test status
Simulation time 273296054 ps
CPU time 1.17 seconds
Started Dec 20 12:28:51 PM PST 23
Finished Dec 20 12:29:26 PM PST 23
Peak memory 197080 kb
Host smart-34aa24dc-835a-48f9-931f-90427146590f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2052162804 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_random_dout_din.2052162804
Directory /workspace/12.gpio_random_dout_din/latest

Test location /workspace/coverage/default/12.gpio_random_dout_din_no_pullup_pulldown.2904711013
Short name T608
Test name
Test status
Simulation time 271795025 ps
CPU time 1.21 seconds
Started Dec 20 12:28:48 PM PST 23
Finished Dec 20 12:29:23 PM PST 23
Peak memory 196716 kb
Host smart-9f620811-d4f5-48e9-9d66-aa1c914b4ed1
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2904711013 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_random_dout_din_no_pullu
p_pulldown.2904711013
Directory /workspace/12.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/12.gpio_random_long_reg_writes_reg_reads.3720848060
Short name T316
Test name
Test status
Simulation time 418586401 ps
CPU time 2.11 seconds
Started Dec 20 12:29:12 PM PST 23
Finished Dec 20 12:29:41 PM PST 23
Peak memory 198108 kb
Host smart-5885acf0-11dd-4f3d-b829-c7bcf365b3d2
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3720848060 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_ra
ndom_long_reg_writes_reg_reads.3720848060
Directory /workspace/12.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/12.gpio_smoke.2199555152
Short name T787
Test name
Test status
Simulation time 68968048 ps
CPU time 1.2 seconds
Started Dec 20 12:29:25 PM PST 23
Finished Dec 20 12:29:49 PM PST 23
Peak memory 196680 kb
Host smart-5abc250d-a556-474e-a08d-ba80f06c749b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2199555152 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_smoke.2199555152
Directory /workspace/12.gpio_smoke/latest

Test location /workspace/coverage/default/12.gpio_smoke_no_pullup_pulldown.2672969906
Short name T827
Test name
Test status
Simulation time 134181441 ps
CPU time 1.13 seconds
Started Dec 20 12:28:51 PM PST 23
Finished Dec 20 12:29:27 PM PST 23
Peak memory 195980 kb
Host smart-917431f4-72e8-4cdf-9641-88326ef773c6
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2672969906 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_smoke_no_pullup_pulldown.2672969906
Directory /workspace/12.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/12.gpio_stress_all.990100652
Short name T474
Test name
Test status
Simulation time 10795222295 ps
CPU time 146.03 seconds
Started Dec 20 12:29:15 PM PST 23
Finished Dec 20 12:32:06 PM PST 23
Peak memory 198180 kb
Host smart-b64d00e1-5e27-41ba-ad98-863f951bef64
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=990100652 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.g
pio_stress_all.990100652
Directory /workspace/12.gpio_stress_all/latest

Test location /workspace/coverage/default/12.gpio_stress_all_with_rand_reset.1256258758
Short name T386
Test name
Test status
Simulation time 150919565681 ps
CPU time 950.83 seconds
Started Dec 20 12:29:20 PM PST 23
Finished Dec 20 12:45:36 PM PST 23
Peak memory 198508 kb
Host smart-2f43a66a-ed0f-4498-87a9-533c36d3d74e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=1256258758 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_stress_all_with_rand_reset.1256258758
Directory /workspace/12.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/13.gpio_alert_test.3023865705
Short name T531
Test name
Test status
Simulation time 92243897 ps
CPU time 0.56 seconds
Started Dec 20 12:29:08 PM PST 23
Finished Dec 20 12:29:38 PM PST 23
Peak memory 193972 kb
Host smart-6db3b93b-ec42-431f-98ad-f5ff46774320
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3023865705 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_alert_test.3023865705
Directory /workspace/13.gpio_alert_test/latest

Test location /workspace/coverage/default/13.gpio_dout_din_regs_random_rw.598147230
Short name T260
Test name
Test status
Simulation time 83471238 ps
CPU time 0.66 seconds
Started Dec 20 12:29:09 PM PST 23
Finished Dec 20 12:29:39 PM PST 23
Peak memory 194980 kb
Host smart-707f59dc-85e3-4f86-8404-7b5e5956bb2d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=598147230 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_dout_din_regs_random_rw.598147230
Directory /workspace/13.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/13.gpio_filter_stress.1913168631
Short name T416
Test name
Test status
Simulation time 1873040578 ps
CPU time 23.39 seconds
Started Dec 20 12:28:50 PM PST 23
Finished Dec 20 12:29:48 PM PST 23
Peak memory 197112 kb
Host smart-6515163e-5ea0-4c2a-b638-a3665cf109cf
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1913168631 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_filter_stre
ss.1913168631
Directory /workspace/13.gpio_filter_stress/latest

Test location /workspace/coverage/default/13.gpio_full_random.447612404
Short name T353
Test name
Test status
Simulation time 196800567 ps
CPU time 0.78 seconds
Started Dec 20 12:28:52 PM PST 23
Finished Dec 20 12:29:27 PM PST 23
Peak memory 195844 kb
Host smart-b8302132-c01c-40b9-947f-f7b9493cec6b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=447612404 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_full_random.447612404
Directory /workspace/13.gpio_full_random/latest

Test location /workspace/coverage/default/13.gpio_intr_rand_pgm.4041378116
Short name T506
Test name
Test status
Simulation time 56747326 ps
CPU time 0.96 seconds
Started Dec 20 12:29:14 PM PST 23
Finished Dec 20 12:29:45 PM PST 23
Peak memory 195968 kb
Host smart-9f4c18c9-38f4-42a2-9917-f159cc55848f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4041378116 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_intr_rand_pgm.4041378116
Directory /workspace/13.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/13.gpio_intr_with_filter_rand_intr_event.2156523501
Short name T578
Test name
Test status
Simulation time 37898500 ps
CPU time 1.47 seconds
Started Dec 20 12:29:28 PM PST 23
Finished Dec 20 12:29:51 PM PST 23
Peak memory 196664 kb
Host smart-1151f2d8-cd38-4dbc-8a11-3d734340cda0
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2156523501 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 13.gpio_intr_with_filter_rand_intr_event.2156523501
Directory /workspace/13.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/13.gpio_rand_intr_trigger.2774465833
Short name T818
Test name
Test status
Simulation time 166287951 ps
CPU time 1.02 seconds
Started Dec 20 12:29:09 PM PST 23
Finished Dec 20 12:29:39 PM PST 23
Peak memory 195704 kb
Host smart-6d930855-643d-4909-be11-c1f742415439
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2774465833 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_rand_intr_trigger
.2774465833
Directory /workspace/13.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/13.gpio_random_dout_din.1352825511
Short name T428
Test name
Test status
Simulation time 73155631 ps
CPU time 1.22 seconds
Started Dec 20 12:28:53 PM PST 23
Finished Dec 20 12:29:28 PM PST 23
Peak memory 195876 kb
Host smart-4583b9dd-263d-4ab5-9066-977409972586
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1352825511 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_random_dout_din.1352825511
Directory /workspace/13.gpio_random_dout_din/latest

Test location /workspace/coverage/default/13.gpio_random_dout_din_no_pullup_pulldown.2868716616
Short name T813
Test name
Test status
Simulation time 48441228 ps
CPU time 0.95 seconds
Started Dec 20 12:29:01 PM PST 23
Finished Dec 20 12:29:34 PM PST 23
Peak memory 196112 kb
Host smart-055dd75b-a353-42e2-be86-37509b11b86b
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2868716616 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_random_dout_din_no_pullu
p_pulldown.2868716616
Directory /workspace/13.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/13.gpio_random_long_reg_writes_reg_reads.2578991345
Short name T503
Test name
Test status
Simulation time 269315676 ps
CPU time 3.51 seconds
Started Dec 20 12:29:03 PM PST 23
Finished Dec 20 12:29:38 PM PST 23
Peak memory 198064 kb
Host smart-74a8332c-5229-4e2c-8f44-a3414843fc2d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2578991345 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_ra
ndom_long_reg_writes_reg_reads.2578991345
Directory /workspace/13.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/13.gpio_smoke.2919627116
Short name T593
Test name
Test status
Simulation time 40368991 ps
CPU time 0.87 seconds
Started Dec 20 12:29:04 PM PST 23
Finished Dec 20 12:29:36 PM PST 23
Peak memory 197228 kb
Host smart-6d68daa7-1df5-47d9-9ec2-481384a90ad6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2919627116 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_smoke.2919627116
Directory /workspace/13.gpio_smoke/latest

Test location /workspace/coverage/default/13.gpio_smoke_no_pullup_pulldown.781851334
Short name T761
Test name
Test status
Simulation time 52511331 ps
CPU time 1.37 seconds
Started Dec 20 12:29:21 PM PST 23
Finished Dec 20 12:29:47 PM PST 23
Peak memory 197080 kb
Host smart-1a9ad81b-eba6-4397-850d-f71ea57665df
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=781851334 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_smoke_no_pullup_pulldown.781851334
Directory /workspace/13.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/13.gpio_stress_all.1105610482
Short name T714
Test name
Test status
Simulation time 3183083703 ps
CPU time 39.22 seconds
Started Dec 20 12:29:28 PM PST 23
Finished Dec 20 12:30:30 PM PST 23
Peak memory 198248 kb
Host smart-ae0fda2b-9414-4403-922a-b2af7d33777a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1105610482 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.
gpio_stress_all.1105610482
Directory /workspace/13.gpio_stress_all/latest

Test location /workspace/coverage/default/13.gpio_stress_all_with_rand_reset.1314537768
Short name T76
Test name
Test status
Simulation time 20875673193 ps
CPU time 290.34 seconds
Started Dec 20 12:29:17 PM PST 23
Finished Dec 20 12:34:33 PM PST 23
Peak memory 198504 kb
Host smart-75a05539-433c-4b18-ac66-59e7daab3614
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=1314537768 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_stress_all_with_rand_reset.1314537768
Directory /workspace/13.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/14.gpio_alert_test.3804167057
Short name T467
Test name
Test status
Simulation time 45246811 ps
CPU time 0.57 seconds
Started Dec 20 12:28:54 PM PST 23
Finished Dec 20 12:29:32 PM PST 23
Peak memory 194744 kb
Host smart-c4c46e00-f1b4-4ebc-be15-dc641e3149bb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3804167057 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_alert_test.3804167057
Directory /workspace/14.gpio_alert_test/latest

Test location /workspace/coverage/default/14.gpio_dout_din_regs_random_rw.3011811335
Short name T298
Test name
Test status
Simulation time 98261596 ps
CPU time 0.95 seconds
Started Dec 20 12:28:54 PM PST 23
Finished Dec 20 12:29:29 PM PST 23
Peak memory 195640 kb
Host smart-aad37cef-0e67-4d08-9140-ccc1dbc19639
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3011811335 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_dout_din_regs_random_rw.3011811335
Directory /workspace/14.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/14.gpio_filter_stress.3551067083
Short name T339
Test name
Test status
Simulation time 712952177 ps
CPU time 20.96 seconds
Started Dec 20 12:28:56 PM PST 23
Finished Dec 20 12:29:51 PM PST 23
Peak memory 198056 kb
Host smart-8979355f-e345-4a01-85e4-a0d47f4121e4
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3551067083 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_filter_stre
ss.3551067083
Directory /workspace/14.gpio_filter_stress/latest

Test location /workspace/coverage/default/14.gpio_full_random.1988589498
Short name T487
Test name
Test status
Simulation time 129496240 ps
CPU time 0.71 seconds
Started Dec 20 12:29:25 PM PST 23
Finished Dec 20 12:29:48 PM PST 23
Peak memory 195816 kb
Host smart-8a4675a4-720f-4f7f-983c-48201b1db966
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1988589498 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_full_random.1988589498
Directory /workspace/14.gpio_full_random/latest

Test location /workspace/coverage/default/14.gpio_intr_rand_pgm.3915463706
Short name T436
Test name
Test status
Simulation time 90649967 ps
CPU time 1.04 seconds
Started Dec 20 12:29:19 PM PST 23
Finished Dec 20 12:29:44 PM PST 23
Peak memory 196204 kb
Host smart-ad9abca9-e2bd-4094-b5e7-714df40cf186
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3915463706 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_intr_rand_pgm.3915463706
Directory /workspace/14.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/14.gpio_intr_with_filter_rand_intr_event.3187070516
Short name T306
Test name
Test status
Simulation time 313633670 ps
CPU time 3.12 seconds
Started Dec 20 12:29:24 PM PST 23
Finished Dec 20 12:29:50 PM PST 23
Peak memory 198184 kb
Host smart-f52340dd-8a1f-4543-b87b-ba8b2079f665
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3187070516 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 14.gpio_intr_with_filter_rand_intr_event.3187070516
Directory /workspace/14.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/14.gpio_rand_intr_trigger.2070451129
Short name T532
Test name
Test status
Simulation time 91545099 ps
CPU time 0.85 seconds
Started Dec 20 12:29:15 PM PST 23
Finished Dec 20 12:29:42 PM PST 23
Peak memory 196256 kb
Host smart-a46888ad-d6f4-4ad4-9e04-fb605a65024d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2070451129 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_rand_intr_trigger
.2070451129
Directory /workspace/14.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/14.gpio_random_dout_din.3856405355
Short name T540
Test name
Test status
Simulation time 43356429 ps
CPU time 0.84 seconds
Started Dec 20 12:29:37 PM PST 23
Finished Dec 20 12:29:57 PM PST 23
Peak memory 196636 kb
Host smart-80bb79fd-dc0d-4f00-9111-0bdeb3b89003
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3856405355 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_random_dout_din.3856405355
Directory /workspace/14.gpio_random_dout_din/latest

Test location /workspace/coverage/default/14.gpio_random_dout_din_no_pullup_pulldown.2728308836
Short name T644
Test name
Test status
Simulation time 98122032 ps
CPU time 0.74 seconds
Started Dec 20 12:29:35 PM PST 23
Finished Dec 20 12:29:56 PM PST 23
Peak memory 195492 kb
Host smart-1564abd1-dd21-4865-b6f5-e21df62559ad
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2728308836 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_random_dout_din_no_pullu
p_pulldown.2728308836
Directory /workspace/14.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/14.gpio_random_long_reg_writes_reg_reads.3445387924
Short name T639
Test name
Test status
Simulation time 240068804 ps
CPU time 2.6 seconds
Started Dec 20 12:28:54 PM PST 23
Finished Dec 20 12:29:31 PM PST 23
Peak memory 197260 kb
Host smart-be7f5c91-224e-4138-b486-970b3218595f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3445387924 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_ra
ndom_long_reg_writes_reg_reads.3445387924
Directory /workspace/14.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/14.gpio_smoke.1458928682
Short name T284
Test name
Test status
Simulation time 309506140 ps
CPU time 1.3 seconds
Started Dec 20 12:29:24 PM PST 23
Finished Dec 20 12:29:48 PM PST 23
Peak memory 197780 kb
Host smart-4b28aabd-ca29-4c7c-8894-16a2418d1d52
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1458928682 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_smoke.1458928682
Directory /workspace/14.gpio_smoke/latest

Test location /workspace/coverage/default/14.gpio_smoke_no_pullup_pulldown.2524403408
Short name T776
Test name
Test status
Simulation time 222101047 ps
CPU time 1.04 seconds
Started Dec 20 12:29:12 PM PST 23
Finished Dec 20 12:29:40 PM PST 23
Peak memory 196728 kb
Host smart-6156174d-081d-415e-b128-57890e0c2c5d
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2524403408 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_smoke_no_pullup_pulldown.2524403408
Directory /workspace/14.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/14.gpio_stress_all.3444412979
Short name T836
Test name
Test status
Simulation time 5661366036 ps
CPU time 119.89 seconds
Started Dec 20 12:29:07 PM PST 23
Finished Dec 20 12:31:37 PM PST 23
Peak memory 198108 kb
Host smart-a04eaa2d-b25e-4aed-9c25-506b21f6f12a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3444412979 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.
gpio_stress_all.3444412979
Directory /workspace/14.gpio_stress_all/latest

Test location /workspace/coverage/default/14.gpio_stress_all_with_rand_reset.1286437260
Short name T461
Test name
Test status
Simulation time 199644000350 ps
CPU time 568.18 seconds
Started Dec 20 12:29:04 PM PST 23
Finished Dec 20 12:39:03 PM PST 23
Peak memory 206440 kb
Host smart-3f141a5e-9916-4e45-9f1b-e96db68bdb95
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=1286437260 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_stress_all_with_rand_reset.1286437260
Directory /workspace/14.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/15.gpio_alert_test.2836374766
Short name T779
Test name
Test status
Simulation time 13747361 ps
CPU time 0.58 seconds
Started Dec 20 12:28:58 PM PST 23
Finished Dec 20 12:29:32 PM PST 23
Peak memory 194812 kb
Host smart-d50e3310-ad1e-47d2-98f7-c85e243b5584
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2836374766 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_alert_test.2836374766
Directory /workspace/15.gpio_alert_test/latest

Test location /workspace/coverage/default/15.gpio_dout_din_regs_random_rw.3151441661
Short name T568
Test name
Test status
Simulation time 146646010 ps
CPU time 0.76 seconds
Started Dec 20 12:29:14 PM PST 23
Finished Dec 20 12:29:41 PM PST 23
Peak memory 196196 kb
Host smart-4c4e5cdd-34a6-4357-97d9-46a5929da41f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3151441661 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_dout_din_regs_random_rw.3151441661
Directory /workspace/15.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/15.gpio_filter_stress.2399762407
Short name T46
Test name
Test status
Simulation time 1513224995 ps
CPU time 9.1 seconds
Started Dec 20 12:29:00 PM PST 23
Finished Dec 20 12:29:42 PM PST 23
Peak memory 197136 kb
Host smart-8c455fc1-a3fc-47a9-808c-68152f49eb33
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2399762407 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_filter_stre
ss.2399762407
Directory /workspace/15.gpio_filter_stress/latest

Test location /workspace/coverage/default/15.gpio_full_random.4233635553
Short name T812
Test name
Test status
Simulation time 46037598 ps
CPU time 0.84 seconds
Started Dec 20 12:28:59 PM PST 23
Finished Dec 20 12:29:33 PM PST 23
Peak memory 196004 kb
Host smart-00f0b386-996e-486f-988a-b6fee2eda154
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4233635553 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_full_random.4233635553
Directory /workspace/15.gpio_full_random/latest

Test location /workspace/coverage/default/15.gpio_intr_rand_pgm.4230188695
Short name T613
Test name
Test status
Simulation time 36706970 ps
CPU time 1.06 seconds
Started Dec 20 12:29:01 PM PST 23
Finished Dec 20 12:29:34 PM PST 23
Peak memory 196260 kb
Host smart-eea7a9a0-8643-4dc6-b960-9e0e2f21972b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4230188695 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_intr_rand_pgm.4230188695
Directory /workspace/15.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/15.gpio_intr_with_filter_rand_intr_event.1826586565
Short name T389
Test name
Test status
Simulation time 50227976 ps
CPU time 1.97 seconds
Started Dec 20 12:29:19 PM PST 23
Finished Dec 20 12:29:46 PM PST 23
Peak memory 196644 kb
Host smart-1b3dd9f9-a853-4060-a475-41f9da1c1813
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1826586565 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 15.gpio_intr_with_filter_rand_intr_event.1826586565
Directory /workspace/15.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/15.gpio_rand_intr_trigger.4292774531
Short name T225
Test name
Test status
Simulation time 50143098 ps
CPU time 1.56 seconds
Started Dec 20 12:30:27 PM PST 23
Finished Dec 20 12:31:17 PM PST 23
Peak memory 196220 kb
Host smart-aff8f8fa-784b-45e2-aa04-0f64f2eaf328
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4292774531 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_rand_intr_trigger
.4292774531
Directory /workspace/15.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/15.gpio_random_dout_din.345760707
Short name T795
Test name
Test status
Simulation time 244301932 ps
CPU time 0.65 seconds
Started Dec 20 12:28:57 PM PST 23
Finished Dec 20 12:29:32 PM PST 23
Peak memory 194260 kb
Host smart-acf33d24-07b6-4eed-b6a9-1dcd553a355b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=345760707 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_random_dout_din.345760707
Directory /workspace/15.gpio_random_dout_din/latest

Test location /workspace/coverage/default/15.gpio_random_dout_din_no_pullup_pulldown.322604010
Short name T557
Test name
Test status
Simulation time 147335079 ps
CPU time 1.01 seconds
Started Dec 20 12:29:23 PM PST 23
Finished Dec 20 12:29:47 PM PST 23
Peak memory 196052 kb
Host smart-c634d975-b971-498d-9cd3-3a62e628a1bc
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=322604010 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_random_dout_din_no_pullup
_pulldown.322604010
Directory /workspace/15.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/15.gpio_random_long_reg_writes_reg_reads.3253823411
Short name T755
Test name
Test status
Simulation time 1769482477 ps
CPU time 5.21 seconds
Started Dec 20 12:29:02 PM PST 23
Finished Dec 20 12:29:39 PM PST 23
Peak memory 198064 kb
Host smart-e784872d-86f9-4a1a-a66a-71a12e69756f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3253823411 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_ra
ndom_long_reg_writes_reg_reads.3253823411
Directory /workspace/15.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/15.gpio_smoke.3892313942
Short name T340
Test name
Test status
Simulation time 76831458 ps
CPU time 1.31 seconds
Started Dec 20 12:29:47 PM PST 23
Finished Dec 20 12:30:07 PM PST 23
Peak memory 195660 kb
Host smart-993c4e8f-3f68-4b1b-b602-f00335d3c207
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3892313942 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_smoke.3892313942
Directory /workspace/15.gpio_smoke/latest

Test location /workspace/coverage/default/15.gpio_smoke_no_pullup_pulldown.2015425767
Short name T707
Test name
Test status
Simulation time 100603015 ps
CPU time 0.92 seconds
Started Dec 20 12:29:06 PM PST 23
Finished Dec 20 12:29:37 PM PST 23
Peak memory 196412 kb
Host smart-20b16297-de71-40df-b862-2496a0c66ba1
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2015425767 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_smoke_no_pullup_pulldown.2015425767
Directory /workspace/15.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/15.gpio_stress_all.928630490
Short name T620
Test name
Test status
Simulation time 12782183629 ps
CPU time 141.34 seconds
Started Dec 20 12:29:02 PM PST 23
Finished Dec 20 12:31:55 PM PST 23
Peak memory 198308 kb
Host smart-aceb38da-f38d-4182-a9f3-6fbc436130ae
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=928630490 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.g
pio_stress_all.928630490
Directory /workspace/15.gpio_stress_all/latest

Test location /workspace/coverage/default/15.gpio_stress_all_with_rand_reset.3011367931
Short name T381
Test name
Test status
Simulation time 286142465347 ps
CPU time 673.82 seconds
Started Dec 20 12:29:46 PM PST 23
Finished Dec 20 12:41:18 PM PST 23
Peak memory 198448 kb
Host smart-1862e243-c28f-4482-bbd5-a893b54eab22
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=3011367931 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_stress_all_with_rand_reset.3011367931
Directory /workspace/15.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/16.gpio_alert_test.4156458341
Short name T646
Test name
Test status
Simulation time 10477639 ps
CPU time 0.56 seconds
Started Dec 20 12:29:43 PM PST 23
Finished Dec 20 12:30:03 PM PST 23
Peak memory 194060 kb
Host smart-9d37e452-c9e6-47de-8b84-c0bc5cdbf22a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4156458341 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_alert_test.4156458341
Directory /workspace/16.gpio_alert_test/latest

Test location /workspace/coverage/default/16.gpio_dout_din_regs_random_rw.253371757
Short name T692
Test name
Test status
Simulation time 29767701 ps
CPU time 0.89 seconds
Started Dec 20 12:29:01 PM PST 23
Finished Dec 20 12:29:34 PM PST 23
Peak memory 196456 kb
Host smart-de539ea0-34f3-4529-b33b-e93a132adcc3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=253371757 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_dout_din_regs_random_rw.253371757
Directory /workspace/16.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/16.gpio_filter_stress.1934740865
Short name T519
Test name
Test status
Simulation time 106989106 ps
CPU time 3.43 seconds
Started Dec 20 12:29:02 PM PST 23
Finished Dec 20 12:29:38 PM PST 23
Peak memory 195720 kb
Host smart-cc57b616-b8d6-4aac-9c66-039372881101
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1934740865 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_filter_stre
ss.1934740865
Directory /workspace/16.gpio_filter_stress/latest

Test location /workspace/coverage/default/16.gpio_full_random.2968392048
Short name T208
Test name
Test status
Simulation time 160743008 ps
CPU time 0.96 seconds
Started Dec 20 12:29:20 PM PST 23
Finished Dec 20 12:29:46 PM PST 23
Peak memory 196620 kb
Host smart-2fadb683-b462-49df-b7b1-31abeb4fdaca
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2968392048 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_full_random.2968392048
Directory /workspace/16.gpio_full_random/latest

Test location /workspace/coverage/default/16.gpio_intr_rand_pgm.1890298214
Short name T441
Test name
Test status
Simulation time 51435704 ps
CPU time 0.93 seconds
Started Dec 20 12:29:17 PM PST 23
Finished Dec 20 12:29:43 PM PST 23
Peak memory 196296 kb
Host smart-b633e5fb-ce00-411e-bbcf-1c2b0044b248
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1890298214 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_intr_rand_pgm.1890298214
Directory /workspace/16.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/16.gpio_intr_with_filter_rand_intr_event.2361400878
Short name T841
Test name
Test status
Simulation time 85340953 ps
CPU time 3.38 seconds
Started Dec 20 12:29:11 PM PST 23
Finished Dec 20 12:29:42 PM PST 23
Peak memory 198092 kb
Host smart-2bceee48-bcdd-45f8-8069-b54a6b29b645
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2361400878 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 16.gpio_intr_with_filter_rand_intr_event.2361400878
Directory /workspace/16.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/16.gpio_rand_intr_trigger.1382221783
Short name T566
Test name
Test status
Simulation time 289930302 ps
CPU time 3.16 seconds
Started Dec 20 12:29:49 PM PST 23
Finished Dec 20 12:30:12 PM PST 23
Peak memory 196020 kb
Host smart-9cb1941a-d86b-45c3-a6d1-1d9dcbd9cb93
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1382221783 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_rand_intr_trigger
.1382221783
Directory /workspace/16.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/16.gpio_random_dout_din.3640641446
Short name T327
Test name
Test status
Simulation time 118959950 ps
CPU time 1.12 seconds
Started Dec 20 12:29:50 PM PST 23
Finished Dec 20 12:30:10 PM PST 23
Peak memory 198240 kb
Host smart-cab312af-799d-44d3-9171-4ccc398b62be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3640641446 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_random_dout_din.3640641446
Directory /workspace/16.gpio_random_dout_din/latest

Test location /workspace/coverage/default/16.gpio_random_dout_din_no_pullup_pulldown.255835680
Short name T252
Test name
Test status
Simulation time 22146030 ps
CPU time 0.91 seconds
Started Dec 20 12:29:09 PM PST 23
Finished Dec 20 12:29:39 PM PST 23
Peak memory 196160 kb
Host smart-18e6f60a-2ccb-4a40-8b3a-3ac568a07ce7
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=255835680 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_random_dout_din_no_pullup
_pulldown.255835680
Directory /workspace/16.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/16.gpio_random_long_reg_writes_reg_reads.2152898259
Short name T574
Test name
Test status
Simulation time 530386638 ps
CPU time 4.37 seconds
Started Dec 20 12:29:04 PM PST 23
Finished Dec 20 12:29:39 PM PST 23
Peak memory 198156 kb
Host smart-a06f73f0-bd24-4a5b-94a1-25ccf644d2d8
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2152898259 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_ra
ndom_long_reg_writes_reg_reads.2152898259
Directory /workspace/16.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/16.gpio_smoke.4263007496
Short name T702
Test name
Test status
Simulation time 39979080 ps
CPU time 0.83 seconds
Started Dec 20 12:29:38 PM PST 23
Finished Dec 20 12:29:58 PM PST 23
Peak memory 195372 kb
Host smart-a1bc50df-69bf-42d8-a59f-b75669363c1d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4263007496 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_smoke.4263007496
Directory /workspace/16.gpio_smoke/latest

Test location /workspace/coverage/default/16.gpio_smoke_no_pullup_pulldown.1136203175
Short name T718
Test name
Test status
Simulation time 295510304 ps
CPU time 1.2 seconds
Started Dec 20 12:29:24 PM PST 23
Finished Dec 20 12:29:48 PM PST 23
Peak memory 195780 kb
Host smart-a5f7bb2c-1704-4f0f-b6f7-08ce9f7476aa
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1136203175 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_smoke_no_pullup_pulldown.1136203175
Directory /workspace/16.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/16.gpio_stress_all.28799020
Short name T473
Test name
Test status
Simulation time 2364128830 ps
CPU time 64.91 seconds
Started Dec 20 12:29:00 PM PST 23
Finished Dec 20 12:30:37 PM PST 23
Peak memory 198332 kb
Host smart-7b09d28f-0645-4af4-b766-b38c747e576a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28799020 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TE
ST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gp
io_stress_all.28799020
Directory /workspace/16.gpio_stress_all/latest

Test location /workspace/coverage/default/16.gpio_stress_all_with_rand_reset.1698647250
Short name T815
Test name
Test status
Simulation time 15959470467 ps
CPU time 249.35 seconds
Started Dec 20 12:28:58 PM PST 23
Finished Dec 20 12:33:41 PM PST 23
Peak memory 198452 kb
Host smart-1bf49079-0e21-4930-bb10-807860cdf693
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=1698647250 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_stress_all_with_rand_reset.1698647250
Directory /workspace/16.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/17.gpio_alert_test.1450693625
Short name T293
Test name
Test status
Simulation time 16064968 ps
CPU time 0.56 seconds
Started Dec 20 12:29:42 PM PST 23
Finished Dec 20 12:30:01 PM PST 23
Peak memory 194932 kb
Host smart-05c764c6-e30b-4d7d-84a6-ac66bdb75e32
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1450693625 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_alert_test.1450693625
Directory /workspace/17.gpio_alert_test/latest

Test location /workspace/coverage/default/17.gpio_dout_din_regs_random_rw.3023679226
Short name T383
Test name
Test status
Simulation time 38368586 ps
CPU time 0.84 seconds
Started Dec 20 12:29:04 PM PST 23
Finished Dec 20 12:29:36 PM PST 23
Peak memory 195584 kb
Host smart-c3f8181a-c63b-42c4-ae94-d937da686fab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3023679226 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_dout_din_regs_random_rw.3023679226
Directory /workspace/17.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/17.gpio_filter_stress.2674265281
Short name T276
Test name
Test status
Simulation time 573703308 ps
CPU time 7.57 seconds
Started Dec 20 12:29:07 PM PST 23
Finished Dec 20 12:29:44 PM PST 23
Peak memory 195576 kb
Host smart-0ddf6cf4-abe8-4c3e-97d1-469c0ab3c8e0
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2674265281 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_filter_stre
ss.2674265281
Directory /workspace/17.gpio_filter_stress/latest

Test location /workspace/coverage/default/17.gpio_full_random.3043148805
Short name T629
Test name
Test status
Simulation time 315257765 ps
CPU time 0.91 seconds
Started Dec 20 12:29:25 PM PST 23
Finished Dec 20 12:29:49 PM PST 23
Peak memory 197216 kb
Host smart-17ebcf7a-043d-43fc-bc33-607e41b409eb
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3043148805 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_full_random.3043148805
Directory /workspace/17.gpio_full_random/latest

Test location /workspace/coverage/default/17.gpio_intr_rand_pgm.3143944220
Short name T272
Test name
Test status
Simulation time 37219081 ps
CPU time 0.96 seconds
Started Dec 20 12:29:02 PM PST 23
Finished Dec 20 12:29:35 PM PST 23
Peak memory 196284 kb
Host smart-e3aa837b-9de1-40f2-b628-24e1f6af4a01
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3143944220 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_intr_rand_pgm.3143944220
Directory /workspace/17.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/17.gpio_intr_with_filter_rand_intr_event.3060850199
Short name T379
Test name
Test status
Simulation time 37766165 ps
CPU time 1.36 seconds
Started Dec 20 12:29:06 PM PST 23
Finished Dec 20 12:29:37 PM PST 23
Peak memory 196776 kb
Host smart-92e23a71-c94c-4d67-96c3-d28984125eb8
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3060850199 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 17.gpio_intr_with_filter_rand_intr_event.3060850199
Directory /workspace/17.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/17.gpio_rand_intr_trigger.715004055
Short name T421
Test name
Test status
Simulation time 281577608 ps
CPU time 1.78 seconds
Started Dec 20 12:29:39 PM PST 23
Finished Dec 20 12:29:59 PM PST 23
Peak memory 196620 kb
Host smart-2644fbc9-47e6-4866-a972-369bd35a8af5
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=715004055 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_rand_intr_trigger.
715004055
Directory /workspace/17.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/17.gpio_random_dout_din.40298020
Short name T247
Test name
Test status
Simulation time 29251679 ps
CPU time 0.75 seconds
Started Dec 20 12:29:05 PM PST 23
Finished Dec 20 12:29:36 PM PST 23
Peak memory 196252 kb
Host smart-a47fd672-32e5-4276-9280-0a4ef46d89eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=40298020 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_random_dout_din.40298020
Directory /workspace/17.gpio_random_dout_din/latest

Test location /workspace/coverage/default/17.gpio_random_dout_din_no_pullup_pulldown.2491588228
Short name T748
Test name
Test status
Simulation time 34956618 ps
CPU time 0.69 seconds
Started Dec 20 12:29:25 PM PST 23
Finished Dec 20 12:29:49 PM PST 23
Peak memory 195388 kb
Host smart-b4b7167b-0d3b-4ded-9ff8-76a18bb865a1
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2491588228 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_random_dout_din_no_pullu
p_pulldown.2491588228
Directory /workspace/17.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/17.gpio_random_long_reg_writes_reg_reads.2474461605
Short name T526
Test name
Test status
Simulation time 70947943 ps
CPU time 1.31 seconds
Started Dec 20 12:29:45 PM PST 23
Finished Dec 20 12:30:04 PM PST 23
Peak memory 198116 kb
Host smart-2bb3305e-a3ce-422f-8dd5-d4742aac54f3
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2474461605 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_ra
ndom_long_reg_writes_reg_reads.2474461605
Directory /workspace/17.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/17.gpio_smoke.851662797
Short name T677
Test name
Test status
Simulation time 49779298 ps
CPU time 1.02 seconds
Started Dec 20 12:29:04 PM PST 23
Finished Dec 20 12:29:35 PM PST 23
Peak memory 195820 kb
Host smart-1d9b8cde-8ccf-4630-8aef-53cc91f6d410
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=851662797 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_smoke.851662797
Directory /workspace/17.gpio_smoke/latest

Test location /workspace/coverage/default/17.gpio_smoke_no_pullup_pulldown.1615010160
Short name T661
Test name
Test status
Simulation time 69515758 ps
CPU time 1.23 seconds
Started Dec 20 12:29:07 PM PST 23
Finished Dec 20 12:29:37 PM PST 23
Peak memory 196056 kb
Host smart-888eabed-dcfc-409e-a425-21f326d7834f
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1615010160 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_smoke_no_pullup_pulldown.1615010160
Directory /workspace/17.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/17.gpio_stress_all.2667130388
Short name T481
Test name
Test status
Simulation time 18464939443 ps
CPU time 50.07 seconds
Started Dec 20 12:29:04 PM PST 23
Finished Dec 20 12:30:25 PM PST 23
Peak memory 198316 kb
Host smart-b7ec112b-fc60-4170-bfd9-0d93302d11d6
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2667130388 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.
gpio_stress_all.2667130388
Directory /workspace/17.gpio_stress_all/latest

Test location /workspace/coverage/default/17.gpio_stress_all_with_rand_reset.1995945501
Short name T599
Test name
Test status
Simulation time 49568082347 ps
CPU time 1149.5 seconds
Started Dec 20 12:29:35 PM PST 23
Finished Dec 20 12:49:04 PM PST 23
Peak memory 198440 kb
Host smart-2de0685b-e582-446e-acfe-0b9f001c13fb
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=1995945501 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_stress_all_with_rand_reset.1995945501
Directory /workspace/17.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/18.gpio_alert_test.717578961
Short name T486
Test name
Test status
Simulation time 77201034 ps
CPU time 0.58 seconds
Started Dec 20 12:29:38 PM PST 23
Finished Dec 20 12:29:58 PM PST 23
Peak memory 195000 kb
Host smart-ca086d67-c6ae-4207-beee-53a50c725596
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=717578961 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_alert_test.717578961
Directory /workspace/18.gpio_alert_test/latest

Test location /workspace/coverage/default/18.gpio_dout_din_regs_random_rw.2317024785
Short name T358
Test name
Test status
Simulation time 17148482 ps
CPU time 0.63 seconds
Started Dec 20 12:29:33 PM PST 23
Finished Dec 20 12:29:55 PM PST 23
Peak memory 194048 kb
Host smart-69dfdeed-ac2e-44f2-85f4-719adad4a98b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2317024785 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_dout_din_regs_random_rw.2317024785
Directory /workspace/18.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/18.gpio_filter_stress.1772812046
Short name T547
Test name
Test status
Simulation time 1075742869 ps
CPU time 27.06 seconds
Started Dec 20 12:29:09 PM PST 23
Finished Dec 20 12:30:05 PM PST 23
Peak memory 196508 kb
Host smart-2e77c4f5-7f17-4c9e-8c14-fdd632e83a7f
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1772812046 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_filter_stre
ss.1772812046
Directory /workspace/18.gpio_filter_stress/latest

Test location /workspace/coverage/default/18.gpio_full_random.2040770246
Short name T516
Test name
Test status
Simulation time 245077397 ps
CPU time 0.85 seconds
Started Dec 20 12:29:09 PM PST 23
Finished Dec 20 12:29:39 PM PST 23
Peak memory 196092 kb
Host smart-463b2d1a-cd17-4adf-89f4-13f57b850255
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2040770246 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_full_random.2040770246
Directory /workspace/18.gpio_full_random/latest

Test location /workspace/coverage/default/18.gpio_intr_rand_pgm.2840107386
Short name T465
Test name
Test status
Simulation time 75119035 ps
CPU time 1.08 seconds
Started Dec 20 12:29:49 PM PST 23
Finished Dec 20 12:30:09 PM PST 23
Peak memory 195968 kb
Host smart-1f25f859-719f-4ef3-bbb9-36eefa830695
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2840107386 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_intr_rand_pgm.2840107386
Directory /workspace/18.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/18.gpio_intr_with_filter_rand_intr_event.583515202
Short name T104
Test name
Test status
Simulation time 434004935 ps
CPU time 2.34 seconds
Started Dec 20 12:29:42 PM PST 23
Finished Dec 20 12:30:02 PM PST 23
Peak memory 198144 kb
Host smart-a9483630-f3a7-44db-88d6-327a8b4d33c0
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=583515202 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 18.gpio_intr_with_filter_rand_intr_event.583515202
Directory /workspace/18.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/18.gpio_rand_intr_trigger.2467093276
Short name T659
Test name
Test status
Simulation time 150503700 ps
CPU time 1.16 seconds
Started Dec 20 12:29:05 PM PST 23
Finished Dec 20 12:29:36 PM PST 23
Peak memory 195872 kb
Host smart-973d897d-6b02-4bd1-8adc-8350b267ad40
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2467093276 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_rand_intr_trigger
.2467093276
Directory /workspace/18.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/18.gpio_random_dout_din.3047732675
Short name T699
Test name
Test status
Simulation time 41577545 ps
CPU time 0.87 seconds
Started Dec 20 12:29:05 PM PST 23
Finished Dec 20 12:29:36 PM PST 23
Peak memory 196132 kb
Host smart-29bd5585-2f39-40c8-a5a4-754cfb94be5e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3047732675 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_random_dout_din.3047732675
Directory /workspace/18.gpio_random_dout_din/latest

Test location /workspace/coverage/default/18.gpio_random_dout_din_no_pullup_pulldown.3382610357
Short name T359
Test name
Test status
Simulation time 17628836 ps
CPU time 0.69 seconds
Started Dec 20 12:29:05 PM PST 23
Finished Dec 20 12:29:36 PM PST 23
Peak memory 194408 kb
Host smart-ef38cfb2-bdb4-4f19-80b4-570dc8e5380a
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3382610357 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_random_dout_din_no_pullu
p_pulldown.3382610357
Directory /workspace/18.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/18.gpio_random_long_reg_writes_reg_reads.4074410876
Short name T257
Test name
Test status
Simulation time 84931821 ps
CPU time 2.11 seconds
Started Dec 20 12:29:40 PM PST 23
Finished Dec 20 12:30:01 PM PST 23
Peak memory 198172 kb
Host smart-ff2c698c-1b6b-48c6-a920-fc769fb371df
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4074410876 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_ra
ndom_long_reg_writes_reg_reads.4074410876
Directory /workspace/18.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/18.gpio_smoke.4172033217
Short name T463
Test name
Test status
Simulation time 522509546 ps
CPU time 1.08 seconds
Started Dec 20 12:29:04 PM PST 23
Finished Dec 20 12:29:36 PM PST 23
Peak memory 196064 kb
Host smart-0c64ad66-e87e-4fab-b1bc-24817bfe8eb7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4172033217 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_smoke.4172033217
Directory /workspace/18.gpio_smoke/latest

Test location /workspace/coverage/default/18.gpio_smoke_no_pullup_pulldown.2844617505
Short name T838
Test name
Test status
Simulation time 233826393 ps
CPU time 1.16 seconds
Started Dec 20 12:29:08 PM PST 23
Finished Dec 20 12:29:39 PM PST 23
Peak memory 196332 kb
Host smart-48943bda-0c4f-472f-9a9e-eeaabe29b5b0
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2844617505 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_smoke_no_pullup_pulldown.2844617505
Directory /workspace/18.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/18.gpio_stress_all.2327757405
Short name T347
Test name
Test status
Simulation time 20307140111 ps
CPU time 109.87 seconds
Started Dec 20 12:29:04 PM PST 23
Finished Dec 20 12:31:25 PM PST 23
Peak memory 198276 kb
Host smart-c73075ea-766e-4f40-9001-cedc4db7b55e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2327757405 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.
gpio_stress_all.2327757405
Directory /workspace/18.gpio_stress_all/latest

Test location /workspace/coverage/default/18.gpio_stress_all_with_rand_reset.2413965255
Short name T255
Test name
Test status
Simulation time 57951005135 ps
CPU time 814.12 seconds
Started Dec 20 12:29:22 PM PST 23
Finished Dec 20 12:43:20 PM PST 23
Peak memory 198360 kb
Host smart-5822d838-41ac-4853-b37d-345cbaf51f60
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=2413965255 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_stress_all_with_rand_reset.2413965255
Directory /workspace/18.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/19.gpio_alert_test.3684882267
Short name T817
Test name
Test status
Simulation time 13060621 ps
CPU time 0.62 seconds
Started Dec 20 12:29:08 PM PST 23
Finished Dec 20 12:29:37 PM PST 23
Peak memory 194116 kb
Host smart-2f859024-643d-41ef-b24b-9a35cb2a8ade
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3684882267 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_alert_test.3684882267
Directory /workspace/19.gpio_alert_test/latest

Test location /workspace/coverage/default/19.gpio_dout_din_regs_random_rw.3846586967
Short name T821
Test name
Test status
Simulation time 32798535 ps
CPU time 0.64 seconds
Started Dec 20 12:29:33 PM PST 23
Finished Dec 20 12:29:55 PM PST 23
Peak memory 194136 kb
Host smart-8aa82f70-d7ba-4ce7-b586-66f8f30ab892
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3846586967 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_dout_din_regs_random_rw.3846586967
Directory /workspace/19.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/19.gpio_filter_stress.2701224353
Short name T363
Test name
Test status
Simulation time 2234575170 ps
CPU time 21.35 seconds
Started Dec 20 12:30:00 PM PST 23
Finished Dec 20 12:31:09 PM PST 23
Peak memory 197080 kb
Host smart-1067559a-aeba-4ad4-99ac-534ea80c1ccb
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2701224353 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_filter_stre
ss.2701224353
Directory /workspace/19.gpio_filter_stress/latest

Test location /workspace/coverage/default/19.gpio_full_random.3163228382
Short name T665
Test name
Test status
Simulation time 201684130 ps
CPU time 0.7 seconds
Started Dec 20 12:29:21 PM PST 23
Finished Dec 20 12:29:46 PM PST 23
Peak memory 194832 kb
Host smart-48cadc54-19eb-4143-9fd3-9887bf40d7f1
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3163228382 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_full_random.3163228382
Directory /workspace/19.gpio_full_random/latest

Test location /workspace/coverage/default/19.gpio_intr_rand_pgm.1486059685
Short name T622
Test name
Test status
Simulation time 15802989 ps
CPU time 0.64 seconds
Started Dec 20 12:29:52 PM PST 23
Finished Dec 20 12:30:12 PM PST 23
Peak memory 194536 kb
Host smart-3f2972f5-52e5-4564-8d70-d1f7bc3a08c0
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1486059685 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_intr_rand_pgm.1486059685
Directory /workspace/19.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/19.gpio_intr_with_filter_rand_intr_event.2192039010
Short name T105
Test name
Test status
Simulation time 194229141 ps
CPU time 1.88 seconds
Started Dec 20 12:29:19 PM PST 23
Finished Dec 20 12:29:46 PM PST 23
Peak memory 198192 kb
Host smart-efab99a8-5f5f-4027-8938-066ecb312e8a
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2192039010 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 19.gpio_intr_with_filter_rand_intr_event.2192039010
Directory /workspace/19.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/19.gpio_rand_intr_trigger.871076499
Short name T299
Test name
Test status
Simulation time 298910138 ps
CPU time 1.86 seconds
Started Dec 20 12:29:55 PM PST 23
Finished Dec 20 12:30:21 PM PST 23
Peak memory 196160 kb
Host smart-0f98de4a-edf3-429e-ad62-e7dfb2031a10
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=871076499 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_rand_intr_trigger.
871076499
Directory /workspace/19.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/19.gpio_random_dout_din.4138292897
Short name T605
Test name
Test status
Simulation time 37970751 ps
CPU time 0.96 seconds
Started Dec 20 12:29:49 PM PST 23
Finished Dec 20 12:30:09 PM PST 23
Peak memory 196972 kb
Host smart-a05c9b0c-4323-4d92-baf1-e16569f16d9c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4138292897 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_random_dout_din.4138292897
Directory /workspace/19.gpio_random_dout_din/latest

Test location /workspace/coverage/default/19.gpio_random_dout_din_no_pullup_pulldown.988110511
Short name T315
Test name
Test status
Simulation time 261630120 ps
CPU time 0.95 seconds
Started Dec 20 12:29:16 PM PST 23
Finished Dec 20 12:29:42 PM PST 23
Peak memory 196164 kb
Host smart-eda66292-9dbb-4fa7-956b-336fe0def609
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=988110511 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_random_dout_din_no_pullup
_pulldown.988110511
Directory /workspace/19.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/19.gpio_random_long_reg_writes_reg_reads.4133136160
Short name T716
Test name
Test status
Simulation time 582910355 ps
CPU time 5.71 seconds
Started Dec 20 12:30:09 PM PST 23
Finished Dec 20 12:31:09 PM PST 23
Peak memory 198252 kb
Host smart-3b38f0fa-42a4-49fc-bc4d-2998027219eb
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4133136160 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_ra
ndom_long_reg_writes_reg_reads.4133136160
Directory /workspace/19.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/19.gpio_smoke.1686179606
Short name T537
Test name
Test status
Simulation time 45372963 ps
CPU time 1.26 seconds
Started Dec 20 12:29:08 PM PST 23
Finished Dec 20 12:29:38 PM PST 23
Peak memory 197008 kb
Host smart-7299d2a6-ee4a-4755-b366-429ae8afd821
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1686179606 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_smoke.1686179606
Directory /workspace/19.gpio_smoke/latest

Test location /workspace/coverage/default/19.gpio_smoke_no_pullup_pulldown.3328356070
Short name T653
Test name
Test status
Simulation time 152901951 ps
CPU time 1.19 seconds
Started Dec 20 12:29:43 PM PST 23
Finished Dec 20 12:30:03 PM PST 23
Peak memory 197204 kb
Host smart-e7cc9657-a310-4a71-8d01-f73e1779365b
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3328356070 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_smoke_no_pullup_pulldown.3328356070
Directory /workspace/19.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/19.gpio_stress_all.2074015735
Short name T512
Test name
Test status
Simulation time 7635596631 ps
CPU time 184.16 seconds
Started Dec 20 12:29:40 PM PST 23
Finished Dec 20 12:33:03 PM PST 23
Peak memory 198316 kb
Host smart-f4d00d7c-ea1a-408f-aba3-2ad70cb763e9
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2074015735 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.
gpio_stress_all.2074015735
Directory /workspace/19.gpio_stress_all/latest

Test location /workspace/coverage/default/19.gpio_stress_all_with_rand_reset.781514448
Short name T604
Test name
Test status
Simulation time 76122406826 ps
CPU time 1779.79 seconds
Started Dec 20 12:29:59 PM PST 23
Finished Dec 20 01:00:26 PM PST 23
Peak memory 198440 kb
Host smart-07e17dd6-3fe9-4e18-8ec7-7534510a3276
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=781514448 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_stress_all_with_rand_reset.781514448
Directory /workspace/19.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/2.gpio_alert_test.1332127498
Short name T689
Test name
Test status
Simulation time 43597221 ps
CPU time 0.58 seconds
Started Dec 20 12:28:37 PM PST 23
Finished Dec 20 12:29:10 PM PST 23
Peak memory 194116 kb
Host smart-11efb94c-71e8-450e-af12-200392a155ea
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1332127498 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_alert_test.1332127498
Directory /workspace/2.gpio_alert_test/latest

Test location /workspace/coverage/default/2.gpio_dout_din_regs_random_rw.1838004837
Short name T720
Test name
Test status
Simulation time 58996618 ps
CPU time 0.95 seconds
Started Dec 20 12:28:40 PM PST 23
Finished Dec 20 12:29:12 PM PST 23
Peak memory 196872 kb
Host smart-44423220-35ba-44d6-ab20-84953ef4670f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1838004837 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_dout_din_regs_random_rw.1838004837
Directory /workspace/2.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/2.gpio_filter_stress.1207641720
Short name T589
Test name
Test status
Simulation time 2742266658 ps
CPU time 20.95 seconds
Started Dec 20 12:28:43 PM PST 23
Finished Dec 20 12:29:36 PM PST 23
Peak memory 196780 kb
Host smart-e9298a20-f6e0-4787-b38f-57b7121c950b
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1207641720 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_filter_stres
s.1207641720
Directory /workspace/2.gpio_filter_stress/latest

Test location /workspace/coverage/default/2.gpio_full_random.2232787720
Short name T482
Test name
Test status
Simulation time 90327483 ps
CPU time 0.63 seconds
Started Dec 20 12:28:56 PM PST 23
Finished Dec 20 12:29:31 PM PST 23
Peak memory 194568 kb
Host smart-03f8ef3e-144e-4f7f-8342-f4048f9ef059
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2232787720 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_full_random.2232787720
Directory /workspace/2.gpio_full_random/latest

Test location /workspace/coverage/default/2.gpio_intr_rand_pgm.552345249
Short name T674
Test name
Test status
Simulation time 187487213 ps
CPU time 1.27 seconds
Started Dec 20 12:28:43 PM PST 23
Finished Dec 20 12:29:17 PM PST 23
Peak memory 197404 kb
Host smart-09e92635-baa3-462b-bd50-09a05af56609
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=552345249 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_intr_rand_pgm.552345249
Directory /workspace/2.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/2.gpio_intr_with_filter_rand_intr_event.1497246350
Short name T597
Test name
Test status
Simulation time 134950493 ps
CPU time 2.48 seconds
Started Dec 20 12:28:41 PM PST 23
Finished Dec 20 12:29:16 PM PST 23
Peak memory 198264 kb
Host smart-da53c631-a64c-4978-bafd-0c800d0604e2
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1497246350 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 2.gpio_intr_with_filter_rand_intr_event.1497246350
Directory /workspace/2.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/2.gpio_rand_intr_trigger.2626763495
Short name T451
Test name
Test status
Simulation time 288451414 ps
CPU time 2.97 seconds
Started Dec 20 12:28:36 PM PST 23
Finished Dec 20 12:29:10 PM PST 23
Peak memory 198184 kb
Host smart-6a20e527-33b6-4fce-a1d1-14bb8b4db14b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2626763495 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_rand_intr_trigger.
2626763495
Directory /workspace/2.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/2.gpio_random_dout_din.2472267747
Short name T742
Test name
Test status
Simulation time 63411348 ps
CPU time 1.18 seconds
Started Dec 20 12:28:42 PM PST 23
Finished Dec 20 12:29:22 PM PST 23
Peak memory 197184 kb
Host smart-86f5b127-83ba-4114-ba51-c5ce39202e36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2472267747 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_random_dout_din.2472267747
Directory /workspace/2.gpio_random_dout_din/latest

Test location /workspace/coverage/default/2.gpio_random_dout_din_no_pullup_pulldown.3531514800
Short name T595
Test name
Test status
Simulation time 25691742 ps
CPU time 0.91 seconds
Started Dec 20 12:28:41 PM PST 23
Finished Dec 20 12:29:14 PM PST 23
Peak memory 196784 kb
Host smart-ad87b9b3-c560-4cd7-82b1-764afd9e3c43
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3531514800 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_random_dout_din_no_pullup
_pulldown.3531514800
Directory /workspace/2.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/2.gpio_random_long_reg_writes_reg_reads.1436010852
Short name T552
Test name
Test status
Simulation time 229305292 ps
CPU time 1.56 seconds
Started Dec 20 12:28:41 PM PST 23
Finished Dec 20 12:29:15 PM PST 23
Peak memory 198020 kb
Host smart-6077f4e4-8e20-4ad3-a617-ec0d038bd623
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1436010852 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_ran
dom_long_reg_writes_reg_reads.1436010852
Directory /workspace/2.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/2.gpio_smoke.929043532
Short name T64
Test name
Test status
Simulation time 246930694 ps
CPU time 1.16 seconds
Started Dec 20 12:28:36 PM PST 23
Finished Dec 20 12:29:08 PM PST 23
Peak memory 195960 kb
Host smart-a3e568de-5c9f-407f-8e99-5c17959731b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=929043532 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_smoke.929043532
Directory /workspace/2.gpio_smoke/latest

Test location /workspace/coverage/default/2.gpio_smoke_no_pullup_pulldown.341687911
Short name T397
Test name
Test status
Simulation time 151584471 ps
CPU time 0.89 seconds
Started Dec 20 12:28:45 PM PST 23
Finished Dec 20 12:29:18 PM PST 23
Peak memory 196464 kb
Host smart-0eaa378f-9581-4d9f-8c46-9ba5dcef1d83
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=341687911 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_smoke_no_pullup_pulldown.341687911
Directory /workspace/2.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/2.gpio_stress_all.2241131564
Short name T480
Test name
Test status
Simulation time 20183123289 ps
CPU time 138.39 seconds
Started Dec 20 12:28:36 PM PST 23
Finished Dec 20 12:31:26 PM PST 23
Peak memory 198276 kb
Host smart-0d23441e-570a-4703-9773-16d0701fe5ac
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2241131564 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.g
pio_stress_all.2241131564
Directory /workspace/2.gpio_stress_all/latest

Test location /workspace/coverage/default/2.gpio_stress_all_with_rand_reset.3146049486
Short name T492
Test name
Test status
Simulation time 488288285814 ps
CPU time 1079.18 seconds
Started Dec 20 12:28:39 PM PST 23
Finished Dec 20 12:47:10 PM PST 23
Peak memory 198420 kb
Host smart-835fd02f-4f2b-45c1-8a74-c9a5d7506794
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=3146049486 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_stress_all_with_rand_reset.3146049486
Directory /workspace/2.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/20.gpio_alert_test.1556464758
Short name T323
Test name
Test status
Simulation time 13335230 ps
CPU time 0.55 seconds
Started Dec 20 12:29:06 PM PST 23
Finished Dec 20 12:29:36 PM PST 23
Peak memory 194020 kb
Host smart-d6e13d7f-597e-4fb3-aa6c-6f71f9447567
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1556464758 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_alert_test.1556464758
Directory /workspace/20.gpio_alert_test/latest

Test location /workspace/coverage/default/20.gpio_dout_din_regs_random_rw.486752711
Short name T630
Test name
Test status
Simulation time 120885298 ps
CPU time 0.82 seconds
Started Dec 20 12:29:44 PM PST 23
Finished Dec 20 12:30:03 PM PST 23
Peak memory 196492 kb
Host smart-6086853b-4b9e-40c6-8eab-cade0be54aa5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=486752711 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_dout_din_regs_random_rw.486752711
Directory /workspace/20.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/20.gpio_filter_stress.3356675095
Short name T396
Test name
Test status
Simulation time 1373264623 ps
CPU time 11.12 seconds
Started Dec 20 12:29:04 PM PST 23
Finished Dec 20 12:29:46 PM PST 23
Peak memory 197304 kb
Host smart-a3d1ee6c-789d-4a67-91b7-a198bf744006
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3356675095 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_filter_stre
ss.3356675095
Directory /workspace/20.gpio_filter_stress/latest

Test location /workspace/coverage/default/20.gpio_full_random.564460831
Short name T786
Test name
Test status
Simulation time 130824835 ps
CPU time 0.96 seconds
Started Dec 20 12:29:52 PM PST 23
Finished Dec 20 12:30:13 PM PST 23
Peak memory 196600 kb
Host smart-4c29dde1-4949-4943-b6b8-d08f23ebda7f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=564460831 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_full_random.564460831
Directory /workspace/20.gpio_full_random/latest

Test location /workspace/coverage/default/20.gpio_intr_rand_pgm.2956625324
Short name T205
Test name
Test status
Simulation time 146253192 ps
CPU time 0.93 seconds
Started Dec 20 12:29:15 PM PST 23
Finished Dec 20 12:29:41 PM PST 23
Peak memory 197624 kb
Host smart-5247ccab-a301-4c27-ace9-c1de3e6742e9
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2956625324 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_intr_rand_pgm.2956625324
Directory /workspace/20.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/20.gpio_intr_with_filter_rand_intr_event.84353868
Short name T246
Test name
Test status
Simulation time 70695076 ps
CPU time 2.56 seconds
Started Dec 20 12:29:37 PM PST 23
Finished Dec 20 12:30:01 PM PST 23
Peak memory 198284 kb
Host smart-bc104d09-fa7f-45a3-9e52-e564c22fac7e
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=84353868 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_S
EQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 20.gpio_intr_with_filter_rand_intr_event.84353868
Directory /workspace/20.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/20.gpio_rand_intr_trigger.1291995465
Short name T259
Test name
Test status
Simulation time 520332688 ps
CPU time 3.41 seconds
Started Dec 20 12:29:55 PM PST 23
Finished Dec 20 12:30:22 PM PST 23
Peak memory 197064 kb
Host smart-c252c066-0556-4331-b57d-27fae3d12227
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1291995465 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_rand_intr_trigger
.1291995465
Directory /workspace/20.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/20.gpio_random_dout_din.3696871709
Short name T233
Test name
Test status
Simulation time 41899970 ps
CPU time 0.94 seconds
Started Dec 20 12:29:49 PM PST 23
Finished Dec 20 12:30:09 PM PST 23
Peak memory 196936 kb
Host smart-8f3c7bd1-b73d-4341-93ff-be5131d04a1c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3696871709 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_random_dout_din.3696871709
Directory /workspace/20.gpio_random_dout_din/latest

Test location /workspace/coverage/default/20.gpio_random_dout_din_no_pullup_pulldown.405859811
Short name T214
Test name
Test status
Simulation time 39423753 ps
CPU time 0.82 seconds
Started Dec 20 12:29:39 PM PST 23
Finished Dec 20 12:29:58 PM PST 23
Peak memory 196604 kb
Host smart-40bf9b59-f87a-481b-b1b0-76a7067938d9
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=405859811 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_random_dout_din_no_pullup
_pulldown.405859811
Directory /workspace/20.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/20.gpio_random_long_reg_writes_reg_reads.469427082
Short name T559
Test name
Test status
Simulation time 60186207 ps
CPU time 1.66 seconds
Started Dec 20 12:29:20 PM PST 23
Finished Dec 20 12:29:47 PM PST 23
Peak memory 198108 kb
Host smart-4d8bdb44-8e2d-4908-8d87-0cef9091f81b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=469427082 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_ran
dom_long_reg_writes_reg_reads.469427082
Directory /workspace/20.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/20.gpio_smoke.1922358429
Short name T515
Test name
Test status
Simulation time 42853054 ps
CPU time 1.15 seconds
Started Dec 20 12:29:40 PM PST 23
Finished Dec 20 12:30:00 PM PST 23
Peak memory 196780 kb
Host smart-b88226a4-9739-401c-90ab-d9667a975bb8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1922358429 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_smoke.1922358429
Directory /workspace/20.gpio_smoke/latest

Test location /workspace/coverage/default/20.gpio_smoke_no_pullup_pulldown.1573015099
Short name T211
Test name
Test status
Simulation time 83271777 ps
CPU time 1.13 seconds
Started Dec 20 12:29:34 PM PST 23
Finished Dec 20 12:29:55 PM PST 23
Peak memory 195552 kb
Host smart-3fac33f7-5f0d-4e0f-97db-db8e29841f48
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1573015099 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_smoke_no_pullup_pulldown.1573015099
Directory /workspace/20.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/20.gpio_stress_all.1523324887
Short name T206
Test name
Test status
Simulation time 5156195769 ps
CPU time 72.24 seconds
Started Dec 20 12:29:23 PM PST 23
Finished Dec 20 12:30:59 PM PST 23
Peak memory 198332 kb
Host smart-2e05314d-ce45-4b08-9d47-07a92d1b7b3b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1523324887 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.
gpio_stress_all.1523324887
Directory /workspace/20.gpio_stress_all/latest

Test location /workspace/coverage/default/20.gpio_stress_all_with_rand_reset.2605701705
Short name T405
Test name
Test status
Simulation time 136082568088 ps
CPU time 475.45 seconds
Started Dec 20 12:29:07 PM PST 23
Finished Dec 20 12:37:32 PM PST 23
Peak memory 198312 kb
Host smart-73e24543-c581-4a97-b65e-b6c83166ca1d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=2605701705 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_stress_all_with_rand_reset.2605701705
Directory /workspace/20.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/21.gpio_alert_test.643459094
Short name T527
Test name
Test status
Simulation time 15667315 ps
CPU time 0.56 seconds
Started Dec 20 12:29:45 PM PST 23
Finished Dec 20 12:30:04 PM PST 23
Peak memory 194332 kb
Host smart-d6c30115-6b5d-4df0-9363-136361e83974
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=643459094 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_alert_test.643459094
Directory /workspace/21.gpio_alert_test/latest

Test location /workspace/coverage/default/21.gpio_dout_din_regs_random_rw.3842180023
Short name T562
Test name
Test status
Simulation time 105753039 ps
CPU time 0.73 seconds
Started Dec 20 12:29:52 PM PST 23
Finished Dec 20 12:30:12 PM PST 23
Peak memory 195556 kb
Host smart-d294aa88-905f-488a-9a22-28594de18ad3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3842180023 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_dout_din_regs_random_rw.3842180023
Directory /workspace/21.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/21.gpio_filter_stress.752356374
Short name T341
Test name
Test status
Simulation time 1910966863 ps
CPU time 26.51 seconds
Started Dec 20 12:29:56 PM PST 23
Finished Dec 20 12:30:54 PM PST 23
Peak memory 196972 kb
Host smart-ccd25f84-1f0c-4825-8815-d657f96677a9
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=752356374 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_filter_stres
s.752356374
Directory /workspace/21.gpio_filter_stress/latest

Test location /workspace/coverage/default/21.gpio_full_random.1640190703
Short name T573
Test name
Test status
Simulation time 77061090 ps
CPU time 1.06 seconds
Started Dec 20 12:29:31 PM PST 23
Finished Dec 20 12:29:53 PM PST 23
Peak memory 196728 kb
Host smart-ecfaf0ab-8b4c-49de-8bc7-27e807171fcd
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1640190703 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_full_random.1640190703
Directory /workspace/21.gpio_full_random/latest

Test location /workspace/coverage/default/21.gpio_intr_rand_pgm.387058706
Short name T618
Test name
Test status
Simulation time 44337674 ps
CPU time 1.17 seconds
Started Dec 20 12:30:05 PM PST 23
Finished Dec 20 12:30:55 PM PST 23
Peak memory 196276 kb
Host smart-a71df4fa-8f0a-48f7-9864-5d5537211599
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=387058706 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_intr_rand_pgm.387058706
Directory /workspace/21.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/21.gpio_intr_with_filter_rand_intr_event.553476401
Short name T524
Test name
Test status
Simulation time 35087647 ps
CPU time 1.38 seconds
Started Dec 20 12:30:11 PM PST 23
Finished Dec 20 12:31:08 PM PST 23
Peak memory 197916 kb
Host smart-a9bb6c6e-3818-49b5-b942-74da55fb3be0
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=553476401 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 21.gpio_intr_with_filter_rand_intr_event.553476401
Directory /workspace/21.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/21.gpio_rand_intr_trigger.1824719834
Short name T778
Test name
Test status
Simulation time 53180692 ps
CPU time 1.39 seconds
Started Dec 20 12:29:54 PM PST 23
Finished Dec 20 12:30:15 PM PST 23
Peak memory 196116 kb
Host smart-21c2c2b9-50bf-4187-99fb-06b12c3d9b43
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1824719834 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_rand_intr_trigger
.1824719834
Directory /workspace/21.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/21.gpio_random_dout_din.1592324480
Short name T432
Test name
Test status
Simulation time 35616714 ps
CPU time 1.11 seconds
Started Dec 20 12:29:59 PM PST 23
Finished Dec 20 12:30:46 PM PST 23
Peak memory 196180 kb
Host smart-c7ab9481-d751-45bb-891a-1e7b103e14da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1592324480 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_random_dout_din.1592324480
Directory /workspace/21.gpio_random_dout_din/latest

Test location /workspace/coverage/default/21.gpio_random_dout_din_no_pullup_pulldown.1317939567
Short name T704
Test name
Test status
Simulation time 19006518 ps
CPU time 0.7 seconds
Started Dec 20 12:29:55 PM PST 23
Finished Dec 20 12:30:22 PM PST 23
Peak memory 196356 kb
Host smart-35b78df9-3d6d-411b-bb18-2abd97345cc8
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1317939567 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_random_dout_din_no_pullu
p_pulldown.1317939567
Directory /workspace/21.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/21.gpio_random_long_reg_writes_reg_reads.2394343503
Short name T417
Test name
Test status
Simulation time 920937964 ps
CPU time 2.81 seconds
Started Dec 20 12:30:13 PM PST 23
Finished Dec 20 12:31:18 PM PST 23
Peak memory 197952 kb
Host smart-fdae8179-2cd4-4a33-a3b5-f5fc8bc9555c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2394343503 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_ra
ndom_long_reg_writes_reg_reads.2394343503
Directory /workspace/21.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/21.gpio_smoke.1776993974
Short name T667
Test name
Test status
Simulation time 167956650 ps
CPU time 1.36 seconds
Started Dec 20 12:29:52 PM PST 23
Finished Dec 20 12:30:13 PM PST 23
Peak memory 196532 kb
Host smart-4186a5cb-34eb-4b58-8341-ce7fed6c38f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1776993974 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_smoke.1776993974
Directory /workspace/21.gpio_smoke/latest

Test location /workspace/coverage/default/21.gpio_smoke_no_pullup_pulldown.3463883456
Short name T737
Test name
Test status
Simulation time 60763155 ps
CPU time 0.9 seconds
Started Dec 20 12:29:12 PM PST 23
Finished Dec 20 12:29:40 PM PST 23
Peak memory 196484 kb
Host smart-15f22647-dc2d-4398-8ab8-7f95a013ba27
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3463883456 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_smoke_no_pullup_pulldown.3463883456
Directory /workspace/21.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/21.gpio_stress_all.2043325483
Short name T660
Test name
Test status
Simulation time 1841291641 ps
CPU time 22.99 seconds
Started Dec 20 12:29:42 PM PST 23
Finished Dec 20 12:30:24 PM PST 23
Peak memory 198156 kb
Host smart-119a22dc-1081-4403-8c4a-8ae05437e599
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2043325483 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.
gpio_stress_all.2043325483
Directory /workspace/21.gpio_stress_all/latest

Test location /workspace/coverage/default/21.gpio_stress_all_with_rand_reset.3741384338
Short name T499
Test name
Test status
Simulation time 129168133808 ps
CPU time 1748.52 seconds
Started Dec 20 12:30:10 PM PST 23
Finished Dec 20 01:00:14 PM PST 23
Peak memory 198424 kb
Host smart-f40a620e-185d-4a0a-bf5f-4648bc16ff47
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=3741384338 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_stress_all_with_rand_reset.3741384338
Directory /workspace/21.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/22.gpio_alert_test.3641935395
Short name T326
Test name
Test status
Simulation time 13349264 ps
CPU time 0.58 seconds
Started Dec 20 12:29:44 PM PST 23
Finished Dec 20 12:30:03 PM PST 23
Peak memory 194220 kb
Host smart-ff8da6ea-71b6-429e-a4d3-4cda4f8f16d3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3641935395 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_alert_test.3641935395
Directory /workspace/22.gpio_alert_test/latest

Test location /workspace/coverage/default/22.gpio_dout_din_regs_random_rw.2775092696
Short name T832
Test name
Test status
Simulation time 36853978 ps
CPU time 0.68 seconds
Started Dec 20 12:30:22 PM PST 23
Finished Dec 20 12:31:27 PM PST 23
Peak memory 195404 kb
Host smart-92bf4cd0-9e64-4ba6-b334-4f05ec07b5d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2775092696 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_dout_din_regs_random_rw.2775092696
Directory /workspace/22.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/22.gpio_filter_stress.4025182502
Short name T223
Test name
Test status
Simulation time 4454173644 ps
CPU time 17.28 seconds
Started Dec 20 12:29:41 PM PST 23
Finished Dec 20 12:30:17 PM PST 23
Peak memory 198168 kb
Host smart-427d82ad-812f-4919-83e6-fd91101639a5
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4025182502 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_filter_stre
ss.4025182502
Directory /workspace/22.gpio_filter_stress/latest

Test location /workspace/coverage/default/22.gpio_full_random.3104960940
Short name T301
Test name
Test status
Simulation time 64735276 ps
CPU time 0.96 seconds
Started Dec 20 12:29:39 PM PST 23
Finished Dec 20 12:29:59 PM PST 23
Peak memory 197796 kb
Host smart-af4bd1e6-ee5e-4b30-964d-deab0a154905
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3104960940 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_full_random.3104960940
Directory /workspace/22.gpio_full_random/latest

Test location /workspace/coverage/default/22.gpio_rand_intr_trigger.2574386232
Short name T483
Test name
Test status
Simulation time 851098692 ps
CPU time 2.78 seconds
Started Dec 20 12:30:01 PM PST 23
Finished Dec 20 12:30:58 PM PST 23
Peak memory 197068 kb
Host smart-40800ffe-170c-4e74-85e1-eedca8e58ffb
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2574386232 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_rand_intr_trigger
.2574386232
Directory /workspace/22.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/22.gpio_random_dout_din.1535473468
Short name T312
Test name
Test status
Simulation time 106949078 ps
CPU time 1.1 seconds
Started Dec 20 12:29:57 PM PST 23
Finished Dec 20 12:30:34 PM PST 23
Peak memory 196244 kb
Host smart-445c907f-d261-4a7c-a883-58512413a719
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1535473468 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_random_dout_din.1535473468
Directory /workspace/22.gpio_random_dout_din/latest

Test location /workspace/coverage/default/22.gpio_random_dout_din_no_pullup_pulldown.902901840
Short name T394
Test name
Test status
Simulation time 55824938 ps
CPU time 1.01 seconds
Started Dec 20 12:29:57 PM PST 23
Finished Dec 20 12:30:39 PM PST 23
Peak memory 196020 kb
Host smart-035fafb2-e01b-4864-b9ee-6a92ff85d662
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=902901840 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_random_dout_din_no_pullup
_pulldown.902901840
Directory /workspace/22.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/22.gpio_random_long_reg_writes_reg_reads.118473412
Short name T430
Test name
Test status
Simulation time 118955145 ps
CPU time 5.26 seconds
Started Dec 20 12:30:09 PM PST 23
Finished Dec 20 12:31:09 PM PST 23
Peak memory 198264 kb
Host smart-9e615c0e-f8b0-4fde-bd78-5b434e3f9b49
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=118473412 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_ran
dom_long_reg_writes_reg_reads.118473412
Directory /workspace/22.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/22.gpio_smoke.304322123
Short name T645
Test name
Test status
Simulation time 47028888 ps
CPU time 1.21 seconds
Started Dec 20 12:29:48 PM PST 23
Finished Dec 20 12:30:07 PM PST 23
Peak memory 196440 kb
Host smart-19df45cb-068d-4fbf-a532-f1435553985f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=304322123 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_smoke.304322123
Directory /workspace/22.gpio_smoke/latest

Test location /workspace/coverage/default/22.gpio_smoke_no_pullup_pulldown.3326829704
Short name T805
Test name
Test status
Simulation time 52122053 ps
CPU time 1.38 seconds
Started Dec 20 12:30:29 PM PST 23
Finished Dec 20 12:31:17 PM PST 23
Peak memory 198176 kb
Host smart-b5c51bdb-1df9-4fa1-a1c7-4201a004d16f
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3326829704 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_smoke_no_pullup_pulldown.3326829704
Directory /workspace/22.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/22.gpio_stress_all.3381000972
Short name T209
Test name
Test status
Simulation time 19756558907 ps
CPU time 198.28 seconds
Started Dec 20 12:30:13 PM PST 23
Finished Dec 20 12:34:27 PM PST 23
Peak memory 198308 kb
Host smart-fa7ddb54-a0b5-4087-a159-acbf0100ed9b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3381000972 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.
gpio_stress_all.3381000972
Directory /workspace/22.gpio_stress_all/latest

Test location /workspace/coverage/default/22.gpio_stress_all_with_rand_reset.2400050512
Short name T635
Test name
Test status
Simulation time 34159423748 ps
CPU time 270.78 seconds
Started Dec 20 12:29:47 PM PST 23
Finished Dec 20 12:34:36 PM PST 23
Peak memory 198412 kb
Host smart-8facc81e-7749-4286-a0a3-7158e2643a8a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=2400050512 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_stress_all_with_rand_reset.2400050512
Directory /workspace/22.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/23.gpio_alert_test.1937056288
Short name T508
Test name
Test status
Simulation time 21687913 ps
CPU time 0.56 seconds
Started Dec 20 12:29:52 PM PST 23
Finished Dec 20 12:30:12 PM PST 23
Peak memory 194168 kb
Host smart-bbb6dece-b901-4fbd-a2fb-2274fe397f65
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1937056288 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_alert_test.1937056288
Directory /workspace/23.gpio_alert_test/latest

Test location /workspace/coverage/default/23.gpio_dout_din_regs_random_rw.3463729467
Short name T793
Test name
Test status
Simulation time 46568043 ps
CPU time 0.85 seconds
Started Dec 20 12:29:59 PM PST 23
Finished Dec 20 12:30:45 PM PST 23
Peak memory 196416 kb
Host smart-229c451a-da80-47e6-93e4-6e37f0738772
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3463729467 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_dout_din_regs_random_rw.3463729467
Directory /workspace/23.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/23.gpio_filter_stress.3216285593
Short name T662
Test name
Test status
Simulation time 1459316321 ps
CPU time 8.41 seconds
Started Dec 20 12:29:53 PM PST 23
Finished Dec 20 12:30:21 PM PST 23
Peak memory 196984 kb
Host smart-4a9f2e94-b4c4-47c7-a186-ae4a316da013
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3216285593 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_filter_stre
ss.3216285593
Directory /workspace/23.gpio_filter_stress/latest

Test location /workspace/coverage/default/23.gpio_full_random.45509865
Short name T839
Test name
Test status
Simulation time 236751997 ps
CPU time 0.86 seconds
Started Dec 20 12:30:05 PM PST 23
Finished Dec 20 12:30:55 PM PST 23
Peak memory 196164 kb
Host smart-46553f47-5b6f-4afe-9cb7-c93cbb2ac087
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=45509865 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_full_random.45509865
Directory /workspace/23.gpio_full_random/latest

Test location /workspace/coverage/default/23.gpio_intr_rand_pgm.784019193
Short name T238
Test name
Test status
Simulation time 166480255 ps
CPU time 0.97 seconds
Started Dec 20 12:29:29 PM PST 23
Finished Dec 20 12:29:52 PM PST 23
Peak memory 195988 kb
Host smart-92e469df-cc65-4fc4-8bc2-bc1f61e128e1
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=784019193 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_intr_rand_pgm.784019193
Directory /workspace/23.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/23.gpio_intr_with_filter_rand_intr_event.2366342562
Short name T845
Test name
Test status
Simulation time 209989316 ps
CPU time 2.6 seconds
Started Dec 20 12:30:09 PM PST 23
Finished Dec 20 12:31:06 PM PST 23
Peak memory 198316 kb
Host smart-15d8cf38-5748-4495-af2d-18450d72f14c
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2366342562 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 23.gpio_intr_with_filter_rand_intr_event.2366342562
Directory /workspace/23.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/23.gpio_random_dout_din.250052111
Short name T248
Test name
Test status
Simulation time 28392687 ps
CPU time 0.94 seconds
Started Dec 20 12:29:59 PM PST 23
Finished Dec 20 12:30:47 PM PST 23
Peak memory 196220 kb
Host smart-6610c597-62bf-4f34-9bed-46343c16d633
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=250052111 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_random_dout_din.250052111
Directory /workspace/23.gpio_random_dout_din/latest

Test location /workspace/coverage/default/23.gpio_random_dout_din_no_pullup_pulldown.2433132280
Short name T409
Test name
Test status
Simulation time 198872687 ps
CPU time 1.12 seconds
Started Dec 20 12:29:49 PM PST 23
Finished Dec 20 12:30:09 PM PST 23
Peak memory 195948 kb
Host smart-28b85bad-5578-4600-841e-4045307c9923
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2433132280 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_random_dout_din_no_pullu
p_pulldown.2433132280
Directory /workspace/23.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/23.gpio_random_long_reg_writes_reg_reads.2122962197
Short name T642
Test name
Test status
Simulation time 824116943 ps
CPU time 3.56 seconds
Started Dec 20 12:29:51 PM PST 23
Finished Dec 20 12:30:13 PM PST 23
Peak memory 198108 kb
Host smart-f7297698-573e-436e-a7c5-bd17fb51a0b7
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2122962197 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_ra
ndom_long_reg_writes_reg_reads.2122962197
Directory /workspace/23.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/23.gpio_smoke.3616489745
Short name T840
Test name
Test status
Simulation time 41245022 ps
CPU time 0.92 seconds
Started Dec 20 12:29:54 PM PST 23
Finished Dec 20 12:30:17 PM PST 23
Peak memory 195492 kb
Host smart-2b369553-26b6-4335-ac19-00d91be41b79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3616489745 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_smoke.3616489745
Directory /workspace/23.gpio_smoke/latest

Test location /workspace/coverage/default/23.gpio_smoke_no_pullup_pulldown.2131743140
Short name T500
Test name
Test status
Simulation time 260257513 ps
CPU time 1.28 seconds
Started Dec 20 12:29:45 PM PST 23
Finished Dec 20 12:30:05 PM PST 23
Peak memory 196972 kb
Host smart-49d67133-da43-4f38-9ef0-96dd4c35ad9d
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2131743140 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_smoke_no_pullup_pulldown.2131743140
Directory /workspace/23.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/23.gpio_stress_all.2038874944
Short name T528
Test name
Test status
Simulation time 23749590979 ps
CPU time 117.84 seconds
Started Dec 20 12:29:53 PM PST 23
Finished Dec 20 12:32:11 PM PST 23
Peak memory 198228 kb
Host smart-af26797d-4e8c-43fd-98f9-b0c88fc35ab7
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2038874944 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.
gpio_stress_all.2038874944
Directory /workspace/23.gpio_stress_all/latest

Test location /workspace/coverage/default/23.gpio_stress_all_with_rand_reset.2214616114
Short name T603
Test name
Test status
Simulation time 46826131199 ps
CPU time 86.71 seconds
Started Dec 20 12:29:55 PM PST 23
Finished Dec 20 12:31:45 PM PST 23
Peak memory 198424 kb
Host smart-a54138df-81bd-41ec-beb0-e86fe7b71fb8
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=2214616114 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_stress_all_with_rand_reset.2214616114
Directory /workspace/23.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/24.gpio_alert_test.4097710543
Short name T523
Test name
Test status
Simulation time 87181092 ps
CPU time 0.56 seconds
Started Dec 20 12:30:09 PM PST 23
Finished Dec 20 12:31:04 PM PST 23
Peak memory 194216 kb
Host smart-ae0bb31b-a3c2-45cd-92b3-c7126aa1c1d9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4097710543 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_alert_test.4097710543
Directory /workspace/24.gpio_alert_test/latest

Test location /workspace/coverage/default/24.gpio_filter_stress.1633258399
Short name T590
Test name
Test status
Simulation time 369562696 ps
CPU time 19.33 seconds
Started Dec 20 12:29:45 PM PST 23
Finished Dec 20 12:30:23 PM PST 23
Peak memory 198196 kb
Host smart-b2c38928-09d2-4080-b483-9a5fb9622228
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1633258399 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_filter_stre
ss.1633258399
Directory /workspace/24.gpio_filter_stress/latest

Test location /workspace/coverage/default/24.gpio_full_random.3822599915
Short name T277
Test name
Test status
Simulation time 267017277 ps
CPU time 1.01 seconds
Started Dec 20 12:30:06 PM PST 23
Finished Dec 20 12:30:56 PM PST 23
Peak memory 196572 kb
Host smart-c7dc3f65-0317-47bc-8048-b3d83d2c2995
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3822599915 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_full_random.3822599915
Directory /workspace/24.gpio_full_random/latest

Test location /workspace/coverage/default/24.gpio_intr_rand_pgm.593260637
Short name T342
Test name
Test status
Simulation time 77205786 ps
CPU time 0.78 seconds
Started Dec 20 12:30:08 PM PST 23
Finished Dec 20 12:31:06 PM PST 23
Peak memory 195320 kb
Host smart-6fb70bf2-9241-48ff-9f48-99c8d3b1d119
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=593260637 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_intr_rand_pgm.593260637
Directory /workspace/24.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/24.gpio_intr_with_filter_rand_intr_event.2651686419
Short name T229
Test name
Test status
Simulation time 85403595 ps
CPU time 1.1 seconds
Started Dec 20 12:29:40 PM PST 23
Finished Dec 20 12:30:00 PM PST 23
Peak memory 198104 kb
Host smart-9286136a-44ba-4f5f-94a4-06bada696121
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2651686419 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 24.gpio_intr_with_filter_rand_intr_event.2651686419
Directory /workspace/24.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/24.gpio_rand_intr_trigger.3287739670
Short name T752
Test name
Test status
Simulation time 224300349 ps
CPU time 1.27 seconds
Started Dec 20 12:30:05 PM PST 23
Finished Dec 20 12:30:55 PM PST 23
Peak memory 196200 kb
Host smart-d7fc5c73-d182-46f9-aa4d-1cfb2a6ea2f0
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3287739670 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_rand_intr_trigger
.3287739670
Directory /workspace/24.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/24.gpio_random_dout_din.4078172664
Short name T816
Test name
Test status
Simulation time 41737485 ps
CPU time 0.66 seconds
Started Dec 20 12:30:05 PM PST 23
Finished Dec 20 12:30:54 PM PST 23
Peak memory 195100 kb
Host smart-68172a3a-fae7-4fae-b82f-b373a45a8e21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4078172664 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_random_dout_din.4078172664
Directory /workspace/24.gpio_random_dout_din/latest

Test location /workspace/coverage/default/24.gpio_random_dout_din_no_pullup_pulldown.534887556
Short name T494
Test name
Test status
Simulation time 60582250 ps
CPU time 0.62 seconds
Started Dec 20 12:30:11 PM PST 23
Finished Dec 20 12:31:08 PM PST 23
Peak memory 194304 kb
Host smart-74289add-2c90-4274-ba61-007c9e59a2ba
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=534887556 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_random_dout_din_no_pullup
_pulldown.534887556
Directory /workspace/24.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/24.gpio_random_long_reg_writes_reg_reads.1838836403
Short name T602
Test name
Test status
Simulation time 2038555645 ps
CPU time 1.92 seconds
Started Dec 20 12:30:02 PM PST 23
Finished Dec 20 12:30:51 PM PST 23
Peak memory 198088 kb
Host smart-bc68b570-eb84-48a5-bde3-ffdf401a36f8
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1838836403 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_ra
ndom_long_reg_writes_reg_reads.1838836403
Directory /workspace/24.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/24.gpio_smoke.1741115860
Short name T203
Test name
Test status
Simulation time 156443578 ps
CPU time 1.07 seconds
Started Dec 20 12:30:34 PM PST 23
Finished Dec 20 12:31:20 PM PST 23
Peak memory 195980 kb
Host smart-e3a7df83-97a6-447b-bc5c-e199364c23dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1741115860 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_smoke.1741115860
Directory /workspace/24.gpio_smoke/latest

Test location /workspace/coverage/default/24.gpio_smoke_no_pullup_pulldown.769025896
Short name T412
Test name
Test status
Simulation time 98316641 ps
CPU time 1.26 seconds
Started Dec 20 12:30:10 PM PST 23
Finished Dec 20 12:31:06 PM PST 23
Peak memory 195800 kb
Host smart-301db82f-daed-461d-aea6-762ce3b06869
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=769025896 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_smoke_no_pullup_pulldown.769025896
Directory /workspace/24.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/24.gpio_stress_all.3436770509
Short name T580
Test name
Test status
Simulation time 11534924730 ps
CPU time 163.86 seconds
Started Dec 20 12:29:47 PM PST 23
Finished Dec 20 12:32:49 PM PST 23
Peak memory 198324 kb
Host smart-ef9ce0a1-ba21-4de6-828e-ebd8cc5cfb81
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3436770509 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.
gpio_stress_all.3436770509
Directory /workspace/24.gpio_stress_all/latest

Test location /workspace/coverage/default/24.gpio_stress_all_with_rand_reset.2715802897
Short name T75
Test name
Test status
Simulation time 49154698934 ps
CPU time 616.44 seconds
Started Dec 20 12:29:53 PM PST 23
Finished Dec 20 12:40:55 PM PST 23
Peak memory 198296 kb
Host smart-f41b9ce6-3ed4-4f11-b096-6650112f8997
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=2715802897 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_stress_all_with_rand_reset.2715802897
Directory /workspace/24.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/25.gpio_alert_test.2449309454
Short name T446
Test name
Test status
Simulation time 53268666 ps
CPU time 0.61 seconds
Started Dec 20 12:30:07 PM PST 23
Finished Dec 20 12:31:02 PM PST 23
Peak memory 194340 kb
Host smart-62ef02df-ad62-46d4-b0ee-62fc4d3df390
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2449309454 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_alert_test.2449309454
Directory /workspace/25.gpio_alert_test/latest

Test location /workspace/coverage/default/25.gpio_dout_din_regs_random_rw.2069320048
Short name T464
Test name
Test status
Simulation time 38986944 ps
CPU time 0.78 seconds
Started Dec 20 12:30:05 PM PST 23
Finished Dec 20 12:30:54 PM PST 23
Peak memory 196256 kb
Host smart-230535de-8622-477d-9140-af74fbd925a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2069320048 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_dout_din_regs_random_rw.2069320048
Directory /workspace/25.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/25.gpio_filter_stress.430368501
Short name T403
Test name
Test status
Simulation time 105162785 ps
CPU time 5.11 seconds
Started Dec 20 12:29:43 PM PST 23
Finished Dec 20 12:30:07 PM PST 23
Peak memory 196984 kb
Host smart-daa610cb-3552-4ac8-9678-21e8c64362a8
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=430368501 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_filter_stres
s.430368501
Directory /workspace/25.gpio_filter_stress/latest

Test location /workspace/coverage/default/25.gpio_full_random.335318643
Short name T757
Test name
Test status
Simulation time 43735643 ps
CPU time 0.73 seconds
Started Dec 20 12:29:57 PM PST 23
Finished Dec 20 12:30:40 PM PST 23
Peak memory 196668 kb
Host smart-c1b028f6-6388-48bc-99e2-66e3912ef8a7
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=335318643 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_full_random.335318643
Directory /workspace/25.gpio_full_random/latest

Test location /workspace/coverage/default/25.gpio_intr_rand_pgm.3498177141
Short name T579
Test name
Test status
Simulation time 429184392 ps
CPU time 1.45 seconds
Started Dec 20 12:30:15 PM PST 23
Finished Dec 20 12:31:11 PM PST 23
Peak memory 196940 kb
Host smart-b2aa3272-feab-44b0-b07f-6851662d5c96
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3498177141 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_intr_rand_pgm.3498177141
Directory /workspace/25.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/25.gpio_intr_with_filter_rand_intr_event.3929448015
Short name T375
Test name
Test status
Simulation time 66575707 ps
CPU time 1.45 seconds
Started Dec 20 12:29:56 PM PST 23
Finished Dec 20 12:30:32 PM PST 23
Peak memory 197004 kb
Host smart-004fa2d7-a55e-4686-b597-ef07c1905840
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3929448015 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 25.gpio_intr_with_filter_rand_intr_event.3929448015
Directory /workspace/25.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/25.gpio_rand_intr_trigger.2594826106
Short name T804
Test name
Test status
Simulation time 212007833 ps
CPU time 1.81 seconds
Started Dec 20 12:29:53 PM PST 23
Finished Dec 20 12:30:15 PM PST 23
Peak memory 196328 kb
Host smart-9e82d607-b4bd-425a-9eaa-c35eb3d86ba7
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2594826106 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_rand_intr_trigger
.2594826106
Directory /workspace/25.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/25.gpio_random_dout_din.1964686340
Short name T280
Test name
Test status
Simulation time 222882202 ps
CPU time 1.13 seconds
Started Dec 20 12:29:43 PM PST 23
Finished Dec 20 12:30:03 PM PST 23
Peak memory 197284 kb
Host smart-cf06f7f6-0ecb-4c30-9379-7cd740fe74aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1964686340 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_random_dout_din.1964686340
Directory /workspace/25.gpio_random_dout_din/latest

Test location /workspace/coverage/default/25.gpio_random_dout_din_no_pullup_pulldown.1594303300
Short name T647
Test name
Test status
Simulation time 161473954 ps
CPU time 1.3 seconds
Started Dec 20 12:29:52 PM PST 23
Finished Dec 20 12:30:13 PM PST 23
Peak memory 195868 kb
Host smart-374a22de-e41c-4baa-816e-316311bc8e89
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1594303300 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_random_dout_din_no_pullu
p_pulldown.1594303300
Directory /workspace/25.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/25.gpio_random_long_reg_writes_reg_reads.39567252
Short name T768
Test name
Test status
Simulation time 576887673 ps
CPU time 2.38 seconds
Started Dec 20 12:29:54 PM PST 23
Finished Dec 20 12:30:16 PM PST 23
Peak memory 198136 kb
Host smart-023ca2da-6af0-4d8c-a3fc-843549896ee1
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39567252 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_w
rites_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_rand
om_long_reg_writes_reg_reads.39567252
Directory /workspace/25.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/25.gpio_smoke.688963436
Short name T680
Test name
Test status
Simulation time 224171385 ps
CPU time 0.91 seconds
Started Dec 20 12:30:10 PM PST 23
Finished Dec 20 12:31:06 PM PST 23
Peak memory 196028 kb
Host smart-f4bbaa70-b81d-4877-b906-d67e9c35a9ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=688963436 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_smoke.688963436
Directory /workspace/25.gpio_smoke/latest

Test location /workspace/coverage/default/25.gpio_smoke_no_pullup_pulldown.685893314
Short name T361
Test name
Test status
Simulation time 27518450 ps
CPU time 0.71 seconds
Started Dec 20 12:29:44 PM PST 23
Finished Dec 20 12:30:03 PM PST 23
Peak memory 195384 kb
Host smart-05543509-e834-4900-b23c-ed3cfa28d71c
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=685893314 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_smoke_no_pullup_pulldown.685893314
Directory /workspace/25.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/25.gpio_stress_all.1408924856
Short name T775
Test name
Test status
Simulation time 34334493658 ps
CPU time 103.84 seconds
Started Dec 20 12:29:46 PM PST 23
Finished Dec 20 12:31:48 PM PST 23
Peak memory 198288 kb
Host smart-0dbc59f9-50e2-40c5-9c77-4aaf99deb0c5
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1408924856 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.
gpio_stress_all.1408924856
Directory /workspace/25.gpio_stress_all/latest

Test location /workspace/coverage/default/25.gpio_stress_all_with_rand_reset.3005215999
Short name T445
Test name
Test status
Simulation time 36972934050 ps
CPU time 636.23 seconds
Started Dec 20 12:30:08 PM PST 23
Finished Dec 20 12:41:39 PM PST 23
Peak memory 198360 kb
Host smart-ba87e9db-b04d-4f44-b855-aa5e73fff4c8
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=3005215999 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_stress_all_with_rand_reset.3005215999
Directory /workspace/25.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/26.gpio_alert_test.1515685831
Short name T682
Test name
Test status
Simulation time 39153296 ps
CPU time 0.56 seconds
Started Dec 20 12:30:28 PM PST 23
Finished Dec 20 12:31:20 PM PST 23
Peak memory 194820 kb
Host smart-555e01d7-0e8a-45bb-894c-00a1fb533470
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1515685831 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_alert_test.1515685831
Directory /workspace/26.gpio_alert_test/latest

Test location /workspace/coverage/default/26.gpio_dout_din_regs_random_rw.197872538
Short name T583
Test name
Test status
Simulation time 42089692 ps
CPU time 0.89 seconds
Started Dec 20 12:29:55 PM PST 23
Finished Dec 20 12:30:19 PM PST 23
Peak memory 196604 kb
Host smart-76185487-1bc4-41d1-a32c-5262bcf69631
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=197872538 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_dout_din_regs_random_rw.197872538
Directory /workspace/26.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/26.gpio_filter_stress.95590435
Short name T331
Test name
Test status
Simulation time 755211541 ps
CPU time 18.68 seconds
Started Dec 20 12:30:00 PM PST 23
Finished Dec 20 12:31:06 PM PST 23
Peak memory 198284 kb
Host smart-c09cc051-fb3a-4461-905c-b402f6666a2a
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=95590435 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter_
stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_filter_stress
.95590435
Directory /workspace/26.gpio_filter_stress/latest

Test location /workspace/coverage/default/26.gpio_full_random.1379162288
Short name T279
Test name
Test status
Simulation time 82042048 ps
CPU time 0.99 seconds
Started Dec 20 12:29:44 PM PST 23
Finished Dec 20 12:30:04 PM PST 23
Peak memory 196824 kb
Host smart-0264fc4f-abea-47f9-b003-4dd6b1e027fe
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1379162288 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_full_random.1379162288
Directory /workspace/26.gpio_full_random/latest

Test location /workspace/coverage/default/26.gpio_intr_rand_pgm.2758722506
Short name T753
Test name
Test status
Simulation time 85630279 ps
CPU time 1.27 seconds
Started Dec 20 12:30:04 PM PST 23
Finished Dec 20 12:30:53 PM PST 23
Peak memory 196656 kb
Host smart-bbfd53a8-09bc-45b7-9a0d-b1c0b7080c23
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2758722506 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_intr_rand_pgm.2758722506
Directory /workspace/26.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/26.gpio_intr_with_filter_rand_intr_event.458666893
Short name T281
Test name
Test status
Simulation time 168212331 ps
CPU time 3.49 seconds
Started Dec 20 12:29:53 PM PST 23
Finished Dec 20 12:30:16 PM PST 23
Peak memory 196672 kb
Host smart-70adc693-4823-40a4-bc48-e09a95121afa
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=458666893 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 26.gpio_intr_with_filter_rand_intr_event.458666893
Directory /workspace/26.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/26.gpio_rand_intr_trigger.3364363461
Short name T346
Test name
Test status
Simulation time 314860867 ps
CPU time 1.55 seconds
Started Dec 20 12:30:10 PM PST 23
Finished Dec 20 12:31:06 PM PST 23
Peak memory 196928 kb
Host smart-ebede2b2-3e20-4944-a7aa-5d2bfbecea52
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3364363461 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_rand_intr_trigger
.3364363461
Directory /workspace/26.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/26.gpio_random_dout_din.2813612336
Short name T594
Test name
Test status
Simulation time 68864892 ps
CPU time 1.54 seconds
Started Dec 20 12:30:07 PM PST 23
Finished Dec 20 12:31:02 PM PST 23
Peak memory 197152 kb
Host smart-f6299066-043c-455e-9619-42061b81d693
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2813612336 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_random_dout_din.2813612336
Directory /workspace/26.gpio_random_dout_din/latest

Test location /workspace/coverage/default/26.gpio_random_long_reg_writes_reg_reads.2508559159
Short name T797
Test name
Test status
Simulation time 125072491 ps
CPU time 1.32 seconds
Started Dec 20 12:30:10 PM PST 23
Finished Dec 20 12:31:06 PM PST 23
Peak memory 198132 kb
Host smart-58f3bc46-c8e9-44a3-9104-006888ee350d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2508559159 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_ra
ndom_long_reg_writes_reg_reads.2508559159
Directory /workspace/26.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/26.gpio_smoke_no_pullup_pulldown.2755341314
Short name T460
Test name
Test status
Simulation time 229259868 ps
CPU time 0.89 seconds
Started Dec 20 12:30:04 PM PST 23
Finished Dec 20 12:30:52 PM PST 23
Peak memory 196564 kb
Host smart-11b5aff0-38ff-4991-9f48-a723d44520d5
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2755341314 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_smoke_no_pullup_pulldown.2755341314
Directory /workspace/26.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/26.gpio_stress_all.2584242130
Short name T756
Test name
Test status
Simulation time 17385232040 ps
CPU time 183.6 seconds
Started Dec 20 12:30:16 PM PST 23
Finished Dec 20 12:34:14 PM PST 23
Peak memory 198304 kb
Host smart-14a636f1-7fc1-47b1-942c-98a5ca3e7d18
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2584242130 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.
gpio_stress_all.2584242130
Directory /workspace/26.gpio_stress_all/latest

Test location /workspace/coverage/default/26.gpio_stress_all_with_rand_reset.1582364710
Short name T66
Test name
Test status
Simulation time 376942008151 ps
CPU time 816.29 seconds
Started Dec 20 12:30:00 PM PST 23
Finished Dec 20 12:44:21 PM PST 23
Peak memory 198488 kb
Host smart-9d57fd0f-10c9-441d-8592-9cbd12ff7c51
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=1582364710 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_stress_all_with_rand_reset.1582364710
Directory /workspace/26.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/27.gpio_alert_test.691893363
Short name T673
Test name
Test status
Simulation time 11457250 ps
CPU time 0.56 seconds
Started Dec 20 12:29:51 PM PST 23
Finished Dec 20 12:30:11 PM PST 23
Peak memory 194124 kb
Host smart-a89ab7ff-f2ec-4efd-a3e6-63cce8a4bb26
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=691893363 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_alert_test.691893363
Directory /workspace/27.gpio_alert_test/latest

Test location /workspace/coverage/default/27.gpio_dout_din_regs_random_rw.2126077407
Short name T278
Test name
Test status
Simulation time 24098579 ps
CPU time 0.69 seconds
Started Dec 20 12:29:55 PM PST 23
Finished Dec 20 12:30:20 PM PST 23
Peak memory 195064 kb
Host smart-7567b10b-3b36-43db-9b91-1ed6ebbfe1aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2126077407 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_dout_din_regs_random_rw.2126077407
Directory /workspace/27.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/27.gpio_full_random.924353914
Short name T625
Test name
Test status
Simulation time 112714605 ps
CPU time 0.68 seconds
Started Dec 20 12:30:06 PM PST 23
Finished Dec 20 12:30:56 PM PST 23
Peak memory 194888 kb
Host smart-a7bfa756-0987-461d-ab70-2604b99780b4
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=924353914 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_full_random.924353914
Directory /workspace/27.gpio_full_random/latest

Test location /workspace/coverage/default/27.gpio_intr_rand_pgm.1467983546
Short name T719
Test name
Test status
Simulation time 30963142 ps
CPU time 0.68 seconds
Started Dec 20 12:29:46 PM PST 23
Finished Dec 20 12:30:05 PM PST 23
Peak memory 194484 kb
Host smart-de33d634-c448-41b2-9f35-08ca903044e9
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1467983546 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_intr_rand_pgm.1467983546
Directory /workspace/27.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/27.gpio_intr_with_filter_rand_intr_event.927194468
Short name T290
Test name
Test status
Simulation time 339932337 ps
CPU time 2.97 seconds
Started Dec 20 12:29:51 PM PST 23
Finished Dec 20 12:30:13 PM PST 23
Peak memory 196616 kb
Host smart-11f49993-17e8-4926-af93-130ab45632b2
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=927194468 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 27.gpio_intr_with_filter_rand_intr_event.927194468
Directory /workspace/27.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/27.gpio_rand_intr_trigger.2736670516
Short name T62
Test name
Test status
Simulation time 772229853 ps
CPU time 1.73 seconds
Started Dec 20 12:30:09 PM PST 23
Finished Dec 20 12:31:04 PM PST 23
Peak memory 196712 kb
Host smart-2431b658-cd7c-4db8-976b-457e6e04866a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2736670516 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_rand_intr_trigger
.2736670516
Directory /workspace/27.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/27.gpio_random_dout_din.2093801229
Short name T751
Test name
Test status
Simulation time 14939429 ps
CPU time 0.66 seconds
Started Dec 20 12:29:51 PM PST 23
Finished Dec 20 12:30:10 PM PST 23
Peak memory 194412 kb
Host smart-e28059fd-ccf3-44d2-923b-4540841e39e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2093801229 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_random_dout_din.2093801229
Directory /workspace/27.gpio_random_dout_din/latest

Test location /workspace/coverage/default/27.gpio_random_dout_din_no_pullup_pulldown.224454229
Short name T687
Test name
Test status
Simulation time 106216776 ps
CPU time 1.2 seconds
Started Dec 20 12:30:10 PM PST 23
Finished Dec 20 12:31:10 PM PST 23
Peak memory 197232 kb
Host smart-42864501-76a3-442d-a538-0da3307efd7c
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=224454229 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_random_dout_din_no_pullup
_pulldown.224454229
Directory /workspace/27.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/27.gpio_smoke.2464935745
Short name T822
Test name
Test status
Simulation time 203392360 ps
CPU time 1.63 seconds
Started Dec 20 12:29:54 PM PST 23
Finished Dec 20 12:30:15 PM PST 23
Peak memory 196888 kb
Host smart-9c0c0a0a-8d6e-4af6-837c-fc0874dfea9e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2464935745 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_smoke.2464935745
Directory /workspace/27.gpio_smoke/latest

Test location /workspace/coverage/default/27.gpio_smoke_no_pullup_pulldown.3166761989
Short name T670
Test name
Test status
Simulation time 21502811 ps
CPU time 0.78 seconds
Started Dec 20 12:29:54 PM PST 23
Finished Dec 20 12:30:16 PM PST 23
Peak memory 195416 kb
Host smart-227bb54a-b37b-4426-acea-207ff925c1ab
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3166761989 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_smoke_no_pullup_pulldown.3166761989
Directory /workspace/27.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/27.gpio_stress_all.550770418
Short name T513
Test name
Test status
Simulation time 11252090564 ps
CPU time 126.66 seconds
Started Dec 20 12:30:00 PM PST 23
Finished Dec 20 12:32:53 PM PST 23
Peak memory 198388 kb
Host smart-7f48c94e-7fba-49c4-92bd-2137f8bf960b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=550770418 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.g
pio_stress_all.550770418
Directory /workspace/27.gpio_stress_all/latest

Test location /workspace/coverage/default/27.gpio_stress_all_with_rand_reset.2908143516
Short name T286
Test name
Test status
Simulation time 36383980478 ps
CPU time 560.87 seconds
Started Dec 20 12:29:53 PM PST 23
Finished Dec 20 12:39:34 PM PST 23
Peak memory 198428 kb
Host smart-90ec9d6f-ce30-4e1c-9641-6ebce3ad06f2
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=2908143516 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_stress_all_with_rand_reset.2908143516
Directory /workspace/27.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/28.gpio_alert_test.3839621975
Short name T406
Test name
Test status
Simulation time 52393793 ps
CPU time 0.56 seconds
Started Dec 20 12:29:38 PM PST 23
Finished Dec 20 12:29:58 PM PST 23
Peak memory 194328 kb
Host smart-21ffa246-4ff4-4f4a-9efd-b11b12279819
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3839621975 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_alert_test.3839621975
Directory /workspace/28.gpio_alert_test/latest

Test location /workspace/coverage/default/28.gpio_dout_din_regs_random_rw.3238215534
Short name T303
Test name
Test status
Simulation time 34018194 ps
CPU time 0.61 seconds
Started Dec 20 12:29:59 PM PST 23
Finished Dec 20 12:30:45 PM PST 23
Peak memory 194068 kb
Host smart-e0312a1f-112c-40a4-a903-388f77d99ab9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3238215534 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_dout_din_regs_random_rw.3238215534
Directory /workspace/28.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/28.gpio_full_random.1141723231
Short name T395
Test name
Test status
Simulation time 88133196 ps
CPU time 0.84 seconds
Started Dec 20 12:30:14 PM PST 23
Finished Dec 20 12:31:21 PM PST 23
Peak memory 196036 kb
Host smart-f025fd45-bc53-409f-869a-e0b4bb552aec
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1141723231 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_full_random.1141723231
Directory /workspace/28.gpio_full_random/latest

Test location /workspace/coverage/default/28.gpio_intr_rand_pgm.2743385079
Short name T294
Test name
Test status
Simulation time 32468939 ps
CPU time 0.81 seconds
Started Dec 20 12:30:07 PM PST 23
Finished Dec 20 12:31:04 PM PST 23
Peak memory 195476 kb
Host smart-db1a9b46-c1db-41c9-b477-3dda06b14e97
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2743385079 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_intr_rand_pgm.2743385079
Directory /workspace/28.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/28.gpio_intr_with_filter_rand_intr_event.2208991206
Short name T657
Test name
Test status
Simulation time 235234074 ps
CPU time 2.28 seconds
Started Dec 20 12:29:54 PM PST 23
Finished Dec 20 12:30:16 PM PST 23
Peak memory 196580 kb
Host smart-c8e49f6f-9cff-4463-8131-f688812a0edc
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2208991206 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 28.gpio_intr_with_filter_rand_intr_event.2208991206
Directory /workspace/28.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/28.gpio_rand_intr_trigger.2838220550
Short name T345
Test name
Test status
Simulation time 175133346 ps
CPU time 2.88 seconds
Started Dec 20 12:29:48 PM PST 23
Finished Dec 20 12:30:09 PM PST 23
Peak memory 196948 kb
Host smart-6f3a5ddc-a10e-46b6-95f3-a094b140a8c2
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2838220550 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_rand_intr_trigger
.2838220550
Directory /workspace/28.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/28.gpio_random_dout_din.2755619784
Short name T725
Test name
Test status
Simulation time 1117564188 ps
CPU time 1.2 seconds
Started Dec 20 12:30:05 PM PST 23
Finished Dec 20 12:30:55 PM PST 23
Peak memory 196036 kb
Host smart-1d7ebf3a-926c-4c1d-bc10-ce847fafdd52
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2755619784 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_random_dout_din.2755619784
Directory /workspace/28.gpio_random_dout_din/latest

Test location /workspace/coverage/default/28.gpio_random_long_reg_writes_reg_reads.3146462462
Short name T212
Test name
Test status
Simulation time 127366040 ps
CPU time 2.83 seconds
Started Dec 20 12:29:52 PM PST 23
Finished Dec 20 12:30:14 PM PST 23
Peak memory 198032 kb
Host smart-b73dca43-21fe-4a42-94ea-0203618420a8
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3146462462 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_ra
ndom_long_reg_writes_reg_reads.3146462462
Directory /workspace/28.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/28.gpio_smoke.1252604677
Short name T237
Test name
Test status
Simulation time 315383027 ps
CPU time 1.04 seconds
Started Dec 20 12:30:00 PM PST 23
Finished Dec 20 12:30:48 PM PST 23
Peak memory 195904 kb
Host smart-f062b5d5-44fe-48f5-b684-d548a33a2f90
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1252604677 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_smoke.1252604677
Directory /workspace/28.gpio_smoke/latest

Test location /workspace/coverage/default/28.gpio_stress_all.1406608513
Short name T356
Test name
Test status
Simulation time 6607756985 ps
CPU time 90.36 seconds
Started Dec 20 12:29:35 PM PST 23
Finished Dec 20 12:31:26 PM PST 23
Peak memory 198124 kb
Host smart-0eda7943-9961-4edb-9249-a3b81b15b30e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1406608513 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.
gpio_stress_all.1406608513
Directory /workspace/28.gpio_stress_all/latest

Test location /workspace/coverage/default/28.gpio_stress_all_with_rand_reset.738470372
Short name T219
Test name
Test status
Simulation time 195015358911 ps
CPU time 1186.84 seconds
Started Dec 20 12:30:11 PM PST 23
Finished Dec 20 12:50:54 PM PST 23
Peak memory 198352 kb
Host smart-6ce70054-c4d3-437c-887a-17de4bb655d4
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=738470372 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_stress_all_with_rand_reset.738470372
Directory /workspace/28.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/29.gpio_alert_test.950103618
Short name T283
Test name
Test status
Simulation time 48736357 ps
CPU time 0.55 seconds
Started Dec 20 12:29:58 PM PST 23
Finished Dec 20 12:30:43 PM PST 23
Peak memory 194288 kb
Host smart-9d1c3b60-fcf9-419c-91c7-a97793c0be02
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=950103618 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_alert_test.950103618
Directory /workspace/29.gpio_alert_test/latest

Test location /workspace/coverage/default/29.gpio_dout_din_regs_random_rw.2086879982
Short name T505
Test name
Test status
Simulation time 18710774 ps
CPU time 0.67 seconds
Started Dec 20 12:30:03 PM PST 23
Finished Dec 20 12:30:53 PM PST 23
Peak memory 194896 kb
Host smart-426b0daa-adeb-41dc-8fc1-60357839f743
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2086879982 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_dout_din_regs_random_rw.2086879982
Directory /workspace/29.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/29.gpio_filter_stress.4133570936
Short name T588
Test name
Test status
Simulation time 1523461921 ps
CPU time 12.03 seconds
Started Dec 20 12:29:57 PM PST 23
Finished Dec 20 12:31:10 PM PST 23
Peak memory 198184 kb
Host smart-8acaed3c-5665-4536-9c48-012fa34d096e
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4133570936 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_filter_stre
ss.4133570936
Directory /workspace/29.gpio_filter_stress/latest

Test location /workspace/coverage/default/29.gpio_full_random.2645053916
Short name T427
Test name
Test status
Simulation time 259751376 ps
CPU time 0.93 seconds
Started Dec 20 12:30:14 PM PST 23
Finished Dec 20 12:31:21 PM PST 23
Peak memory 197092 kb
Host smart-00a5f6b3-a52a-4acb-b4a3-6e128905bec6
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2645053916 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_full_random.2645053916
Directory /workspace/29.gpio_full_random/latest

Test location /workspace/coverage/default/29.gpio_intr_rand_pgm.1836239996
Short name T652
Test name
Test status
Simulation time 219084036 ps
CPU time 0.92 seconds
Started Dec 20 12:30:00 PM PST 23
Finished Dec 20 12:30:48 PM PST 23
Peak memory 196600 kb
Host smart-44cc3806-a391-4ba2-9d38-a0d520dc361f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1836239996 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_intr_rand_pgm.1836239996
Directory /workspace/29.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/29.gpio_intr_with_filter_rand_intr_event.2030822047
Short name T501
Test name
Test status
Simulation time 187944794 ps
CPU time 2.55 seconds
Started Dec 20 12:30:00 PM PST 23
Finished Dec 20 12:30:50 PM PST 23
Peak memory 198192 kb
Host smart-9a0ed08f-d0cf-458b-8257-71f0cd4a407b
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2030822047 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 29.gpio_intr_with_filter_rand_intr_event.2030822047
Directory /workspace/29.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/29.gpio_rand_intr_trigger.1008472895
Short name T210
Test name
Test status
Simulation time 476805505 ps
CPU time 2.67 seconds
Started Dec 20 12:29:37 PM PST 23
Finished Dec 20 12:30:00 PM PST 23
Peak memory 197292 kb
Host smart-68107e29-67ab-4eb9-9002-ae2c65fe6374
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1008472895 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_rand_intr_trigger
.1008472895
Directory /workspace/29.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/29.gpio_random_dout_din.3357455929
Short name T484
Test name
Test status
Simulation time 191461984 ps
CPU time 0.91 seconds
Started Dec 20 12:30:02 PM PST 23
Finished Dec 20 12:30:50 PM PST 23
Peak memory 196056 kb
Host smart-4660cbdf-0a6d-4b0a-9857-e15303788faf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3357455929 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_random_dout_din.3357455929
Directory /workspace/29.gpio_random_dout_din/latest

Test location /workspace/coverage/default/29.gpio_random_dout_din_no_pullup_pulldown.2038147745
Short name T370
Test name
Test status
Simulation time 33174779 ps
CPU time 0.75 seconds
Started Dec 20 12:29:59 PM PST 23
Finished Dec 20 12:30:47 PM PST 23
Peak memory 195436 kb
Host smart-1648dbd0-ad39-40fe-a3fc-b06915ee3557
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2038147745 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_random_dout_din_no_pullu
p_pulldown.2038147745
Directory /workspace/29.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/29.gpio_random_long_reg_writes_reg_reads.1746779613
Short name T530
Test name
Test status
Simulation time 28680867 ps
CPU time 1.32 seconds
Started Dec 20 12:30:10 PM PST 23
Finished Dec 20 12:31:06 PM PST 23
Peak memory 198072 kb
Host smart-c0c3441e-104c-4f36-ac80-82f3d2df663c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1746779613 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_ra
ndom_long_reg_writes_reg_reads.1746779613
Directory /workspace/29.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/29.gpio_smoke.2749226532
Short name T740
Test name
Test status
Simulation time 66945715 ps
CPU time 1.18 seconds
Started Dec 20 12:29:41 PM PST 23
Finished Dec 20 12:30:01 PM PST 23
Peak memory 195836 kb
Host smart-ac3f6f2a-3cf5-4be1-b7c7-8a0977a5ec36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2749226532 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_smoke.2749226532
Directory /workspace/29.gpio_smoke/latest

Test location /workspace/coverage/default/29.gpio_smoke_no_pullup_pulldown.1721244661
Short name T202
Test name
Test status
Simulation time 241117388 ps
CPU time 1.2 seconds
Started Dec 20 12:29:43 PM PST 23
Finished Dec 20 12:30:02 PM PST 23
Peak memory 196940 kb
Host smart-98fd77bf-a23a-45dd-816f-0aa70f10dbae
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1721244661 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_smoke_no_pullup_pulldown.1721244661
Directory /workspace/29.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/29.gpio_stress_all.4030646045
Short name T640
Test name
Test status
Simulation time 24684502043 ps
CPU time 231.52 seconds
Started Dec 20 12:29:57 PM PST 23
Finished Dec 20 12:34:30 PM PST 23
Peak memory 198256 kb
Host smart-571b515b-74bf-4e6e-b1dd-cf9a814a1832
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4030646045 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.
gpio_stress_all.4030646045
Directory /workspace/29.gpio_stress_all/latest

Test location /workspace/coverage/default/29.gpio_stress_all_with_rand_reset.2212183015
Short name T261
Test name
Test status
Simulation time 55933668193 ps
CPU time 412.25 seconds
Started Dec 20 12:30:04 PM PST 23
Finished Dec 20 12:37:44 PM PST 23
Peak memory 198376 kb
Host smart-dd107033-ba0d-4b16-9e57-48afe783274d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=2212183015 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_stress_all_with_rand_reset.2212183015
Directory /workspace/29.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/3.gpio_alert_test.4034551521
Short name T521
Test name
Test status
Simulation time 14804092 ps
CPU time 0.62 seconds
Started Dec 20 12:30:11 PM PST 23
Finished Dec 20 12:31:07 PM PST 23
Peak memory 194312 kb
Host smart-85cbb90c-e0c9-4fe3-a1bd-e37d2362ddce
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4034551521 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_alert_test.4034551521
Directory /workspace/3.gpio_alert_test/latest

Test location /workspace/coverage/default/3.gpio_dout_din_regs_random_rw.1154374005
Short name T324
Test name
Test status
Simulation time 82641214 ps
CPU time 0.93 seconds
Started Dec 20 12:28:43 PM PST 23
Finished Dec 20 12:29:16 PM PST 23
Peak memory 196720 kb
Host smart-700462cd-2c6c-4d19-99fe-3fceff713424
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1154374005 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_dout_din_regs_random_rw.1154374005
Directory /workspace/3.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/3.gpio_filter_stress.4083403621
Short name T470
Test name
Test status
Simulation time 1804375878 ps
CPU time 11.81 seconds
Started Dec 20 12:28:49 PM PST 23
Finished Dec 20 12:29:35 PM PST 23
Peak memory 198040 kb
Host smart-cc3f0aeb-d72d-4749-a98a-1c2320f38265
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4083403621 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_filter_stres
s.4083403621
Directory /workspace/3.gpio_filter_stress/latest

Test location /workspace/coverage/default/3.gpio_full_random.3214267257
Short name T450
Test name
Test status
Simulation time 295805028 ps
CPU time 0.83 seconds
Started Dec 20 12:28:39 PM PST 23
Finished Dec 20 12:29:11 PM PST 23
Peak memory 196216 kb
Host smart-fe5fcf26-b591-47f8-b657-abc9aca8b39f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3214267257 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_full_random.3214267257
Directory /workspace/3.gpio_full_random/latest

Test location /workspace/coverage/default/3.gpio_intr_rand_pgm.3393058712
Short name T297
Test name
Test status
Simulation time 72539807 ps
CPU time 1.04 seconds
Started Dec 20 12:28:40 PM PST 23
Finished Dec 20 12:29:13 PM PST 23
Peak memory 196692 kb
Host smart-1d3fbb23-84c6-45d5-be8e-11eedad71f52
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3393058712 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_intr_rand_pgm.3393058712
Directory /workspace/3.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/3.gpio_intr_with_filter_rand_intr_event.1107586784
Short name T319
Test name
Test status
Simulation time 58359418 ps
CPU time 2.29 seconds
Started Dec 20 12:28:37 PM PST 23
Finished Dec 20 12:29:11 PM PST 23
Peak memory 198356 kb
Host smart-179cc812-183c-4b82-91a7-cadb47656932
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1107586784 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 3.gpio_intr_with_filter_rand_intr_event.1107586784
Directory /workspace/3.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/3.gpio_rand_intr_trigger.2351193514
Short name T391
Test name
Test status
Simulation time 551305000 ps
CPU time 2.57 seconds
Started Dec 20 12:28:39 PM PST 23
Finished Dec 20 12:29:13 PM PST 23
Peak memory 197280 kb
Host smart-5f44b0a9-ebd8-4b57-84bb-daa8099c7326
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2351193514 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_rand_intr_trigger.
2351193514
Directory /workspace/3.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/3.gpio_random_dout_din.3041708515
Short name T539
Test name
Test status
Simulation time 102180406 ps
CPU time 1.03 seconds
Started Dec 20 12:28:45 PM PST 23
Finished Dec 20 12:29:18 PM PST 23
Peak memory 196256 kb
Host smart-324312a2-1b64-44e0-8251-8abfd5abe1e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3041708515 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_random_dout_din.3041708515
Directory /workspace/3.gpio_random_dout_din/latest

Test location /workspace/coverage/default/3.gpio_random_dout_din_no_pullup_pulldown.186430584
Short name T235
Test name
Test status
Simulation time 38441037 ps
CPU time 0.64 seconds
Started Dec 20 12:28:46 PM PST 23
Finished Dec 20 12:29:19 PM PST 23
Peak memory 194436 kb
Host smart-07d683b2-617a-4965-9bc9-2e6ef715fdb5
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=186430584 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_random_dout_din_no_pullup_
pulldown.186430584
Directory /workspace/3.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/3.gpio_random_long_reg_writes_reg_reads.3880298011
Short name T517
Test name
Test status
Simulation time 1153430966 ps
CPU time 3.52 seconds
Started Dec 20 12:28:39 PM PST 23
Finished Dec 20 12:29:14 PM PST 23
Peak memory 198176 kb
Host smart-c8c9647f-784d-4667-aeb4-ae14f2ec858c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3880298011 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_ran
dom_long_reg_writes_reg_reads.3880298011
Directory /workspace/3.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/3.gpio_sec_cm.2409060067
Short name T29
Test name
Test status
Simulation time 130624856 ps
CPU time 0.74 seconds
Started Dec 20 12:28:44 PM PST 23
Finished Dec 20 12:29:17 PM PST 23
Peak memory 213480 kb
Host smart-46f55de4-1e02-454c-9b00-67ef921dc0bb
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2409060067 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_sec_cm.2409060067
Directory /workspace/3.gpio_sec_cm/latest

Test location /workspace/coverage/default/3.gpio_smoke.2390342374
Short name T535
Test name
Test status
Simulation time 146259580 ps
CPU time 1.24 seconds
Started Dec 20 12:28:45 PM PST 23
Finished Dec 20 12:29:19 PM PST 23
Peak memory 196048 kb
Host smart-e9d333ea-2aa8-4d22-9320-8e348e2c510d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2390342374 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_smoke.2390342374
Directory /workspace/3.gpio_smoke/latest

Test location /workspace/coverage/default/3.gpio_smoke_no_pullup_pulldown.1177673771
Short name T268
Test name
Test status
Simulation time 148301210 ps
CPU time 0.86 seconds
Started Dec 20 12:28:48 PM PST 23
Finished Dec 20 12:29:23 PM PST 23
Peak memory 196644 kb
Host smart-4cf65a9b-4c4b-4d85-9a6b-f44efcd9db0f
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1177673771 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_smoke_no_pullup_pulldown.1177673771
Directory /workspace/3.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/3.gpio_stress_all.3320339667
Short name T638
Test name
Test status
Simulation time 24793837140 ps
CPU time 155.33 seconds
Started Dec 20 12:28:50 PM PST 23
Finished Dec 20 12:31:59 PM PST 23
Peak memory 198252 kb
Host smart-3faaecf8-7ab4-4c42-be29-cecf7f3d8363
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3320339667 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.g
pio_stress_all.3320339667
Directory /workspace/3.gpio_stress_all/latest

Test location /workspace/coverage/default/3.gpio_stress_all_with_rand_reset.3897119637
Short name T658
Test name
Test status
Simulation time 202531104854 ps
CPU time 571.93 seconds
Started Dec 20 12:28:48 PM PST 23
Finished Dec 20 12:38:54 PM PST 23
Peak memory 198428 kb
Host smart-ea9a35ba-3504-495e-952b-13a4895e4ddc
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=3897119637 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_stress_all_with_rand_reset.3897119637
Directory /workspace/3.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/30.gpio_alert_test.3364486453
Short name T596
Test name
Test status
Simulation time 16572606 ps
CPU time 0.55 seconds
Started Dec 20 12:29:57 PM PST 23
Finished Dec 20 12:30:40 PM PST 23
Peak memory 194096 kb
Host smart-b6ff874a-45da-4edd-ad4d-3bd35f8d7b8d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3364486453 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_alert_test.3364486453
Directory /workspace/30.gpio_alert_test/latest

Test location /workspace/coverage/default/30.gpio_dout_din_regs_random_rw.293437185
Short name T462
Test name
Test status
Simulation time 32547107 ps
CPU time 0.81 seconds
Started Dec 20 12:29:59 PM PST 23
Finished Dec 20 12:30:56 PM PST 23
Peak memory 195560 kb
Host smart-1adc1895-17a9-4aa0-99ff-80d904b97b18
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=293437185 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_dout_din_regs_random_rw.293437185
Directory /workspace/30.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/30.gpio_filter_stress.4040918893
Short name T287
Test name
Test status
Simulation time 140444897 ps
CPU time 4.51 seconds
Started Dec 20 12:29:56 PM PST 23
Finished Dec 20 12:30:31 PM PST 23
Peak memory 195656 kb
Host smart-ce3bee79-e2ec-4e65-b66a-0ecd7bf5d585
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4040918893 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_filter_stre
ss.4040918893
Directory /workspace/30.gpio_filter_stress/latest

Test location /workspace/coverage/default/30.gpio_full_random.419787319
Short name T48
Test name
Test status
Simulation time 167076145 ps
CPU time 0.85 seconds
Started Dec 20 12:29:53 PM PST 23
Finished Dec 20 12:30:14 PM PST 23
Peak memory 196064 kb
Host smart-db41ea4f-c9a4-4042-9658-c29c68065cf0
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=419787319 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_full_random.419787319
Directory /workspace/30.gpio_full_random/latest

Test location /workspace/coverage/default/30.gpio_intr_rand_pgm.1652171171
Short name T554
Test name
Test status
Simulation time 144464366 ps
CPU time 1.18 seconds
Started Dec 20 12:29:57 PM PST 23
Finished Dec 20 12:30:34 PM PST 23
Peak memory 195980 kb
Host smart-b18c962a-2cb7-410f-9682-480423e0a86b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1652171171 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_intr_rand_pgm.1652171171
Directory /workspace/30.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/30.gpio_intr_with_filter_rand_intr_event.4157043869
Short name T668
Test name
Test status
Simulation time 202519129 ps
CPU time 1.96 seconds
Started Dec 20 12:30:25 PM PST 23
Finished Dec 20 12:31:20 PM PST 23
Peak memory 196308 kb
Host smart-ee519fa5-4b6a-4260-9954-5d3ebf72f955
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4157043869 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 30.gpio_intr_with_filter_rand_intr_event.4157043869
Directory /workspace/30.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/30.gpio_rand_intr_trigger.1472941651
Short name T785
Test name
Test status
Simulation time 88008627 ps
CPU time 1.11 seconds
Started Dec 20 12:30:01 PM PST 23
Finished Dec 20 12:30:49 PM PST 23
Peak memory 195648 kb
Host smart-422c3fbd-627f-44ba-a75b-8cebd23a86d2
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1472941651 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_rand_intr_trigger
.1472941651
Directory /workspace/30.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/30.gpio_random_dout_din.3676774419
Short name T371
Test name
Test status
Simulation time 90267731 ps
CPU time 0.77 seconds
Started Dec 20 12:30:09 PM PST 23
Finished Dec 20 12:31:05 PM PST 23
Peak memory 195628 kb
Host smart-43ce052f-0eda-4adb-8cb0-4f0e8263f01c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3676774419 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_random_dout_din.3676774419
Directory /workspace/30.gpio_random_dout_din/latest

Test location /workspace/coverage/default/30.gpio_random_dout_din_no_pullup_pulldown.161196611
Short name T697
Test name
Test status
Simulation time 62613243 ps
CPU time 1.14 seconds
Started Dec 20 12:29:52 PM PST 23
Finished Dec 20 12:30:13 PM PST 23
Peak memory 198196 kb
Host smart-dcfa0e33-ec76-47ff-902d-d0390b22455c
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=161196611 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_random_dout_din_no_pullup
_pulldown.161196611
Directory /workspace/30.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/30.gpio_random_long_reg_writes_reg_reads.3785928413
Short name T305
Test name
Test status
Simulation time 2379130870 ps
CPU time 5.49 seconds
Started Dec 20 12:30:07 PM PST 23
Finished Dec 20 12:31:09 PM PST 23
Peak memory 198180 kb
Host smart-3038f9b5-187c-409a-a575-fdb9658f8fe8
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3785928413 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_ra
ndom_long_reg_writes_reg_reads.3785928413
Directory /workspace/30.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/30.gpio_smoke.1319090023
Short name T770
Test name
Test status
Simulation time 139802180 ps
CPU time 1.21 seconds
Started Dec 20 12:30:00 PM PST 23
Finished Dec 20 12:30:48 PM PST 23
Peak memory 197108 kb
Host smart-03bd902d-8ca0-4071-add0-38d026c9ae85
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1319090023 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_smoke.1319090023
Directory /workspace/30.gpio_smoke/latest

Test location /workspace/coverage/default/30.gpio_smoke_no_pullup_pulldown.1822380180
Short name T197
Test name
Test status
Simulation time 191746272 ps
CPU time 1.35 seconds
Started Dec 20 12:29:47 PM PST 23
Finished Dec 20 12:30:07 PM PST 23
Peak memory 197000 kb
Host smart-4bff2392-f60b-495f-bb4c-cf72fc7922b0
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1822380180 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_smoke_no_pullup_pulldown.1822380180
Directory /workspace/30.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/30.gpio_stress_all.472101090
Short name T520
Test name
Test status
Simulation time 7007110642 ps
CPU time 48 seconds
Started Dec 20 12:30:04 PM PST 23
Finished Dec 20 12:31:40 PM PST 23
Peak memory 198300 kb
Host smart-9ff34d72-3c95-4b89-a5f4-6e51ac150a7f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=472101090 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.g
pio_stress_all.472101090
Directory /workspace/30.gpio_stress_all/latest

Test location /workspace/coverage/default/30.gpio_stress_all_with_rand_reset.1319089289
Short name T663
Test name
Test status
Simulation time 24515315812 ps
CPU time 299.06 seconds
Started Dec 20 12:29:57 PM PST 23
Finished Dec 20 12:35:38 PM PST 23
Peak memory 198100 kb
Host smart-98a4bda9-fcec-45e6-88a9-e77c1077f76a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=1319089289 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_stress_all_with_rand_reset.1319089289
Directory /workspace/30.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/31.gpio_alert_test.3273681623
Short name T49
Test name
Test status
Simulation time 27243606 ps
CPU time 0.6 seconds
Started Dec 20 12:30:27 PM PST 23
Finished Dec 20 12:31:16 PM PST 23
Peak memory 194752 kb
Host smart-2168c718-e779-4f69-9534-c1aa6471ec47
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3273681623 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_alert_test.3273681623
Directory /workspace/31.gpio_alert_test/latest

Test location /workspace/coverage/default/31.gpio_dout_din_regs_random_rw.1161534643
Short name T207
Test name
Test status
Simulation time 24183175 ps
CPU time 0.66 seconds
Started Dec 20 12:29:58 PM PST 23
Finished Dec 20 12:30:48 PM PST 23
Peak memory 194288 kb
Host smart-955a8e0a-e678-4bcd-9066-d8da57a84e03
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1161534643 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_dout_din_regs_random_rw.1161534643
Directory /workspace/31.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/31.gpio_filter_stress.274625844
Short name T641
Test name
Test status
Simulation time 2113997982 ps
CPU time 16.02 seconds
Started Dec 20 12:30:26 PM PST 23
Finished Dec 20 12:31:31 PM PST 23
Peak memory 197048 kb
Host smart-c6eebfd1-e01c-45c8-9a43-9e82d6742ff4
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=274625844 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_filter_stres
s.274625844
Directory /workspace/31.gpio_filter_stress/latest

Test location /workspace/coverage/default/31.gpio_full_random.215718693
Short name T672
Test name
Test status
Simulation time 136455648 ps
CPU time 1 seconds
Started Dec 20 12:30:13 PM PST 23
Finished Dec 20 12:31:11 PM PST 23
Peak memory 198208 kb
Host smart-43ec0f46-b9ee-43ac-ba58-9ba5d32bd888
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=215718693 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_full_random.215718693
Directory /workspace/31.gpio_full_random/latest

Test location /workspace/coverage/default/31.gpio_intr_rand_pgm.2018617896
Short name T457
Test name
Test status
Simulation time 29861101 ps
CPU time 0.94 seconds
Started Dec 20 12:30:00 PM PST 23
Finished Dec 20 12:30:48 PM PST 23
Peak memory 196080 kb
Host smart-1164f396-8f89-4396-8999-3fd1e2268951
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2018617896 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_intr_rand_pgm.2018617896
Directory /workspace/31.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/31.gpio_rand_intr_trigger.41382215
Short name T820
Test name
Test status
Simulation time 1684655319 ps
CPU time 3 seconds
Started Dec 20 12:30:20 PM PST 23
Finished Dec 20 12:31:22 PM PST 23
Peak memory 196720 kb
Host smart-3cc51d18-48a1-44c0-9945-2bd977f83f9f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41382215 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigger
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_rand_intr_trigger.41382215
Directory /workspace/31.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/31.gpio_random_dout_din.399160192
Short name T810
Test name
Test status
Simulation time 186199115 ps
CPU time 1.13 seconds
Started Dec 20 12:30:06 PM PST 23
Finished Dec 20 12:31:05 PM PST 23
Peak memory 196864 kb
Host smart-a95313b7-416d-4d79-b135-bd0526a3879e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=399160192 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_random_dout_din.399160192
Directory /workspace/31.gpio_random_dout_din/latest

Test location /workspace/coverage/default/31.gpio_random_dout_din_no_pullup_pulldown.2287744588
Short name T311
Test name
Test status
Simulation time 150454345 ps
CPU time 0.99 seconds
Started Dec 20 12:29:50 PM PST 23
Finished Dec 20 12:30:10 PM PST 23
Peak memory 196480 kb
Host smart-5c9dcce9-852a-42b7-bb01-ead10bd4a401
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2287744588 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_random_dout_din_no_pullu
p_pulldown.2287744588
Directory /workspace/31.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/31.gpio_random_long_reg_writes_reg_reads.1919926209
Short name T425
Test name
Test status
Simulation time 1168691656 ps
CPU time 3.11 seconds
Started Dec 20 12:30:09 PM PST 23
Finished Dec 20 12:31:07 PM PST 23
Peak memory 198212 kb
Host smart-65127ab6-8def-44cb-ae30-5c303b7a8f3f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1919926209 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_ra
ndom_long_reg_writes_reg_reads.1919926209
Directory /workspace/31.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/31.gpio_smoke.3449200425
Short name T561
Test name
Test status
Simulation time 45266440 ps
CPU time 0.68 seconds
Started Dec 20 12:30:06 PM PST 23
Finished Dec 20 12:30:56 PM PST 23
Peak memory 194224 kb
Host smart-c7bfa80c-b435-4557-991e-890d77d28867
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3449200425 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_smoke.3449200425
Directory /workspace/31.gpio_smoke/latest

Test location /workspace/coverage/default/31.gpio_smoke_no_pullup_pulldown.2884683373
Short name T355
Test name
Test status
Simulation time 97509418 ps
CPU time 1.04 seconds
Started Dec 20 12:29:54 PM PST 23
Finished Dec 20 12:30:17 PM PST 23
Peak memory 195844 kb
Host smart-0dfec15c-a355-4b79-90e1-5336617a3b56
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2884683373 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_smoke_no_pullup_pulldown.2884683373
Directory /workspace/31.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/31.gpio_stress_all.522599836
Short name T736
Test name
Test status
Simulation time 9057669731 ps
CPU time 171.4 seconds
Started Dec 20 12:30:10 PM PST 23
Finished Dec 20 12:33:56 PM PST 23
Peak memory 198260 kb
Host smart-750bc0f2-edaf-4dbb-9c34-44e34f2fb701
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=522599836 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.g
pio_stress_all.522599836
Directory /workspace/31.gpio_stress_all/latest

Test location /workspace/coverage/default/31.gpio_stress_all_with_rand_reset.2954020213
Short name T365
Test name
Test status
Simulation time 183899431984 ps
CPU time 613.64 seconds
Started Dec 20 12:30:16 PM PST 23
Finished Dec 20 12:41:24 PM PST 23
Peak memory 198368 kb
Host smart-d5b76969-9882-4d08-83a5-7ae4bd3a8b4f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=2954020213 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_stress_all_with_rand_reset.2954020213
Directory /workspace/31.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/32.gpio_alert_test.1743814337
Short name T551
Test name
Test status
Simulation time 35183856 ps
CPU time 0.57 seconds
Started Dec 20 12:29:52 PM PST 23
Finished Dec 20 12:30:13 PM PST 23
Peak memory 194204 kb
Host smart-871fd1ef-0524-444e-8567-b098d7b708c6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1743814337 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_alert_test.1743814337
Directory /workspace/32.gpio_alert_test/latest

Test location /workspace/coverage/default/32.gpio_dout_din_regs_random_rw.64147859
Short name T759
Test name
Test status
Simulation time 35024278 ps
CPU time 0.67 seconds
Started Dec 20 12:29:59 PM PST 23
Finished Dec 20 12:30:57 PM PST 23
Peak memory 194468 kb
Host smart-523cc2af-c32c-42fd-b297-04b3ce6ef3b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=64147859 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_dout_din_regs_random_rw.64147859
Directory /workspace/32.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/32.gpio_filter_stress.3052344015
Short name T585
Test name
Test status
Simulation time 187421041 ps
CPU time 5.55 seconds
Started Dec 20 12:30:25 PM PST 23
Finished Dec 20 12:31:23 PM PST 23
Peak memory 197168 kb
Host smart-b3d00ec5-9594-4df0-adde-c02d8ce307d1
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3052344015 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_filter_stre
ss.3052344015
Directory /workspace/32.gpio_filter_stress/latest

Test location /workspace/coverage/default/32.gpio_full_random.2400598870
Short name T362
Test name
Test status
Simulation time 90200227 ps
CPU time 0.94 seconds
Started Dec 20 12:30:03 PM PST 23
Finished Dec 20 12:30:52 PM PST 23
Peak memory 196764 kb
Host smart-ce332534-0b17-4606-877f-a50b55a5b6cd
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2400598870 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_full_random.2400598870
Directory /workspace/32.gpio_full_random/latest

Test location /workspace/coverage/default/32.gpio_intr_with_filter_rand_intr_event.2269181863
Short name T334
Test name
Test status
Simulation time 100404497 ps
CPU time 3.01 seconds
Started Dec 20 12:29:52 PM PST 23
Finished Dec 20 12:30:15 PM PST 23
Peak memory 197320 kb
Host smart-f01979e3-3ed3-451d-b032-56e340cacf44
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2269181863 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 32.gpio_intr_with_filter_rand_intr_event.2269181863
Directory /workspace/32.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/32.gpio_rand_intr_trigger.4204946771
Short name T567
Test name
Test status
Simulation time 111086307 ps
CPU time 1.67 seconds
Started Dec 20 12:30:09 PM PST 23
Finished Dec 20 12:31:07 PM PST 23
Peak memory 196296 kb
Host smart-3b833880-c4d1-4970-b897-7d5104a226fd
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4204946771 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_rand_intr_trigger
.4204946771
Directory /workspace/32.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/32.gpio_random_dout_din.3599765808
Short name T790
Test name
Test status
Simulation time 61074915 ps
CPU time 1.12 seconds
Started Dec 20 12:30:31 PM PST 23
Finished Dec 20 12:31:16 PM PST 23
Peak memory 196000 kb
Host smart-5720af1b-19b8-4106-b115-c15bdc98e717
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3599765808 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_random_dout_din.3599765808
Directory /workspace/32.gpio_random_dout_din/latest

Test location /workspace/coverage/default/32.gpio_random_dout_din_no_pullup_pulldown.1587592634
Short name T610
Test name
Test status
Simulation time 41960137 ps
CPU time 1.05 seconds
Started Dec 20 12:30:15 PM PST 23
Finished Dec 20 12:31:17 PM PST 23
Peak memory 196184 kb
Host smart-0fb22c6c-0043-4a4c-a8f2-cfa5070912ae
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1587592634 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_random_dout_din_no_pullu
p_pulldown.1587592634
Directory /workspace/32.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/32.gpio_random_long_reg_writes_reg_reads.1029923299
Short name T846
Test name
Test status
Simulation time 658636150 ps
CPU time 5.23 seconds
Started Dec 20 12:30:26 PM PST 23
Finished Dec 20 12:31:20 PM PST 23
Peak memory 197948 kb
Host smart-ec575f4a-7447-42bc-b6ec-d63c7c4c5624
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1029923299 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_ra
ndom_long_reg_writes_reg_reads.1029923299
Directory /workspace/32.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/32.gpio_smoke.1579722841
Short name T200
Test name
Test status
Simulation time 184093334 ps
CPU time 1.3 seconds
Started Dec 20 12:30:02 PM PST 23
Finished Dec 20 12:30:50 PM PST 23
Peak memory 196840 kb
Host smart-abe99761-cf81-4ab0-81b0-42d4414f3c33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1579722841 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_smoke.1579722841
Directory /workspace/32.gpio_smoke/latest

Test location /workspace/coverage/default/32.gpio_smoke_no_pullup_pulldown.3118110571
Short name T808
Test name
Test status
Simulation time 79154970 ps
CPU time 0.81 seconds
Started Dec 20 12:30:07 PM PST 23
Finished Dec 20 12:31:02 PM PST 23
Peak memory 195564 kb
Host smart-7bf8f206-b1ef-4d2a-a2bf-220acfdddb03
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3118110571 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_smoke_no_pullup_pulldown.3118110571
Directory /workspace/32.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/32.gpio_stress_all.901641082
Short name T582
Test name
Test status
Simulation time 28495610887 ps
CPU time 175.48 seconds
Started Dec 20 12:30:15 PM PST 23
Finished Dec 20 12:34:18 PM PST 23
Peak memory 198256 kb
Host smart-91369ba2-2a5f-41f3-bf63-85f3422c18ee
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=901641082 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.g
pio_stress_all.901641082
Directory /workspace/32.gpio_stress_all/latest

Test location /workspace/coverage/default/32.gpio_stress_all_with_rand_reset.2590363601
Short name T420
Test name
Test status
Simulation time 552530038378 ps
CPU time 1430.74 seconds
Started Dec 20 12:29:56 PM PST 23
Finished Dec 20 12:54:12 PM PST 23
Peak memory 206620 kb
Host smart-d3568c74-5c1b-4d0f-8a9e-bbaf3046543f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=2590363601 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_stress_all_with_rand_reset.2590363601
Directory /workspace/32.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/33.gpio_alert_test.1695547323
Short name T525
Test name
Test status
Simulation time 22407086 ps
CPU time 0.55 seconds
Started Dec 20 12:29:59 PM PST 23
Finished Dec 20 12:30:47 PM PST 23
Peak memory 194776 kb
Host smart-842a3508-2403-419e-be6f-d950dc5bf11c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1695547323 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_alert_test.1695547323
Directory /workspace/33.gpio_alert_test/latest

Test location /workspace/coverage/default/33.gpio_dout_din_regs_random_rw.667368563
Short name T231
Test name
Test status
Simulation time 13297976 ps
CPU time 0.59 seconds
Started Dec 20 12:30:20 PM PST 23
Finished Dec 20 12:31:17 PM PST 23
Peak memory 194496 kb
Host smart-603c9f12-88f5-4569-95da-40f707410c57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=667368563 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_dout_din_regs_random_rw.667368563
Directory /workspace/33.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/33.gpio_filter_stress.1275712605
Short name T507
Test name
Test status
Simulation time 131994447 ps
CPU time 3.65 seconds
Started Dec 20 12:30:09 PM PST 23
Finished Dec 20 12:31:07 PM PST 23
Peak memory 196028 kb
Host smart-09408bc2-6647-4579-9c92-7552f7a84f30
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1275712605 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_filter_stre
ss.1275712605
Directory /workspace/33.gpio_filter_stress/latest

Test location /workspace/coverage/default/33.gpio_intr_rand_pgm.2629440617
Short name T250
Test name
Test status
Simulation time 61186577 ps
CPU time 1.1 seconds
Started Dec 20 12:30:26 PM PST 23
Finished Dec 20 12:31:16 PM PST 23
Peak memory 195856 kb
Host smart-cef7d23a-6982-47b9-98d7-0017a4ccbaf5
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2629440617 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_intr_rand_pgm.2629440617
Directory /workspace/33.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/33.gpio_intr_with_filter_rand_intr_event.54918046
Short name T493
Test name
Test status
Simulation time 349584900 ps
CPU time 3.48 seconds
Started Dec 20 12:29:47 PM PST 23
Finished Dec 20 12:30:09 PM PST 23
Peak memory 198352 kb
Host smart-ac8a8fca-2a65-456b-8b67-716c144e6254
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=54918046 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_S
EQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 33.gpio_intr_with_filter_rand_intr_event.54918046
Directory /workspace/33.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/33.gpio_random_dout_din.1010140574
Short name T236
Test name
Test status
Simulation time 87244793 ps
CPU time 0.68 seconds
Started Dec 20 12:30:18 PM PST 23
Finished Dec 20 12:31:19 PM PST 23
Peak memory 195080 kb
Host smart-6d413473-f48a-434d-b395-527232bad462
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1010140574 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_random_dout_din.1010140574
Directory /workspace/33.gpio_random_dout_din/latest

Test location /workspace/coverage/default/33.gpio_random_dout_din_no_pullup_pulldown.2086136268
Short name T600
Test name
Test status
Simulation time 88148980 ps
CPU time 1.16 seconds
Started Dec 20 12:29:58 PM PST 23
Finished Dec 20 12:30:43 PM PST 23
Peak memory 196116 kb
Host smart-d7205646-7055-4966-912f-15d3dabb65e4
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2086136268 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_random_dout_din_no_pullu
p_pulldown.2086136268
Directory /workspace/33.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/33.gpio_random_long_reg_writes_reg_reads.646743833
Short name T97
Test name
Test status
Simulation time 195473341 ps
CPU time 4.07 seconds
Started Dec 20 12:30:16 PM PST 23
Finished Dec 20 12:31:29 PM PST 23
Peak memory 197968 kb
Host smart-e734f07c-8b38-424d-9eac-b0477215a3ee
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=646743833 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_ran
dom_long_reg_writes_reg_reads.646743833
Directory /workspace/33.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/33.gpio_smoke.3910492662
Short name T623
Test name
Test status
Simulation time 38481884 ps
CPU time 1.07 seconds
Started Dec 20 12:29:55 PM PST 23
Finished Dec 20 12:30:20 PM PST 23
Peak memory 195704 kb
Host smart-84c043c6-7135-4249-b3a8-d2bb6660c026
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3910492662 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_smoke.3910492662
Directory /workspace/33.gpio_smoke/latest

Test location /workspace/coverage/default/33.gpio_smoke_no_pullup_pulldown.671189295
Short name T239
Test name
Test status
Simulation time 188097865 ps
CPU time 1.15 seconds
Started Dec 20 12:30:10 PM PST 23
Finished Dec 20 12:31:06 PM PST 23
Peak memory 196716 kb
Host smart-32e4f596-cc52-40d0-8021-7fd145ea936b
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=671189295 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_smoke_no_pullup_pulldown.671189295
Directory /workspace/33.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/33.gpio_stress_all.849203445
Short name T769
Test name
Test status
Simulation time 6106058796 ps
CPU time 34.54 seconds
Started Dec 20 12:30:26 PM PST 23
Finished Dec 20 12:32:01 PM PST 23
Peak memory 198192 kb
Host smart-46ce3e30-924d-4118-a062-ffcd236c7eae
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=849203445 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.g
pio_stress_all.849203445
Directory /workspace/33.gpio_stress_all/latest

Test location /workspace/coverage/default/33.gpio_stress_all_with_rand_reset.3470447045
Short name T478
Test name
Test status
Simulation time 124196026202 ps
CPU time 997.58 seconds
Started Dec 20 12:30:10 PM PST 23
Finished Dec 20 12:47:42 PM PST 23
Peak memory 198220 kb
Host smart-27b155dd-d401-4985-bb04-218e426307bd
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=3470447045 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_stress_all_with_rand_reset.3470447045
Directory /workspace/33.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/34.gpio_alert_test.1235266953
Short name T444
Test name
Test status
Simulation time 12335640 ps
CPU time 0.55 seconds
Started Dec 20 12:29:57 PM PST 23
Finished Dec 20 12:30:47 PM PST 23
Peak memory 194116 kb
Host smart-6eb0769d-8cf8-461a-994c-9283b175a537
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1235266953 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_alert_test.1235266953
Directory /workspace/34.gpio_alert_test/latest

Test location /workspace/coverage/default/34.gpio_filter_stress.1029718345
Short name T556
Test name
Test status
Simulation time 904930782 ps
CPU time 22.37 seconds
Started Dec 20 12:30:35 PM PST 23
Finished Dec 20 12:31:38 PM PST 23
Peak memory 196924 kb
Host smart-94acbe95-fad5-4775-ba94-5efa90d353c8
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1029718345 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_filter_stre
ss.1029718345
Directory /workspace/34.gpio_filter_stress/latest

Test location /workspace/coverage/default/34.gpio_full_random.2520774298
Short name T738
Test name
Test status
Simulation time 296968305 ps
CPU time 0.81 seconds
Started Dec 20 12:30:32 PM PST 23
Finished Dec 20 12:31:18 PM PST 23
Peak memory 195904 kb
Host smart-3cba3d37-355b-4d21-b55e-1376fc34b77b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2520774298 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_full_random.2520774298
Directory /workspace/34.gpio_full_random/latest

Test location /workspace/coverage/default/34.gpio_intr_rand_pgm.2311934876
Short name T611
Test name
Test status
Simulation time 68404189 ps
CPU time 0.83 seconds
Started Dec 20 12:30:09 PM PST 23
Finished Dec 20 12:31:04 PM PST 23
Peak memory 196364 kb
Host smart-6b92854e-76f6-438b-a1dc-236aa4bde161
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2311934876 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_intr_rand_pgm.2311934876
Directory /workspace/34.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/34.gpio_intr_with_filter_rand_intr_event.3377123922
Short name T434
Test name
Test status
Simulation time 101350420 ps
CPU time 2.87 seconds
Started Dec 20 12:29:52 PM PST 23
Finished Dec 20 12:30:15 PM PST 23
Peak memory 198288 kb
Host smart-e3a68e9d-fb7a-4bbb-8b63-9859e3bfdfa0
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3377123922 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 34.gpio_intr_with_filter_rand_intr_event.3377123922
Directory /workspace/34.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/34.gpio_rand_intr_trigger.176733794
Short name T619
Test name
Test status
Simulation time 70168262 ps
CPU time 1.4 seconds
Started Dec 20 12:29:57 PM PST 23
Finished Dec 20 12:30:39 PM PST 23
Peak memory 196864 kb
Host smart-0c871d2c-0990-4b29-a6c1-bad9c1b0ae45
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=176733794 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_rand_intr_trigger.
176733794
Directory /workspace/34.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/34.gpio_random_dout_din.1068445834
Short name T763
Test name
Test status
Simulation time 317437397 ps
CPU time 0.79 seconds
Started Dec 20 12:30:01 PM PST 23
Finished Dec 20 12:30:49 PM PST 23
Peak memory 196380 kb
Host smart-e6b39eb2-ba85-457b-ac75-dfa38b77ee26
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1068445834 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_random_dout_din.1068445834
Directory /workspace/34.gpio_random_dout_din/latest

Test location /workspace/coverage/default/34.gpio_random_dout_din_no_pullup_pulldown.902767228
Short name T724
Test name
Test status
Simulation time 69550208 ps
CPU time 0.84 seconds
Started Dec 20 12:30:19 PM PST 23
Finished Dec 20 12:31:12 PM PST 23
Peak memory 196156 kb
Host smart-f1f5bda5-fa6b-4fc3-94a3-ca514d4401ab
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=902767228 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_random_dout_din_no_pullup
_pulldown.902767228
Directory /workspace/34.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/34.gpio_random_long_reg_writes_reg_reads.3763953876
Short name T511
Test name
Test status
Simulation time 331896572 ps
CPU time 5.63 seconds
Started Dec 20 12:30:25 PM PST 23
Finished Dec 20 12:31:23 PM PST 23
Peak memory 197540 kb
Host smart-7f7b7656-953a-4925-8bf5-7a24050fb27b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3763953876 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_ra
ndom_long_reg_writes_reg_reads.3763953876
Directory /workspace/34.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/34.gpio_smoke.3987816310
Short name T824
Test name
Test status
Simulation time 91723954 ps
CPU time 0.93 seconds
Started Dec 20 12:30:11 PM PST 23
Finished Dec 20 12:31:06 PM PST 23
Peak memory 195768 kb
Host smart-3db91528-a312-4e7e-813f-13692baf771e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3987816310 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_smoke.3987816310
Directory /workspace/34.gpio_smoke/latest

Test location /workspace/coverage/default/34.gpio_smoke_no_pullup_pulldown.2068682433
Short name T536
Test name
Test status
Simulation time 1006438681 ps
CPU time 1.42 seconds
Started Dec 20 12:30:17 PM PST 23
Finished Dec 20 12:31:12 PM PST 23
Peak memory 195688 kb
Host smart-fec0e3e9-45c1-41c5-a289-66ac6ee98efa
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2068682433 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_smoke_no_pullup_pulldown.2068682433
Directory /workspace/34.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/34.gpio_stress_all.3875220324
Short name T291
Test name
Test status
Simulation time 2476277901 ps
CPU time 28.17 seconds
Started Dec 20 12:30:12 PM PST 23
Finished Dec 20 12:31:39 PM PST 23
Peak memory 198212 kb
Host smart-ef14a5ba-1e6d-458c-9588-c0afdf2d6f4b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3875220324 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.
gpio_stress_all.3875220324
Directory /workspace/34.gpio_stress_all/latest

Test location /workspace/coverage/default/34.gpio_stress_all_with_rand_reset.3084870002
Short name T558
Test name
Test status
Simulation time 18993930692 ps
CPU time 29.98 seconds
Started Dec 20 12:29:59 PM PST 23
Finished Dec 20 12:31:14 PM PST 23
Peak memory 198544 kb
Host smart-57bdce12-0715-467a-9565-7f5729761e7b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=3084870002 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_stress_all_with_rand_reset.3084870002
Directory /workspace/34.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/35.gpio_alert_test.852480121
Short name T601
Test name
Test status
Simulation time 30692249 ps
CPU time 0.58 seconds
Started Dec 20 12:30:24 PM PST 23
Finished Dec 20 12:31:20 PM PST 23
Peak memory 194348 kb
Host smart-d3f74987-64ca-41aa-bc9d-b9921dd815e3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=852480121 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_alert_test.852480121
Directory /workspace/35.gpio_alert_test/latest

Test location /workspace/coverage/default/35.gpio_dout_din_regs_random_rw.576130589
Short name T543
Test name
Test status
Simulation time 52505560 ps
CPU time 0.61 seconds
Started Dec 20 12:30:39 PM PST 23
Finished Dec 20 12:31:27 PM PST 23
Peak memory 194912 kb
Host smart-8544f249-fd2d-4c44-a133-b069b6eacbba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=576130589 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_dout_din_regs_random_rw.576130589
Directory /workspace/35.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/35.gpio_intr_rand_pgm.621542357
Short name T452
Test name
Test status
Simulation time 71834483 ps
CPU time 1.09 seconds
Started Dec 20 12:30:20 PM PST 23
Finished Dec 20 12:31:17 PM PST 23
Peak memory 196200 kb
Host smart-bb7f5853-e755-4928-9482-bf5e4b80a832
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=621542357 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_intr_rand_pgm.621542357
Directory /workspace/35.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/35.gpio_intr_with_filter_rand_intr_event.414510294
Short name T708
Test name
Test status
Simulation time 37594445 ps
CPU time 1.39 seconds
Started Dec 20 12:31:09 PM PST 23
Finished Dec 20 12:31:59 PM PST 23
Peak memory 196988 kb
Host smart-48da684b-a038-4bef-b54a-309e41593c27
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=414510294 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 35.gpio_intr_with_filter_rand_intr_event.414510294
Directory /workspace/35.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/35.gpio_rand_intr_trigger.1918379143
Short name T402
Test name
Test status
Simulation time 838038396 ps
CPU time 2.73 seconds
Started Dec 20 12:30:24 PM PST 23
Finished Dec 20 12:31:18 PM PST 23
Peak memory 196876 kb
Host smart-c9b78c82-87d4-4ff1-b07c-761ce3c1fc5d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1918379143 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_rand_intr_trigger
.1918379143
Directory /workspace/35.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/35.gpio_random_dout_din.3943746340
Short name T270
Test name
Test status
Simulation time 163972893 ps
CPU time 0.87 seconds
Started Dec 20 12:29:59 PM PST 23
Finished Dec 20 12:30:47 PM PST 23
Peak memory 196888 kb
Host smart-6549fc8f-4b0c-4f97-9f9a-f87b80ebb409
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3943746340 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_random_dout_din.3943746340
Directory /workspace/35.gpio_random_dout_din/latest

Test location /workspace/coverage/default/35.gpio_random_dout_din_no_pullup_pulldown.741659558
Short name T466
Test name
Test status
Simulation time 99790552 ps
CPU time 1.02 seconds
Started Dec 20 12:30:00 PM PST 23
Finished Dec 20 12:30:48 PM PST 23
Peak memory 196736 kb
Host smart-66de5024-d6df-4b52-9334-b0bffeea9aae
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=741659558 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_random_dout_din_no_pullup
_pulldown.741659558
Directory /workspace/35.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/35.gpio_smoke.1405630765
Short name T419
Test name
Test status
Simulation time 71122933 ps
CPU time 1.11 seconds
Started Dec 20 12:30:23 PM PST 23
Finished Dec 20 12:31:17 PM PST 23
Peak memory 195844 kb
Host smart-9adec2c1-f892-42d9-b3c7-7d8c654d9969
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1405630765 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_smoke.1405630765
Directory /workspace/35.gpio_smoke/latest

Test location /workspace/coverage/default/35.gpio_smoke_no_pullup_pulldown.3132223865
Short name T617
Test name
Test status
Simulation time 48887688 ps
CPU time 1.22 seconds
Started Dec 20 12:30:01 PM PST 23
Finished Dec 20 12:30:49 PM PST 23
Peak memory 196868 kb
Host smart-055c2276-31b7-4e3b-acdd-158a31e5ed46
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3132223865 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_smoke_no_pullup_pulldown.3132223865
Directory /workspace/35.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/35.gpio_stress_all.1309846346
Short name T433
Test name
Test status
Simulation time 25181638122 ps
CPU time 175.39 seconds
Started Dec 20 12:30:29 PM PST 23
Finished Dec 20 12:34:22 PM PST 23
Peak memory 198252 kb
Host smart-fdd14e63-0241-448e-8378-5545f80a91f5
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1309846346 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.
gpio_stress_all.1309846346
Directory /workspace/35.gpio_stress_all/latest

Test location /workspace/coverage/default/35.gpio_stress_all_with_rand_reset.249912947
Short name T766
Test name
Test status
Simulation time 74101367836 ps
CPU time 1565.67 seconds
Started Dec 20 12:30:07 PM PST 23
Finished Dec 20 12:57:07 PM PST 23
Peak memory 198452 kb
Host smart-c0b248a7-4a63-4b3b-bd12-64142925b889
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=249912947 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_stress_all_with_rand_reset.249912947
Directory /workspace/35.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/36.gpio_alert_test.2375056941
Short name T705
Test name
Test status
Simulation time 80125514 ps
CPU time 0.67 seconds
Started Dec 20 12:30:20 PM PST 23
Finished Dec 20 12:31:17 PM PST 23
Peak memory 194784 kb
Host smart-6ee565b8-7b1d-4645-ae16-a2eb38f4647f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2375056941 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_alert_test.2375056941
Directory /workspace/36.gpio_alert_test/latest

Test location /workspace/coverage/default/36.gpio_dout_din_regs_random_rw.3214808456
Short name T746
Test name
Test status
Simulation time 218919235 ps
CPU time 0.73 seconds
Started Dec 20 12:30:03 PM PST 23
Finished Dec 20 12:30:52 PM PST 23
Peak memory 195324 kb
Host smart-8a2c9a2b-bbfa-4629-8f6c-0807accc7068
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3214808456 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_dout_din_regs_random_rw.3214808456
Directory /workspace/36.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/36.gpio_filter_stress.974471009
Short name T577
Test name
Test status
Simulation time 1371337610 ps
CPU time 16.46 seconds
Started Dec 20 12:30:11 PM PST 23
Finished Dec 20 12:31:25 PM PST 23
Peak memory 196936 kb
Host smart-de57f296-b256-4b37-9008-30dc5c96434e
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=974471009 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_filter_stres
s.974471009
Directory /workspace/36.gpio_filter_stress/latest

Test location /workspace/coverage/default/36.gpio_full_random.4247912945
Short name T479
Test name
Test status
Simulation time 34507508 ps
CPU time 0.71 seconds
Started Dec 20 12:30:25 PM PST 23
Finished Dec 20 12:31:16 PM PST 23
Peak memory 195340 kb
Host smart-9e8cc02f-ddb7-4733-8be1-7b608b1fb98c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4247912945 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_full_random.4247912945
Directory /workspace/36.gpio_full_random/latest

Test location /workspace/coverage/default/36.gpio_intr_rand_pgm.1990646698
Short name T538
Test name
Test status
Simulation time 89633084 ps
CPU time 0.71 seconds
Started Dec 20 12:30:02 PM PST 23
Finished Dec 20 12:30:50 PM PST 23
Peak memory 194988 kb
Host smart-5656bb3e-596a-40ef-914b-51be05f25e6a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1990646698 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_intr_rand_pgm.1990646698
Directory /workspace/36.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/36.gpio_intr_with_filter_rand_intr_event.2054535041
Short name T575
Test name
Test status
Simulation time 77326394 ps
CPU time 2.85 seconds
Started Dec 20 12:30:23 PM PST 23
Finished Dec 20 12:31:19 PM PST 23
Peak memory 198216 kb
Host smart-b531812c-ad2d-486a-9631-c5cd75a727fe
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2054535041 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 36.gpio_intr_with_filter_rand_intr_event.2054535041
Directory /workspace/36.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/36.gpio_rand_intr_trigger.2984915322
Short name T337
Test name
Test status
Simulation time 66655241 ps
CPU time 0.95 seconds
Started Dec 20 12:30:15 PM PST 23
Finished Dec 20 12:31:18 PM PST 23
Peak memory 195516 kb
Host smart-6d8c1217-2e0d-4eff-95cb-2f976d28bbd0
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2984915322 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_rand_intr_trigger
.2984915322
Directory /workspace/36.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/36.gpio_random_dout_din.2595420123
Short name T636
Test name
Test status
Simulation time 123212149 ps
CPU time 1.2 seconds
Started Dec 20 12:30:23 PM PST 23
Finished Dec 20 12:31:17 PM PST 23
Peak memory 198284 kb
Host smart-2668e8ff-c545-45ad-8736-0a5bec6bd261
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2595420123 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_random_dout_din.2595420123
Directory /workspace/36.gpio_random_dout_din/latest

Test location /workspace/coverage/default/36.gpio_random_dout_din_no_pullup_pulldown.1443922001
Short name T681
Test name
Test status
Simulation time 96504237 ps
CPU time 0.74 seconds
Started Dec 20 12:30:03 PM PST 23
Finished Dec 20 12:30:51 PM PST 23
Peak memory 196268 kb
Host smart-27d84aff-8bfb-4d5d-8152-b53da0597a5b
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1443922001 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_random_dout_din_no_pullu
p_pulldown.1443922001
Directory /workspace/36.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/36.gpio_random_long_reg_writes_reg_reads.1411687431
Short name T226
Test name
Test status
Simulation time 186767590 ps
CPU time 2.51 seconds
Started Dec 20 12:30:05 PM PST 23
Finished Dec 20 12:30:57 PM PST 23
Peak memory 198148 kb
Host smart-b74e9998-e335-4b18-a4d5-38c4853621b9
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1411687431 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_ra
ndom_long_reg_writes_reg_reads.1411687431
Directory /workspace/36.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/36.gpio_smoke.714890190
Short name T448
Test name
Test status
Simulation time 134054835 ps
CPU time 1.27 seconds
Started Dec 20 12:30:43 PM PST 23
Finished Dec 20 12:31:19 PM PST 23
Peak memory 197000 kb
Host smart-d1479403-a547-451b-93cd-cd03810e5551
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=714890190 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_smoke.714890190
Directory /workspace/36.gpio_smoke/latest

Test location /workspace/coverage/default/36.gpio_smoke_no_pullup_pulldown.165026054
Short name T695
Test name
Test status
Simulation time 146130169 ps
CPU time 1.28 seconds
Started Dec 20 12:30:08 PM PST 23
Finished Dec 20 12:31:05 PM PST 23
Peak memory 198188 kb
Host smart-b497117f-03a3-432f-8e6a-45103c5c1ac5
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=165026054 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_smoke_no_pullup_pulldown.165026054
Directory /workspace/36.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/36.gpio_stress_all.701636446
Short name T606
Test name
Test status
Simulation time 28055625397 ps
CPU time 100.32 seconds
Started Dec 20 12:29:59 PM PST 23
Finished Dec 20 12:32:26 PM PST 23
Peak memory 198256 kb
Host smart-a1f36412-2e61-4c2c-b491-c952d295de3f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=701636446 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.g
pio_stress_all.701636446
Directory /workspace/36.gpio_stress_all/latest

Test location /workspace/coverage/default/36.gpio_stress_all_with_rand_reset.2848593094
Short name T774
Test name
Test status
Simulation time 34984564629 ps
CPU time 226.53 seconds
Started Dec 20 12:30:02 PM PST 23
Finished Dec 20 12:34:36 PM PST 23
Peak memory 206496 kb
Host smart-fb628b36-a9e5-4199-a20d-66a95eef22f7
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=2848593094 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_stress_all_with_rand_reset.2848593094
Directory /workspace/36.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/37.gpio_dout_din_regs_random_rw.1987528006
Short name T204
Test name
Test status
Simulation time 34352050 ps
CPU time 0.82 seconds
Started Dec 20 12:30:14 PM PST 23
Finished Dec 20 12:31:10 PM PST 23
Peak memory 196216 kb
Host smart-c7d72b70-3089-483f-8bd7-d75224536ef4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1987528006 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_dout_din_regs_random_rw.1987528006
Directory /workspace/37.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/37.gpio_filter_stress.2549655996
Short name T472
Test name
Test status
Simulation time 1304609759 ps
CPU time 8.4 seconds
Started Dec 20 12:30:10 PM PST 23
Finished Dec 20 12:31:13 PM PST 23
Peak memory 196716 kb
Host smart-6e671e64-148f-44e8-b79b-d77b579d4085
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2549655996 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_filter_stre
ss.2549655996
Directory /workspace/37.gpio_filter_stress/latest

Test location /workspace/coverage/default/37.gpio_full_random.3019492908
Short name T243
Test name
Test status
Simulation time 42589319 ps
CPU time 0.77 seconds
Started Dec 20 12:30:38 PM PST 23
Finished Dec 20 12:31:16 PM PST 23
Peak memory 196792 kb
Host smart-a3cc43e7-b8fd-4868-8b89-1fea6cb597a6
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3019492908 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_full_random.3019492908
Directory /workspace/37.gpio_full_random/latest

Test location /workspace/coverage/default/37.gpio_intr_rand_pgm.1692431075
Short name T764
Test name
Test status
Simulation time 117444106 ps
CPU time 0.75 seconds
Started Dec 20 12:30:07 PM PST 23
Finished Dec 20 12:31:03 PM PST 23
Peak memory 195456 kb
Host smart-4e59e124-723c-48f4-ae5f-c9b4aba500b9
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1692431075 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_intr_rand_pgm.1692431075
Directory /workspace/37.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/37.gpio_intr_with_filter_rand_intr_event.525677090
Short name T694
Test name
Test status
Simulation time 693567567 ps
CPU time 2.37 seconds
Started Dec 20 12:29:58 PM PST 23
Finished Dec 20 12:30:47 PM PST 23
Peak memory 198240 kb
Host smart-3a132a31-4c3b-48cf-a8e4-33a0b98f3e4f
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=525677090 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 37.gpio_intr_with_filter_rand_intr_event.525677090
Directory /workspace/37.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/37.gpio_rand_intr_trigger.219127628
Short name T217
Test name
Test status
Simulation time 342501562 ps
CPU time 1.31 seconds
Started Dec 20 12:30:08 PM PST 23
Finished Dec 20 12:31:07 PM PST 23
Peak memory 196256 kb
Host smart-8c566e40-f409-4094-894c-412d4e249d7d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=219127628 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_rand_intr_trigger.
219127628
Directory /workspace/37.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/37.gpio_random_dout_din.4158550589
Short name T317
Test name
Test status
Simulation time 61195385 ps
CPU time 0.64 seconds
Started Dec 20 12:30:10 PM PST 23
Finished Dec 20 12:31:09 PM PST 23
Peak memory 194280 kb
Host smart-4e261fc4-4060-46ef-9e1e-325fac87a63e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4158550589 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_random_dout_din.4158550589
Directory /workspace/37.gpio_random_dout_din/latest

Test location /workspace/coverage/default/37.gpio_random_dout_din_no_pullup_pulldown.928198545
Short name T251
Test name
Test status
Simulation time 51972435 ps
CPU time 1.04 seconds
Started Dec 20 12:30:15 PM PST 23
Finished Dec 20 12:31:19 PM PST 23
Peak memory 196096 kb
Host smart-eec96609-d43e-4116-9493-440b18f73cc0
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=928198545 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_random_dout_din_no_pullup
_pulldown.928198545
Directory /workspace/37.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/37.gpio_random_long_reg_writes_reg_reads.2302396222
Short name T369
Test name
Test status
Simulation time 2197786673 ps
CPU time 4.45 seconds
Started Dec 20 12:30:09 PM PST 23
Finished Dec 20 12:31:08 PM PST 23
Peak memory 198012 kb
Host smart-6d20ec3d-a4fd-4869-912a-3400e415bb4e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2302396222 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_ra
ndom_long_reg_writes_reg_reads.2302396222
Directory /workspace/37.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/37.gpio_smoke.3050963068
Short name T546
Test name
Test status
Simulation time 99332930 ps
CPU time 0.93 seconds
Started Dec 20 12:30:10 PM PST 23
Finished Dec 20 12:31:05 PM PST 23
Peak memory 196328 kb
Host smart-5abff8c5-d02f-490e-a120-fc481e6874a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3050963068 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_smoke.3050963068
Directory /workspace/37.gpio_smoke/latest

Test location /workspace/coverage/default/37.gpio_stress_all.3670923555
Short name T447
Test name
Test status
Simulation time 54960512746 ps
CPU time 187.55 seconds
Started Dec 20 12:30:23 PM PST 23
Finished Dec 20 12:34:24 PM PST 23
Peak memory 198244 kb
Host smart-d8a3c74b-374c-4d4c-8a51-15d09af26e19
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3670923555 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.
gpio_stress_all.3670923555
Directory /workspace/37.gpio_stress_all/latest

Test location /workspace/coverage/default/37.gpio_stress_all_with_rand_reset.3583355020
Short name T373
Test name
Test status
Simulation time 528017655227 ps
CPU time 2322.61 seconds
Started Dec 20 12:30:39 PM PST 23
Finished Dec 20 01:09:59 PM PST 23
Peak memory 198456 kb
Host smart-1db5fb54-a855-42ef-b59f-9750b007d069
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=3583355020 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_stress_all_with_rand_reset.3583355020
Directory /workspace/37.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/38.gpio_alert_test.3286797442
Short name T407
Test name
Test status
Simulation time 53381689 ps
CPU time 0.55 seconds
Started Dec 20 12:30:15 PM PST 23
Finished Dec 20 12:31:11 PM PST 23
Peak memory 194916 kb
Host smart-fa7a3d58-c682-427a-94a2-e8fe85f97009
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3286797442 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_alert_test.3286797442
Directory /workspace/38.gpio_alert_test/latest

Test location /workspace/coverage/default/38.gpio_dout_din_regs_random_rw.1344986222
Short name T717
Test name
Test status
Simulation time 155775322 ps
CPU time 0.65 seconds
Started Dec 20 12:30:03 PM PST 23
Finished Dec 20 12:30:51 PM PST 23
Peak memory 194124 kb
Host smart-28e31134-1f75-4b28-9173-74e22f9bc43f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1344986222 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_dout_din_regs_random_rw.1344986222
Directory /workspace/38.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/38.gpio_filter_stress.2612967126
Short name T330
Test name
Test status
Simulation time 578923737 ps
CPU time 7.61 seconds
Started Dec 20 12:30:42 PM PST 23
Finished Dec 20 12:31:34 PM PST 23
Peak memory 198168 kb
Host smart-219d0ab8-2c25-4d80-a927-3c04b9dd1479
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2612967126 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_filter_stre
ss.2612967126
Directory /workspace/38.gpio_filter_stress/latest

Test location /workspace/coverage/default/38.gpio_full_random.3393619314
Short name T352
Test name
Test status
Simulation time 36082082 ps
CPU time 0.67 seconds
Started Dec 20 12:30:09 PM PST 23
Finished Dec 20 12:31:06 PM PST 23
Peak memory 194884 kb
Host smart-619402d8-79d9-4e3e-a1f8-f87168fce961
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3393619314 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_full_random.3393619314
Directory /workspace/38.gpio_full_random/latest

Test location /workspace/coverage/default/38.gpio_intr_rand_pgm.453167440
Short name T690
Test name
Test status
Simulation time 97758467 ps
CPU time 1.29 seconds
Started Dec 20 12:30:03 PM PST 23
Finished Dec 20 12:30:52 PM PST 23
Peak memory 197396 kb
Host smart-ffcd52c4-c463-481a-8af6-bf9a018f894b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=453167440 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_intr_rand_pgm.453167440
Directory /workspace/38.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/38.gpio_intr_with_filter_rand_intr_event.1756195348
Short name T637
Test name
Test status
Simulation time 88812106 ps
CPU time 3.44 seconds
Started Dec 20 12:30:29 PM PST 23
Finished Dec 20 12:31:30 PM PST 23
Peak memory 198200 kb
Host smart-52d03cdc-479f-4de8-a6d0-9b1fd4baff28
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1756195348 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 38.gpio_intr_with_filter_rand_intr_event.1756195348
Directory /workspace/38.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/38.gpio_random_dout_din.409895133
Short name T789
Test name
Test status
Simulation time 67214754 ps
CPU time 1.11 seconds
Started Dec 20 12:30:13 PM PST 23
Finished Dec 20 12:31:09 PM PST 23
Peak memory 197020 kb
Host smart-bb226cde-0729-4fc3-a192-2d8c8b683485
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=409895133 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_random_dout_din.409895133
Directory /workspace/38.gpio_random_dout_din/latest

Test location /workspace/coverage/default/38.gpio_random_dout_din_no_pullup_pulldown.58897046
Short name T328
Test name
Test status
Simulation time 14424320 ps
CPU time 0.65 seconds
Started Dec 20 12:30:17 PM PST 23
Finished Dec 20 12:31:11 PM PST 23
Peak memory 195100 kb
Host smart-9e465231-a825-409b-8e38-dfe7c3c4b6ab
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=58897046 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_random_dout_din_no_pullup_
pulldown.58897046
Directory /workspace/38.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/38.gpio_smoke.1209620308
Short name T564
Test name
Test status
Simulation time 104994912 ps
CPU time 0.77 seconds
Started Dec 20 12:30:34 PM PST 23
Finished Dec 20 12:31:21 PM PST 23
Peak memory 196144 kb
Host smart-54a75ea4-f537-478f-b264-e52120a07b77
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1209620308 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_smoke.1209620308
Directory /workspace/38.gpio_smoke/latest

Test location /workspace/coverage/default/38.gpio_smoke_no_pullup_pulldown.52877849
Short name T733
Test name
Test status
Simulation time 242580818 ps
CPU time 1.25 seconds
Started Dec 20 12:30:07 PM PST 23
Finished Dec 20 12:31:04 PM PST 23
Peak memory 195884 kb
Host smart-e579f265-46b3-4f03-aa3f-fb7e3b5ea39a
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=52877849 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_smoke_no_pullup_pulldown.52877849
Directory /workspace/38.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/38.gpio_stress_all_with_rand_reset.1196553546
Short name T240
Test name
Test status
Simulation time 26946298671 ps
CPU time 339.43 seconds
Started Dec 20 12:30:24 PM PST 23
Finished Dec 20 12:37:01 PM PST 23
Peak memory 198512 kb
Host smart-5969ffff-4b6c-45f0-bc6a-fcbdd523fcfa
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=1196553546 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_stress_all_with_rand_reset.1196553546
Directory /workspace/38.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/39.gpio_alert_test.233423084
Short name T796
Test name
Test status
Simulation time 11400769 ps
CPU time 0.57 seconds
Started Dec 20 12:30:48 PM PST 23
Finished Dec 20 12:31:25 PM PST 23
Peak memory 194064 kb
Host smart-675d8495-6219-4c0d-ad58-b8313f5cdacf
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=233423084 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_alert_test.233423084
Directory /workspace/39.gpio_alert_test/latest

Test location /workspace/coverage/default/39.gpio_dout_din_regs_random_rw.1773014991
Short name T713
Test name
Test status
Simulation time 56776180 ps
CPU time 0.72 seconds
Started Dec 20 12:30:29 PM PST 23
Finished Dec 20 12:31:27 PM PST 23
Peak memory 195528 kb
Host smart-42a0bcf3-dbc7-40f4-aad9-4e3ace529000
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1773014991 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_dout_din_regs_random_rw.1773014991
Directory /workspace/39.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/39.gpio_filter_stress.3178049271
Short name T529
Test name
Test status
Simulation time 111191300 ps
CPU time 5.67 seconds
Started Dec 20 12:30:33 PM PST 23
Finished Dec 20 12:31:37 PM PST 23
Peak memory 197072 kb
Host smart-f268aeca-080f-46de-8f53-c7b96c9af0e8
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3178049271 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_filter_stre
ss.3178049271
Directory /workspace/39.gpio_filter_stress/latest

Test location /workspace/coverage/default/39.gpio_full_random.1362322729
Short name T413
Test name
Test status
Simulation time 296989091 ps
CPU time 0.97 seconds
Started Dec 20 12:30:34 PM PST 23
Finished Dec 20 12:31:17 PM PST 23
Peak memory 196456 kb
Host smart-b34c7357-f3b8-41a5-a7fe-6b0f881b05da
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1362322729 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_full_random.1362322729
Directory /workspace/39.gpio_full_random/latest

Test location /workspace/coverage/default/39.gpio_intr_rand_pgm.4004822001
Short name T378
Test name
Test status
Simulation time 62294293 ps
CPU time 0.66 seconds
Started Dec 20 12:30:21 PM PST 23
Finished Dec 20 12:31:26 PM PST 23
Peak memory 194208 kb
Host smart-1e8e9669-7ea0-4023-9b3f-0633187a2d99
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4004822001 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_intr_rand_pgm.4004822001
Directory /workspace/39.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/39.gpio_intr_with_filter_rand_intr_event.66977466
Short name T216
Test name
Test status
Simulation time 389847585 ps
CPU time 1.26 seconds
Started Dec 20 12:31:05 PM PST 23
Finished Dec 20 12:31:53 PM PST 23
Peak memory 198004 kb
Host smart-fb60878b-e8ad-445b-9bb4-c84718b67ba3
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=66977466 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_S
EQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 39.gpio_intr_with_filter_rand_intr_event.66977466
Directory /workspace/39.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/39.gpio_rand_intr_trigger.1798154179
Short name T414
Test name
Test status
Simulation time 322008519 ps
CPU time 1.81 seconds
Started Dec 20 12:30:38 PM PST 23
Finished Dec 20 12:31:17 PM PST 23
Peak memory 196788 kb
Host smart-e0537145-16ee-4910-806b-48de496538cc
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1798154179 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_rand_intr_trigger
.1798154179
Directory /workspace/39.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/39.gpio_random_dout_din.1750116085
Short name T228
Test name
Test status
Simulation time 83407789 ps
CPU time 0.96 seconds
Started Dec 20 12:29:59 PM PST 23
Finished Dec 20 12:30:47 PM PST 23
Peak memory 196208 kb
Host smart-8e61ef6d-4ff7-4632-a9ac-94fe7e0ae743
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1750116085 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_random_dout_din.1750116085
Directory /workspace/39.gpio_random_dout_din/latest

Test location /workspace/coverage/default/39.gpio_random_dout_din_no_pullup_pulldown.3035870164
Short name T627
Test name
Test status
Simulation time 43982136 ps
CPU time 1.01 seconds
Started Dec 20 12:29:57 PM PST 23
Finished Dec 20 12:30:40 PM PST 23
Peak memory 195700 kb
Host smart-b3346c73-582e-4959-aa4e-eda55c06bd93
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3035870164 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_random_dout_din_no_pullu
p_pulldown.3035870164
Directory /workspace/39.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/39.gpio_random_long_reg_writes_reg_reads.4039842585
Short name T384
Test name
Test status
Simulation time 992990109 ps
CPU time 4.63 seconds
Started Dec 20 12:30:59 PM PST 23
Finished Dec 20 12:31:47 PM PST 23
Peak memory 198196 kb
Host smart-1ad69023-17ec-438c-b2c9-44f35b14857b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4039842585 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_ra
ndom_long_reg_writes_reg_reads.4039842585
Directory /workspace/39.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/39.gpio_smoke.903111386
Short name T825
Test name
Test status
Simulation time 44531194 ps
CPU time 0.92 seconds
Started Dec 20 12:30:27 PM PST 23
Finished Dec 20 12:31:17 PM PST 23
Peak memory 197204 kb
Host smart-93f2f193-e850-405f-ba11-b3bfea630db6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=903111386 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_smoke.903111386
Directory /workspace/39.gpio_smoke/latest

Test location /workspace/coverage/default/39.gpio_smoke_no_pullup_pulldown.586927686
Short name T431
Test name
Test status
Simulation time 114104240 ps
CPU time 1.19 seconds
Started Dec 20 12:30:00 PM PST 23
Finished Dec 20 12:30:49 PM PST 23
Peak memory 196808 kb
Host smart-3f3c42fa-fe65-4d2e-93e4-9440d2111689
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=586927686 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_smoke_no_pullup_pulldown.586927686
Directory /workspace/39.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/39.gpio_stress_all.240940924
Short name T624
Test name
Test status
Simulation time 16242532233 ps
CPU time 111.25 seconds
Started Dec 20 12:30:26 PM PST 23
Finished Dec 20 12:33:09 PM PST 23
Peak memory 198284 kb
Host smart-020e3288-c931-455d-a627-358eb84e2900
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=240940924 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.g
pio_stress_all.240940924
Directory /workspace/39.gpio_stress_all/latest

Test location /workspace/coverage/default/39.gpio_stress_all_with_rand_reset.1089040950
Short name T633
Test name
Test status
Simulation time 89397659301 ps
CPU time 1830.56 seconds
Started Dec 20 12:30:26 PM PST 23
Finished Dec 20 01:01:49 PM PST 23
Peak memory 198312 kb
Host smart-5952aca8-7a1f-4415-93ee-19b8c06735e5
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=1089040950 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_stress_all_with_rand_reset.1089040950
Directory /workspace/39.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/4.gpio_alert_test.2661358383
Short name T275
Test name
Test status
Simulation time 34172787 ps
CPU time 0.58 seconds
Started Dec 20 12:28:47 PM PST 23
Finished Dec 20 12:29:21 PM PST 23
Peak memory 193896 kb
Host smart-24ffadd2-56d5-472e-94b4-f1ee9421c0a7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2661358383 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_alert_test.2661358383
Directory /workspace/4.gpio_alert_test/latest

Test location /workspace/coverage/default/4.gpio_dout_din_regs_random_rw.2102896577
Short name T553
Test name
Test status
Simulation time 192298860 ps
CPU time 0.88 seconds
Started Dec 20 12:28:51 PM PST 23
Finished Dec 20 12:29:26 PM PST 23
Peak memory 196176 kb
Host smart-bd7e25d3-8092-46d3-8320-306ee60726b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2102896577 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_dout_din_regs_random_rw.2102896577
Directory /workspace/4.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/4.gpio_filter_stress.3106675884
Short name T502
Test name
Test status
Simulation time 1699318506 ps
CPU time 25.54 seconds
Started Dec 20 12:28:45 PM PST 23
Finished Dec 20 12:29:43 PM PST 23
Peak memory 197256 kb
Host smart-44e74744-f6c3-435c-a3cb-f7ed323d926f
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3106675884 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_filter_stres
s.3106675884
Directory /workspace/4.gpio_filter_stress/latest

Test location /workspace/coverage/default/4.gpio_full_random.2295639020
Short name T679
Test name
Test status
Simulation time 42690314 ps
CPU time 0.76 seconds
Started Dec 20 12:28:42 PM PST 23
Finished Dec 20 12:29:15 PM PST 23
Peak memory 196624 kb
Host smart-833ead7f-039e-4221-94ba-0e662e14eaba
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2295639020 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_full_random.2295639020
Directory /workspace/4.gpio_full_random/latest

Test location /workspace/coverage/default/4.gpio_intr_rand_pgm.3333195248
Short name T735
Test name
Test status
Simulation time 309303857 ps
CPU time 1.36 seconds
Started Dec 20 12:28:45 PM PST 23
Finished Dec 20 12:29:19 PM PST 23
Peak memory 198120 kb
Host smart-46aab244-b72c-4bae-aa60-3950adec8cc3
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3333195248 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_intr_rand_pgm.3333195248
Directory /workspace/4.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/4.gpio_intr_with_filter_rand_intr_event.1555775082
Short name T325
Test name
Test status
Simulation time 63468815 ps
CPU time 2.39 seconds
Started Dec 20 12:28:40 PM PST 23
Finished Dec 20 12:29:15 PM PST 23
Peak memory 198180 kb
Host smart-d9d315c5-52c6-4a6e-ba25-e9e19c843c64
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1555775082 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 4.gpio_intr_with_filter_rand_intr_event.1555775082
Directory /workspace/4.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/4.gpio_rand_intr_trigger.188409669
Short name T802
Test name
Test status
Simulation time 118630858 ps
CPU time 2.29 seconds
Started Dec 20 12:28:45 PM PST 23
Finished Dec 20 12:29:19 PM PST 23
Peak memory 197320 kb
Host smart-13334d09-b969-47cd-9ba3-d373eb310eda
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=188409669 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_rand_intr_trigger.188409669
Directory /workspace/4.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/4.gpio_random_dout_din.3524302046
Short name T39
Test name
Test status
Simulation time 46646830 ps
CPU time 1 seconds
Started Dec 20 12:28:47 PM PST 23
Finished Dec 20 12:29:22 PM PST 23
Peak memory 196132 kb
Host smart-c05998e9-432d-4443-8468-9e5dc37bb11c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3524302046 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_random_dout_din.3524302046
Directory /workspace/4.gpio_random_dout_din/latest

Test location /workspace/coverage/default/4.gpio_random_dout_din_no_pullup_pulldown.2186535791
Short name T571
Test name
Test status
Simulation time 35877597 ps
CPU time 0.85 seconds
Started Dec 20 12:28:42 PM PST 23
Finished Dec 20 12:29:15 PM PST 23
Peak memory 196068 kb
Host smart-92ae56f2-39c4-4c46-9ed1-1a1711bf0cc3
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2186535791 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_random_dout_din_no_pullup
_pulldown.2186535791
Directory /workspace/4.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/4.gpio_random_long_reg_writes_reg_reads.1029035898
Short name T772
Test name
Test status
Simulation time 39979505 ps
CPU time 1.79 seconds
Started Dec 20 12:29:20 PM PST 23
Finished Dec 20 12:29:47 PM PST 23
Peak memory 198156 kb
Host smart-63e9e2a0-e792-44c2-9ab8-767e8737076c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1029035898 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_ran
dom_long_reg_writes_reg_reads.1029035898
Directory /workspace/4.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/4.gpio_sec_cm.2021214542
Short name T60
Test name
Test status
Simulation time 351431502 ps
CPU time 0.87 seconds
Started Dec 20 12:28:35 PM PST 23
Finished Dec 20 12:29:07 PM PST 23
Peak memory 213580 kb
Host smart-bc68c6e0-4410-4a2f-adfb-e9f5d0162372
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2021214542 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_sec_cm.2021214542
Directory /workspace/4.gpio_sec_cm/latest

Test location /workspace/coverage/default/4.gpio_smoke.3542772691
Short name T338
Test name
Test status
Simulation time 123620911 ps
CPU time 1.14 seconds
Started Dec 20 12:28:40 PM PST 23
Finished Dec 20 12:29:13 PM PST 23
Peak memory 195736 kb
Host smart-57bf1682-e5d1-4ca0-9c3a-8a6235696b11
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3542772691 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_smoke.3542772691
Directory /workspace/4.gpio_smoke/latest

Test location /workspace/coverage/default/4.gpio_smoke_no_pullup_pulldown.1991110420
Short name T264
Test name
Test status
Simulation time 158403095 ps
CPU time 1.02 seconds
Started Dec 20 12:28:49 PM PST 23
Finished Dec 20 12:29:24 PM PST 23
Peak memory 195548 kb
Host smart-12126b3e-7ce6-4b38-92f7-02c3f22a4d86
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1991110420 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_smoke_no_pullup_pulldown.1991110420
Directory /workspace/4.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/4.gpio_stress_all.1970873670
Short name T455
Test name
Test status
Simulation time 10416573807 ps
CPU time 71.27 seconds
Started Dec 20 12:28:40 PM PST 23
Finished Dec 20 12:30:23 PM PST 23
Peak memory 198276 kb
Host smart-bee9e25d-ed41-431e-874d-91f5c94e105f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1970873670 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.g
pio_stress_all.1970873670
Directory /workspace/4.gpio_stress_all/latest

Test location /workspace/coverage/default/4.gpio_stress_all_with_rand_reset.36600518
Short name T607
Test name
Test status
Simulation time 149139383984 ps
CPU time 294.79 seconds
Started Dec 20 12:28:40 PM PST 23
Finished Dec 20 12:34:06 PM PST 23
Peak memory 198216 kb
Host smart-af31a0b7-729f-47e4-bd97-ac4dd0e8b1c9
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=36600518 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_stress_all_with_rand_reset.36600518
Directory /workspace/4.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/40.gpio_alert_test.1546060206
Short name T475
Test name
Test status
Simulation time 18558446 ps
CPU time 0.54 seconds
Started Dec 20 12:30:29 PM PST 23
Finished Dec 20 12:31:27 PM PST 23
Peak memory 193940 kb
Host smart-453d58fc-6dea-430d-b51e-25f3a479b674
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1546060206 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_alert_test.1546060206
Directory /workspace/40.gpio_alert_test/latest

Test location /workspace/coverage/default/40.gpio_dout_din_regs_random_rw.1947082590
Short name T258
Test name
Test status
Simulation time 21597888 ps
CPU time 0.65 seconds
Started Dec 20 12:30:24 PM PST 23
Finished Dec 20 12:31:22 PM PST 23
Peak memory 193968 kb
Host smart-0afe80b4-ce8f-4589-84dc-e56da2d8dade
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1947082590 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_dout_din_regs_random_rw.1947082590
Directory /workspace/40.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/40.gpio_filter_stress.3516824025
Short name T830
Test name
Test status
Simulation time 706402702 ps
CPU time 23.46 seconds
Started Dec 20 12:30:33 PM PST 23
Finished Dec 20 12:31:41 PM PST 23
Peak memory 198048 kb
Host smart-8c736e82-f062-4839-9585-b92c5ce1426f
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3516824025 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_filter_stre
ss.3516824025
Directory /workspace/40.gpio_filter_stress/latest

Test location /workspace/coverage/default/40.gpio_full_random.2886041282
Short name T631
Test name
Test status
Simulation time 510171611 ps
CPU time 0.86 seconds
Started Dec 20 12:30:34 PM PST 23
Finished Dec 20 12:31:20 PM PST 23
Peak memory 195992 kb
Host smart-b41b8062-57f7-4a27-9d8f-f2851965a285
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2886041282 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_full_random.2886041282
Directory /workspace/40.gpio_full_random/latest

Test location /workspace/coverage/default/40.gpio_intr_rand_pgm.2917482149
Short name T67
Test name
Test status
Simulation time 123549457 ps
CPU time 0.87 seconds
Started Dec 20 12:30:22 PM PST 23
Finished Dec 20 12:31:27 PM PST 23
Peak memory 196820 kb
Host smart-b1087d81-4308-4e7a-94ac-953f21cfe52f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2917482149 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_intr_rand_pgm.2917482149
Directory /workspace/40.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/40.gpio_intr_with_filter_rand_intr_event.309656474
Short name T368
Test name
Test status
Simulation time 68224109 ps
CPU time 0.96 seconds
Started Dec 20 12:30:17 PM PST 23
Finished Dec 20 12:31:18 PM PST 23
Peak memory 196408 kb
Host smart-5e1daea2-fd8c-4d76-9816-aabf7406f947
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=309656474 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 40.gpio_intr_with_filter_rand_intr_event.309656474
Directory /workspace/40.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/40.gpio_rand_intr_trigger.2365723422
Short name T560
Test name
Test status
Simulation time 199404544 ps
CPU time 1.02 seconds
Started Dec 20 12:30:24 PM PST 23
Finished Dec 20 12:31:20 PM PST 23
Peak memory 195740 kb
Host smart-10db96f1-da2b-4e7a-90b0-ce4faaa8708d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2365723422 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_rand_intr_trigger
.2365723422
Directory /workspace/40.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/40.gpio_random_dout_din.431534387
Short name T449
Test name
Test status
Simulation time 775650817 ps
CPU time 1.14 seconds
Started Dec 20 12:30:31 PM PST 23
Finished Dec 20 12:31:27 PM PST 23
Peak memory 196744 kb
Host smart-5307aaf0-ac70-4146-8617-88fb1731ddec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=431534387 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_random_dout_din.431534387
Directory /workspace/40.gpio_random_dout_din/latest

Test location /workspace/coverage/default/40.gpio_random_dout_din_no_pullup_pulldown.3533058109
Short name T634
Test name
Test status
Simulation time 21732602 ps
CPU time 0.94 seconds
Started Dec 20 12:30:39 PM PST 23
Finished Dec 20 12:31:27 PM PST 23
Peak memory 195972 kb
Host smart-29ee709a-1ebc-476a-9390-735ff3a107a3
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3533058109 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_random_dout_din_no_pullu
p_pulldown.3533058109
Directory /workspace/40.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/40.gpio_random_long_reg_writes_reg_reads.427130187
Short name T68
Test name
Test status
Simulation time 3607176175 ps
CPU time 4.01 seconds
Started Dec 20 12:30:32 PM PST 23
Finished Dec 20 12:31:22 PM PST 23
Peak memory 198292 kb
Host smart-c8f8bb97-ec81-4aba-8e18-1f2a4c83feef
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=427130187 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_ran
dom_long_reg_writes_reg_reads.427130187
Directory /workspace/40.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/40.gpio_smoke.430765745
Short name T439
Test name
Test status
Simulation time 23968512 ps
CPU time 0.84 seconds
Started Dec 20 12:30:27 PM PST 23
Finished Dec 20 12:31:17 PM PST 23
Peak memory 197260 kb
Host smart-6657c368-898d-4e07-90cf-90b97bb49d2f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=430765745 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_smoke.430765745
Directory /workspace/40.gpio_smoke/latest

Test location /workspace/coverage/default/40.gpio_smoke_no_pullup_pulldown.2309020446
Short name T782
Test name
Test status
Simulation time 41025514 ps
CPU time 1.13 seconds
Started Dec 20 12:30:54 PM PST 23
Finished Dec 20 12:31:36 PM PST 23
Peak memory 196684 kb
Host smart-55263b73-881f-45cb-9035-54bf09cd6fe4
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2309020446 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_smoke_no_pullup_pulldown.2309020446
Directory /workspace/40.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/40.gpio_stress_all.406143431
Short name T497
Test name
Test status
Simulation time 4074331008 ps
CPU time 44.33 seconds
Started Dec 20 12:31:08 PM PST 23
Finished Dec 20 12:32:40 PM PST 23
Peak memory 198324 kb
Host smart-0dc77248-da29-475a-b20e-b2a6382e8f50
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=406143431 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.g
pio_stress_all.406143431
Directory /workspace/40.gpio_stress_all/latest

Test location /workspace/coverage/default/40.gpio_stress_all_with_rand_reset.1232122363
Short name T70
Test name
Test status
Simulation time 98687260605 ps
CPU time 1177.75 seconds
Started Dec 20 12:30:52 PM PST 23
Finished Dec 20 12:51:08 PM PST 23
Peak memory 198220 kb
Host smart-b4062942-e7b8-4406-94db-4a5b418e00c4
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=1232122363 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_stress_all_with_rand_reset.1232122363
Directory /workspace/40.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/41.gpio_alert_test.1299723592
Short name T50
Test name
Test status
Simulation time 48245993 ps
CPU time 0.56 seconds
Started Dec 20 12:30:34 PM PST 23
Finished Dec 20 12:31:17 PM PST 23
Peak memory 194272 kb
Host smart-9366a5b1-4055-49af-a1da-0279a68c5060
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1299723592 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_alert_test.1299723592
Directory /workspace/41.gpio_alert_test/latest

Test location /workspace/coverage/default/41.gpio_dout_din_regs_random_rw.2240247508
Short name T791
Test name
Test status
Simulation time 18141820 ps
CPU time 0.61 seconds
Started Dec 20 12:30:30 PM PST 23
Finished Dec 20 12:31:23 PM PST 23
Peak memory 193812 kb
Host smart-9c736b75-8964-4992-aac8-6995c0b9b809
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2240247508 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_dout_din_regs_random_rw.2240247508
Directory /workspace/41.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/41.gpio_filter_stress.172480545
Short name T834
Test name
Test status
Simulation time 1680637779 ps
CPU time 27.92 seconds
Started Dec 20 12:30:31 PM PST 23
Finished Dec 20 12:31:52 PM PST 23
Peak memory 196716 kb
Host smart-0a70b7c3-0df9-44ea-ba8a-a7d95fda3af9
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=172480545 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_filter_stres
s.172480545
Directory /workspace/41.gpio_filter_stress/latest

Test location /workspace/coverage/default/41.gpio_full_random.511565913
Short name T760
Test name
Test status
Simulation time 33375652 ps
CPU time 0.69 seconds
Started Dec 20 12:30:39 PM PST 23
Finished Dec 20 12:31:27 PM PST 23
Peak memory 194700 kb
Host smart-88e245bf-1ffe-4f10-9e7d-b0c576dd803a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=511565913 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_full_random.511565913
Directory /workspace/41.gpio_full_random/latest

Test location /workspace/coverage/default/41.gpio_intr_rand_pgm.1479176315
Short name T828
Test name
Test status
Simulation time 156734950 ps
CPU time 1.39 seconds
Started Dec 20 12:30:14 PM PST 23
Finished Dec 20 12:31:17 PM PST 23
Peak memory 198264 kb
Host smart-27786a0a-61cd-46ff-8a7e-586100b9a055
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1479176315 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_intr_rand_pgm.1479176315
Directory /workspace/41.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/41.gpio_intr_with_filter_rand_intr_event.2862064524
Short name T350
Test name
Test status
Simulation time 188459287 ps
CPU time 1.94 seconds
Started Dec 20 12:31:11 PM PST 23
Finished Dec 20 12:32:04 PM PST 23
Peak memory 198176 kb
Host smart-3a91b43e-b140-47af-a3d1-e6f637a645ff
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2862064524 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 41.gpio_intr_with_filter_rand_intr_event.2862064524
Directory /workspace/41.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/41.gpio_rand_intr_trigger.389228746
Short name T709
Test name
Test status
Simulation time 35579182 ps
CPU time 0.97 seconds
Started Dec 20 12:30:17 PM PST 23
Finished Dec 20 12:31:12 PM PST 23
Peak memory 195600 kb
Host smart-e4c8d6ce-5aad-429b-9d84-ac350d382a22
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=389228746 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_rand_intr_trigger.
389228746
Directory /workspace/41.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/41.gpio_random_dout_din.3067889646
Short name T374
Test name
Test status
Simulation time 152657814 ps
CPU time 0.92 seconds
Started Dec 20 12:30:37 PM PST 23
Finished Dec 20 12:31:17 PM PST 23
Peak memory 196184 kb
Host smart-04c78bdb-bca0-4467-b093-287e8ba93935
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3067889646 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_random_dout_din.3067889646
Directory /workspace/41.gpio_random_dout_din/latest

Test location /workspace/coverage/default/41.gpio_random_dout_din_no_pullup_pulldown.4042131625
Short name T332
Test name
Test status
Simulation time 45643283 ps
CPU time 1.02 seconds
Started Dec 20 12:30:55 PM PST 23
Finished Dec 20 12:31:36 PM PST 23
Peak memory 196072 kb
Host smart-4cdb8d10-17a1-4666-abf9-9ad796833631
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4042131625 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_random_dout_din_no_pullu
p_pulldown.4042131625
Directory /workspace/41.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/41.gpio_random_long_reg_writes_reg_reads.3241056096
Short name T335
Test name
Test status
Simulation time 4413333731 ps
CPU time 5.25 seconds
Started Dec 20 12:31:00 PM PST 23
Finished Dec 20 12:31:49 PM PST 23
Peak memory 198212 kb
Host smart-79071807-b00f-4469-9913-7d252a23d2ed
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3241056096 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_ra
ndom_long_reg_writes_reg_reads.3241056096
Directory /workspace/41.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/41.gpio_smoke.3318959882
Short name T357
Test name
Test status
Simulation time 105520128 ps
CPU time 1.05 seconds
Started Dec 20 12:31:04 PM PST 23
Finished Dec 20 12:31:50 PM PST 23
Peak memory 195964 kb
Host smart-461ca9e6-4182-492d-9632-f92b3518eb29
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3318959882 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_smoke.3318959882
Directory /workspace/41.gpio_smoke/latest

Test location /workspace/coverage/default/41.gpio_smoke_no_pullup_pulldown.2717043270
Short name T614
Test name
Test status
Simulation time 224583207 ps
CPU time 1.42 seconds
Started Dec 20 12:30:24 PM PST 23
Finished Dec 20 12:31:18 PM PST 23
Peak memory 195688 kb
Host smart-f75c16c7-fbb2-4f3e-a3ad-5cd52e29a03a
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2717043270 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_smoke_no_pullup_pulldown.2717043270
Directory /workspace/41.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/41.gpio_stress_all.2883353126
Short name T747
Test name
Test status
Simulation time 4712593783 ps
CPU time 106.86 seconds
Started Dec 20 12:30:32 PM PST 23
Finished Dec 20 12:33:05 PM PST 23
Peak memory 198300 kb
Host smart-790e403c-13b4-43c7-baf9-4c6532300ba7
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2883353126 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.
gpio_stress_all.2883353126
Directory /workspace/41.gpio_stress_all/latest

Test location /workspace/coverage/default/41.gpio_stress_all_with_rand_reset.2581515103
Short name T800
Test name
Test status
Simulation time 463205222410 ps
CPU time 1459.48 seconds
Started Dec 20 12:30:31 PM PST 23
Finished Dec 20 12:55:35 PM PST 23
Peak memory 198568 kb
Host smart-5e7ca436-1f96-4d91-abe3-fa48d8f491af
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=2581515103 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_stress_all_with_rand_reset.2581515103
Directory /workspace/41.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/42.gpio_alert_test.4227308538
Short name T443
Test name
Test status
Simulation time 16323727 ps
CPU time 0.57 seconds
Started Dec 20 12:30:25 PM PST 23
Finished Dec 20 12:31:18 PM PST 23
Peak memory 194080 kb
Host smart-8004f8b6-7b88-4db6-a026-5e26d292873d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4227308538 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_alert_test.4227308538
Directory /workspace/42.gpio_alert_test/latest

Test location /workspace/coverage/default/42.gpio_dout_din_regs_random_rw.2563451637
Short name T329
Test name
Test status
Simulation time 20192155 ps
CPU time 0.71 seconds
Started Dec 20 12:30:24 PM PST 23
Finished Dec 20 12:31:16 PM PST 23
Peak memory 195348 kb
Host smart-462ff71a-26b0-48d5-a591-6f70b51874d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2563451637 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_dout_din_regs_random_rw.2563451637
Directory /workspace/42.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/42.gpio_filter_stress.1466966007
Short name T675
Test name
Test status
Simulation time 1443238999 ps
CPU time 14.25 seconds
Started Dec 20 12:30:15 PM PST 23
Finished Dec 20 12:31:24 PM PST 23
Peak memory 195772 kb
Host smart-10e41629-9758-4c36-9537-11686c1e36bb
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1466966007 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_filter_stre
ss.1466966007
Directory /workspace/42.gpio_filter_stress/latest

Test location /workspace/coverage/default/42.gpio_full_random.621237989
Short name T263
Test name
Test status
Simulation time 76501155 ps
CPU time 0.62 seconds
Started Dec 20 12:30:22 PM PST 23
Finished Dec 20 12:31:27 PM PST 23
Peak memory 194512 kb
Host smart-f59828ba-8563-4071-a9bf-8e159e57472d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=621237989 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_full_random.621237989
Directory /workspace/42.gpio_full_random/latest

Test location /workspace/coverage/default/42.gpio_intr_rand_pgm.4202816542
Short name T745
Test name
Test status
Simulation time 84876039 ps
CPU time 0.8 seconds
Started Dec 20 12:30:55 PM PST 23
Finished Dec 20 12:31:37 PM PST 23
Peak memory 196160 kb
Host smart-820b28e8-3dfb-46df-840a-9e8a0856a3b3
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4202816542 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_intr_rand_pgm.4202816542
Directory /workspace/42.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/42.gpio_intr_with_filter_rand_intr_event.4251051964
Short name T382
Test name
Test status
Simulation time 198525858 ps
CPU time 2 seconds
Started Dec 20 12:30:15 PM PST 23
Finished Dec 20 12:31:12 PM PST 23
Peak memory 198092 kb
Host smart-e555ffe5-091b-4ed2-a522-d68e2b2b1bba
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4251051964 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 42.gpio_intr_with_filter_rand_intr_event.4251051964
Directory /workspace/42.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/42.gpio_rand_intr_trigger.3350672568
Short name T732
Test name
Test status
Simulation time 1254129171 ps
CPU time 3.38 seconds
Started Dec 20 12:30:25 PM PST 23
Finished Dec 20 12:31:21 PM PST 23
Peak memory 198248 kb
Host smart-7b9e1f0c-9de5-492b-bded-66b598ff2075
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3350672568 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_rand_intr_trigger
.3350672568
Directory /workspace/42.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/42.gpio_random_dout_din.2728964380
Short name T426
Test name
Test status
Simulation time 45030285 ps
CPU time 0.93 seconds
Started Dec 20 12:30:29 PM PST 23
Finished Dec 20 12:31:27 PM PST 23
Peak memory 196164 kb
Host smart-cff8eecd-0779-441e-a4e3-abe6c0edc45d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2728964380 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_random_dout_din.2728964380
Directory /workspace/42.gpio_random_dout_din/latest

Test location /workspace/coverage/default/42.gpio_random_dout_din_no_pullup_pulldown.3970407801
Short name T688
Test name
Test status
Simulation time 58014038 ps
CPU time 1.29 seconds
Started Dec 20 12:31:02 PM PST 23
Finished Dec 20 12:31:48 PM PST 23
Peak memory 195980 kb
Host smart-32ab829e-4149-4c38-836f-546e3490830e
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3970407801 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_random_dout_din_no_pullu
p_pulldown.3970407801
Directory /workspace/42.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/42.gpio_random_long_reg_writes_reg_reads.2242337204
Short name T390
Test name
Test status
Simulation time 382907978 ps
CPU time 1.54 seconds
Started Dec 20 12:30:31 PM PST 23
Finished Dec 20 12:31:26 PM PST 23
Peak memory 198156 kb
Host smart-d5dd8d95-3373-466f-aff7-2edd96bd00e8
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2242337204 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_ra
ndom_long_reg_writes_reg_reads.2242337204
Directory /workspace/42.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/42.gpio_smoke.3578961147
Short name T367
Test name
Test status
Simulation time 125639891 ps
CPU time 1.05 seconds
Started Dec 20 12:30:57 PM PST 23
Finished Dec 20 12:31:39 PM PST 23
Peak memory 195712 kb
Host smart-7926c1a6-b9da-47db-8c72-4cb1dac279bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3578961147 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_smoke.3578961147
Directory /workspace/42.gpio_smoke/latest

Test location /workspace/coverage/default/42.gpio_smoke_no_pullup_pulldown.581848007
Short name T671
Test name
Test status
Simulation time 234541436 ps
CPU time 1.23 seconds
Started Dec 20 12:30:15 PM PST 23
Finished Dec 20 12:31:18 PM PST 23
Peak memory 196028 kb
Host smart-8bfee9e1-0209-4e6d-a1fc-188a60bbc3b5
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=581848007 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_smoke_no_pullup_pulldown.581848007
Directory /workspace/42.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/42.gpio_stress_all.165008305
Short name T626
Test name
Test status
Simulation time 14605176538 ps
CPU time 196.18 seconds
Started Dec 20 12:30:31 PM PST 23
Finished Dec 20 12:34:41 PM PST 23
Peak memory 198372 kb
Host smart-f8289054-1df2-464b-9afe-208ad4719dd3
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=165008305 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.g
pio_stress_all.165008305
Directory /workspace/42.gpio_stress_all/latest

Test location /workspace/coverage/default/42.gpio_stress_all_with_rand_reset.3041009716
Short name T514
Test name
Test status
Simulation time 97708644585 ps
CPU time 1618.59 seconds
Started Dec 20 12:30:34 PM PST 23
Finished Dec 20 12:58:18 PM PST 23
Peak memory 198372 kb
Host smart-03011d2e-494d-4553-b454-c74c7f7d453f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=3041009716 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_stress_all_with_rand_reset.3041009716
Directory /workspace/42.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/43.gpio_alert_test.3139869889
Short name T304
Test name
Test status
Simulation time 52630529 ps
CPU time 0.56 seconds
Started Dec 20 12:30:37 PM PST 23
Finished Dec 20 12:31:17 PM PST 23
Peak memory 194168 kb
Host smart-35c30add-a54c-4628-8dd8-b8a28e857e78
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3139869889 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_alert_test.3139869889
Directory /workspace/43.gpio_alert_test/latest

Test location /workspace/coverage/default/43.gpio_dout_din_regs_random_rw.3219760800
Short name T572
Test name
Test status
Simulation time 14693236 ps
CPU time 0.58 seconds
Started Dec 20 12:30:39 PM PST 23
Finished Dec 20 12:31:27 PM PST 23
Peak memory 194012 kb
Host smart-3d5e49d5-48d1-4c13-8570-ecc1ff476daf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3219760800 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_dout_din_regs_random_rw.3219760800
Directory /workspace/43.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/43.gpio_filter_stress.1090030281
Short name T783
Test name
Test status
Simulation time 3522268951 ps
CPU time 25 seconds
Started Dec 20 12:30:37 PM PST 23
Finished Dec 20 12:31:41 PM PST 23
Peak memory 198156 kb
Host smart-b3e60099-bc49-46c8-b7e1-f3d37c41178e
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1090030281 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_filter_stre
ss.1090030281
Directory /workspace/43.gpio_filter_stress/latest

Test location /workspace/coverage/default/43.gpio_full_random.101189494
Short name T731
Test name
Test status
Simulation time 176289477 ps
CPU time 0.94 seconds
Started Dec 20 12:30:31 PM PST 23
Finished Dec 20 12:31:25 PM PST 23
Peak memory 196644 kb
Host smart-2df40e86-f4f6-4a38-9431-7f86a4cca971
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=101189494 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_full_random.101189494
Directory /workspace/43.gpio_full_random/latest

Test location /workspace/coverage/default/43.gpio_intr_rand_pgm.4201714358
Short name T651
Test name
Test status
Simulation time 115192901 ps
CPU time 1.14 seconds
Started Dec 20 12:30:20 PM PST 23
Finished Dec 20 12:31:17 PM PST 23
Peak memory 196704 kb
Host smart-3feeeecb-659a-455d-8c8d-4dfdcec6e397
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4201714358 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_intr_rand_pgm.4201714358
Directory /workspace/43.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/43.gpio_intr_with_filter_rand_intr_event.370374492
Short name T456
Test name
Test status
Simulation time 356102915 ps
CPU time 3.15 seconds
Started Dec 20 12:30:44 PM PST 23
Finished Dec 20 12:31:22 PM PST 23
Peak memory 196468 kb
Host smart-2dd8c000-9dd4-4f8e-aa69-591a12d4bc2b
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=370374492 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 43.gpio_intr_with_filter_rand_intr_event.370374492
Directory /workspace/43.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/43.gpio_rand_intr_trigger.112024867
Short name T322
Test name
Test status
Simulation time 155150899 ps
CPU time 2.39 seconds
Started Dec 20 12:30:34 PM PST 23
Finished Dec 20 12:31:21 PM PST 23
Peak memory 197296 kb
Host smart-126f743e-a071-48c7-b07e-e8f82102d37d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=112024867 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_rand_intr_trigger.
112024867
Directory /workspace/43.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/43.gpio_random_dout_din.989208375
Short name T650
Test name
Test status
Simulation time 54317399 ps
CPU time 1.14 seconds
Started Dec 20 12:30:38 PM PST 23
Finished Dec 20 12:31:21 PM PST 23
Peak memory 198196 kb
Host smart-92fd0316-4d61-4026-a941-e5e704310f7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=989208375 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_random_dout_din.989208375
Directory /workspace/43.gpio_random_dout_din/latest

Test location /workspace/coverage/default/43.gpio_random_dout_din_no_pullup_pulldown.1417027972
Short name T723
Test name
Test status
Simulation time 40707923 ps
CPU time 0.95 seconds
Started Dec 20 12:30:54 PM PST 23
Finished Dec 20 12:31:35 PM PST 23
Peak memory 196820 kb
Host smart-8ee7f4ec-dc48-4125-a1a3-ef91542c7bc2
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1417027972 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_random_dout_din_no_pullu
p_pulldown.1417027972
Directory /workspace/43.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/43.gpio_random_long_reg_writes_reg_reads.3256013324
Short name T696
Test name
Test status
Simulation time 140147938 ps
CPU time 3.08 seconds
Started Dec 20 12:30:36 PM PST 23
Finished Dec 20 12:31:21 PM PST 23
Peak memory 198080 kb
Host smart-a21485fe-6adb-4386-b73f-a3fcafe962b7
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3256013324 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_ra
ndom_long_reg_writes_reg_reads.3256013324
Directory /workspace/43.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/43.gpio_smoke.27080878
Short name T591
Test name
Test status
Simulation time 139047564 ps
CPU time 1.29 seconds
Started Dec 20 12:30:20 PM PST 23
Finished Dec 20 12:31:17 PM PST 23
Peak memory 195984 kb
Host smart-97720710-094e-4705-a7bf-6412d8072af3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=27080878 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_smoke.27080878
Directory /workspace/43.gpio_smoke/latest

Test location /workspace/coverage/default/43.gpio_smoke_no_pullup_pulldown.757499669
Short name T387
Test name
Test status
Simulation time 111086657 ps
CPU time 0.92 seconds
Started Dec 20 12:30:38 PM PST 23
Finished Dec 20 12:31:16 PM PST 23
Peak memory 196584 kb
Host smart-bf689053-fc7b-4371-9e06-10886b828882
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=757499669 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_smoke_no_pullup_pulldown.757499669
Directory /workspace/43.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/43.gpio_stress_all.926617013
Short name T488
Test name
Test status
Simulation time 1709490811 ps
CPU time 42.9 seconds
Started Dec 20 12:30:36 PM PST 23
Finished Dec 20 12:32:04 PM PST 23
Peak memory 198176 kb
Host smart-4e420e8d-283a-4df3-9150-c6dff430898b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=926617013 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.g
pio_stress_all.926617013
Directory /workspace/43.gpio_stress_all/latest

Test location /workspace/coverage/default/44.gpio_alert_test.1488263482
Short name T678
Test name
Test status
Simulation time 14176334 ps
CPU time 0.58 seconds
Started Dec 20 12:30:31 PM PST 23
Finished Dec 20 12:31:25 PM PST 23
Peak memory 194116 kb
Host smart-6774fba5-488c-4e89-844c-33a265a44a2b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1488263482 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_alert_test.1488263482
Directory /workspace/44.gpio_alert_test/latest

Test location /workspace/coverage/default/44.gpio_dout_din_regs_random_rw.2079634744
Short name T581
Test name
Test status
Simulation time 83574911 ps
CPU time 0.65 seconds
Started Dec 20 12:30:33 PM PST 23
Finished Dec 20 12:31:18 PM PST 23
Peak memory 194972 kb
Host smart-0f47ce68-ebb3-47ea-a12d-b9a1056ac429
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2079634744 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_dout_din_regs_random_rw.2079634744
Directory /workspace/44.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/44.gpio_filter_stress.4188172843
Short name T685
Test name
Test status
Simulation time 950951318 ps
CPU time 11.92 seconds
Started Dec 20 12:30:38 PM PST 23
Finished Dec 20 12:31:36 PM PST 23
Peak memory 197080 kb
Host smart-bc560dd4-e8fe-4f60-91e1-36033f298cbe
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4188172843 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_filter_stre
ss.4188172843
Directory /workspace/44.gpio_filter_stress/latest

Test location /workspace/coverage/default/44.gpio_full_random.3453634174
Short name T454
Test name
Test status
Simulation time 85266532 ps
CPU time 0.64 seconds
Started Dec 20 12:30:33 PM PST 23
Finished Dec 20 12:31:32 PM PST 23
Peak memory 194696 kb
Host smart-ec7effee-9098-45b2-84a5-3d92d6cb4e26
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3453634174 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_full_random.3453634174
Directory /workspace/44.gpio_full_random/latest

Test location /workspace/coverage/default/44.gpio_intr_rand_pgm.3040120116
Short name T469
Test name
Test status
Simulation time 190680474 ps
CPU time 0.91 seconds
Started Dec 20 12:30:59 PM PST 23
Finished Dec 20 12:31:42 PM PST 23
Peak memory 195972 kb
Host smart-43087329-d48a-4429-8ff3-bef363f71b42
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3040120116 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_intr_rand_pgm.3040120116
Directory /workspace/44.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/44.gpio_intr_with_filter_rand_intr_event.676818916
Short name T749
Test name
Test status
Simulation time 30440626 ps
CPU time 1.22 seconds
Started Dec 20 12:30:39 PM PST 23
Finished Dec 20 12:31:28 PM PST 23
Peak memory 197164 kb
Host smart-eefacd61-d44c-44f0-9f64-cd3fb19670dd
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=676818916 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 44.gpio_intr_with_filter_rand_intr_event.676818916
Directory /workspace/44.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/44.gpio_rand_intr_trigger.962020468
Short name T518
Test name
Test status
Simulation time 108271436 ps
CPU time 1.09 seconds
Started Dec 20 12:30:39 PM PST 23
Finished Dec 20 12:31:27 PM PST 23
Peak memory 196512 kb
Host smart-e9be7327-49d5-4cd1-9372-df6bc80d0ecb
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=962020468 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_rand_intr_trigger.
962020468
Directory /workspace/44.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/44.gpio_random_dout_din.4291994486
Short name T490
Test name
Test status
Simulation time 112576807 ps
CPU time 0.79 seconds
Started Dec 20 12:30:30 PM PST 23
Finished Dec 20 12:31:18 PM PST 23
Peak memory 195500 kb
Host smart-898fc719-9512-46ba-8cc7-f158326b7cef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4291994486 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_random_dout_din.4291994486
Directory /workspace/44.gpio_random_dout_din/latest

Test location /workspace/coverage/default/44.gpio_random_dout_din_no_pullup_pulldown.273800892
Short name T313
Test name
Test status
Simulation time 82343260 ps
CPU time 1.02 seconds
Started Dec 20 12:31:10 PM PST 23
Finished Dec 20 12:32:02 PM PST 23
Peak memory 196752 kb
Host smart-2170c515-3428-42e3-be27-101ad397757d
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=273800892 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_random_dout_din_no_pullup
_pulldown.273800892
Directory /workspace/44.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/44.gpio_random_long_reg_writes_reg_reads.3804178519
Short name T333
Test name
Test status
Simulation time 33610931 ps
CPU time 1.56 seconds
Started Dec 20 12:30:34 PM PST 23
Finished Dec 20 12:31:21 PM PST 23
Peak memory 198156 kb
Host smart-7178aa95-b9e8-4563-9138-3d9e3b6a003e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3804178519 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_ra
ndom_long_reg_writes_reg_reads.3804178519
Directory /workspace/44.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/44.gpio_smoke.76313904
Short name T739
Test name
Test status
Simulation time 180069916 ps
CPU time 0.96 seconds
Started Dec 20 12:30:27 PM PST 23
Finished Dec 20 12:31:17 PM PST 23
Peak memory 196516 kb
Host smart-8e63bc9f-86a0-4ca0-9e05-c95f97a6c707
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=76313904 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_smoke.76313904
Directory /workspace/44.gpio_smoke/latest

Test location /workspace/coverage/default/44.gpio_smoke_no_pullup_pulldown.1247861973
Short name T833
Test name
Test status
Simulation time 441483751 ps
CPU time 1.32 seconds
Started Dec 20 12:30:31 PM PST 23
Finished Dec 20 12:31:16 PM PST 23
Peak memory 197312 kb
Host smart-25e5731f-ee6f-4886-bcf1-9f03735b480a
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1247861973 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_smoke_no_pullup_pulldown.1247861973
Directory /workspace/44.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/44.gpio_stress_all.322536664
Short name T656
Test name
Test status
Simulation time 44964315359 ps
CPU time 108.32 seconds
Started Dec 20 12:30:59 PM PST 23
Finished Dec 20 12:33:29 PM PST 23
Peak memory 198328 kb
Host smart-7269a692-0539-4822-991f-90c1b2e3044e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=322536664 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.g
pio_stress_all.322536664
Directory /workspace/44.gpio_stress_all/latest

Test location /workspace/coverage/default/44.gpio_stress_all_with_rand_reset.3751488685
Short name T422
Test name
Test status
Simulation time 96887078773 ps
CPU time 2096.3 seconds
Started Dec 20 12:30:42 PM PST 23
Finished Dec 20 01:06:14 PM PST 23
Peak memory 198408 kb
Host smart-f8300833-b0da-4c0d-abc2-424c321c11e3
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=3751488685 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_stress_all_with_rand_reset.3751488685
Directory /workspace/44.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/45.gpio_alert_test.3639305002
Short name T489
Test name
Test status
Simulation time 13118174 ps
CPU time 0.6 seconds
Started Dec 20 12:30:39 PM PST 23
Finished Dec 20 12:31:27 PM PST 23
Peak memory 194104 kb
Host smart-f1e1f724-c2f0-4bfd-88f2-93e27cc231d4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3639305002 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_alert_test.3639305002
Directory /workspace/45.gpio_alert_test/latest

Test location /workspace/coverage/default/45.gpio_dout_din_regs_random_rw.1918687812
Short name T683
Test name
Test status
Simulation time 41977924 ps
CPU time 0.67 seconds
Started Dec 20 12:31:05 PM PST 23
Finished Dec 20 12:31:56 PM PST 23
Peak memory 196128 kb
Host smart-d11291ff-1375-4312-8ead-8b069a9d301f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1918687812 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_dout_din_regs_random_rw.1918687812
Directory /workspace/45.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/45.gpio_filter_stress.3481909763
Short name T495
Test name
Test status
Simulation time 196953531 ps
CPU time 6.84 seconds
Started Dec 20 12:31:12 PM PST 23
Finished Dec 20 12:32:11 PM PST 23
Peak memory 196892 kb
Host smart-9e789134-fd3f-4335-a018-242e07529491
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3481909763 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_filter_stre
ss.3481909763
Directory /workspace/45.gpio_filter_stress/latest

Test location /workspace/coverage/default/45.gpio_full_random.1932655472
Short name T314
Test name
Test status
Simulation time 127475792 ps
CPU time 0.65 seconds
Started Dec 20 12:30:54 PM PST 23
Finished Dec 20 12:31:34 PM PST 23
Peak memory 195372 kb
Host smart-03de17a5-f98b-4c07-bc80-93146371cf4a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1932655472 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_full_random.1932655472
Directory /workspace/45.gpio_full_random/latest

Test location /workspace/coverage/default/45.gpio_intr_rand_pgm.191362401
Short name T477
Test name
Test status
Simulation time 184438688 ps
CPU time 0.97 seconds
Started Dec 20 12:30:43 PM PST 23
Finished Dec 20 12:31:28 PM PST 23
Peak memory 196308 kb
Host smart-2b70153d-da01-402a-ac1e-d31d5c428e24
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=191362401 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_intr_rand_pgm.191362401
Directory /workspace/45.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/45.gpio_intr_with_filter_rand_intr_event.854436067
Short name T831
Test name
Test status
Simulation time 38406101 ps
CPU time 1.56 seconds
Started Dec 20 12:31:08 PM PST 23
Finished Dec 20 12:31:58 PM PST 23
Peak memory 196432 kb
Host smart-ada0411e-7e0a-4673-b0aa-a88baebe5b30
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=854436067 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 45.gpio_intr_with_filter_rand_intr_event.854436067
Directory /workspace/45.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/45.gpio_rand_intr_trigger.1533335637
Short name T265
Test name
Test status
Simulation time 266086243 ps
CPU time 2.89 seconds
Started Dec 20 12:30:49 PM PST 23
Finished Dec 20 12:31:29 PM PST 23
Peak memory 198188 kb
Host smart-5e784b68-2b44-431c-8682-0797d137e41b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1533335637 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_rand_intr_trigger
.1533335637
Directory /workspace/45.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/45.gpio_random_dout_din.3835862635
Short name T734
Test name
Test status
Simulation time 28891838 ps
CPU time 1.07 seconds
Started Dec 20 12:31:04 PM PST 23
Finished Dec 20 12:31:52 PM PST 23
Peak memory 195972 kb
Host smart-ee3971c1-c217-42d4-aeaa-2ca730bd3319
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3835862635 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_random_dout_din.3835862635
Directory /workspace/45.gpio_random_dout_din/latest

Test location /workspace/coverage/default/45.gpio_random_dout_din_no_pullup_pulldown.796764067
Short name T549
Test name
Test status
Simulation time 69747765 ps
CPU time 1.26 seconds
Started Dec 20 12:30:39 PM PST 23
Finished Dec 20 12:31:17 PM PST 23
Peak memory 196644 kb
Host smart-7e507c32-0568-48d1-8e07-d2bec7064926
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=796764067 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_random_dout_din_no_pullup
_pulldown.796764067
Directory /workspace/45.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/45.gpio_random_long_reg_writes_reg_reads.3534574018
Short name T220
Test name
Test status
Simulation time 269508824 ps
CPU time 4.43 seconds
Started Dec 20 12:31:00 PM PST 23
Finished Dec 20 12:31:51 PM PST 23
Peak memory 198140 kb
Host smart-4b2a3432-8df0-4e4f-9283-64d8cd80fda7
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3534574018 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_ra
ndom_long_reg_writes_reg_reads.3534574018
Directory /workspace/45.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/45.gpio_smoke.2645352482
Short name T267
Test name
Test status
Simulation time 63425146 ps
CPU time 1.13 seconds
Started Dec 20 12:31:09 PM PST 23
Finished Dec 20 12:32:00 PM PST 23
Peak memory 195624 kb
Host smart-717c1d00-89bb-46e9-b471-8f8ac5a0515c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2645352482 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_smoke.2645352482
Directory /workspace/45.gpio_smoke/latest

Test location /workspace/coverage/default/45.gpio_smoke_no_pullup_pulldown.3359176271
Short name T262
Test name
Test status
Simulation time 176541502 ps
CPU time 1.07 seconds
Started Dec 20 12:30:59 PM PST 23
Finished Dec 20 12:31:44 PM PST 23
Peak memory 195736 kb
Host smart-fd683835-5bec-4a88-abb3-b267be9d7957
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3359176271 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_smoke_no_pullup_pulldown.3359176271
Directory /workspace/45.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/45.gpio_stress_all.1767435069
Short name T453
Test name
Test status
Simulation time 6422571832 ps
CPU time 171.01 seconds
Started Dec 20 12:30:28 PM PST 23
Finished Dec 20 12:34:11 PM PST 23
Peak memory 198284 kb
Host smart-76dade45-daab-4c0b-b9d8-3cc9b6da1e0b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1767435069 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.
gpio_stress_all.1767435069
Directory /workspace/45.gpio_stress_all/latest

Test location /workspace/coverage/default/45.gpio_stress_all_with_rand_reset.123547268
Short name T376
Test name
Test status
Simulation time 194651316512 ps
CPU time 774 seconds
Started Dec 20 12:30:38 PM PST 23
Finished Dec 20 12:44:09 PM PST 23
Peak memory 206572 kb
Host smart-7d1c4912-fc5c-427a-b0cc-f29d7b401f8b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=123547268 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_stress_all_with_rand_reset.123547268
Directory /workspace/45.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/46.gpio_alert_test.2349354667
Short name T807
Test name
Test status
Simulation time 11826415 ps
CPU time 0.55 seconds
Started Dec 20 12:30:50 PM PST 23
Finished Dec 20 12:31:29 PM PST 23
Peak memory 194748 kb
Host smart-27326fd5-0c07-4f4b-8714-aa3b4802cf4b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2349354667 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_alert_test.2349354667
Directory /workspace/46.gpio_alert_test/latest

Test location /workspace/coverage/default/46.gpio_dout_din_regs_random_rw.370385381
Short name T544
Test name
Test status
Simulation time 55231312 ps
CPU time 0.85 seconds
Started Dec 20 12:30:57 PM PST 23
Finished Dec 20 12:31:38 PM PST 23
Peak memory 196000 kb
Host smart-7d203ba1-526d-4dfd-a1d8-22634bf29a93
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=370385381 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_dout_din_regs_random_rw.370385381
Directory /workspace/46.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/46.gpio_filter_stress.934989802
Short name T65
Test name
Test status
Simulation time 211844057 ps
CPU time 7.54 seconds
Started Dec 20 12:30:31 PM PST 23
Finished Dec 20 12:31:32 PM PST 23
Peak memory 197140 kb
Host smart-05b810e5-f874-4215-8713-9c3a58597b89
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=934989802 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_filter_stres
s.934989802
Directory /workspace/46.gpio_filter_stress/latest

Test location /workspace/coverage/default/46.gpio_full_random.3238180150
Short name T534
Test name
Test status
Simulation time 25950364 ps
CPU time 0.63 seconds
Started Dec 20 12:30:37 PM PST 23
Finished Dec 20 12:31:16 PM PST 23
Peak memory 194612 kb
Host smart-2c84a266-041c-4b37-884d-6f58cb88ac79
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3238180150 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_full_random.3238180150
Directory /workspace/46.gpio_full_random/latest

Test location /workspace/coverage/default/46.gpio_intr_rand_pgm.2285958900
Short name T773
Test name
Test status
Simulation time 35831644 ps
CPU time 1.08 seconds
Started Dec 20 12:30:24 PM PST 23
Finished Dec 20 12:31:20 PM PST 23
Peak memory 196712 kb
Host smart-461dd257-5dd6-4155-8a24-a3d364829796
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2285958900 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_intr_rand_pgm.2285958900
Directory /workspace/46.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/46.gpio_intr_with_filter_rand_intr_event.1325230162
Short name T676
Test name
Test status
Simulation time 30044784 ps
CPU time 1.21 seconds
Started Dec 20 12:30:26 PM PST 23
Finished Dec 20 12:31:19 PM PST 23
Peak memory 196564 kb
Host smart-64827ce6-45e9-467a-99a6-2b2a4dce9e18
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1325230162 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 46.gpio_intr_with_filter_rand_intr_event.1325230162
Directory /workspace/46.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/46.gpio_rand_intr_trigger.1498050176
Short name T221
Test name
Test status
Simulation time 321753470 ps
CPU time 2.23 seconds
Started Dec 20 12:30:25 PM PST 23
Finished Dec 20 12:31:17 PM PST 23
Peak memory 197136 kb
Host smart-388c3a9a-f15c-4707-a250-b8583c5bea6c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1498050176 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_rand_intr_trigger
.1498050176
Directory /workspace/46.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/46.gpio_random_dout_din.749184063
Short name T758
Test name
Test status
Simulation time 38616873 ps
CPU time 0.66 seconds
Started Dec 20 12:30:37 PM PST 23
Finished Dec 20 12:31:15 PM PST 23
Peak memory 195380 kb
Host smart-b9ac1ed4-9035-4496-bfc9-85c07ee3c27f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=749184063 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_random_dout_din.749184063
Directory /workspace/46.gpio_random_dout_din/latest

Test location /workspace/coverage/default/46.gpio_random_dout_din_no_pullup_pulldown.4021811239
Short name T40
Test name
Test status
Simulation time 47850035 ps
CPU time 0.67 seconds
Started Dec 20 12:30:34 PM PST 23
Finished Dec 20 12:31:23 PM PST 23
Peak memory 194344 kb
Host smart-e857af7f-b4ce-4455-bf8d-7c9d6afb35da
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4021811239 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_random_dout_din_no_pullu
p_pulldown.4021811239
Directory /workspace/46.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/46.gpio_random_long_reg_writes_reg_reads.4173494378
Short name T393
Test name
Test status
Simulation time 351154608 ps
CPU time 4.11 seconds
Started Dec 20 12:30:31 PM PST 23
Finished Dec 20 12:31:23 PM PST 23
Peak memory 198096 kb
Host smart-7e603d12-d331-4295-8de6-d9a473f4051e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4173494378 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_ra
ndom_long_reg_writes_reg_reads.4173494378
Directory /workspace/46.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/46.gpio_smoke.29348824
Short name T269
Test name
Test status
Simulation time 39794563 ps
CPU time 0.7 seconds
Started Dec 20 12:30:20 PM PST 23
Finished Dec 20 12:31:18 PM PST 23
Peak memory 195120 kb
Host smart-b641efeb-5ce1-4cb0-ab93-a10a36140e51
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=29348824 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_smoke.29348824
Directory /workspace/46.gpio_smoke/latest

Test location /workspace/coverage/default/46.gpio_smoke_no_pullup_pulldown.3196079113
Short name T754
Test name
Test status
Simulation time 120439232 ps
CPU time 0.92 seconds
Started Dec 20 12:31:00 PM PST 23
Finished Dec 20 12:31:44 PM PST 23
Peak memory 195548 kb
Host smart-ced63cb7-9ff8-49d5-9fc4-8ab96b57ea3a
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3196079113 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_smoke_no_pullup_pulldown.3196079113
Directory /workspace/46.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/46.gpio_stress_all.1792472540
Short name T485
Test name
Test status
Simulation time 63839112062 ps
CPU time 113.56 seconds
Started Dec 20 12:30:27 PM PST 23
Finished Dec 20 12:33:09 PM PST 23
Peak memory 198356 kb
Host smart-bbd6b571-a3fc-41b6-8b02-a92508103dd9
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1792472540 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.
gpio_stress_all.1792472540
Directory /workspace/46.gpio_stress_all/latest

Test location /workspace/coverage/default/46.gpio_stress_all_with_rand_reset.1253117122
Short name T410
Test name
Test status
Simulation time 29778900880 ps
CPU time 751.85 seconds
Started Dec 20 12:30:42 PM PST 23
Finished Dec 20 12:43:50 PM PST 23
Peak memory 198412 kb
Host smart-906cdc0e-fc3c-4bce-8b8b-9656cdae25a5
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=1253117122 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_stress_all_with_rand_reset.1253117122
Directory /workspace/46.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/47.gpio_alert_test.3978633999
Short name T438
Test name
Test status
Simulation time 14588234 ps
CPU time 0.57 seconds
Started Dec 20 12:31:13 PM PST 23
Finished Dec 20 12:32:07 PM PST 23
Peak memory 194832 kb
Host smart-13b3edfa-5dca-47e7-b435-35d4bd489dd1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3978633999 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_alert_test.3978633999
Directory /workspace/47.gpio_alert_test/latest

Test location /workspace/coverage/default/47.gpio_dout_din_regs_random_rw.1634585575
Short name T392
Test name
Test status
Simulation time 25629946 ps
CPU time 0.75 seconds
Started Dec 20 12:30:51 PM PST 23
Finished Dec 20 12:31:30 PM PST 23
Peak memory 195248 kb
Host smart-c4eb8373-da16-4459-bbb0-4c78a3511ba7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1634585575 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_dout_din_regs_random_rw.1634585575
Directory /workspace/47.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/47.gpio_filter_stress.3486544713
Short name T351
Test name
Test status
Simulation time 606980370 ps
CPU time 16.38 seconds
Started Dec 20 12:31:10 PM PST 23
Finished Dec 20 12:32:17 PM PST 23
Peak memory 195760 kb
Host smart-96de6a22-c13b-48aa-b312-d5b084811bde
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3486544713 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_filter_stre
ss.3486544713
Directory /workspace/47.gpio_filter_stress/latest

Test location /workspace/coverage/default/47.gpio_full_random.2851447235
Short name T288
Test name
Test status
Simulation time 110064177 ps
CPU time 0.75 seconds
Started Dec 20 12:30:44 PM PST 23
Finished Dec 20 12:31:20 PM PST 23
Peak memory 194828 kb
Host smart-17a69725-fc41-4dd7-a11d-322155151bcf
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2851447235 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_full_random.2851447235
Directory /workspace/47.gpio_full_random/latest

Test location /workspace/coverage/default/47.gpio_intr_rand_pgm.1148380914
Short name T615
Test name
Test status
Simulation time 175508185 ps
CPU time 0.91 seconds
Started Dec 20 12:30:53 PM PST 23
Finished Dec 20 12:31:34 PM PST 23
Peak memory 196656 kb
Host smart-10c0d845-5304-4760-95ab-049c92807844
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1148380914 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_intr_rand_pgm.1148380914
Directory /workspace/47.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/47.gpio_intr_with_filter_rand_intr_event.3324532190
Short name T809
Test name
Test status
Simulation time 405940119 ps
CPU time 1.19 seconds
Started Dec 20 12:31:10 PM PST 23
Finished Dec 20 12:32:02 PM PST 23
Peak memory 196852 kb
Host smart-54e32e4c-b33d-4eef-90d9-25acfde9697b
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3324532190 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 47.gpio_intr_with_filter_rand_intr_event.3324532190
Directory /workspace/47.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/47.gpio_rand_intr_trigger.1128305631
Short name T598
Test name
Test status
Simulation time 82074915 ps
CPU time 1.84 seconds
Started Dec 20 12:30:48 PM PST 23
Finished Dec 20 12:31:26 PM PST 23
Peak memory 196128 kb
Host smart-1b9873af-3205-4675-9e1e-52ca097d45bd
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1128305631 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_rand_intr_trigger
.1128305631
Directory /workspace/47.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/47.gpio_random_dout_din.214744657
Short name T729
Test name
Test status
Simulation time 223711917 ps
CPU time 1.13 seconds
Started Dec 20 12:30:37 PM PST 23
Finished Dec 20 12:31:17 PM PST 23
Peak memory 197056 kb
Host smart-bffe86ab-74d4-4375-b91a-cfde734aa684
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=214744657 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_random_dout_din.214744657
Directory /workspace/47.gpio_random_dout_din/latest

Test location /workspace/coverage/default/47.gpio_random_dout_din_no_pullup_pulldown.2752470948
Short name T285
Test name
Test status
Simulation time 34947350 ps
CPU time 1.22 seconds
Started Dec 20 12:30:52 PM PST 23
Finished Dec 20 12:31:32 PM PST 23
Peak memory 198252 kb
Host smart-05a902a6-97eb-46c1-99ee-86a163060916
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2752470948 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_random_dout_din_no_pullu
p_pulldown.2752470948
Directory /workspace/47.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/47.gpio_random_long_reg_writes_reg_reads.2271956757
Short name T510
Test name
Test status
Simulation time 348585631 ps
CPU time 3.86 seconds
Started Dec 20 12:30:55 PM PST 23
Finished Dec 20 12:31:39 PM PST 23
Peak memory 198168 kb
Host smart-0def8979-dc3d-4cb7-9fad-2a1ac785ad6a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2271956757 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_ra
ndom_long_reg_writes_reg_reads.2271956757
Directory /workspace/47.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/47.gpio_smoke.252862209
Short name T648
Test name
Test status
Simulation time 31700066 ps
CPU time 0.82 seconds
Started Dec 20 12:30:35 PM PST 23
Finished Dec 20 12:31:20 PM PST 23
Peak memory 196036 kb
Host smart-1b74554d-de4c-4d84-955e-73474fe2fb56
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=252862209 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_smoke.252862209
Directory /workspace/47.gpio_smoke/latest

Test location /workspace/coverage/default/47.gpio_smoke_no_pullup_pulldown.1048805966
Short name T701
Test name
Test status
Simulation time 91130131 ps
CPU time 1.33 seconds
Started Dec 20 12:30:58 PM PST 23
Finished Dec 20 12:31:39 PM PST 23
Peak memory 198188 kb
Host smart-6bf01f34-e3c5-4c8c-becb-a1b8e90827ab
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1048805966 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_smoke_no_pullup_pulldown.1048805966
Directory /workspace/47.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/47.gpio_stress_all.4197611733
Short name T811
Test name
Test status
Simulation time 17642806440 ps
CPU time 110.15 seconds
Started Dec 20 12:30:56 PM PST 23
Finished Dec 20 12:33:27 PM PST 23
Peak memory 198244 kb
Host smart-16b82255-d3f9-4d1c-be7a-8a3c0f69d2ec
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4197611733 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.
gpio_stress_all.4197611733
Directory /workspace/47.gpio_stress_all/latest

Test location /workspace/coverage/default/47.gpio_stress_all_with_rand_reset.1619973261
Short name T289
Test name
Test status
Simulation time 247515285005 ps
CPU time 997.91 seconds
Started Dec 20 12:30:49 PM PST 23
Finished Dec 20 12:48:07 PM PST 23
Peak memory 206620 kb
Host smart-c2142f73-0228-40c0-b0fb-8d74c3f31278
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=1619973261 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_stress_all_with_rand_reset.1619973261
Directory /workspace/47.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/48.gpio_alert_test.2911549499
Short name T722
Test name
Test status
Simulation time 13645534 ps
CPU time 0.56 seconds
Started Dec 20 12:31:10 PM PST 23
Finished Dec 20 12:32:00 PM PST 23
Peak memory 194800 kb
Host smart-901637c5-ccf4-45b9-8a28-ad994e09553d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2911549499 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_alert_test.2911549499
Directory /workspace/48.gpio_alert_test/latest

Test location /workspace/coverage/default/48.gpio_dout_din_regs_random_rw.291233500
Short name T366
Test name
Test status
Simulation time 24944164 ps
CPU time 0.68 seconds
Started Dec 20 12:30:37 PM PST 23
Finished Dec 20 12:31:17 PM PST 23
Peak memory 194344 kb
Host smart-fafa9096-4610-49a5-91a2-5ffadde6b683
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=291233500 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_dout_din_regs_random_rw.291233500
Directory /workspace/48.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/48.gpio_filter_stress.2220279701
Short name T628
Test name
Test status
Simulation time 4650787418 ps
CPU time 26.18 seconds
Started Dec 20 12:30:52 PM PST 23
Finished Dec 20 12:31:57 PM PST 23
Peak memory 197188 kb
Host smart-16245264-e367-4734-888a-d06ca0bd84a5
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2220279701 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_filter_stre
ss.2220279701
Directory /workspace/48.gpio_filter_stress/latest

Test location /workspace/coverage/default/48.gpio_full_random.2169552595
Short name T784
Test name
Test status
Simulation time 102526431 ps
CPU time 0.87 seconds
Started Dec 20 12:30:37 PM PST 23
Finished Dec 20 12:31:16 PM PST 23
Peak memory 195916 kb
Host smart-52cbf6f6-b14f-47d0-a15b-ee9bc94de996
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2169552595 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_full_random.2169552595
Directory /workspace/48.gpio_full_random/latest

Test location /workspace/coverage/default/48.gpio_intr_rand_pgm.183539869
Short name T765
Test name
Test status
Simulation time 198395299 ps
CPU time 0.71 seconds
Started Dec 20 12:30:43 PM PST 23
Finished Dec 20 12:31:19 PM PST 23
Peak memory 194536 kb
Host smart-60e6056f-cdad-4c9e-9a33-53435575ff74
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=183539869 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_intr_rand_pgm.183539869
Directory /workspace/48.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/48.gpio_intr_with_filter_rand_intr_event.425012091
Short name T309
Test name
Test status
Simulation time 70906188 ps
CPU time 2.78 seconds
Started Dec 20 12:30:54 PM PST 23
Finished Dec 20 12:31:36 PM PST 23
Peak memory 196584 kb
Host smart-e2cfed5e-3a61-4a3c-aa03-0e411573ace6
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=425012091 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 48.gpio_intr_with_filter_rand_intr_event.425012091
Directory /workspace/48.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/48.gpio_rand_intr_trigger.1156216309
Short name T63
Test name
Test status
Simulation time 122438147 ps
CPU time 2.29 seconds
Started Dec 20 12:30:46 PM PST 23
Finished Dec 20 12:31:25 PM PST 23
Peak memory 197364 kb
Host smart-f75c472d-1039-44ba-b577-8f63e9f38e5d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1156216309 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_rand_intr_trigger
.1156216309
Directory /workspace/48.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/48.gpio_random_dout_din.2076009405
Short name T310
Test name
Test status
Simulation time 62123610 ps
CPU time 0.71 seconds
Started Dec 20 12:30:38 PM PST 23
Finished Dec 20 12:31:20 PM PST 23
Peak memory 195588 kb
Host smart-ba27345e-67b7-4296-b9fd-44b3df30f977
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2076009405 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_random_dout_din.2076009405
Directory /workspace/48.gpio_random_dout_din/latest

Test location /workspace/coverage/default/48.gpio_random_dout_din_no_pullup_pulldown.3399769329
Short name T669
Test name
Test status
Simulation time 100114940 ps
CPU time 0.76 seconds
Started Dec 20 12:31:09 PM PST 23
Finished Dec 20 12:31:59 PM PST 23
Peak memory 196320 kb
Host smart-4a2d75f4-92f3-41fd-9307-a40f29da542e
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3399769329 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_random_dout_din_no_pullu
p_pulldown.3399769329
Directory /workspace/48.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/48.gpio_random_long_reg_writes_reg_reads.3606563130
Short name T649
Test name
Test status
Simulation time 442277432 ps
CPU time 5.83 seconds
Started Dec 20 12:30:51 PM PST 23
Finished Dec 20 12:31:35 PM PST 23
Peak memory 198120 kb
Host smart-66345ad1-c978-4ffe-b41c-da233d4ead73
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3606563130 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_ra
ndom_long_reg_writes_reg_reads.3606563130
Directory /workspace/48.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/48.gpio_smoke.1484893683
Short name T232
Test name
Test status
Simulation time 40555790 ps
CPU time 1.1 seconds
Started Dec 20 12:30:41 PM PST 23
Finished Dec 20 12:31:17 PM PST 23
Peak memory 195904 kb
Host smart-45f09334-99ce-45f6-a1c3-356cd2b26930
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1484893683 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_smoke.1484893683
Directory /workspace/48.gpio_smoke/latest

Test location /workspace/coverage/default/48.gpio_smoke_no_pullup_pulldown.4261036504
Short name T344
Test name
Test status
Simulation time 51171561 ps
CPU time 0.88 seconds
Started Dec 20 12:31:04 PM PST 23
Finished Dec 20 12:31:51 PM PST 23
Peak memory 196048 kb
Host smart-8c61febc-099a-420b-9efd-908351311028
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4261036504 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_smoke_no_pullup_pulldown.4261036504
Directory /workspace/48.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/48.gpio_stress_all.474459400
Short name T584
Test name
Test status
Simulation time 15334526019 ps
CPU time 154.93 seconds
Started Dec 20 12:30:56 PM PST 23
Finished Dec 20 12:34:12 PM PST 23
Peak memory 198296 kb
Host smart-0b7f1857-8c51-43d4-9789-3c37a862937c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=474459400 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.g
pio_stress_all.474459400
Directory /workspace/48.gpio_stress_all/latest

Test location /workspace/coverage/default/48.gpio_stress_all_with_rand_reset.1309540681
Short name T693
Test name
Test status
Simulation time 297945476439 ps
CPU time 1918.82 seconds
Started Dec 20 12:30:28 PM PST 23
Finished Dec 20 01:03:24 PM PST 23
Peak memory 198388 kb
Host smart-e427b5c4-486b-47bb-96dd-ebc5f1f88b4e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=1309540681 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_stress_all_with_rand_reset.1309540681
Directory /workspace/48.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/49.gpio_alert_test.3868728852
Short name T563
Test name
Test status
Simulation time 10963684 ps
CPU time 0.54 seconds
Started Dec 20 12:30:38 PM PST 23
Finished Dec 20 12:31:16 PM PST 23
Peak memory 193936 kb
Host smart-dde190c9-838e-475b-8858-dcee92a85009
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3868728852 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_alert_test.3868728852
Directory /workspace/49.gpio_alert_test/latest

Test location /workspace/coverage/default/49.gpio_dout_din_regs_random_rw.2604586607
Short name T576
Test name
Test status
Simulation time 38386282 ps
CPU time 0.66 seconds
Started Dec 20 12:30:59 PM PST 23
Finished Dec 20 12:31:43 PM PST 23
Peak memory 194104 kb
Host smart-17c8d640-ba60-4bc9-b39b-8744f3e1f7ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2604586607 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_dout_din_regs_random_rw.2604586607
Directory /workspace/49.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/49.gpio_filter_stress.3328609292
Short name T801
Test name
Test status
Simulation time 932139560 ps
CPU time 21.67 seconds
Started Dec 20 12:30:31 PM PST 23
Finished Dec 20 12:31:48 PM PST 23
Peak memory 197112 kb
Host smart-790ad6db-3234-479b-8250-213e1089a13a
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3328609292 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_filter_stre
ss.3328609292
Directory /workspace/49.gpio_filter_stress/latest

Test location /workspace/coverage/default/49.gpio_full_random.1088049530
Short name T504
Test name
Test status
Simulation time 276427520 ps
CPU time 1.02 seconds
Started Dec 20 12:30:37 PM PST 23
Finished Dec 20 12:31:16 PM PST 23
Peak memory 196644 kb
Host smart-19568ac0-0190-4053-94dd-44ab872bc637
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1088049530 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_full_random.1088049530
Directory /workspace/49.gpio_full_random/latest

Test location /workspace/coverage/default/49.gpio_intr_rand_pgm.1716473736
Short name T364
Test name
Test status
Simulation time 364976595 ps
CPU time 1.42 seconds
Started Dec 20 12:30:54 PM PST 23
Finished Dec 20 12:31:35 PM PST 23
Peak memory 198296 kb
Host smart-b9e87ac6-ce75-412f-9852-81448a4fe088
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1716473736 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_intr_rand_pgm.1716473736
Directory /workspace/49.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/49.gpio_intr_with_filter_rand_intr_event.800896013
Short name T826
Test name
Test status
Simulation time 353987429 ps
CPU time 2.84 seconds
Started Dec 20 12:31:00 PM PST 23
Finished Dec 20 12:31:47 PM PST 23
Peak memory 198312 kb
Host smart-50ccbe09-d134-407c-bc3b-ed4910ce494b
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=800896013 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 49.gpio_intr_with_filter_rand_intr_event.800896013
Directory /workspace/49.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/49.gpio_rand_intr_trigger.4080807069
Short name T698
Test name
Test status
Simulation time 68606250 ps
CPU time 1.77 seconds
Started Dec 20 12:30:57 PM PST 23
Finished Dec 20 12:31:39 PM PST 23
Peak memory 197016 kb
Host smart-0270f5b5-c2c7-482e-97a6-cb0f689c3d52
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4080807069 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_rand_intr_trigger
.4080807069
Directory /workspace/49.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/49.gpio_random_dout_din.3088197561
Short name T654
Test name
Test status
Simulation time 52844836 ps
CPU time 1.07 seconds
Started Dec 20 12:30:49 PM PST 23
Finished Dec 20 12:31:27 PM PST 23
Peak memory 195996 kb
Host smart-3ddc4351-8535-412d-a643-881b6daf1b3a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3088197561 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_random_dout_din.3088197561
Directory /workspace/49.gpio_random_dout_din/latest

Test location /workspace/coverage/default/49.gpio_random_dout_din_no_pullup_pulldown.3357694675
Short name T234
Test name
Test status
Simulation time 57643459 ps
CPU time 0.68 seconds
Started Dec 20 12:31:18 PM PST 23
Finished Dec 20 12:32:10 PM PST 23
Peak memory 195504 kb
Host smart-3f15a0a7-279a-432a-a5ff-b3dbd73159f1
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3357694675 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_random_dout_din_no_pullu
p_pulldown.3357694675
Directory /workspace/49.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/49.gpio_random_long_reg_writes_reg_reads.2411856816
Short name T823
Test name
Test status
Simulation time 478183236 ps
CPU time 4.67 seconds
Started Dec 20 12:30:41 PM PST 23
Finished Dec 20 12:31:29 PM PST 23
Peak memory 198000 kb
Host smart-8f3657dd-ce5f-41fb-a3dd-5161059dbd3f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2411856816 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_ra
ndom_long_reg_writes_reg_reads.2411856816
Directory /workspace/49.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/49.gpio_smoke.638447874
Short name T213
Test name
Test status
Simulation time 71851146 ps
CPU time 1.4 seconds
Started Dec 20 12:31:00 PM PST 23
Finished Dec 20 12:31:45 PM PST 23
Peak memory 197008 kb
Host smart-c4cbbac9-1510-4225-9a0a-10a0cc134ac8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=638447874 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_smoke.638447874
Directory /workspace/49.gpio_smoke/latest

Test location /workspace/coverage/default/49.gpio_smoke_no_pullup_pulldown.3440891699
Short name T781
Test name
Test status
Simulation time 618234777 ps
CPU time 1.13 seconds
Started Dec 20 12:30:44 PM PST 23
Finished Dec 20 12:31:23 PM PST 23
Peak memory 195896 kb
Host smart-ed6b1f4a-c7cb-4876-a3aa-f854f10cae37
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3440891699 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_smoke_no_pullup_pulldown.3440891699
Directory /workspace/49.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/49.gpio_stress_all.2286282638
Short name T771
Test name
Test status
Simulation time 65951183167 ps
CPU time 142.23 seconds
Started Dec 20 12:30:40 PM PST 23
Finished Dec 20 12:33:38 PM PST 23
Peak memory 198176 kb
Host smart-d423794f-16f2-4de7-b626-8b71c1bc94ce
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2286282638 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.
gpio_stress_all.2286282638
Directory /workspace/49.gpio_stress_all/latest

Test location /workspace/coverage/default/49.gpio_stress_all_with_rand_reset.1933247878
Short name T491
Test name
Test status
Simulation time 340854669577 ps
CPU time 1389.3 seconds
Started Dec 20 12:31:02 PM PST 23
Finished Dec 20 12:54:56 PM PST 23
Peak memory 198448 kb
Host smart-6b30861f-3185-45d3-887c-3ba85a7e8b7a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=1933247878 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_stress_all_with_rand_reset.1933247878
Directory /workspace/49.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/5.gpio_alert_test.4158052327
Short name T715
Test name
Test status
Simulation time 14850224 ps
CPU time 0.57 seconds
Started Dec 20 12:29:04 PM PST 23
Finished Dec 20 12:29:35 PM PST 23
Peak memory 194272 kb
Host smart-24e21d6a-b489-4518-b5dc-f3dfe4c7ebde
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4158052327 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_alert_test.4158052327
Directory /workspace/5.gpio_alert_test/latest

Test location /workspace/coverage/default/5.gpio_dout_din_regs_random_rw.695864320
Short name T222
Test name
Test status
Simulation time 14558765 ps
CPU time 0.6 seconds
Started Dec 20 12:28:36 PM PST 23
Finished Dec 20 12:29:08 PM PST 23
Peak memory 194056 kb
Host smart-06c53757-d530-4ff7-8b77-00f67b366252
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=695864320 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_dout_din_regs_random_rw.695864320
Directory /workspace/5.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/5.gpio_filter_stress.91931943
Short name T471
Test name
Test status
Simulation time 819841145 ps
CPU time 8.42 seconds
Started Dec 20 12:28:36 PM PST 23
Finished Dec 20 12:29:16 PM PST 23
Peak memory 198088 kb
Host smart-03b9b708-7be9-4b33-b617-6862b909fbf2
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=91931943 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter_
stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_filter_stress.91931943
Directory /workspace/5.gpio_filter_stress/latest

Test location /workspace/coverage/default/5.gpio_full_random.1201357332
Short name T95
Test name
Test status
Simulation time 47902636 ps
CPU time 0.86 seconds
Started Dec 20 12:28:44 PM PST 23
Finished Dec 20 12:29:17 PM PST 23
Peak memory 197924 kb
Host smart-4cb2645d-c2e1-4b91-9060-f33b788caf5a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1201357332 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_full_random.1201357332
Directory /workspace/5.gpio_full_random/latest

Test location /workspace/coverage/default/5.gpio_intr_rand_pgm.2310972676
Short name T354
Test name
Test status
Simulation time 271563486 ps
CPU time 1.32 seconds
Started Dec 20 12:28:48 PM PST 23
Finished Dec 20 12:29:23 PM PST 23
Peak memory 197252 kb
Host smart-47fe755c-d109-4876-ab54-f720b07b67e8
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2310972676 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_intr_rand_pgm.2310972676
Directory /workspace/5.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/5.gpio_rand_intr_trigger.423783856
Short name T318
Test name
Test status
Simulation time 425432873 ps
CPU time 2.07 seconds
Started Dec 20 12:29:05 PM PST 23
Finished Dec 20 12:29:38 PM PST 23
Peak memory 196372 kb
Host smart-a2eeffb8-372e-48bb-9d14-1737b65c8a58
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=423783856 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_rand_intr_trigger.423783856
Directory /workspace/5.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/5.gpio_random_dout_din.933214770
Short name T400
Test name
Test status
Simulation time 33042230 ps
CPU time 1.23 seconds
Started Dec 20 12:28:35 PM PST 23
Finished Dec 20 12:29:08 PM PST 23
Peak memory 198224 kb
Host smart-3e873abf-4f2b-4f02-9d16-cacbc1364cf3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=933214770 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_random_dout_din.933214770
Directory /workspace/5.gpio_random_dout_din/latest

Test location /workspace/coverage/default/5.gpio_random_dout_din_no_pullup_pulldown.1033979586
Short name T442
Test name
Test status
Simulation time 83957595 ps
CPU time 1.03 seconds
Started Dec 20 12:28:32 PM PST 23
Finished Dec 20 12:29:06 PM PST 23
Peak memory 196200 kb
Host smart-15d525ea-8373-46b4-b104-376ab67b089d
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1033979586 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_random_dout_din_no_pullup
_pulldown.1033979586
Directory /workspace/5.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/5.gpio_random_long_reg_writes_reg_reads.3646900152
Short name T550
Test name
Test status
Simulation time 75328726 ps
CPU time 3.12 seconds
Started Dec 20 12:28:33 PM PST 23
Finished Dec 20 12:29:09 PM PST 23
Peak memory 198152 kb
Host smart-632b52c7-b443-4938-bc55-586c52466f62
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3646900152 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_ran
dom_long_reg_writes_reg_reads.3646900152
Directory /workspace/5.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/5.gpio_smoke.3314622824
Short name T215
Test name
Test status
Simulation time 145018043 ps
CPU time 1 seconds
Started Dec 20 12:28:47 PM PST 23
Finished Dec 20 12:29:21 PM PST 23
Peak memory 196540 kb
Host smart-42680fcf-f0f4-4421-9a09-01a787534dff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3314622824 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_smoke.3314622824
Directory /workspace/5.gpio_smoke/latest

Test location /workspace/coverage/default/5.gpio_smoke_no_pullup_pulldown.3432538684
Short name T587
Test name
Test status
Simulation time 170646586 ps
CPU time 0.97 seconds
Started Dec 20 12:28:38 PM PST 23
Finished Dec 20 12:29:10 PM PST 23
Peak memory 196700 kb
Host smart-78b533f2-7867-44f1-bce0-2b95e990db23
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3432538684 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_smoke_no_pullup_pulldown.3432538684
Directory /workspace/5.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/5.gpio_stress_all.3471046779
Short name T218
Test name
Test status
Simulation time 13606633060 ps
CPU time 188.72 seconds
Started Dec 20 12:28:37 PM PST 23
Finished Dec 20 12:32:18 PM PST 23
Peak memory 198364 kb
Host smart-a75b9844-9dc1-4618-842f-9eea7ce4791a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3471046779 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.g
pio_stress_all.3471046779
Directory /workspace/5.gpio_stress_all/latest

Test location /workspace/coverage/default/5.gpio_stress_all_with_rand_reset.2133321322
Short name T612
Test name
Test status
Simulation time 54618398934 ps
CPU time 183.54 seconds
Started Dec 20 12:28:43 PM PST 23
Finished Dec 20 12:32:19 PM PST 23
Peak memory 198416 kb
Host smart-d8398234-010f-4743-80b6-225ec467ab06
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=2133321322 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_stress_all_with_rand_reset.2133321322
Directory /workspace/5.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/6.gpio_alert_test.2611229655
Short name T266
Test name
Test status
Simulation time 37900713 ps
CPU time 0.55 seconds
Started Dec 20 12:28:40 PM PST 23
Finished Dec 20 12:29:12 PM PST 23
Peak memory 194680 kb
Host smart-96664a05-0a94-4958-b825-8cea0199749e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2611229655 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_alert_test.2611229655
Directory /workspace/6.gpio_alert_test/latest

Test location /workspace/coverage/default/6.gpio_dout_din_regs_random_rw.713399883
Short name T743
Test name
Test status
Simulation time 45631889 ps
CPU time 0.84 seconds
Started Dec 20 12:28:36 PM PST 23
Finished Dec 20 12:29:08 PM PST 23
Peak memory 195392 kb
Host smart-7587abd2-edd7-487b-abd2-2eac9b915b08
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=713399883 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_dout_din_regs_random_rw.713399883
Directory /workspace/6.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/6.gpio_filter_stress.3418210352
Short name T307
Test name
Test status
Simulation time 430411740 ps
CPU time 15.53 seconds
Started Dec 20 12:28:40 PM PST 23
Finished Dec 20 12:29:27 PM PST 23
Peak memory 197264 kb
Host smart-f10815d3-0c5d-439d-b15f-c4bed4319481
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3418210352 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_filter_stres
s.3418210352
Directory /workspace/6.gpio_filter_stress/latest

Test location /workspace/coverage/default/6.gpio_full_random.1140850081
Short name T509
Test name
Test status
Simulation time 491765389 ps
CPU time 0.84 seconds
Started Dec 20 12:28:50 PM PST 23
Finished Dec 20 12:29:25 PM PST 23
Peak memory 196856 kb
Host smart-f8d1f81d-bdb9-457e-995e-4a4f2d1ed604
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1140850081 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_full_random.1140850081
Directory /workspace/6.gpio_full_random/latest

Test location /workspace/coverage/default/6.gpio_intr_rand_pgm.1997916722
Short name T565
Test name
Test status
Simulation time 33788340 ps
CPU time 0.76 seconds
Started Dec 20 12:28:42 PM PST 23
Finished Dec 20 12:29:15 PM PST 23
Peak memory 195572 kb
Host smart-fec86949-d2d7-4ec4-b7b3-f8d2bc5a3736
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1997916722 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_intr_rand_pgm.1997916722
Directory /workspace/6.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/6.gpio_intr_with_filter_rand_intr_event.178246214
Short name T308
Test name
Test status
Simulation time 665056327 ps
CPU time 2.03 seconds
Started Dec 20 12:28:43 PM PST 23
Finished Dec 20 12:29:18 PM PST 23
Peak memory 198036 kb
Host smart-0910658d-7c8d-46b5-a98b-d044ced92bda
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=178246214 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 6.gpio_intr_with_filter_rand_intr_event.178246214
Directory /workspace/6.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/6.gpio_rand_intr_trigger.2972762326
Short name T245
Test name
Test status
Simulation time 162445116 ps
CPU time 1.14 seconds
Started Dec 20 12:28:39 PM PST 23
Finished Dec 20 12:29:12 PM PST 23
Peak memory 196900 kb
Host smart-af1fd690-8a23-47f9-99d3-0c4530cc1108
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2972762326 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_rand_intr_trigger.
2972762326
Directory /workspace/6.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/6.gpio_random_dout_din.243627914
Short name T843
Test name
Test status
Simulation time 28773129 ps
CPU time 0.74 seconds
Started Dec 20 12:28:41 PM PST 23
Finished Dec 20 12:29:14 PM PST 23
Peak memory 195200 kb
Host smart-d4692dd7-accd-4e28-99b0-7df761cca51a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=243627914 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_random_dout_din.243627914
Directory /workspace/6.gpio_random_dout_din/latest

Test location /workspace/coverage/default/6.gpio_random_dout_din_no_pullup_pulldown.391954294
Short name T829
Test name
Test status
Simulation time 429125526 ps
CPU time 0.97 seconds
Started Dec 20 12:28:29 PM PST 23
Finished Dec 20 12:29:03 PM PST 23
Peak memory 196024 kb
Host smart-188bd69b-df60-4afb-979e-b54bf94867f9
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=391954294 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_random_dout_din_no_pullup_
pulldown.391954294
Directory /workspace/6.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/6.gpio_random_long_reg_writes_reg_reads.613948967
Short name T570
Test name
Test status
Simulation time 128326078 ps
CPU time 2.26 seconds
Started Dec 20 12:28:44 PM PST 23
Finished Dec 20 12:29:19 PM PST 23
Peak memory 197956 kb
Host smart-7ff4bd1c-bbfc-4c32-8670-66d9ddc96fe7
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=613948967 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_rand
om_long_reg_writes_reg_reads.613948967
Directory /workspace/6.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/6.gpio_smoke.822763159
Short name T555
Test name
Test status
Simulation time 101537760 ps
CPU time 0.77 seconds
Started Dec 20 12:28:28 PM PST 23
Finished Dec 20 12:29:02 PM PST 23
Peak memory 195256 kb
Host smart-5395c1e7-51e2-48d0-9163-b2c16e1ad7f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=822763159 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_smoke.822763159
Directory /workspace/6.gpio_smoke/latest

Test location /workspace/coverage/default/6.gpio_smoke_no_pullup_pulldown.1250225772
Short name T429
Test name
Test status
Simulation time 50919011 ps
CPU time 1.01 seconds
Started Dec 20 12:28:44 PM PST 23
Finished Dec 20 12:29:17 PM PST 23
Peak memory 195784 kb
Host smart-13cd39f4-2c51-4cc0-b96a-63ff7ddc69b5
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1250225772 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_smoke_no_pullup_pulldown.1250225772
Directory /workspace/6.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/6.gpio_stress_all.435550977
Short name T541
Test name
Test status
Simulation time 19550249656 ps
CPU time 96.33 seconds
Started Dec 20 12:28:41 PM PST 23
Finished Dec 20 12:30:50 PM PST 23
Peak memory 198252 kb
Host smart-f3f1ed30-02e5-4ad2-8556-2a057fb3d760
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=435550977 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gp
io_stress_all.435550977
Directory /workspace/6.gpio_stress_all/latest

Test location /workspace/coverage/default/6.gpio_stress_all_with_rand_reset.2653905093
Short name T476
Test name
Test status
Simulation time 60667230425 ps
CPU time 260.45 seconds
Started Dec 20 12:28:35 PM PST 23
Finished Dec 20 12:33:27 PM PST 23
Peak memory 198448 kb
Host smart-e0dc6f93-b414-4f96-bf12-9f7e724c4d57
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=2653905093 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_stress_all_with_rand_reset.2653905093
Directory /workspace/6.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/7.gpio_alert_test.3021751277
Short name T51
Test name
Test status
Simulation time 117274222 ps
CPU time 0.57 seconds
Started Dec 20 12:29:08 PM PST 23
Finished Dec 20 12:29:40 PM PST 23
Peak memory 194356 kb
Host smart-dfc7c247-477a-44ca-837e-c6005738901b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3021751277 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_alert_test.3021751277
Directory /workspace/7.gpio_alert_test/latest

Test location /workspace/coverage/default/7.gpio_dout_din_regs_random_rw.3605826500
Short name T711
Test name
Test status
Simulation time 34766983 ps
CPU time 0.74 seconds
Started Dec 20 12:28:54 PM PST 23
Finished Dec 20 12:29:29 PM PST 23
Peak memory 195272 kb
Host smart-b4c6d5fe-988d-4e36-b469-fdb3458cea9e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3605826500 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_dout_din_regs_random_rw.3605826500
Directory /workspace/7.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/7.gpio_filter_stress.3288052412
Short name T744
Test name
Test status
Simulation time 349421818 ps
CPU time 13.4 seconds
Started Dec 20 12:28:56 PM PST 23
Finished Dec 20 12:29:43 PM PST 23
Peak memory 197148 kb
Host smart-dea7cd4b-fb5d-4572-b9dd-cf082075af90
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3288052412 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_filter_stres
s.3288052412
Directory /workspace/7.gpio_filter_stress/latest

Test location /workspace/coverage/default/7.gpio_full_random.907692660
Short name T703
Test name
Test status
Simulation time 129113676 ps
CPU time 0.92 seconds
Started Dec 20 12:28:50 PM PST 23
Finished Dec 20 12:29:25 PM PST 23
Peak memory 197676 kb
Host smart-671dd408-82f8-4069-8c8c-1dc61b4bebcd
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=907692660 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_full_random.907692660
Directory /workspace/7.gpio_full_random/latest

Test location /workspace/coverage/default/7.gpio_intr_rand_pgm.1906521084
Short name T244
Test name
Test status
Simulation time 34670199 ps
CPU time 0.78 seconds
Started Dec 20 12:28:48 PM PST 23
Finished Dec 20 12:29:22 PM PST 23
Peak memory 196372 kb
Host smart-9bf8ffed-8046-460c-9441-27afa2eef8f4
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1906521084 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_intr_rand_pgm.1906521084
Directory /workspace/7.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/7.gpio_intr_with_filter_rand_intr_event.3193229289
Short name T249
Test name
Test status
Simulation time 136738458 ps
CPU time 2.64 seconds
Started Dec 20 12:28:35 PM PST 23
Finished Dec 20 12:29:09 PM PST 23
Peak memory 196496 kb
Host smart-13240dff-8600-4276-9354-71dd369df75d
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3193229289 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 7.gpio_intr_with_filter_rand_intr_event.3193229289
Directory /workspace/7.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/7.gpio_rand_intr_trigger.679942572
Short name T199
Test name
Test status
Simulation time 263735963 ps
CPU time 2.27 seconds
Started Dec 20 12:28:51 PM PST 23
Finished Dec 20 12:29:27 PM PST 23
Peak memory 197340 kb
Host smart-3403d60b-5767-4a5e-838b-13fa24678bc5
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=679942572 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_rand_intr_trigger.679942572
Directory /workspace/7.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/7.gpio_random_dout_din.3914674190
Short name T336
Test name
Test status
Simulation time 18486604 ps
CPU time 0.67 seconds
Started Dec 20 12:28:41 PM PST 23
Finished Dec 20 12:29:14 PM PST 23
Peak memory 194456 kb
Host smart-2b1a5821-a1b5-4041-b9c1-e2e86b9019ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3914674190 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_random_dout_din.3914674190
Directory /workspace/7.gpio_random_dout_din/latest

Test location /workspace/coverage/default/7.gpio_random_dout_din_no_pullup_pulldown.1727167060
Short name T292
Test name
Test status
Simulation time 70745860 ps
CPU time 0.79 seconds
Started Dec 20 12:28:36 PM PST 23
Finished Dec 20 12:29:08 PM PST 23
Peak memory 196788 kb
Host smart-a1bf92ed-09c7-4810-8ce7-5e4c04bc595a
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1727167060 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_random_dout_din_no_pullup
_pulldown.1727167060
Directory /workspace/7.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/7.gpio_random_long_reg_writes_reg_reads.4138127230
Short name T271
Test name
Test status
Simulation time 93828376 ps
CPU time 3.9 seconds
Started Dec 20 12:28:46 PM PST 23
Finished Dec 20 12:29:23 PM PST 23
Peak memory 198152 kb
Host smart-3dc09cdc-0eeb-4f7f-9916-384eca8449ff
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4138127230 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_ran
dom_long_reg_writes_reg_reads.4138127230
Directory /workspace/7.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/7.gpio_smoke.337011125
Short name T435
Test name
Test status
Simulation time 159770998 ps
CPU time 1.06 seconds
Started Dec 20 12:28:38 PM PST 23
Finished Dec 20 12:29:10 PM PST 23
Peak memory 195608 kb
Host smart-233c4a16-ff08-427b-81cd-e897da8d13de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=337011125 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_smoke.337011125
Directory /workspace/7.gpio_smoke/latest

Test location /workspace/coverage/default/7.gpio_smoke_no_pullup_pulldown.3795437783
Short name T254
Test name
Test status
Simulation time 310061356 ps
CPU time 1.32 seconds
Started Dec 20 12:28:36 PM PST 23
Finished Dec 20 12:29:09 PM PST 23
Peak memory 196952 kb
Host smart-ff99ded0-abc0-48a1-b2d0-4016cffb7765
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3795437783 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_smoke_no_pullup_pulldown.3795437783
Directory /workspace/7.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/7.gpio_stress_all.2159118697
Short name T798
Test name
Test status
Simulation time 6258144429 ps
CPU time 156.09 seconds
Started Dec 20 12:28:49 PM PST 23
Finished Dec 20 12:31:59 PM PST 23
Peak memory 198180 kb
Host smart-9c5d74d0-f586-49b1-aa6c-059caaac6323
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2159118697 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.g
pio_stress_all.2159118697
Directory /workspace/7.gpio_stress_all/latest

Test location /workspace/coverage/default/7.gpio_stress_all_with_rand_reset.3277499525
Short name T69
Test name
Test status
Simulation time 204090194457 ps
CPU time 554.17 seconds
Started Dec 20 12:28:49 PM PST 23
Finished Dec 20 12:38:38 PM PST 23
Peak memory 198512 kb
Host smart-85cdead1-b595-49b3-ba4c-aac6cafc2902
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=3277499525 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_stress_all_with_rand_reset.3277499525
Directory /workspace/7.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/8.gpio_alert_test.72485925
Short name T372
Test name
Test status
Simulation time 74304584 ps
CPU time 0.56 seconds
Started Dec 20 12:29:24 PM PST 23
Finished Dec 20 12:29:47 PM PST 23
Peak memory 194316 kb
Host smart-3caa0d12-bb6d-48e1-958c-051742592c13
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=72485925 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_alert_test.72485925
Directory /workspace/8.gpio_alert_test/latest

Test location /workspace/coverage/default/8.gpio_dout_din_regs_random_rw.1034143700
Short name T273
Test name
Test status
Simulation time 27530748 ps
CPU time 0.83 seconds
Started Dec 20 12:29:05 PM PST 23
Finished Dec 20 12:29:36 PM PST 23
Peak memory 196548 kb
Host smart-04379089-87c2-435c-b104-597ca69865f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1034143700 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_dout_din_regs_random_rw.1034143700
Directory /workspace/8.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/8.gpio_filter_stress.3153176532
Short name T343
Test name
Test status
Simulation time 281343640 ps
CPU time 14.86 seconds
Started Dec 20 12:28:45 PM PST 23
Finished Dec 20 12:29:32 PM PST 23
Peak memory 196692 kb
Host smart-c37a8aa8-77b2-436b-ad53-7705a4456765
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3153176532 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_filter_stres
s.3153176532
Directory /workspace/8.gpio_filter_stress/latest

Test location /workspace/coverage/default/8.gpio_full_random.3167812727
Short name T767
Test name
Test status
Simulation time 70879331 ps
CPU time 0.91 seconds
Started Dec 20 12:29:33 PM PST 23
Finished Dec 20 12:29:55 PM PST 23
Peak memory 196540 kb
Host smart-d5abe6af-16ee-4c85-bbbd-a13e8961da5f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3167812727 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_full_random.3167812727
Directory /workspace/8.gpio_full_random/latest

Test location /workspace/coverage/default/8.gpio_intr_rand_pgm.4022089767
Short name T401
Test name
Test status
Simulation time 62752457 ps
CPU time 0.71 seconds
Started Dec 20 12:29:03 PM PST 23
Finished Dec 20 12:29:35 PM PST 23
Peak memory 194392 kb
Host smart-5aacecd6-4b5e-4682-9050-4f9729d463e0
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4022089767 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_intr_rand_pgm.4022089767
Directory /workspace/8.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/8.gpio_intr_with_filter_rand_intr_event.1316655474
Short name T274
Test name
Test status
Simulation time 63263461 ps
CPU time 2.45 seconds
Started Dec 20 12:28:52 PM PST 23
Finished Dec 20 12:29:29 PM PST 23
Peak memory 198352 kb
Host smart-23a2f80c-84c8-410b-a7e4-109b680f1818
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1316655474 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 8.gpio_intr_with_filter_rand_intr_event.1316655474
Directory /workspace/8.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/8.gpio_rand_intr_trigger.3449008346
Short name T706
Test name
Test status
Simulation time 313810731 ps
CPU time 1.72 seconds
Started Dec 20 12:28:52 PM PST 23
Finished Dec 20 12:29:28 PM PST 23
Peak memory 196300 kb
Host smart-b3e328a8-ee11-426a-aba5-c993643aed35
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3449008346 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_rand_intr_trigger.
3449008346
Directory /workspace/8.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/8.gpio_random_dout_din.4090513202
Short name T385
Test name
Test status
Simulation time 29055712 ps
CPU time 1.11 seconds
Started Dec 20 12:29:14 PM PST 23
Finished Dec 20 12:29:41 PM PST 23
Peak memory 196960 kb
Host smart-3f150784-b393-4678-95f1-26525d9d7394
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4090513202 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_random_dout_din.4090513202
Directory /workspace/8.gpio_random_dout_din/latest

Test location /workspace/coverage/default/8.gpio_random_dout_din_no_pullup_pulldown.194388743
Short name T609
Test name
Test status
Simulation time 114379193 ps
CPU time 0.86 seconds
Started Dec 20 12:28:54 PM PST 23
Finished Dec 20 12:29:30 PM PST 23
Peak memory 196240 kb
Host smart-8cd52ee7-3344-4d26-b3c9-12e9320ff630
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=194388743 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_random_dout_din_no_pullup_
pulldown.194388743
Directory /workspace/8.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/8.gpio_random_long_reg_writes_reg_reads.2207345718
Short name T788
Test name
Test status
Simulation time 893930527 ps
CPU time 2.62 seconds
Started Dec 20 12:28:50 PM PST 23
Finished Dec 20 12:29:27 PM PST 23
Peak memory 198012 kb
Host smart-2c06e466-8cdb-4cd2-bffc-0d89c643037c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2207345718 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_ran
dom_long_reg_writes_reg_reads.2207345718
Directory /workspace/8.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/8.gpio_smoke.2399699622
Short name T727
Test name
Test status
Simulation time 68128642 ps
CPU time 1.15 seconds
Started Dec 20 12:28:45 PM PST 23
Finished Dec 20 12:29:19 PM PST 23
Peak memory 195636 kb
Host smart-3506b920-68e0-47b8-9a40-7216889d1b9c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2399699622 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_smoke.2399699622
Directory /workspace/8.gpio_smoke/latest

Test location /workspace/coverage/default/8.gpio_smoke_no_pullup_pulldown.2072955673
Short name T408
Test name
Test status
Simulation time 38486883 ps
CPU time 0.94 seconds
Started Dec 20 12:29:23 PM PST 23
Finished Dec 20 12:29:51 PM PST 23
Peak memory 195756 kb
Host smart-3ff7234c-4bed-421c-9d22-d78c03d5d48f
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2072955673 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_smoke_no_pullup_pulldown.2072955673
Directory /workspace/8.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/8.gpio_stress_all.1778090200
Short name T799
Test name
Test status
Simulation time 3989613089 ps
CPU time 55.13 seconds
Started Dec 20 12:29:40 PM PST 23
Finished Dec 20 12:30:54 PM PST 23
Peak memory 198292 kb
Host smart-95c0a438-fb92-4cb0-a50d-fad09a4397c4
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1778090200 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.g
pio_stress_all.1778090200
Directory /workspace/8.gpio_stress_all/latest

Test location /workspace/coverage/default/8.gpio_stress_all_with_rand_reset.3715247406
Short name T792
Test name
Test status
Simulation time 174828792959 ps
CPU time 1047.93 seconds
Started Dec 20 12:28:50 PM PST 23
Finished Dec 20 12:46:52 PM PST 23
Peak memory 198336 kb
Host smart-5a7ce88b-fbf0-4bf6-8812-e050ea0bbbed
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=3715247406 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_stress_all_with_rand_reset.3715247406
Directory /workspace/8.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/9.gpio_alert_test.3101700389
Short name T621
Test name
Test status
Simulation time 12441568 ps
CPU time 0.55 seconds
Started Dec 20 12:29:22 PM PST 23
Finished Dec 20 12:29:46 PM PST 23
Peak memory 194112 kb
Host smart-7571eddb-969f-49c7-b77e-99cf85b81cf2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3101700389 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_alert_test.3101700389
Directory /workspace/9.gpio_alert_test/latest

Test location /workspace/coverage/default/9.gpio_dout_din_regs_random_rw.572274596
Short name T684
Test name
Test status
Simulation time 44331180 ps
CPU time 0.72 seconds
Started Dec 20 12:29:17 PM PST 23
Finished Dec 20 12:29:43 PM PST 23
Peak memory 196136 kb
Host smart-b2a241d0-e66d-42eb-a432-9724445168ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=572274596 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_dout_din_regs_random_rw.572274596
Directory /workspace/9.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/9.gpio_filter_stress.1506704025
Short name T586
Test name
Test status
Simulation time 929768156 ps
CPU time 25.69 seconds
Started Dec 20 12:29:11 PM PST 23
Finished Dec 20 12:30:04 PM PST 23
Peak memory 195736 kb
Host smart-6aabbee2-32d2-4783-8a1c-875cb3572ef1
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1506704025 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_filter_stres
s.1506704025
Directory /workspace/9.gpio_filter_stress/latest

Test location /workspace/coverage/default/9.gpio_full_random.3974485417
Short name T302
Test name
Test status
Simulation time 43267119 ps
CPU time 0.78 seconds
Started Dec 20 12:29:03 PM PST 23
Finished Dec 20 12:29:36 PM PST 23
Peak memory 195928 kb
Host smart-c4a47646-2d9b-4e95-a30c-cfbafc74c78a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3974485417 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_full_random.3974485417
Directory /workspace/9.gpio_full_random/latest

Test location /workspace/coverage/default/9.gpio_intr_rand_pgm.3601281150
Short name T533
Test name
Test status
Simulation time 28874502 ps
CPU time 0.73 seconds
Started Dec 20 12:29:05 PM PST 23
Finished Dec 20 12:29:36 PM PST 23
Peak memory 196248 kb
Host smart-ca900fed-6ae1-41ee-9ec7-06bf191bed6d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3601281150 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_intr_rand_pgm.3601281150
Directory /workspace/9.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/9.gpio_intr_with_filter_rand_intr_event.1113615498
Short name T710
Test name
Test status
Simulation time 229748616 ps
CPU time 2.33 seconds
Started Dec 20 12:28:50 PM PST 23
Finished Dec 20 12:29:27 PM PST 23
Peak memory 198304 kb
Host smart-013bc52f-34a9-4055-a0a2-aab7f8b9db5f
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1113615498 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 9.gpio_intr_with_filter_rand_intr_event.1113615498
Directory /workspace/9.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/9.gpio_rand_intr_trigger.3319266562
Short name T750
Test name
Test status
Simulation time 142587206 ps
CPU time 2.72 seconds
Started Dec 20 12:28:53 PM PST 23
Finished Dec 20 12:29:30 PM PST 23
Peak memory 197532 kb
Host smart-a61338ad-545a-4371-9875-a62966066c60
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3319266562 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_rand_intr_trigger.
3319266562
Directory /workspace/9.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/9.gpio_random_dout_din.1936854682
Short name T320
Test name
Test status
Simulation time 32406260 ps
CPU time 0.86 seconds
Started Dec 20 12:29:24 PM PST 23
Finished Dec 20 12:29:48 PM PST 23
Peak memory 197108 kb
Host smart-9ba3200b-0052-4dca-aad4-16244178787f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1936854682 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_random_dout_din.1936854682
Directory /workspace/9.gpio_random_dout_din/latest

Test location /workspace/coverage/default/9.gpio_random_dout_din_no_pullup_pulldown.3071754355
Short name T458
Test name
Test status
Simulation time 80391103 ps
CPU time 1.03 seconds
Started Dec 20 12:29:11 PM PST 23
Finished Dec 20 12:29:39 PM PST 23
Peak memory 195980 kb
Host smart-706f0e2e-a529-424d-902e-d5042b94fcd4
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3071754355 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_random_dout_din_no_pullup
_pulldown.3071754355
Directory /workspace/9.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/9.gpio_random_long_reg_writes_reg_reads.3992933062
Short name T296
Test name
Test status
Simulation time 72010529 ps
CPU time 3.11 seconds
Started Dec 20 12:28:52 PM PST 23
Finished Dec 20 12:29:29 PM PST 23
Peak memory 198032 kb
Host smart-80c513dc-c7d0-4190-b933-c4fe0970301a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3992933062 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_ran
dom_long_reg_writes_reg_reads.3992933062
Directory /workspace/9.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/9.gpio_smoke.2568119576
Short name T803
Test name
Test status
Simulation time 129704181 ps
CPU time 1.35 seconds
Started Dec 20 12:28:50 PM PST 23
Finished Dec 20 12:29:26 PM PST 23
Peak memory 198064 kb
Host smart-b48ee721-7da9-4354-8d68-c4595f379b20
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2568119576 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_smoke.2568119576
Directory /workspace/9.gpio_smoke/latest

Test location /workspace/coverage/default/9.gpio_smoke_no_pullup_pulldown.3989187389
Short name T380
Test name
Test status
Simulation time 42605986 ps
CPU time 1.12 seconds
Started Dec 20 12:29:38 PM PST 23
Finished Dec 20 12:29:59 PM PST 23
Peak memory 195728 kb
Host smart-e46b209a-9166-4bed-a831-28c952fb9b50
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3989187389 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_smoke_no_pullup_pulldown.3989187389
Directory /workspace/9.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/9.gpio_stress_all.3400839577
Short name T835
Test name
Test status
Simulation time 4688262172 ps
CPU time 123.45 seconds
Started Dec 20 12:28:54 PM PST 23
Finished Dec 20 12:31:31 PM PST 23
Peak memory 198280 kb
Host smart-f61e8a2e-ad4f-49d2-bfef-fbe209cb2eb0
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3400839577 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.g
pio_stress_all.3400839577
Directory /workspace/9.gpio_stress_all/latest

Test location /workspace/coverage/default/9.gpio_stress_all_with_rand_reset.2852680774
Short name T806
Test name
Test status
Simulation time 633136746577 ps
CPU time 898.89 seconds
Started Dec 20 12:28:52 PM PST 23
Finished Dec 20 12:44:26 PM PST 23
Peak memory 198408 kb
Host smart-a1e10b7e-c460-44cb-aa57-dc4ba1557ec3
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=2852680774 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_stress_all_with_rand_reset.2852680774
Directory /workspace/9.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/en_cdc_prims/0.gpio_smoke_en_cdc_prim.3513271346
Short name T137
Test name
Test status
Simulation time 84270792 ps
CPU time 1.19 seconds
Started Dec 20 12:20:23 PM PST 23
Finished Dec 20 12:20:27 PM PST 23
Peak memory 195392 kb
Host smart-35167bc4-71b6-4445-b26e-86cbc47a8694
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3513271346 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 0.gpio_smoke_en_cdc_prim.3513271346
Directory /workspace/0.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/0.gpio_smoke_no_pullup_pulldown_en_cdc_prim.613498946
Short name T139
Test name
Test status
Simulation time 124204044 ps
CPU time 1.24 seconds
Started Dec 20 12:20:25 PM PST 23
Finished Dec 20 12:20:31 PM PST 23
Peak memory 196064 kb
Host smart-db66c0b7-88da-4989-8c8c-caa5d0891374
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=613498946 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 0.gpio_smoke_no_pullup_pulldown_e
n_cdc_prim.613498946
Directory /workspace/0.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/1.gpio_smoke_en_cdc_prim.1284258883
Short name T173
Test name
Test status
Simulation time 64672904 ps
CPU time 0.91 seconds
Started Dec 20 12:20:24 PM PST 23
Finished Dec 20 12:20:28 PM PST 23
Peak memory 196208 kb
Host smart-bcfed44f-f867-4046-8f55-2ad7453065e1
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1284258883 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 1.gpio_smoke_en_cdc_prim.1284258883
Directory /workspace/1.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/1.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2422910532
Short name T115
Test name
Test status
Simulation time 173291377 ps
CPU time 1.15 seconds
Started Dec 20 12:20:24 PM PST 23
Finished Dec 20 12:20:30 PM PST 23
Peak memory 196296 kb
Host smart-8b684fba-5ad9-4da2-82f6-b05d8ea9fa4c
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2422910532 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 1.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.2422910532
Directory /workspace/1.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/10.gpio_smoke_en_cdc_prim.1288068191
Short name T121
Test name
Test status
Simulation time 88181915 ps
CPU time 0.8 seconds
Started Dec 20 12:20:47 PM PST 23
Finished Dec 20 12:20:54 PM PST 23
Peak memory 195228 kb
Host smart-32bfda4b-5fc1-490e-a45d-7b466811c9ae
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1288068191 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 10.gpio_smoke_en_cdc_prim.1288068191
Directory /workspace/10.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/10.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2987787389
Short name T184
Test name
Test status
Simulation time 46077889 ps
CPU time 0.89 seconds
Started Dec 20 12:20:22 PM PST 23
Finished Dec 20 12:20:25 PM PST 23
Peak memory 195048 kb
Host smart-564ca718-3c6f-4faf-ae37-82a288e5608b
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2987787389 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 10.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2987787389
Directory /workspace/10.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/11.gpio_smoke_en_cdc_prim.897626837
Short name T192
Test name
Test status
Simulation time 740799026 ps
CPU time 1.19 seconds
Started Dec 20 12:20:56 PM PST 23
Finished Dec 20 12:21:03 PM PST 23
Peak memory 196588 kb
Host smart-f298ccbc-1151-40a6-b45a-9a15ede589e7
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=897626837 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 11.gpio_smoke_en_cdc_prim.897626837
Directory /workspace/11.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/11.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2170417851
Short name T191
Test name
Test status
Simulation time 267559197 ps
CPU time 0.81 seconds
Started Dec 20 12:20:38 PM PST 23
Finished Dec 20 12:20:44 PM PST 23
Peak memory 196316 kb
Host smart-0402c63e-a6d0-4b7e-9448-1c0124746603
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2170417851 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 11.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2170417851
Directory /workspace/11.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/12.gpio_smoke_en_cdc_prim.404133684
Short name T136
Test name
Test status
Simulation time 178606277 ps
CPU time 1.2 seconds
Started Dec 20 12:20:22 PM PST 23
Finished Dec 20 12:20:25 PM PST 23
Peak memory 195644 kb
Host smart-dfd12ad9-1e0b-45cd-8545-4c3a0832235b
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=404133684 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 12.gpio_smoke_en_cdc_prim.404133684
Directory /workspace/12.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/12.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3031497975
Short name T124
Test name
Test status
Simulation time 160714655 ps
CPU time 1.25 seconds
Started Dec 20 12:20:52 PM PST 23
Finished Dec 20 12:21:01 PM PST 23
Peak memory 195368 kb
Host smart-53a12c01-c1d6-46a8-8ec0-1693cb2654e8
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3031497975 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 12.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.3031497975
Directory /workspace/12.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/13.gpio_smoke_en_cdc_prim.1831278812
Short name T182
Test name
Test status
Simulation time 103717956 ps
CPU time 0.99 seconds
Started Dec 20 12:20:25 PM PST 23
Finished Dec 20 12:20:32 PM PST 23
Peak memory 196184 kb
Host smart-6b642b85-db4b-4e41-b508-e29a4cf5e58f
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1831278812 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 13.gpio_smoke_en_cdc_prim.1831278812
Directory /workspace/13.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/13.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1666332507
Short name T154
Test name
Test status
Simulation time 58671615 ps
CPU time 1.14 seconds
Started Dec 20 12:20:25 PM PST 23
Finished Dec 20 12:20:31 PM PST 23
Peak memory 196228 kb
Host smart-8af5aaf3-e158-4f2f-a19e-7e00895f0634
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1666332507 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 13.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.1666332507
Directory /workspace/13.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/14.gpio_smoke_en_cdc_prim.557941418
Short name T130
Test name
Test status
Simulation time 592503891 ps
CPU time 1.4 seconds
Started Dec 20 12:20:43 PM PST 23
Finished Dec 20 12:20:50 PM PST 23
Peak memory 197808 kb
Host smart-986fc245-9f86-40f9-998b-d8c57ed427e2
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=557941418 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 14.gpio_smoke_en_cdc_prim.557941418
Directory /workspace/14.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/14.gpio_smoke_no_pullup_pulldown_en_cdc_prim.884510148
Short name T164
Test name
Test status
Simulation time 41881455 ps
CPU time 0.93 seconds
Started Dec 20 12:20:39 PM PST 23
Finished Dec 20 12:20:45 PM PST 23
Peak memory 197728 kb
Host smart-b9c8b39e-a219-4783-b0fe-d1bde6725010
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=884510148 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 14.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.884510148
Directory /workspace/14.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/15.gpio_smoke_en_cdc_prim.4019128471
Short name T142
Test name
Test status
Simulation time 70041896 ps
CPU time 0.82 seconds
Started Dec 20 12:20:24 PM PST 23
Finished Dec 20 12:20:28 PM PST 23
Peak memory 197068 kb
Host smart-c6281b65-5377-4b18-8a05-fceb762da363
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=4019128471 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 15.gpio_smoke_en_cdc_prim.4019128471
Directory /workspace/15.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/15.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1802696961
Short name T141
Test name
Test status
Simulation time 81012608 ps
CPU time 1.2 seconds
Started Dec 20 12:20:15 PM PST 23
Finished Dec 20 12:20:18 PM PST 23
Peak memory 195620 kb
Host smart-18616e99-f11b-4cb6-b298-025846e3a81c
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1802696961 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 15.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.1802696961
Directory /workspace/15.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/16.gpio_smoke_en_cdc_prim.3813794760
Short name T166
Test name
Test status
Simulation time 141105046 ps
CPU time 0.98 seconds
Started Dec 20 12:20:20 PM PST 23
Finished Dec 20 12:20:22 PM PST 23
Peak memory 196420 kb
Host smart-42c46ef6-1c43-4e89-86f7-3fcf3b078b2e
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3813794760 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 16.gpio_smoke_en_cdc_prim.3813794760
Directory /workspace/16.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/16.gpio_smoke_no_pullup_pulldown_en_cdc_prim.4274959994
Short name T179
Test name
Test status
Simulation time 154700200 ps
CPU time 1.34 seconds
Started Dec 20 12:20:20 PM PST 23
Finished Dec 20 12:20:23 PM PST 23
Peak memory 196516 kb
Host smart-394cedad-eabc-4169-a85d-9bec8387bcf8
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4274959994 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 16.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.4274959994
Directory /workspace/16.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/17.gpio_smoke_en_cdc_prim.3282129394
Short name T150
Test name
Test status
Simulation time 406017906 ps
CPU time 1.25 seconds
Started Dec 20 12:20:24 PM PST 23
Finished Dec 20 12:20:29 PM PST 23
Peak memory 196692 kb
Host smart-3c9f64c7-f4bf-4918-816e-6a1a4288b80c
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3282129394 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 17.gpio_smoke_en_cdc_prim.3282129394
Directory /workspace/17.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/17.gpio_smoke_no_pullup_pulldown_en_cdc_prim.452499384
Short name T58
Test name
Test status
Simulation time 156430212 ps
CPU time 0.96 seconds
Started Dec 20 12:20:42 PM PST 23
Finished Dec 20 12:20:48 PM PST 23
Peak memory 196360 kb
Host smart-d6b826e7-d026-43f6-b6ed-607c815b0795
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=452499384 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 17.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.452499384
Directory /workspace/17.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/18.gpio_smoke_en_cdc_prim.1563181124
Short name T132
Test name
Test status
Simulation time 79420359 ps
CPU time 0.76 seconds
Started Dec 20 12:20:59 PM PST 23
Finished Dec 20 12:21:06 PM PST 23
Peak memory 195896 kb
Host smart-c6a02bff-0ce7-4d33-a37e-d3775e357d1a
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1563181124 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 18.gpio_smoke_en_cdc_prim.1563181124
Directory /workspace/18.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/18.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1275961395
Short name T193
Test name
Test status
Simulation time 103137271 ps
CPU time 0.8 seconds
Started Dec 20 12:21:01 PM PST 23
Finished Dec 20 12:21:10 PM PST 23
Peak memory 195320 kb
Host smart-c8f9e8e2-d9b0-40b1-9501-fe176a01e9cb
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1275961395 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 18.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.1275961395
Directory /workspace/18.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/19.gpio_smoke_en_cdc_prim.1263316196
Short name T144
Test name
Test status
Simulation time 316736817 ps
CPU time 1.46 seconds
Started Dec 20 12:21:01 PM PST 23
Finished Dec 20 12:21:11 PM PST 23
Peak memory 196488 kb
Host smart-f3161d02-f242-4be4-a89a-5e2e900efb59
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1263316196 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 19.gpio_smoke_en_cdc_prim.1263316196
Directory /workspace/19.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/19.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1686779652
Short name T183
Test name
Test status
Simulation time 802382492 ps
CPU time 1.23 seconds
Started Dec 20 12:20:50 PM PST 23
Finished Dec 20 12:20:59 PM PST 23
Peak memory 195700 kb
Host smart-ea64e2c5-77e8-4d78-acb2-d0c0204126aa
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1686779652 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 19.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.1686779652
Directory /workspace/19.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/2.gpio_smoke_en_cdc_prim.3182355704
Short name T161
Test name
Test status
Simulation time 86985181 ps
CPU time 1.05 seconds
Started Dec 20 12:20:23 PM PST 23
Finished Dec 20 12:20:27 PM PST 23
Peak memory 196292 kb
Host smart-211a7c22-394b-4e72-b763-ef5ada2ebaf2
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3182355704 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 2.gpio_smoke_en_cdc_prim.3182355704
Directory /workspace/2.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/2.gpio_smoke_no_pullup_pulldown_en_cdc_prim.657719662
Short name T52
Test name
Test status
Simulation time 85481260 ps
CPU time 0.81 seconds
Started Dec 20 12:20:56 PM PST 23
Finished Dec 20 12:21:03 PM PST 23
Peak memory 195416 kb
Host smart-0f6a0288-f40d-44f0-a08f-eb4811ac16d4
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=657719662 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 2.gpio_smoke_no_pullup_pulldown_e
n_cdc_prim.657719662
Directory /workspace/2.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/20.gpio_smoke_en_cdc_prim.1265416484
Short name T171
Test name
Test status
Simulation time 40564899 ps
CPU time 0.83 seconds
Started Dec 20 12:20:24 PM PST 23
Finished Dec 20 12:20:28 PM PST 23
Peak memory 195144 kb
Host smart-47238d75-bc38-4ff7-8334-d681fd5ff95d
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1265416484 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 20.gpio_smoke_en_cdc_prim.1265416484
Directory /workspace/20.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/20.gpio_smoke_no_pullup_pulldown_en_cdc_prim.451585438
Short name T157
Test name
Test status
Simulation time 44462596 ps
CPU time 0.85 seconds
Started Dec 20 12:20:25 PM PST 23
Finished Dec 20 12:20:31 PM PST 23
Peak memory 195032 kb
Host smart-b6c67c5e-ebed-4046-a50e-2c28917ef2de
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=451585438 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 20.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.451585438
Directory /workspace/20.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/21.gpio_smoke_en_cdc_prim.2536118843
Short name T56
Test name
Test status
Simulation time 266705910 ps
CPU time 1.17 seconds
Started Dec 20 12:20:23 PM PST 23
Finished Dec 20 12:20:27 PM PST 23
Peak memory 197692 kb
Host smart-bcfe931b-587c-4574-a34d-1382c6747d5d
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2536118843 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 21.gpio_smoke_en_cdc_prim.2536118843
Directory /workspace/21.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/21.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3608476562
Short name T118
Test name
Test status
Simulation time 112708586 ps
CPU time 1.08 seconds
Started Dec 20 12:20:21 PM PST 23
Finished Dec 20 12:20:23 PM PST 23
Peak memory 197712 kb
Host smart-73341785-d896-4773-9a9c-6e18bc92ce2b
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3608476562 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 21.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.3608476562
Directory /workspace/21.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/22.gpio_smoke_en_cdc_prim.4250370575
Short name T195
Test name
Test status
Simulation time 136901710 ps
CPU time 1.24 seconds
Started Dec 20 12:20:43 PM PST 23
Finished Dec 20 12:20:50 PM PST 23
Peak memory 197728 kb
Host smart-f20c1e6f-a08d-4b19-aa56-dd12ea0115bb
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=4250370575 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 22.gpio_smoke_en_cdc_prim.4250370575
Directory /workspace/22.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/22.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2877920976
Short name T145
Test name
Test status
Simulation time 138992498 ps
CPU time 1.13 seconds
Started Dec 20 12:20:16 PM PST 23
Finished Dec 20 12:20:18 PM PST 23
Peak memory 195464 kb
Host smart-89bd0266-59e4-4ac2-8245-2105365c5f03
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2877920976 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 22.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2877920976
Directory /workspace/22.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/23.gpio_smoke_no_pullup_pulldown_en_cdc_prim.479468222
Short name T190
Test name
Test status
Simulation time 525987779 ps
CPU time 0.88 seconds
Started Dec 20 12:20:56 PM PST 23
Finished Dec 20 12:21:03 PM PST 23
Peak memory 196316 kb
Host smart-e1b9b9c0-5a67-420f-98fb-b3b194dc8ae1
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=479468222 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 23.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.479468222
Directory /workspace/23.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/24.gpio_smoke_en_cdc_prim.2303306712
Short name T151
Test name
Test status
Simulation time 85508444 ps
CPU time 0.82 seconds
Started Dec 20 12:20:22 PM PST 23
Finished Dec 20 12:20:26 PM PST 23
Peak memory 195076 kb
Host smart-a615dcd0-24e7-4b5b-bd62-3414e212b56a
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2303306712 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 24.gpio_smoke_en_cdc_prim.2303306712
Directory /workspace/24.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/24.gpio_smoke_no_pullup_pulldown_en_cdc_prim.4025721427
Short name T165
Test name
Test status
Simulation time 190402540 ps
CPU time 0.82 seconds
Started Dec 20 12:20:53 PM PST 23
Finished Dec 20 12:21:01 PM PST 23
Peak memory 196080 kb
Host smart-bffdfdd1-0005-4fe5-9a20-71536c0d0cf6
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4025721427 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 24.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.4025721427
Directory /workspace/24.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/25.gpio_smoke_en_cdc_prim.1296882038
Short name T100
Test name
Test status
Simulation time 64504952 ps
CPU time 1.12 seconds
Started Dec 20 12:20:57 PM PST 23
Finished Dec 20 12:21:05 PM PST 23
Peak memory 196524 kb
Host smart-fa430d1d-918b-4ec8-a6e6-3c347047c4d8
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1296882038 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 25.gpio_smoke_en_cdc_prim.1296882038
Directory /workspace/25.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/25.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2120658893
Short name T54
Test name
Test status
Simulation time 118558647 ps
CPU time 0.86 seconds
Started Dec 20 12:20:57 PM PST 23
Finished Dec 20 12:21:04 PM PST 23
Peak memory 196308 kb
Host smart-0aca6a89-8d5f-49e5-ae63-a5d90db7cbc9
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2120658893 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 25.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2120658893
Directory /workspace/25.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/26.gpio_smoke_en_cdc_prim.1103048744
Short name T112
Test name
Test status
Simulation time 129729791 ps
CPU time 0.97 seconds
Started Dec 20 12:20:59 PM PST 23
Finished Dec 20 12:21:06 PM PST 23
Peak memory 195632 kb
Host smart-68be70b9-fa58-4e4d-b24d-b18ae7cf5bce
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1103048744 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 26.gpio_smoke_en_cdc_prim.1103048744
Directory /workspace/26.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/26.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1943292039
Short name T170
Test name
Test status
Simulation time 370416471 ps
CPU time 1.22 seconds
Started Dec 20 12:20:54 PM PST 23
Finished Dec 20 12:21:02 PM PST 23
Peak memory 196472 kb
Host smart-10eb1c72-0725-41be-8f8c-70ba53d8b120
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1943292039 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 26.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.1943292039
Directory /workspace/26.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/27.gpio_smoke_en_cdc_prim.1540190285
Short name T127
Test name
Test status
Simulation time 130305792 ps
CPU time 1.3 seconds
Started Dec 20 12:20:26 PM PST 23
Finished Dec 20 12:20:33 PM PST 23
Peak memory 196600 kb
Host smart-26020396-a93c-49f6-925b-a136a8227b04
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1540190285 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 27.gpio_smoke_en_cdc_prim.1540190285
Directory /workspace/27.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/27.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2223773796
Short name T167
Test name
Test status
Simulation time 85802694 ps
CPU time 1.02 seconds
Started Dec 20 12:20:56 PM PST 23
Finished Dec 20 12:21:03 PM PST 23
Peak memory 196288 kb
Host smart-17a222b4-cfcd-4239-bbff-8d1389c7e43b
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2223773796 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 27.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2223773796
Directory /workspace/27.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/28.gpio_smoke_en_cdc_prim.318444542
Short name T99
Test name
Test status
Simulation time 46709944 ps
CPU time 1.27 seconds
Started Dec 20 12:20:25 PM PST 23
Finished Dec 20 12:20:32 PM PST 23
Peak memory 197476 kb
Host smart-3b94ee1d-9f71-4160-ace7-ea94e0b4ff6e
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=318444542 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 28.gpio_smoke_en_cdc_prim.318444542
Directory /workspace/28.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/28.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1614819025
Short name T176
Test name
Test status
Simulation time 66441988 ps
CPU time 0.75 seconds
Started Dec 20 12:20:25 PM PST 23
Finished Dec 20 12:20:32 PM PST 23
Peak memory 195068 kb
Host smart-34982461-c4da-4f4c-b45b-0a187b7b367b
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1614819025 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 28.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.1614819025
Directory /workspace/28.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/29.gpio_smoke_en_cdc_prim.2043173528
Short name T168
Test name
Test status
Simulation time 100066557 ps
CPU time 1 seconds
Started Dec 20 12:20:47 PM PST 23
Finished Dec 20 12:20:54 PM PST 23
Peak memory 195448 kb
Host smart-24d6d5ac-b47e-4431-af3b-97220e2fe0cd
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2043173528 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 29.gpio_smoke_en_cdc_prim.2043173528
Directory /workspace/29.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/29.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2401141303
Short name T126
Test name
Test status
Simulation time 193260598 ps
CPU time 1.13 seconds
Started Dec 20 12:20:18 PM PST 23
Finished Dec 20 12:20:21 PM PST 23
Peak memory 196748 kb
Host smart-89261b37-a957-48d2-9c4b-e0b8b8f5a958
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2401141303 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 29.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2401141303
Directory /workspace/29.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/3.gpio_smoke_en_cdc_prim.2323526625
Short name T129
Test name
Test status
Simulation time 40350128 ps
CPU time 0.88 seconds
Started Dec 20 12:20:25 PM PST 23
Finished Dec 20 12:20:32 PM PST 23
Peak memory 197292 kb
Host smart-1992412c-b926-4a0e-8853-222417e91db6
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2323526625 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 3.gpio_smoke_en_cdc_prim.2323526625
Directory /workspace/3.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/3.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2835412773
Short name T178
Test name
Test status
Simulation time 51876062 ps
CPU time 1.34 seconds
Started Dec 20 12:20:26 PM PST 23
Finished Dec 20 12:20:33 PM PST 23
Peak memory 197728 kb
Host smart-6550867d-f440-4061-9e89-993d861fd122
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2835412773 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 3.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.2835412773
Directory /workspace/3.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/30.gpio_smoke_en_cdc_prim.89330968
Short name T194
Test name
Test status
Simulation time 76819523 ps
CPU time 1.03 seconds
Started Dec 20 12:20:56 PM PST 23
Finished Dec 20 12:21:03 PM PST 23
Peak memory 196480 kb
Host smart-16067882-1007-4460-b90a-0e69e1f1bea3
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=89330968 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 30.gpio_smoke_en_cdc_prim.89330968
Directory /workspace/30.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/30.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3041996329
Short name T134
Test name
Test status
Simulation time 141974383 ps
CPU time 1.15 seconds
Started Dec 20 12:20:57 PM PST 23
Finished Dec 20 12:21:04 PM PST 23
Peak memory 196164 kb
Host smart-232197d1-1284-421a-9674-97676105430b
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3041996329 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 30.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.3041996329
Directory /workspace/30.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/31.gpio_smoke_en_cdc_prim.3582516408
Short name T111
Test name
Test status
Simulation time 44969800 ps
CPU time 0.91 seconds
Started Dec 20 12:20:57 PM PST 23
Finished Dec 20 12:21:04 PM PST 23
Peak memory 196452 kb
Host smart-0e34ea37-1299-4d61-9494-314db8d1886a
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3582516408 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 31.gpio_smoke_en_cdc_prim.3582516408
Directory /workspace/31.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/31.gpio_smoke_no_pullup_pulldown_en_cdc_prim.686414599
Short name T117
Test name
Test status
Simulation time 194297490 ps
CPU time 1.07 seconds
Started Dec 20 12:20:57 PM PST 23
Finished Dec 20 12:21:05 PM PST 23
Peak memory 195640 kb
Host smart-8c4a11f7-7a06-4fd5-9447-b76a390e90dc
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=686414599 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 31.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.686414599
Directory /workspace/31.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/32.gpio_smoke_en_cdc_prim.3051102015
Short name T196
Test name
Test status
Simulation time 86698263 ps
CPU time 0.72 seconds
Started Dec 20 12:20:56 PM PST 23
Finished Dec 20 12:21:03 PM PST 23
Peak memory 195200 kb
Host smart-58c1048c-57eb-4eed-911c-dafb560b781d
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3051102015 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 32.gpio_smoke_en_cdc_prim.3051102015
Directory /workspace/32.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/32.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3642827798
Short name T181
Test name
Test status
Simulation time 55167488 ps
CPU time 0.73 seconds
Started Dec 20 12:20:48 PM PST 23
Finished Dec 20 12:21:01 PM PST 23
Peak memory 195124 kb
Host smart-a4506f31-fdfc-4571-ab8b-62f70c067729
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3642827798 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 32.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.3642827798
Directory /workspace/32.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/33.gpio_smoke_en_cdc_prim.424593120
Short name T113
Test name
Test status
Simulation time 153708111 ps
CPU time 1.04 seconds
Started Dec 20 12:20:58 PM PST 23
Finished Dec 20 12:21:05 PM PST 23
Peak memory 197764 kb
Host smart-bd44328b-c616-485d-b543-bebfac516dd1
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=424593120 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 33.gpio_smoke_en_cdc_prim.424593120
Directory /workspace/33.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/33.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2563792983
Short name T131
Test name
Test status
Simulation time 155642815 ps
CPU time 0.95 seconds
Started Dec 20 12:20:22 PM PST 23
Finished Dec 20 12:20:25 PM PST 23
Peak memory 196472 kb
Host smart-68606323-52ed-4dfa-8004-de564a364931
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2563792983 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 33.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2563792983
Directory /workspace/33.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/34.gpio_smoke_en_cdc_prim.3849581958
Short name T57
Test name
Test status
Simulation time 106295972 ps
CPU time 0.89 seconds
Started Dec 20 12:20:21 PM PST 23
Finished Dec 20 12:20:24 PM PST 23
Peak memory 195372 kb
Host smart-2f55e469-0d5a-4ac1-9ae6-bf6b874b844b
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3849581958 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 34.gpio_smoke_en_cdc_prim.3849581958
Directory /workspace/34.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/34.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2383888422
Short name T162
Test name
Test status
Simulation time 37401157 ps
CPU time 0.93 seconds
Started Dec 20 12:19:41 PM PST 23
Finished Dec 20 12:19:43 PM PST 23
Peak memory 195440 kb
Host smart-3f62d571-5580-44d6-bd01-4872489dadeb
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2383888422 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 34.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2383888422
Directory /workspace/34.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/35.gpio_smoke_en_cdc_prim.2781372327
Short name T177
Test name
Test status
Simulation time 134629450 ps
CPU time 1.07 seconds
Started Dec 20 12:20:21 PM PST 23
Finished Dec 20 12:20:24 PM PST 23
Peak memory 197720 kb
Host smart-7761ca4e-7111-492a-8f90-83e0dac2cb21
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2781372327 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 35.gpio_smoke_en_cdc_prim.2781372327
Directory /workspace/35.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/35.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2305114022
Short name T110
Test name
Test status
Simulation time 164473799 ps
CPU time 0.97 seconds
Started Dec 20 12:20:21 PM PST 23
Finished Dec 20 12:20:24 PM PST 23
Peak memory 195368 kb
Host smart-6f60bde8-2364-4140-9263-5266b787b2c8
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2305114022 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 35.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2305114022
Directory /workspace/35.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/36.gpio_smoke_en_cdc_prim.511995249
Short name T163
Test name
Test status
Simulation time 56784842 ps
CPU time 0.72 seconds
Started Dec 20 12:20:19 PM PST 23
Finished Dec 20 12:20:20 PM PST 23
Peak memory 195248 kb
Host smart-7b673c57-9d95-46ee-8cb0-93cc5bd3c07b
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=511995249 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 36.gpio_smoke_en_cdc_prim.511995249
Directory /workspace/36.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/36.gpio_smoke_no_pullup_pulldown_en_cdc_prim.4052320165
Short name T122
Test name
Test status
Simulation time 408602750 ps
CPU time 1.38 seconds
Started Dec 20 12:20:22 PM PST 23
Finished Dec 20 12:20:26 PM PST 23
Peak memory 195588 kb
Host smart-e7be0c93-d2e2-46fc-b989-4e9c7836a9fd
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4052320165 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 36.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.4052320165
Directory /workspace/36.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/37.gpio_smoke_en_cdc_prim.2784955218
Short name T153
Test name
Test status
Simulation time 186307575 ps
CPU time 0.93 seconds
Started Dec 20 12:20:57 PM PST 23
Finished Dec 20 12:21:04 PM PST 23
Peak memory 197764 kb
Host smart-78d4ab00-ac60-4c4b-85a3-8d38826b7d6b
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2784955218 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 37.gpio_smoke_en_cdc_prim.2784955218
Directory /workspace/37.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/37.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2712269874
Short name T125
Test name
Test status
Simulation time 62601514 ps
CPU time 1.07 seconds
Started Dec 20 12:20:49 PM PST 23
Finished Dec 20 12:20:58 PM PST 23
Peak memory 196324 kb
Host smart-4e6039f5-5646-46a8-8daa-268a880f9998
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2712269874 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 37.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2712269874
Directory /workspace/37.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/38.gpio_smoke_en_cdc_prim.512508310
Short name T149
Test name
Test status
Simulation time 994466026 ps
CPU time 1.01 seconds
Started Dec 20 12:20:46 PM PST 23
Finished Dec 20 12:20:54 PM PST 23
Peak memory 195488 kb
Host smart-21f7a7fe-9a6d-4330-b004-ec9aaaee74b9
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=512508310 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 38.gpio_smoke_en_cdc_prim.512508310
Directory /workspace/38.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/38.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2267310441
Short name T53
Test name
Test status
Simulation time 30013578 ps
CPU time 0.96 seconds
Started Dec 20 12:20:44 PM PST 23
Finished Dec 20 12:20:52 PM PST 23
Peak memory 196276 kb
Host smart-f2f33c04-2974-4c47-9754-ffb701d8cd36
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2267310441 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 38.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2267310441
Directory /workspace/38.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/39.gpio_smoke_en_cdc_prim.714905943
Short name T186
Test name
Test status
Simulation time 21007324 ps
CPU time 0.79 seconds
Started Dec 20 12:20:19 PM PST 23
Finished Dec 20 12:20:22 PM PST 23
Peak memory 195380 kb
Host smart-d5937f1c-1991-4716-8e03-a3f3c18af74e
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=714905943 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 39.gpio_smoke_en_cdc_prim.714905943
Directory /workspace/39.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/39.gpio_smoke_no_pullup_pulldown_en_cdc_prim.330810946
Short name T109
Test name
Test status
Simulation time 304601403 ps
CPU time 0.76 seconds
Started Dec 20 12:20:23 PM PST 23
Finished Dec 20 12:20:27 PM PST 23
Peak memory 195168 kb
Host smart-a7eea68b-499a-458d-ac9b-b808dc9fa550
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=330810946 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 39.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.330810946
Directory /workspace/39.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/4.gpio_smoke_en_cdc_prim.1931233852
Short name T152
Test name
Test status
Simulation time 116393986 ps
CPU time 0.86 seconds
Started Dec 20 12:20:26 PM PST 23
Finished Dec 20 12:20:33 PM PST 23
Peak memory 196364 kb
Host smart-0f9bf620-b051-4f44-94dc-3c34e90e235c
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1931233852 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 4.gpio_smoke_en_cdc_prim.1931233852
Directory /workspace/4.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/4.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1863784170
Short name T123
Test name
Test status
Simulation time 106562937 ps
CPU time 1.06 seconds
Started Dec 20 12:20:57 PM PST 23
Finished Dec 20 12:21:04 PM PST 23
Peak memory 195744 kb
Host smart-10561cb9-c338-41f8-8e36-f8ada9d17fbb
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1863784170 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 4.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.1863784170
Directory /workspace/4.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/40.gpio_smoke_en_cdc_prim.3475710334
Short name T155
Test name
Test status
Simulation time 223439605 ps
CPU time 1.19 seconds
Started Dec 20 12:20:24 PM PST 23
Finished Dec 20 12:20:29 PM PST 23
Peak memory 197736 kb
Host smart-9c062c57-9a6b-4450-8d5a-9893c5497e1f
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3475710334 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 40.gpio_smoke_en_cdc_prim.3475710334
Directory /workspace/40.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/40.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1267182013
Short name T120
Test name
Test status
Simulation time 1216116346 ps
CPU time 1.2 seconds
Started Dec 20 12:20:24 PM PST 23
Finished Dec 20 12:20:29 PM PST 23
Peak memory 197680 kb
Host smart-1185ae32-c1bd-4ef2-b25b-629f6fbb0ae9
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1267182013 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 40.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.1267182013
Directory /workspace/40.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/41.gpio_smoke_en_cdc_prim.2925212203
Short name T146
Test name
Test status
Simulation time 160104381 ps
CPU time 0.87 seconds
Started Dec 20 12:20:48 PM PST 23
Finished Dec 20 12:20:56 PM PST 23
Peak memory 196372 kb
Host smart-546e04f3-14ce-413c-b9e5-9c24c1e5e700
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2925212203 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 41.gpio_smoke_en_cdc_prim.2925212203
Directory /workspace/41.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/41.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3605321689
Short name T143
Test name
Test status
Simulation time 358050373 ps
CPU time 1.04 seconds
Started Dec 20 12:20:57 PM PST 23
Finished Dec 20 12:21:03 PM PST 23
Peak memory 197672 kb
Host smart-e1cdeb18-b44c-4ba7-85d9-29f722994a7b
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3605321689 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 41.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.3605321689
Directory /workspace/41.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/42.gpio_smoke_en_cdc_prim.1931289265
Short name T138
Test name
Test status
Simulation time 167351997 ps
CPU time 1.23 seconds
Started Dec 20 12:20:25 PM PST 23
Finished Dec 20 12:20:32 PM PST 23
Peak memory 196216 kb
Host smart-bb5e4cb2-bbb7-4ee6-a9db-5741fa44e7e4
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1931289265 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 42.gpio_smoke_en_cdc_prim.1931289265
Directory /workspace/42.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/42.gpio_smoke_no_pullup_pulldown_en_cdc_prim.4225169243
Short name T172
Test name
Test status
Simulation time 68626568 ps
CPU time 1.13 seconds
Started Dec 20 12:20:24 PM PST 23
Finished Dec 20 12:20:30 PM PST 23
Peak memory 196128 kb
Host smart-d0080031-0f05-40c7-a619-40c01d4c5e93
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4225169243 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 42.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.4225169243
Directory /workspace/42.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/43.gpio_smoke_en_cdc_prim.3135220976
Short name T114
Test name
Test status
Simulation time 327929008 ps
CPU time 1.4 seconds
Started Dec 20 12:20:42 PM PST 23
Finished Dec 20 12:20:48 PM PST 23
Peak memory 196496 kb
Host smart-25684b3f-9e27-41bf-8a25-e47bd547688c
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3135220976 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 43.gpio_smoke_en_cdc_prim.3135220976
Directory /workspace/43.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/43.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3983611479
Short name T158
Test name
Test status
Simulation time 19576678 ps
CPU time 0.77 seconds
Started Dec 20 12:20:24 PM PST 23
Finished Dec 20 12:20:27 PM PST 23
Peak memory 195760 kb
Host smart-a6710318-86bf-4d18-bae3-ba91d22ff0c6
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3983611479 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 43.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.3983611479
Directory /workspace/43.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/44.gpio_smoke_en_cdc_prim.3289507307
Short name T175
Test name
Test status
Simulation time 23444236 ps
CPU time 0.73 seconds
Started Dec 20 12:20:20 PM PST 23
Finished Dec 20 12:20:22 PM PST 23
Peak memory 195024 kb
Host smart-1a4fc456-cd7f-4ef1-bf3d-e3928fb6512a
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3289507307 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 44.gpio_smoke_en_cdc_prim.3289507307
Directory /workspace/44.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/45.gpio_smoke_en_cdc_prim.2978985026
Short name T135
Test name
Test status
Simulation time 67856014 ps
CPU time 1.1 seconds
Started Dec 20 12:21:03 PM PST 23
Finished Dec 20 12:21:13 PM PST 23
Peak memory 196488 kb
Host smart-eb7f86df-13cf-4d23-920a-6c1bf88f83a2
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2978985026 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 45.gpio_smoke_en_cdc_prim.2978985026
Directory /workspace/45.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/45.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3187077364
Short name T189
Test name
Test status
Simulation time 92314311 ps
CPU time 1.25 seconds
Started Dec 20 12:20:20 PM PST 23
Finished Dec 20 12:20:23 PM PST 23
Peak memory 196452 kb
Host smart-51216949-6e9c-4286-9a99-0fad53e7ecac
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3187077364 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 45.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.3187077364
Directory /workspace/45.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/46.gpio_smoke_en_cdc_prim.3687995391
Short name T159
Test name
Test status
Simulation time 61943838 ps
CPU time 0.82 seconds
Started Dec 20 12:21:01 PM PST 23
Finished Dec 20 12:21:10 PM PST 23
Peak memory 195160 kb
Host smart-10871ff4-bf8b-4a80-938c-f56c4c2f2bd9
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3687995391 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 46.gpio_smoke_en_cdc_prim.3687995391
Directory /workspace/46.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/46.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2103872059
Short name T147
Test name
Test status
Simulation time 84415470 ps
CPU time 1.36 seconds
Started Dec 20 12:20:20 PM PST 23
Finished Dec 20 12:20:23 PM PST 23
Peak memory 196480 kb
Host smart-fac5b43f-d192-47d2-88cb-cfccdab94170
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2103872059 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 46.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2103872059
Directory /workspace/46.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/47.gpio_smoke_en_cdc_prim.3564331904
Short name T133
Test name
Test status
Simulation time 82040170 ps
CPU time 1.19 seconds
Started Dec 20 12:20:24 PM PST 23
Finished Dec 20 12:20:29 PM PST 23
Peak memory 195688 kb
Host smart-2a96036e-b7e2-4bd9-9c30-d6c5fecd1dfa
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3564331904 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 47.gpio_smoke_en_cdc_prim.3564331904
Directory /workspace/47.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/47.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1827833070
Short name T188
Test name
Test status
Simulation time 440285619 ps
CPU time 1.25 seconds
Started Dec 20 12:20:24 PM PST 23
Finished Dec 20 12:20:29 PM PST 23
Peak memory 196564 kb
Host smart-62c3c01d-6ae6-4b1e-9d1f-1878a5982a31
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1827833070 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 47.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.1827833070
Directory /workspace/47.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/48.gpio_smoke_en_cdc_prim.1799750798
Short name T128
Test name
Test status
Simulation time 147098203 ps
CPU time 0.74 seconds
Started Dec 20 12:20:21 PM PST 23
Finished Dec 20 12:20:23 PM PST 23
Peak memory 195148 kb
Host smart-1d01f433-445f-4049-a56a-fd92d08f52ed
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1799750798 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 48.gpio_smoke_en_cdc_prim.1799750798
Directory /workspace/48.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/48.gpio_smoke_no_pullup_pulldown_en_cdc_prim.55034452
Short name T185
Test name
Test status
Simulation time 135091219 ps
CPU time 1.2 seconds
Started Dec 20 12:20:58 PM PST 23
Finished Dec 20 12:21:05 PM PST 23
Peak memory 196396 kb
Host smart-8cb83954-c841-4715-9007-333931b46099
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=55034452 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 48.gpio_smoke_no_pullup_pulldown_e
n_cdc_prim.55034452
Directory /workspace/48.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/49.gpio_smoke_en_cdc_prim.1886834778
Short name T44
Test name
Test status
Simulation time 134738986 ps
CPU time 0.81 seconds
Started Dec 20 12:20:24 PM PST 23
Finished Dec 20 12:20:29 PM PST 23
Peak memory 195228 kb
Host smart-c516b9ed-15c9-4de6-ba43-73505bbd589c
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1886834778 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 49.gpio_smoke_en_cdc_prim.1886834778
Directory /workspace/49.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/49.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1759449565
Short name T169
Test name
Test status
Simulation time 87434107 ps
CPU time 0.94 seconds
Started Dec 20 12:20:24 PM PST 23
Finished Dec 20 12:20:30 PM PST 23
Peak memory 197580 kb
Host smart-cf683803-a110-4f69-bf74-ae06af3f6953
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1759449565 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 49.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.1759449565
Directory /workspace/49.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/5.gpio_smoke_en_cdc_prim.3954057026
Short name T119
Test name
Test status
Simulation time 167212937 ps
CPU time 1.22 seconds
Started Dec 20 12:20:25 PM PST 23
Finished Dec 20 12:20:32 PM PST 23
Peak memory 196212 kb
Host smart-c3348d74-b0b9-4b23-9190-5e2651266b1e
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3954057026 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 5.gpio_smoke_en_cdc_prim.3954057026
Directory /workspace/5.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/5.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2177841261
Short name T140
Test name
Test status
Simulation time 106811138 ps
CPU time 0.91 seconds
Started Dec 20 12:20:18 PM PST 23
Finished Dec 20 12:20:20 PM PST 23
Peak memory 197148 kb
Host smart-ab1742a3-7550-441b-b141-56fe8faf9a7c
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2177841261 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 5.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.2177841261
Directory /workspace/5.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/6.gpio_smoke_en_cdc_prim.4283633853
Short name T116
Test name
Test status
Simulation time 129079675 ps
CPU time 1.05 seconds
Started Dec 20 12:20:43 PM PST 23
Finished Dec 20 12:20:49 PM PST 23
Peak memory 196188 kb
Host smart-1c478e27-81cd-40f5-b7b6-36dd3c6423a7
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=4283633853 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 6.gpio_smoke_en_cdc_prim.4283633853
Directory /workspace/6.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/6.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2403564503
Short name T174
Test name
Test status
Simulation time 52438730 ps
CPU time 0.95 seconds
Started Dec 20 12:20:44 PM PST 23
Finished Dec 20 12:20:52 PM PST 23
Peak memory 197748 kb
Host smart-97935028-04ee-4a13-b526-135b2525a2fe
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2403564503 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 6.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.2403564503
Directory /workspace/6.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/7.gpio_smoke_en_cdc_prim.620057969
Short name T156
Test name
Test status
Simulation time 33004882 ps
CPU time 0.93 seconds
Started Dec 20 12:20:58 PM PST 23
Finished Dec 20 12:21:05 PM PST 23
Peak memory 196392 kb
Host smart-9753f5e8-a673-436c-8d17-65fbbed209f2
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=620057969 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 7.gpio_smoke_en_cdc_prim.620057969
Directory /workspace/7.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/7.gpio_smoke_no_pullup_pulldown_en_cdc_prim.4043215166
Short name T148
Test name
Test status
Simulation time 222256578 ps
CPU time 0.97 seconds
Started Dec 20 12:20:54 PM PST 23
Finished Dec 20 12:21:02 PM PST 23
Peak memory 196512 kb
Host smart-5b3e41ed-f890-42aa-9238-f881cab52169
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4043215166 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 7.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.4043215166
Directory /workspace/7.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/8.gpio_smoke_en_cdc_prim.3310409027
Short name T180
Test name
Test status
Simulation time 474344985 ps
CPU time 1.42 seconds
Started Dec 20 12:20:58 PM PST 23
Finished Dec 20 12:21:06 PM PST 23
Peak memory 196352 kb
Host smart-5be73dd9-2845-466c-94ca-85a735a0a65f
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3310409027 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 8.gpio_smoke_en_cdc_prim.3310409027
Directory /workspace/8.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/8.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1669353701
Short name T43
Test name
Test status
Simulation time 39460477 ps
CPU time 0.82 seconds
Started Dec 20 12:20:58 PM PST 23
Finished Dec 20 12:21:04 PM PST 23
Peak memory 196004 kb
Host smart-427aefb2-d5d5-42ed-8605-94cb627868eb
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1669353701 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 8.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.1669353701
Directory /workspace/8.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/9.gpio_smoke_en_cdc_prim.3368837242
Short name T187
Test name
Test status
Simulation time 194735184 ps
CPU time 1.3 seconds
Started Dec 20 12:20:19 PM PST 23
Finished Dec 20 12:20:21 PM PST 23
Peak memory 197752 kb
Host smart-15f81290-a9a4-42ba-8ec4-dfc781a6c42e
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3368837242 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 9.gpio_smoke_en_cdc_prim.3368837242
Directory /workspace/9.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/9.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3989470355
Short name T160
Test name
Test status
Simulation time 111310645 ps
CPU time 1 seconds
Started Dec 20 12:21:02 PM PST 23
Finished Dec 20 12:21:12 PM PST 23
Peak memory 196288 kb
Host smart-c7932683-38b9-4c0b-9735-d22d74edbb77
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3989470355 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 9.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.3989470355
Directory /workspace/9.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest
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