Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=31}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=31}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=31}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	36	0	36	100.00
Crosses	128	0	128	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=31}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	32	0	32	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=31}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	128	0	128	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	32	0	32	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	22812075	1			T21	3		T22	21		T1	24
all_values[1]	22812075	1			T21	3		T22	21		T1	24
all_values[2]	22812075	1			T21	3		T22	21		T1	24
all_values[3]	22812075	1			T21	3		T22	21		T1	24
all_values[4]	22812075	1			T21	3		T22	21		T1	24
all_values[5]	22812075	1			T21	3		T22	21		T1	24
all_values[6]	22812075	1			T21	3		T22	21		T1	24
all_values[7]	22812075	1			T21	3		T22	21		T1	24
all_values[8]	22812075	1			T21	3		T22	21		T1	24
all_values[9]	22812075	1			T21	3		T22	21		T1	24
all_values[10]	22812075	1			T21	3		T22	21		T1	24
all_values[11]	22812075	1			T21	3		T22	21		T1	24
all_values[12]	22812075	1			T21	3		T22	21		T1	24
all_values[13]	22812075	1			T21	3		T22	21		T1	24
all_values[14]	22812075	1			T21	3		T22	21		T1	24
all_values[15]	22812075	1			T21	3		T22	21		T1	24
all_values[16]	22812075	1			T21	3		T22	21		T1	24
all_values[17]	22812075	1			T21	3		T22	21		T1	24
all_values[18]	22812075	1			T21	3		T22	21		T1	24
all_values[19]	22812075	1			T21	3		T22	21		T1	24
all_values[20]	22812075	1			T21	3		T22	21		T1	24
all_values[21]	22812075	1			T21	3		T22	21		T1	24
all_values[22]	22812075	1			T21	3		T22	21		T1	24
all_values[23]	22812075	1			T21	3		T22	21		T1	24
all_values[24]	22812075	1			T21	3		T22	21		T1	24
all_values[25]	22812075	1			T21	3		T22	21		T1	24
all_values[26]	22812075	1			T21	3		T22	21		T1	24
all_values[27]	22812075	1			T21	3		T22	21		T1	24
all_values[28]	22812075	1			T21	3		T22	21		T1	24
all_values[29]	22812075	1			T21	3		T22	21		T1	24
all_values[30]	22812075	1			T21	3		T22	21		T1	24
all_values[31]	22812075	1			T21	3		T22	21		T1	24

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

401085135

1

T21

84

T22

371

T1

424

auto[1]

328901265

1

T21

12

T22

301

T1

344

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

133416909

1

T21

76

T22

370

T1

357

auto[1]

596569491

1

T21

20

T22

302

T1

411

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	128	0	128	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	3199673	1			T21	2		T22	6		T1	3
all_values[0]	auto[0]	auto[1]	9340809	1			T22	6		T1	2		T11	4
all_values[0]	auto[1]	auto[0]	965332	1			T21	1		T22	3		T1	19
all_values[0]	auto[1]	auto[1]	9306261	1			T22	6		T11	1		T12	2
all_values[1]	auto[0]	auto[0]	3218409	1			T21	2		T22	5		T1	5
all_values[1]	auto[0]	auto[1]	9357717	1			T21	1		T22	7		T11	4
all_values[1]	auto[1]	auto[0]	960699	1			T22	4		T11	3		T12	3
all_values[1]	auto[1]	auto[1]	9275250	1			T22	5		T1	19		T11	3
all_values[2]	auto[0]	auto[0]	3207307	1			T21	2		T22	1		T1	2
all_values[2]	auto[0]	auto[1]	9317783	1			T21	1		T22	7		T11	5
all_values[2]	auto[1]	auto[0]	945000	1			T22	1		T1	19		T11	3
all_values[2]	auto[1]	auto[1]	9341985	1			T22	12		T1	3		T11	2
all_values[3]	auto[0]	auto[0]	3205253	1			T21	2		T22	6		T1	8
all_values[3]	auto[0]	auto[1]	9327792	1			T21	1		T22	6		T1	3
all_values[3]	auto[1]	auto[0]	947636	1			T22	4		T1	13		T11	1
all_values[3]	auto[1]	auto[1]	9331394	1			T22	5		T11	4		T12	1
all_values[4]	auto[0]	auto[0]	3208022	1			T21	2		T22	13		T1	2
all_values[4]	auto[0]	auto[1]	9292496	1			T22	1		T1	19		T11	5
all_values[4]	auto[1]	auto[0]	973981	1			T21	1		T22	4		T1	3
all_values[4]	auto[1]	auto[1]	9337576	1			T22	3		T11	1		T12	2
all_values[5]	auto[0]	auto[0]	3213930	1			T21	2		T22	6		T1	2
all_values[5]	auto[0]	auto[1]	9317504	1			T21	1		T22	4		T1	9
all_values[5]	auto[1]	auto[0]	967952	1			T22	4		T11	2		T12	3
all_values[5]	auto[1]	auto[1]	9312689	1			T22	7		T1	13		T11	3
all_values[6]	auto[0]	auto[0]	3219269	1			T21	3		T22	11		T1	2
all_values[6]	auto[0]	auto[1]	9344582	1			T1	19		T11	4		T12	3
all_values[6]	auto[1]	auto[0]	964806	1			T22	9		T1	3		T11	7
all_values[6]	auto[1]	auto[1]	9283418	1			T22	1		T12	1		T2	14
all_values[7]	auto[0]	auto[0]	3210688	1			T21	2		T22	5		T1	2
all_values[7]	auto[0]	auto[1]	9343433	1			T21	1		T22	10		T1	6
all_values[7]	auto[1]	auto[0]	960119	1			T22	2		T1	13		T11	3
all_values[7]	auto[1]	auto[1]	9297835	1			T22	4		T1	3		T11	4
all_values[8]	auto[0]	auto[0]	3203832	1			T21	2		T22	6		T1	2
all_values[8]	auto[0]	auto[1]	9295668	1			T21	1		T22	1		T1	6
all_values[8]	auto[1]	auto[0]	961373	1			T22	3		T1	3		T11	4
all_values[8]	auto[1]	auto[1]	9351202	1			T22	11		T1	13		T11	2
all_values[9]	auto[0]	auto[0]	3212076	1			T21	2		T22	14		T1	5
all_values[9]	auto[0]	auto[1]	9321468	1			T21	1		T22	4		T1	19
all_values[9]	auto[1]	auto[0]	965922	1			T22	3		T11	4		T12	3
all_values[9]	auto[1]	auto[1]	9312609	1			T2	24		T16	8		T18	4
all_values[10]	auto[0]	auto[0]	3208256	1			T21	2		T22	3		T1	5
all_values[10]	auto[0]	auto[1]	9321202	1			T22	4		T1	6		T11	7
all_values[10]	auto[1]	auto[0]	951003	1			T22	6		T1	2		T11	2
all_values[10]	auto[1]	auto[1]	9331614	1			T21	1		T22	8		T1	11
all_values[11]	auto[0]	auto[0]	3212812	1			T21	2		T22	7		T1	4
all_values[11]	auto[0]	auto[1]	9315375	1			T21	1		T22	8		T1	20
all_values[11]	auto[1]	auto[0]	960576	1			T22	3		T11	3		T12	6
all_values[11]	auto[1]	auto[1]	9323312	1			T22	3		T11	4		T2	12
all_values[12]	auto[0]	auto[0]	3221385	1			T21	2		T22	3		T1	2
all_values[12]	auto[0]	auto[1]	9337469	1			T21	1		T22	3		T1	6
all_values[12]	auto[1]	auto[0]	961178	1			T22	5		T1	16		T11	5
all_values[12]	auto[1]	auto[1]	9292043	1			T22	10		T11	2		T12	1
all_values[13]	auto[0]	auto[0]	3212800	1			T21	3		T22	4		T1	2
all_values[13]	auto[0]	auto[1]	9373425	1			T1	3		T11	7		T12	1
all_values[13]	auto[1]	auto[0]	963606	1			T22	8		T1	19		T11	3
all_values[13]	auto[1]	auto[1]	9262244	1			T22	9		T11	1		T2	12
all_values[14]	auto[0]	auto[0]	3210358	1			T21	2		T22	10		T1	2
all_values[14]	auto[0]	auto[1]	9324777	1			T22	3		T1	22		T11	7
all_values[14]	auto[1]	auto[0]	965479	1			T22	2		T11	3		T12	3
all_values[14]	auto[1]	auto[1]	9311461	1			T21	1		T22	6		T11	4
all_values[15]	auto[0]	auto[0]	3202954	1			T21	2		T22	9		T1	2
all_values[15]	auto[0]	auto[1]	9357030	1			T21	1		T22	1		T1	3
all_values[15]	auto[1]	auto[0]	961164	1			T22	7		T11	6		T12	1
all_values[15]	auto[1]	auto[1]	9290927	1			T22	4		T1	19		T11	2
all_values[16]	auto[0]	auto[0]	3212487	1			T21	3		T22	4		T1	15
all_values[16]	auto[0]	auto[1]	9297350	1			T22	13		T1	3		T11	4
all_values[16]	auto[1]	auto[0]	954043	1			T1	6		T11	6		T12	3
all_values[16]	auto[1]	auto[1]	9348195	1			T22	4		T11	4		T12	2
all_values[17]	auto[0]	auto[0]	3209828	1			T21	3		T22	7		T1	2
all_values[17]	auto[0]	auto[1]	9333481	1			T22	9		T1	6		T11	3
all_values[17]	auto[1]	auto[0]	959663	1			T22	2		T11	4		T12	4
all_values[17]	auto[1]	auto[1]	9309103	1			T22	3		T1	16		T11	2
all_values[18]	auto[0]	auto[0]	3203663	1			T21	3		T22	1		T1	2
all_values[18]	auto[0]	auto[1]	9316646	1			T22	2		T1	16		T11	5
all_values[18]	auto[1]	auto[0]	961663	1			T22	14		T11	5		T12	4
all_values[18]	auto[1]	auto[1]	9330103	1			T22	4		T1	6		T11	3
all_values[19]	auto[0]	auto[0]	3221105	1			T21	2		T22	8		T1	2
all_values[19]	auto[0]	auto[1]	9372845	1			T22	4		T11	3		T12	1
all_values[19]	auto[1]	auto[0]	962056	1			T21	1		T22	5		T1	3
all_values[19]	auto[1]	auto[1]	9256069	1			T22	4		T1	19		T11	3
all_values[20]	auto[0]	auto[0]	3199056	1			T21	2		T22	7		T1	2
all_values[20]	auto[0]	auto[1]	9291603	1			T22	5		T11	7		T2	8
all_values[20]	auto[1]	auto[0]	954659	1			T21	1		T22	9		T1	22
all_values[20]	auto[1]	auto[1]	9366757	1			T11	2		T12	1		T2	24
all_values[21]	auto[0]	auto[0]	3200178	1			T21	3		T22	7		T1	2
all_values[21]	auto[0]	auto[1]	9363661	1			T22	5		T1	19		T11	7
all_values[21]	auto[1]	auto[0]	957959	1			T22	5		T11	4		T12	2
all_values[21]	auto[1]	auto[1]	9290277	1			T22	4		T1	3		T11	2
all_values[22]	auto[0]	auto[0]	3223596	1			T21	2		T22	13		T1	15
all_values[22]	auto[0]	auto[1]	9325448	1			T21	1		T11	3		T12	1
all_values[22]	auto[1]	auto[0]	958680	1			T22	3		T1	1		T11	2
all_values[22]	auto[1]	auto[1]	9304351	1			T22	5		T1	8		T11	6
all_values[23]	auto[0]	auto[0]	3215379	1			T21	2		T22	3		T1	2
all_values[23]	auto[0]	auto[1]	9290583	1			T21	1		T22	4		T11	2
all_values[23]	auto[1]	auto[0]	954016	1			T22	3		T11	5		T12	4
all_values[23]	auto[1]	auto[1]	9352097	1			T22	11		T1	22		T11	2
all_values[24]	auto[0]	auto[0]	3204099	1			T21	2		T22	8		T1	2
all_values[24]	auto[0]	auto[1]	9301336	1			T22	3		T1	22		T11	5
all_values[24]	auto[1]	auto[0]	958828	1			T22	9		T11	6		T12	1
all_values[24]	auto[1]	auto[1]	9347812	1			T21	1		T22	1		T11	2
all_values[25]	auto[0]	auto[0]	3196882	1			T21	2		T22	4		T1	24
all_values[25]	auto[0]	auto[1]	9297042	1			T22	3		T11	6		T12	3
all_values[25]	auto[1]	auto[0]	956939	1			T22	6		T11	5		T12	1
all_values[25]	auto[1]	auto[1]	9361212	1			T21	1		T22	8		T11	1
all_values[26]	auto[0]	auto[0]	3219214	1			T21	2		T22	9		T1	15
all_values[26]	auto[0]	auto[1]	9339324	1			T1	3		T11	4		T12	1
all_values[26]	auto[1]	auto[0]	956860	1			T22	10		T1	6		T11	3
all_values[26]	auto[1]	auto[1]	9296677	1			T21	1		T22	2		T11	4
all_values[27]	auto[0]	auto[0]	3203372	1			T21	2		T22	6		T1	2
all_values[27]	auto[0]	auto[1]	9336758	1			T21	1		T22	5		T1	19
all_values[27]	auto[1]	auto[0]	950378	1			T22	4		T11	5		T12	1
all_values[27]	auto[1]	auto[1]	9321567	1			T22	6		T1	3		T11	3
all_values[28]	auto[0]	auto[0]	3215196	1			T21	2		T22	4		T1	21
all_values[28]	auto[0]	auto[1]	9326706	1			T22	14		T11	6		T12	1
all_values[28]	auto[1]	auto[0]	965494	1			T21	1		T22	2		T1	3
all_values[28]	auto[1]	auto[1]	9304679	1			T22	1		T11	3		T12	2
all_values[29]	auto[0]	auto[0]	3202666	1			T21	2		T22	10		T1	24
all_values[29]	auto[0]	auto[1]	9326323	1			T22	5		T11	4		T12	1
all_values[29]	auto[1]	auto[0]	962265	1			T21	1		T22	1		T11	3
all_values[29]	auto[1]	auto[1]	9320821	1			T22	5		T11	3		T12	1
all_values[30]	auto[0]	auto[0]	3202903	1			T21	2		T22	14		T1	2
all_values[30]	auto[0]	auto[1]	9274680	1			T22	6		T11	4		T12	3
all_values[30]	auto[1]	auto[0]	960229	1			T22	1		T1	19		T11	2
all_values[30]	auto[1]	auto[1]	9374263	1			T21	1		T1	3		T11	4
all_values[31]	auto[0]	auto[0]	3207439	1			T21	2		T22	10		T1	5
all_values[31]	auto[0]	auto[1]	9298732	1			T21	1		T22	4		T1	6
all_values[31]	auto[1]	auto[0]	963264	1			T22	4		T11	4		T12	2
all_values[31]	auto[1]	auto[1]	9342640	1			T22	3		T1	13		T11	2