Summary for Variable cp_var1
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_var1
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
347627 |
1 |
|
|
T32 |
8 |
|
T48 |
1105 |
|
T49 |
2218 |
auto[1] |
349573 |
1 |
|
|
T32 |
12 |
|
T48 |
1142 |
|
T49 |
2237 |
Summary for Variable cp_var2
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_var2
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
348464 |
1 |
|
|
T32 |
8 |
|
T48 |
1122 |
|
T49 |
2230 |
auto[1] |
348736 |
1 |
|
|
T32 |
12 |
|
T48 |
1125 |
|
T49 |
2225 |
Summary for Cross cp_var1_var2_cross
Samples crossed: cp_var1 cp_var2
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for cp_var1_var2_cross
Bins
cp_var1 | cp_var2 | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
173776 |
1 |
|
|
T32 |
2 |
|
T48 |
547 |
|
T49 |
1117 |
auto[0] |
auto[1] |
173851 |
1 |
|
|
T32 |
6 |
|
T48 |
558 |
|
T49 |
1101 |
auto[1] |
auto[0] |
174688 |
1 |
|
|
T32 |
6 |
|
T48 |
575 |
|
T49 |
1113 |
auto[1] |
auto[1] |
174885 |
1 |
|
|
T32 |
6 |
|
T48 |
567 |
|
T49 |
1124 |
Summary for Variable cp_var1
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_var1
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
348371 |
1 |
|
|
T32 |
9 |
|
T48 |
1105 |
|
T49 |
2204 |
auto[1] |
348829 |
1 |
|
|
T32 |
11 |
|
T48 |
1142 |
|
T49 |
2251 |
Summary for Variable cp_var2
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_var2
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
348360 |
1 |
|
|
T32 |
10 |
|
T48 |
1147 |
|
T49 |
2237 |
auto[1] |
348840 |
1 |
|
|
T32 |
10 |
|
T48 |
1100 |
|
T49 |
2218 |
Summary for Cross cp_var1_var2_cross
Samples crossed: cp_var1 cp_var2
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for cp_var1_var2_cross
Bins
cp_var1 | cp_var2 | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
174049 |
1 |
|
|
T32 |
5 |
|
T48 |
579 |
|
T49 |
1077 |
auto[0] |
auto[1] |
174322 |
1 |
|
|
T32 |
4 |
|
T48 |
526 |
|
T49 |
1127 |
auto[1] |
auto[0] |
174311 |
1 |
|
|
T32 |
5 |
|
T48 |
568 |
|
T49 |
1160 |
auto[1] |
auto[1] |
174518 |
1 |
|
|
T32 |
6 |
|
T48 |
574 |
|
T49 |
1091 |
Summary for Variable cp_var1
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_var1
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
348857 |
1 |
|
|
T32 |
10 |
|
T48 |
1096 |
|
T49 |
2234 |
auto[1] |
348343 |
1 |
|
|
T32 |
10 |
|
T48 |
1151 |
|
T49 |
2221 |
Summary for Variable cp_var2
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_var2
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
348620 |
1 |
|
|
T32 |
10 |
|
T48 |
1155 |
|
T49 |
2141 |
auto[1] |
348580 |
1 |
|
|
T32 |
10 |
|
T48 |
1092 |
|
T49 |
2314 |
Summary for Cross cp_var1_var2_cross
Samples crossed: cp_var1 cp_var2
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for cp_var1_var2_cross
Bins
cp_var1 | cp_var2 | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
174022 |
1 |
|
|
T32 |
7 |
|
T48 |
556 |
|
T49 |
1090 |
auto[0] |
auto[1] |
174835 |
1 |
|
|
T32 |
3 |
|
T48 |
540 |
|
T49 |
1144 |
auto[1] |
auto[0] |
174598 |
1 |
|
|
T32 |
3 |
|
T48 |
599 |
|
T49 |
1051 |
auto[1] |
auto[1] |
173745 |
1 |
|
|
T32 |
7 |
|
T48 |
552 |
|
T49 |
1170 |
Summary for Variable cp_var1
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_var1
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
348411 |
1 |
|
|
T32 |
13 |
|
T48 |
1188 |
|
T49 |
2236 |
auto[1] |
348789 |
1 |
|
|
T32 |
7 |
|
T48 |
1059 |
|
T49 |
2219 |
Summary for Variable cp_var2
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_var2
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
348017 |
1 |
|
|
T32 |
5 |
|
T48 |
1091 |
|
T49 |
2264 |
auto[1] |
349183 |
1 |
|
|
T32 |
15 |
|
T48 |
1156 |
|
T49 |
2191 |
Summary for Cross cp_var1_var2_cross
Samples crossed: cp_var1 cp_var2
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for cp_var1_var2_cross
Bins
cp_var1 | cp_var2 | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
173635 |
1 |
|
|
T32 |
5 |
|
T48 |
589 |
|
T49 |
1121 |
auto[0] |
auto[1] |
174776 |
1 |
|
|
T32 |
8 |
|
T48 |
599 |
|
T49 |
1115 |
auto[1] |
auto[0] |
174382 |
1 |
|
|
T48 |
502 |
|
T49 |
1143 |
|
T113 |
9 |
auto[1] |
auto[1] |
174407 |
1 |
|
|
T32 |
7 |
|
T48 |
557 |
|
T49 |
1076 |
Summary for Variable cp_var1
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_var1
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
348926 |
1 |
|
|
T32 |
8 |
|
T48 |
1152 |
|
T49 |
2244 |
auto[1] |
348274 |
1 |
|
|
T32 |
12 |
|
T48 |
1095 |
|
T49 |
2211 |
Summary for Variable cp_var2
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_var2
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
348541 |
1 |
|
|
T32 |
4 |
|
T48 |
1142 |
|
T49 |
2199 |
auto[1] |
348659 |
1 |
|
|
T32 |
16 |
|
T48 |
1105 |
|
T49 |
2256 |
Summary for Cross cp_var1_var2_cross
Samples crossed: cp_var1 cp_var2
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for cp_var1_var2_cross
Bins
cp_var1 | cp_var2 | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
174429 |
1 |
|
|
T32 |
2 |
|
T48 |
564 |
|
T49 |
1093 |
auto[0] |
auto[1] |
174497 |
1 |
|
|
T32 |
6 |
|
T48 |
588 |
|
T49 |
1151 |
auto[1] |
auto[0] |
174112 |
1 |
|
|
T32 |
2 |
|
T48 |
578 |
|
T49 |
1106 |
auto[1] |
auto[1] |
174162 |
1 |
|
|
T32 |
10 |
|
T48 |
517 |
|
T49 |
1105 |