Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=31}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=31}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=31}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	36	0	36	100.00
Crosses	128	0	128	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=31}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	32	0	32	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=31}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	128	0	128	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	32	0	32	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	6912383	1			T21	3		T22	18		T1	13
all_pins[1]	6912383	1			T21	3		T22	18		T1	13
all_pins[2]	6912383	1			T21	3		T22	18		T1	13
all_pins[3]	6912383	1			T21	3		T22	18		T1	13
all_pins[4]	6912383	1			T21	3		T22	18		T1	13
all_pins[5]	6912383	1			T21	3		T22	18		T1	13
all_pins[6]	6912383	1			T21	3		T22	18		T1	13
all_pins[7]	6912383	1			T21	3		T22	18		T1	13
all_pins[8]	6912383	1			T21	3		T22	18		T1	13
all_pins[9]	6912383	1			T21	3		T22	18		T1	13
all_pins[10]	6912383	1			T21	3		T22	18		T1	13
all_pins[11]	6912383	1			T21	3		T22	18		T1	13
all_pins[12]	6912383	1			T21	3		T22	18		T1	13
all_pins[13]	6912383	1			T21	3		T22	18		T1	13
all_pins[14]	6912383	1			T21	3		T22	18		T1	13
all_pins[15]	6912383	1			T21	3		T22	18		T1	13
all_pins[16]	6912383	1			T21	3		T22	18		T1	13
all_pins[17]	6912383	1			T21	3		T22	18		T1	13
all_pins[18]	6912383	1			T21	3		T22	18		T1	13
all_pins[19]	6912383	1			T21	3		T22	18		T1	13
all_pins[20]	6912383	1			T21	3		T22	18		T1	13
all_pins[21]	6912383	1			T21	3		T22	18		T1	13
all_pins[22]	6912383	1			T21	3		T22	18		T1	13
all_pins[23]	6912383	1			T21	3		T22	18		T1	13
all_pins[24]	6912383	1			T21	3		T22	18		T1	13
all_pins[25]	6912383	1			T21	3		T22	18		T1	13
all_pins[26]	6912383	1			T21	3		T22	18		T1	13
all_pins[27]	6912383	1			T21	3		T22	18		T1	13
all_pins[28]	6912383	1			T21	3		T22	18		T1	13
all_pins[29]	6912383	1			T21	3		T22	18		T1	13
all_pins[30]	6912383	1			T21	3		T22	18		T1	13
all_pins[31]	6912383	1			T21	3		T22	18		T1	13

---

Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	137141368	1			T21	90		T22	430		T1	267
values[0x1]	84054888	1			T21	6		T22	146		T1	149
transitions[0x0=>0x1]	50294464	1			T21	4		T22	104		T1	87
transitions[0x1=>0x0]	50294321	1			T21	4		T22	104		T1	87

---

Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	128	0	128	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	4285876	1			T21	3		T22	12		T1	10
all_pins[0]	values[0x1]	2626507	1			T22	6		T1	3		T11	1
all_pins[0]	transitions[0x0=>0x1]	1623975	1			T22	5		T1	2		T11	1
all_pins[0]	transitions[0x1=>0x0]	1623742	1			T22	2		T1	4		T11	7
all_pins[1]	values[0x0]	4292264	1			T21	3		T22	13		T1	7
all_pins[1]	values[0x1]	2620119	1			T22	5		T1	6		T11	4
all_pins[1]	transitions[0x0=>0x1]	1564516	1			T22	2		T1	3		T11	4
all_pins[1]	transitions[0x1=>0x0]	1570904	1			T22	3		T11	1		T12	4
all_pins[2]	values[0x0]	4282014	1			T21	3		T22	7		T1	7
all_pins[2]	values[0x1]	2630369	1			T22	11		T1	6		T11	11
all_pins[2]	transitions[0x0=>0x1]	1575470	1			T22	6		T1	4		T11	10
all_pins[2]	transitions[0x1=>0x0]	1565220	1			T1	4		T11	3		T12	4
all_pins[3]	values[0x0]	4282900	1			T21	3		T22	13		T1	11
all_pins[3]	values[0x1]	2629483	1			T22	5		T1	2		T11	13
all_pins[3]	transitions[0x0=>0x1]	1571171	1			T22	1		T1	1		T11	9
all_pins[3]	transitions[0x1=>0x0]	1572057	1			T22	7		T1	5		T11	7
all_pins[4]	values[0x0]	4290570	1			T21	3		T22	15		T1	8
all_pins[4]	values[0x1]	2621813	1			T22	3		T1	5		T11	8
all_pins[4]	transitions[0x0=>0x1]	1566561	1			T22	1		T1	5		T11	5
all_pins[4]	transitions[0x1=>0x0]	1574231	1			T22	3		T1	2		T11	10
all_pins[5]	values[0x0]	4285552	1			T21	3		T22	11		T1	9
all_pins[5]	values[0x1]	2626831	1			T22	7		T1	4		T11	7
all_pins[5]	transitions[0x0=>0x1]	1572001	1			T22	6		T1	3		T11	5
all_pins[5]	transitions[0x1=>0x0]	1566983	1			T22	2		T1	4		T11	6
all_pins[6]	values[0x0]	4291193	1			T21	3		T22	17		T1	7
all_pins[6]	values[0x1]	2621190	1			T22	1		T1	6		T11	7
all_pins[6]	transitions[0x0=>0x1]	1563671	1			T1	4		T11	6		T12	3
all_pins[6]	transitions[0x1=>0x0]	1569312	1			T22	6		T1	2		T11	6
all_pins[7]	values[0x0]	4287087	1			T21	3		T22	14		T1	7
all_pins[7]	values[0x1]	2625296	1			T22	4		T1	6		T11	14
all_pins[7]	transitions[0x0=>0x1]	1567543	1			T22	4		T1	3		T11	7
all_pins[7]	transitions[0x1=>0x0]	1563437	1			T22	1		T1	3		T12	2
all_pins[8]	values[0x0]	4280793	1			T21	3		T22	8		T1	9
all_pins[8]	values[0x1]	2631590	1			T22	10		T1	4		T11	7
all_pins[8]	transitions[0x0=>0x1]	1575400	1			T22	7		T1	2		T11	5
all_pins[8]	transitions[0x1=>0x0]	1569106	1			T22	1		T1	4		T11	12
all_pins[9]	values[0x0]	4283874	1			T21	3		T22	18		T1	11
all_pins[9]	values[0x1]	2628509	1			T1	2		T11	5		T12	3
all_pins[9]	transitions[0x0=>0x1]	1569830	1			T1	1		T11	4		T12	3
all_pins[9]	transitions[0x1=>0x0]	1572911	1			T22	10		T1	3		T11	6
all_pins[10]	values[0x0]	4281444	1			T21	2		T22	11		T1	9
all_pins[10]	values[0x1]	2630939	1			T21	1		T22	7		T1	4
all_pins[10]	transitions[0x0=>0x1]	1571148	1			T21	1		T22	7		T1	2
all_pins[10]	transitions[0x1=>0x0]	1568718	1			T11	4		T12	3		T2	10
all_pins[11]	values[0x0]	4284880	1			T21	3		T22	15		T1	10
all_pins[11]	values[0x1]	2627503	1			T22	3		T1	3		T11	9
all_pins[11]	transitions[0x0=>0x1]	1569412	1			T22	3		T1	3		T11	7
all_pins[11]	transitions[0x1=>0x0]	1572848	1			T21	1		T22	7		T1	4
all_pins[12]	values[0x0]	4291960	1			T21	3		T22	9		T1	9
all_pins[12]	values[0x1]	2620423	1			T22	9		T1	4		T11	10
all_pins[12]	transitions[0x0=>0x1]	1570189	1			T22	9		T1	2		T11	6
all_pins[12]	transitions[0x1=>0x0]	1577269	1			T22	3		T1	1		T11	5
all_pins[13]	values[0x0]	4284830	1			T21	3		T22	10		T1	8
all_pins[13]	values[0x1]	2627553	1			T22	8		T1	5		T11	4
all_pins[13]	transitions[0x0=>0x1]	1572300	1			T22	3		T1	2		T11	3
all_pins[13]	transitions[0x1=>0x0]	1565170	1			T22	4		T1	1		T11	9
all_pins[14]	values[0x0]	4289040	1			T21	2		T22	12		T1	10
all_pins[14]	values[0x1]	2623343	1			T21	1		T22	6		T1	3
all_pins[14]	transitions[0x0=>0x1]	1566251	1			T21	1		T22	3		T1	2
all_pins[14]	transitions[0x1=>0x0]	1570461	1			T22	5		T1	4		T11	3
all_pins[15]	values[0x0]	4290147	1			T21	3		T22	15		T1	7
all_pins[15]	values[0x1]	2622236	1			T22	3		T1	6		T11	7
all_pins[15]	transitions[0x0=>0x1]	1568439	1			T22	2		T1	4		T11	4
all_pins[15]	transitions[0x1=>0x0]	1569546	1			T21	1		T22	5		T1	1
all_pins[16]	values[0x0]	4280487	1			T21	3		T22	14		T1	11
all_pins[16]	values[0x1]	2631896	1			T22	4		T1	2		T11	11
all_pins[16]	transitions[0x0=>0x1]	1573526	1			T22	4		T11	10		T12	5
all_pins[16]	transitions[0x1=>0x0]	1563866	1			T22	3		T1	4		T11	6
all_pins[17]	values[0x0]	4280534	1			T21	3		T22	15		T1	7
all_pins[17]	values[0x1]	2631849	1			T22	3		T1	6		T11	8
all_pins[17]	transitions[0x0=>0x1]	1573188	1			T22	3		T1	5		T11	8
all_pins[17]	transitions[0x1=>0x0]	1573235	1			T22	4		T1	1		T11	11
all_pins[18]	values[0x0]	4283204	1			T21	3		T22	14		T1	7
all_pins[18]	values[0x1]	2629179	1			T22	4		T1	6		T11	15
all_pins[18]	transitions[0x0=>0x1]	1568599	1			T22	3		T1	5		T11	10
all_pins[18]	transitions[0x1=>0x0]	1571269	1			T22	2		T1	5		T11	3
all_pins[19]	values[0x0]	4289424	1			T21	3		T22	14		T1	10
all_pins[19]	values[0x1]	2622959	1			T22	4		T1	3		T11	12
all_pins[19]	transitions[0x0=>0x1]	1564482	1			T22	3		T1	1		T11	9
all_pins[19]	transitions[0x1=>0x0]	1570702	1			T22	3		T1	4		T11	12
all_pins[20]	values[0x0]	4283133	1			T21	3		T22	18		T1	4
all_pins[20]	values[0x1]	2629250	1			T1	9		T11	8		T12	6
all_pins[20]	transitions[0x0=>0x1]	1572261	1			T1	6		T11	7		T12	4
all_pins[20]	transitions[0x1=>0x0]	1565970	1			T22	4		T11	11		T12	4
all_pins[21]	values[0x0]	4291447	1			T21	3		T22	14		T1	8
all_pins[21]	values[0x1]	2620936	1			T22	4		T1	5		T11	7
all_pins[21]	transitions[0x0=>0x1]	1565687	1			T22	4		T1	1		T11	1
all_pins[21]	transitions[0x1=>0x0]	1574001	1			T1	5		T11	2		T12	3
all_pins[22]	values[0x0]	4280174	1			T21	3		T22	13		T1	5
all_pins[22]	values[0x1]	2632209	1			T22	5		T1	8		T11	18
all_pins[22]	transitions[0x0=>0x1]	1574760	1			T22	4		T1	3		T11	13
all_pins[22]	transitions[0x1=>0x0]	1563487	1			T22	3		T11	2		T12	6
all_pins[23]	values[0x0]	4290853	1			T21	3		T22	8		T1	8
all_pins[23]	values[0x1]	2621530	1			T22	10		T1	5		T11	8
all_pins[23]	transitions[0x0=>0x1]	1566946	1			T22	5		T1	1		T11	4
all_pins[23]	transitions[0x1=>0x0]	1577625	1			T1	4		T11	14		T12	3
all_pins[24]	values[0x0]	4279709	1			T21	2		T22	17		T1	11
all_pins[24]	values[0x1]	2632674	1			T21	1		T22	1		T1	2
all_pins[24]	transitions[0x0=>0x1]	1576076	1			T21	1		T1	2		T11	8
all_pins[24]	transitions[0x1=>0x0]	1564932	1			T22	9		T1	5		T11	8
all_pins[25]	values[0x0]	4286638	1			T21	2		T22	11		T1	10
all_pins[25]	values[0x1]	2625745	1			T21	1		T22	7		T1	3
all_pins[25]	transitions[0x0=>0x1]	1568797	1			T22	6		T1	2		T11	11
all_pins[25]	transitions[0x1=>0x0]	1575726	1			T1	1		T11	8		T12	6
all_pins[26]	values[0x0]	4291330	1			T21	2		T22	16		T1	9
all_pins[26]	values[0x1]	2621053	1			T21	1		T22	2		T1	4
all_pins[26]	transitions[0x0=>0x1]	1567090	1			T22	1		T1	3		T11	6
all_pins[26]	transitions[0x1=>0x0]	1571782	1			T22	6		T1	2		T11	3
all_pins[27]	values[0x0]	4286522	1			T21	3		T22	12		T1	7
all_pins[27]	values[0x1]	2625861	1			T22	6		T1	6		T11	12
all_pins[27]	transitions[0x0=>0x1]	1573640	1			T22	4		T1	4		T11	7
all_pins[27]	transitions[0x1=>0x0]	1568832	1			T21	1		T1	2		T11	9
all_pins[28]	values[0x0]	4284398	1			T21	3		T22	17		T1	11
all_pins[28]	values[0x1]	2627985	1			T22	1		T1	2		T11	9
all_pins[28]	transitions[0x0=>0x1]	1568761	1			T22	1		T1	1		T11	7
all_pins[28]	transitions[0x1=>0x0]	1566637	1			T22	6		T1	5		T11	10
all_pins[29]	values[0x0]	4283465	1			T21	3		T22	14		T1	9
all_pins[29]	values[0x1]	2628918	1			T22	4		T1	4		T11	9
all_pins[29]	transitions[0x0=>0x1]	1573725	1			T22	4		T1	3		T11	6
all_pins[29]	transitions[0x1=>0x0]	1572792	1			T22	1		T1	1		T11	6
all_pins[30]	values[0x0]	4279660	1			T21	2		T22	18		T1	3
all_pins[30]	values[0x1]	2632723	1			T21	1		T1	10		T11	12
all_pins[30]	transitions[0x0=>0x1]	1571271	1			T21	1		T1	6		T11	9
all_pins[30]	transitions[0x1=>0x0]	1567466	1			T22	4		T11	6		T12	6
all_pins[31]	values[0x0]	4285966	1			T21	3		T22	15		T1	8
all_pins[31]	values[0x1]	2626417	1			T22	3		T1	5		T11	7
all_pins[31]	transitions[0x0=>0x1]	1567778	1			T22	3		T1	1		T11	4
all_pins[31]	transitions[0x1=>0x0]	1574084	1			T21	1		T1	6		T11	9