Unified Coverage Report :: Group :: cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=31}

Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=31}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=31}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	192	0	192	100.00

Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=31}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	32	0	32	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2
cp_intr_test	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=31}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_test_cg_cc	192	0	192	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	32	0	32	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	22812075	1			T21	3		T22	21		T1	24
all_values[1]	22812075	1			T21	3		T22	21		T1	24
all_values[2]	22812075	1			T21	3		T22	21		T1	24
all_values[3]	22812075	1			T21	3		T22	21		T1	24
all_values[4]	22812075	1			T21	3		T22	21		T1	24
all_values[5]	22812075	1			T21	3		T22	21		T1	24
all_values[6]	22812075	1			T21	3		T22	21		T1	24
all_values[7]	22812075	1			T21	3		T22	21		T1	24
all_values[8]	22812075	1			T21	3		T22	21		T1	24
all_values[9]	22812075	1			T21	3		T22	21		T1	24
all_values[10]	22812075	1			T21	3		T22	21		T1	24
all_values[11]	22812075	1			T21	3		T22	21		T1	24
all_values[12]	22812075	1			T21	3		T22	21		T1	24
all_values[13]	22812075	1			T21	3		T22	21		T1	24
all_values[14]	22812075	1			T21	3		T22	21		T1	24
all_values[15]	22812075	1			T21	3		T22	21		T1	24
all_values[16]	22812075	1			T21	3		T22	21		T1	24
all_values[17]	22812075	1			T21	3		T22	21		T1	24
all_values[18]	22812075	1			T21	3		T22	21		T1	24
all_values[19]	22812075	1			T21	3		T22	21		T1	24
all_values[20]	22812075	1			T21	3		T22	21		T1	24
all_values[21]	22812075	1			T21	3		T22	21		T1	24
all_values[22]	22812075	1			T21	3		T22	21		T1	24
all_values[23]	22812075	1			T21	3		T22	21		T1	24
all_values[24]	22812075	1			T21	3		T22	21		T1	24
all_values[25]	22812075	1			T21	3		T22	21		T1	24
all_values[26]	22812075	1			T21	3		T22	21		T1	24
all_values[27]	22812075	1			T21	3		T22	21		T1	24
all_values[28]	22812075	1			T21	3		T22	21		T1	24
all_values[29]	22812075	1			T21	3		T22	21		T1	24
all_values[30]	22812075	1			T21	3		T22	21		T1	24
all_values[31]	22812075	1			T21	3		T22	21		T1	24

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

401085135

1

T21

84

T22

371

T1

424

auto[1]

328901265

1

T21

12

T22

301

T1

344

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

133416909

1

T21

76

T22

370

T1

357

auto[1]

596569491

1

T21

20

T22

302

T1

411

---

Summary for Variable cp_intr_test

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_test

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

721635771

1

T21

96

T22

573

T1

768

auto[1]

8350629

1

T22

99

T16

141

T18

142

---

Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	192	0	192	100.00
Automatically Generated Cross Bins	192	0	192	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for intr_test_cg_cc

Bins

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	auto[0]	3199673	1			T21	2		T22	6		T1	3
all_values[0]	auto[0]	auto[0]	auto[1]	9209970	1			T22	5		T1	2		T11	4
all_values[0]	auto[0]	auto[1]	auto[0]	965332	1			T21	1		T22	3		T1	19
all_values[0]	auto[0]	auto[1]	auto[1]	9176412	1			T22	3		T11	1		T12	2
all_values[0]	auto[1]	auto[0]	auto[1]	130839	1			T22	1		T16	7		T18	3
all_values[0]	auto[1]	auto[1]	auto[1]	129849	1			T22	3		T18	3		T103	3
all_values[1]	auto[0]	auto[0]	auto[0]	3218409	1			T21	2		T22	5		T1	5
all_values[1]	auto[0]	auto[0]	auto[1]	9227002	1			T21	1		T22	4		T11	4
all_values[1]	auto[0]	auto[1]	auto[0]	960699	1			T22	4		T11	3		T12	3
all_values[1]	auto[0]	auto[1]	auto[1]	9144813	1			T22	4		T1	19		T11	3
all_values[1]	auto[1]	auto[0]	auto[1]	130715	1			T22	3		T16	2		T18	4
all_values[1]	auto[1]	auto[1]	auto[1]	130437	1			T22	1		T16	1		T19	1
all_values[2]	auto[0]	auto[0]	auto[0]	3207307	1			T21	2		T22	1		T1	2
all_values[2]	auto[0]	auto[0]	auto[1]	9187192	1			T21	1		T22	6		T11	5
all_values[2]	auto[0]	auto[1]	auto[0]	945000	1			T22	1		T1	19		T11	3
all_values[2]	auto[0]	auto[1]	auto[1]	9211244	1			T22	10		T1	3		T11	2
all_values[2]	auto[1]	auto[0]	auto[1]	130591	1			T22	1		T16	5		T18	1
all_values[2]	auto[1]	auto[1]	auto[1]	130741	1			T22	2		T18	3		T103	2
all_values[3]	auto[0]	auto[0]	auto[0]	3205253	1			T21	2		T22	6		T1	8
all_values[3]	auto[0]	auto[0]	auto[1]	9197968	1			T21	1		T22	4		T1	3
all_values[3]	auto[0]	auto[1]	auto[0]	947636	1			T22	4		T1	13		T11	1
all_values[3]	auto[0]	auto[1]	auto[1]	9200615	1			T22	4		T11	4		T12	1
all_values[3]	auto[1]	auto[0]	auto[1]	129824	1			T22	2		T16	4		T18	6
all_values[3]	auto[1]	auto[1]	auto[1]	130779	1			T22	1		T16	2		T18	1
all_values[4]	auto[0]	auto[0]	auto[0]	3208022	1			T21	2		T22	13		T1	2
all_values[4]	auto[0]	auto[0]	auto[1]	9161750	1			T1	19		T11	5		T12	1
all_values[4]	auto[0]	auto[1]	auto[0]	973981	1			T21	1		T22	4		T1	3
all_values[4]	auto[0]	auto[1]	auto[1]	9207561	1			T22	1		T11	1		T12	2
all_values[4]	auto[1]	auto[0]	auto[1]	130746	1			T22	1		T16	2		T18	6
all_values[4]	auto[1]	auto[1]	auto[1]	130015	1			T22	2		T16	3		T18	2
all_values[5]	auto[0]	auto[0]	auto[0]	3213930	1			T21	2		T22	6		T1	2
all_values[5]	auto[0]	auto[0]	auto[1]	9187642	1			T21	1		T22	3		T1	9
all_values[5]	auto[0]	auto[1]	auto[0]	967952	1			T22	4		T11	2		T12	3
all_values[5]	auto[0]	auto[1]	auto[1]	9181498	1			T22	4		T1	13		T11	3
all_values[5]	auto[1]	auto[0]	auto[1]	129862	1			T22	1		T16	1		T18	4
all_values[5]	auto[1]	auto[1]	auto[1]	131191	1			T22	3		T16	2		T18	1
all_values[6]	auto[0]	auto[0]	auto[0]	3219269	1			T21	3		T22	11		T1	2
all_values[6]	auto[0]	auto[0]	auto[1]	9213333	1			T1	19		T11	4		T12	3
all_values[6]	auto[0]	auto[1]	auto[0]	964806	1			T22	9		T1	3		T11	7
all_values[6]	auto[0]	auto[1]	auto[1]	9153168	1			T12	1		T2	14		T14	1
all_values[6]	auto[1]	auto[0]	auto[1]	131249	1			T16	2		T18	4		T19	2
all_values[6]	auto[1]	auto[1]	auto[1]	130250	1			T22	1		T16	1		T18	1
all_values[7]	auto[0]	auto[0]	auto[0]	3210688	1			T21	2		T22	5		T1	2
all_values[7]	auto[0]	auto[0]	auto[1]	9212402	1			T21	1		T22	8		T1	6
all_values[7]	auto[0]	auto[1]	auto[0]	960119	1			T22	2		T1	13		T11	3
all_values[7]	auto[0]	auto[1]	auto[1]	9168041	1			T22	3		T1	3		T11	4
all_values[7]	auto[1]	auto[0]	auto[1]	131031	1			T22	2		T16	1		T18	5
all_values[7]	auto[1]	auto[1]	auto[1]	129794	1			T22	1		T16	3		T18	1
all_values[8]	auto[0]	auto[0]	auto[0]	3203832	1			T21	2		T22	6		T1	2
all_values[8]	auto[0]	auto[0]	auto[1]	9165320	1			T21	1		T22	1		T1	6
all_values[8]	auto[0]	auto[1]	auto[0]	961373	1			T22	3		T1	3		T11	4
all_values[8]	auto[0]	auto[1]	auto[1]	9220481	1			T22	8		T1	13		T11	2
all_values[8]	auto[1]	auto[0]	auto[1]	130348	1			T16	4		T18	2		T19	3
all_values[8]	auto[1]	auto[1]	auto[1]	130721	1			T22	3		T16	1		T18	2
all_values[9]	auto[0]	auto[0]	auto[0]	3212076	1			T21	2		T22	14		T1	5
all_values[9]	auto[0]	auto[0]	auto[1]	9191082	1			T21	1		T22	1		T1	19
all_values[9]	auto[0]	auto[1]	auto[0]	965922	1			T22	3		T11	4		T12	3
all_values[9]	auto[0]	auto[1]	auto[1]	9181555	1			T2	24		T16	6		T18	2
all_values[9]	auto[1]	auto[0]	auto[1]	130386	1			T22	3		T16	1		T18	2
all_values[9]	auto[1]	auto[1]	auto[1]	131054	1			T16	2		T18	2		T103	4
all_values[10]	auto[0]	auto[0]	auto[0]	3208256	1			T21	2		T22	3		T1	5
all_values[10]	auto[0]	auto[0]	auto[1]	9190392	1			T22	4		T1	6		T11	7
all_values[10]	auto[0]	auto[1]	auto[0]	951003	1			T22	6		T1	2		T11	2
all_values[10]	auto[0]	auto[1]	auto[1]	9201269	1			T21	1		T22	5		T1	11
all_values[10]	auto[1]	auto[0]	auto[1]	130810	1			T16	3		T18	3		T103	4
all_values[10]	auto[1]	auto[1]	auto[1]	130345	1			T22	3		T16	1		T103	2
all_values[11]	auto[0]	auto[0]	auto[0]	3212812	1			T21	2		T22	7		T1	4
all_values[11]	auto[0]	auto[0]	auto[1]	9184603	1			T21	1		T22	5		T1	20
all_values[11]	auto[0]	auto[1]	auto[0]	960576	1			T22	3		T11	3		T12	6
all_values[11]	auto[0]	auto[1]	auto[1]	9193793	1			T22	2		T11	4		T2	12
all_values[11]	auto[1]	auto[0]	auto[1]	130772	1			T22	3		T16	2		T18	1
all_values[11]	auto[1]	auto[1]	auto[1]	129519	1			T22	1		T16	5		T18	1
all_values[12]	auto[0]	auto[0]	auto[0]	3221385	1			T21	2		T22	3		T1	2
all_values[12]	auto[0]	auto[0]	auto[1]	9206428	1			T21	1		T22	1		T1	6
all_values[12]	auto[0]	auto[1]	auto[0]	961178	1			T22	5		T1	16		T11	5
all_values[12]	auto[0]	auto[1]	auto[1]	9162109	1			T22	8		T11	2		T12	1
all_values[12]	auto[1]	auto[0]	auto[1]	131041	1			T22	2		T16	3		T103	3
all_values[12]	auto[1]	auto[1]	auto[1]	129934	1			T22	2		T16	1		T18	3
all_values[13]	auto[0]	auto[0]	auto[0]	3212800	1			T21	3		T22	4		T1	2
all_values[13]	auto[0]	auto[0]	auto[1]	9242339	1			T1	3		T11	7		T12	1
all_values[13]	auto[0]	auto[1]	auto[0]	963606	1			T22	8		T1	19		T11	3
all_values[13]	auto[0]	auto[1]	auto[1]	9132877	1			T22	5		T11	1		T2	12
all_values[13]	auto[1]	auto[0]	auto[1]	131086	1			T16	1		T18	1		T103	3
all_values[13]	auto[1]	auto[1]	auto[1]	129367	1			T22	4		T16	2		T18	4
all_values[14]	auto[0]	auto[0]	auto[0]	3210358	1			T21	2		T22	10		T1	2
all_values[14]	auto[0]	auto[0]	auto[1]	9194411	1			T22	2		T1	22		T11	7
all_values[14]	auto[0]	auto[1]	auto[0]	965479	1			T22	2		T11	3		T12	3
all_values[14]	auto[0]	auto[1]	auto[1]	9181045	1			T21	1		T22	4		T11	4
all_values[14]	auto[1]	auto[0]	auto[1]	130366	1			T22	1		T16	3		T18	3
all_values[14]	auto[1]	auto[1]	auto[1]	130416	1			T22	2		T16	3		T18	2
all_values[15]	auto[0]	auto[0]	auto[0]	3202954	1			T21	2		T22	9		T1	2
all_values[15]	auto[0]	auto[0]	auto[1]	9225796	1			T21	1		T1	3		T11	3
all_values[15]	auto[0]	auto[1]	auto[0]	961164	1			T22	7		T11	6		T12	1
all_values[15]	auto[0]	auto[1]	auto[1]	9161384	1			T22	3		T1	19		T11	2
all_values[15]	auto[1]	auto[0]	auto[1]	131234	1			T22	1		T16	3		T18	1
all_values[15]	auto[1]	auto[1]	auto[1]	129543	1			T22	1		T16	1		T103	5
all_values[16]	auto[0]	auto[0]	auto[0]	3212487	1			T21	3		T22	4		T1	15
all_values[16]	auto[0]	auto[0]	auto[1]	9167695	1			T22	9		T1	3		T11	4
all_values[16]	auto[0]	auto[1]	auto[0]	954043	1			T1	6		T11	6		T12	3
all_values[16]	auto[0]	auto[1]	auto[1]	9217140	1			T22	3		T11	4		T12	2
all_values[16]	auto[1]	auto[0]	auto[1]	129655	1			T22	4		T16	1		T18	4
all_values[16]	auto[1]	auto[1]	auto[1]	131055	1			T22	1		T16	3		T18	2
all_values[17]	auto[0]	auto[0]	auto[0]	3209828	1			T21	3		T22	7		T1	2
all_values[17]	auto[0]	auto[0]	auto[1]	9202625	1			T22	6		T1	6		T11	3
all_values[17]	auto[0]	auto[1]	auto[0]	959663	1			T22	2		T11	4		T12	4
all_values[17]	auto[0]	auto[1]	auto[1]	9178887	1			T22	2		T1	16		T11	2
all_values[17]	auto[1]	auto[0]	auto[1]	130856	1			T22	3		T16	5		T103	3
all_values[17]	auto[1]	auto[1]	auto[1]	130216	1			T22	1		T18	2		T103	1
all_values[18]	auto[0]	auto[0]	auto[0]	3203663	1			T21	3		T22	1		T1	2
all_values[18]	auto[0]	auto[0]	auto[1]	9185544	1			T22	1		T1	16		T11	5
all_values[18]	auto[0]	auto[1]	auto[0]	961663	1			T22	14		T11	5		T12	4
all_values[18]	auto[0]	auto[1]	auto[1]	9200368	1			T22	3		T1	6		T11	3
all_values[18]	auto[1]	auto[0]	auto[1]	131102	1			T22	1		T16	3		T103	1
all_values[18]	auto[1]	auto[1]	auto[1]	129735	1			T22	1		T16	5		T18	4
all_values[19]	auto[0]	auto[0]	auto[0]	3221105	1			T21	2		T22	8		T1	2
all_values[19]	auto[0]	auto[0]	auto[1]	9241161	1			T22	3		T11	3		T12	1
all_values[19]	auto[0]	auto[1]	auto[0]	962056	1			T21	1		T22	5		T1	3
all_values[19]	auto[0]	auto[1]	auto[1]	9126614	1			T22	2		T1	19		T11	3
all_values[19]	auto[1]	auto[0]	auto[1]	131684	1			T22	1		T16	1		T18	2
all_values[19]	auto[1]	auto[1]	auto[1]	129455	1			T22	2		T16	3		T18	2
all_values[20]	auto[0]	auto[0]	auto[0]	3199056	1			T21	2		T22	7		T1	2
all_values[20]	auto[0]	auto[0]	auto[1]	9160422	1			T22	3		T11	7		T2	8
all_values[20]	auto[0]	auto[1]	auto[0]	954659	1			T21	1		T22	9		T1	22
all_values[20]	auto[0]	auto[1]	auto[1]	9236425	1			T11	2		T12	1		T2	24
all_values[20]	auto[1]	auto[0]	auto[1]	131181	1			T22	2		T16	3		T18	1
all_values[20]	auto[1]	auto[1]	auto[1]	130332	1			T16	1		T18	4		T103	1
all_values[21]	auto[0]	auto[0]	auto[0]	3200178	1			T21	3		T22	7		T1	2
all_values[21]	auto[0]	auto[0]	auto[1]	9233253	1			T22	3		T1	19		T11	7
all_values[21]	auto[0]	auto[1]	auto[0]	957959	1			T22	5		T11	4		T12	2
all_values[21]	auto[0]	auto[1]	auto[1]	9160128	1			T22	4		T1	3		T11	2
all_values[21]	auto[1]	auto[0]	auto[1]	130408	1			T22	2		T16	1		T18	1
all_values[21]	auto[1]	auto[1]	auto[1]	130149	1			T16	3		T18	3		T103	2
all_values[22]	auto[0]	auto[0]	auto[0]	3223596	1			T21	2		T22	13		T1	15
all_values[22]	auto[0]	auto[0]	auto[1]	9194512	1			T21	1		T11	3		T12	1
all_values[22]	auto[0]	auto[1]	auto[0]	958680	1			T22	3		T1	1		T11	2
all_values[22]	auto[0]	auto[1]	auto[1]	9173933	1			T22	4		T1	8		T11	6
all_values[22]	auto[1]	auto[0]	auto[1]	130936	1			T16	3		T18	1		T103	1
all_values[22]	auto[1]	auto[1]	auto[1]	130418	1			T22	1		T18	2		T103	5
all_values[23]	auto[0]	auto[0]	auto[0]	3215379	1			T21	2		T22	3		T1	2
all_values[23]	auto[0]	auto[0]	auto[1]	9160316	1			T21	1		T22	3		T11	2
all_values[23]	auto[0]	auto[1]	auto[0]	954016	1			T22	3		T11	5		T12	4
all_values[23]	auto[0]	auto[1]	auto[1]	9221697	1			T22	8		T1	22		T11	2
all_values[23]	auto[1]	auto[0]	auto[1]	130267	1			T22	1		T18	2		T103	2
all_values[23]	auto[1]	auto[1]	auto[1]	130400	1			T22	3		T16	2		T18	4
all_values[24]	auto[0]	auto[0]	auto[0]	3204099	1			T21	2		T22	8		T1	2
all_values[24]	auto[0]	auto[0]	auto[1]	9171112	1			T22	2		T1	22		T11	5
all_values[24]	auto[0]	auto[1]	auto[0]	958828	1			T22	9		T11	6		T12	1
all_values[24]	auto[0]	auto[1]	auto[1]	9217157	1			T21	1		T11	2		T12	3
all_values[24]	auto[1]	auto[0]	auto[1]	130224	1			T22	1		T16	1		T18	1
all_values[24]	auto[1]	auto[1]	auto[1]	130655	1			T22	1		T16	2		T18	2
all_values[25]	auto[0]	auto[0]	auto[0]	3196882	1			T21	2		T22	4		T1	24
all_values[25]	auto[0]	auto[0]	auto[1]	9166556	1			T22	3		T11	6		T12	3
all_values[25]	auto[0]	auto[1]	auto[0]	956939	1			T22	6		T11	5		T12	1
all_values[25]	auto[0]	auto[1]	auto[1]	9230594	1			T21	1		T22	6		T11	1
all_values[25]	auto[1]	auto[0]	auto[1]	130486	1			T16	4		T18	2		T103	3
all_values[25]	auto[1]	auto[1]	auto[1]	130618	1			T22	2		T16	1		T18	4
all_values[26]	auto[0]	auto[0]	auto[0]	3219214	1			T21	2		T22	9		T1	15
all_values[26]	auto[0]	auto[0]	auto[1]	9208167	1			T1	3		T11	4		T12	1
all_values[26]	auto[0]	auto[1]	auto[0]	956860	1			T22	10		T1	6		T11	3
all_values[26]	auto[0]	auto[1]	auto[1]	9166696	1			T21	1		T11	4		T12	1
all_values[26]	auto[1]	auto[0]	auto[1]	131157	1			T16	1		T18	3		T103	3
all_values[26]	auto[1]	auto[1]	auto[1]	129981	1			T22	2		T16	2		T103	2
all_values[27]	auto[0]	auto[0]	auto[0]	3203372	1			T21	2		T22	6		T1	2
all_values[27]	auto[0]	auto[0]	auto[1]	9205667	1			T21	1		T22	2		T1	19
all_values[27]	auto[0]	auto[1]	auto[0]	950378	1			T22	4		T11	5		T12	1
all_values[27]	auto[0]	auto[1]	auto[1]	9191765	1			T22	4		T1	3		T11	3
all_values[27]	auto[1]	auto[0]	auto[1]	131091	1			T22	3		T16	2		T18	4
all_values[27]	auto[1]	auto[1]	auto[1]	129802	1			T22	2		T16	2		T18	1
all_values[28]	auto[0]	auto[0]	auto[0]	3215196	1			T21	2		T22	4		T1	21
all_values[28]	auto[0]	auto[0]	auto[1]	9195843	1			T22	11		T11	6		T12	1
all_values[28]	auto[0]	auto[1]	auto[0]	965494	1			T21	1		T22	2		T1	3
all_values[28]	auto[0]	auto[1]	auto[1]	9174393	1			T11	3		T12	2		T2	12
all_values[28]	auto[1]	auto[0]	auto[1]	130863	1			T22	3		T16	4		T18	6
all_values[28]	auto[1]	auto[1]	auto[1]	130286	1			T22	1		T16	1		T103	3
all_values[29]	auto[0]	auto[0]	auto[0]	3202666	1			T21	2		T22	10		T1	24
all_values[29]	auto[0]	auto[0]	auto[1]	9195404	1			T22	2		T11	4		T12	1
all_values[29]	auto[0]	auto[1]	auto[0]	962265	1			T21	1		T22	1		T11	3
all_values[29]	auto[0]	auto[1]	auto[1]	9190780	1			T22	5		T11	3		T12	1
all_values[29]	auto[1]	auto[0]	auto[1]	130919	1			T22	3		T16	1		T18	5
all_values[29]	auto[1]	auto[1]	auto[1]	130041	1			T16	3		T103	4		T20	1
all_values[30]	auto[0]	auto[0]	auto[0]	3202903	1			T21	2		T22	14		T1	2
all_values[30]	auto[0]	auto[0]	auto[1]	9143633	1			T22	1		T11	4		T12	3
all_values[30]	auto[0]	auto[1]	auto[0]	960229	1			T22	1		T1	19		T11	2
all_values[30]	auto[0]	auto[1]	auto[1]	9244335	1			T21	1		T1	3		T11	4
all_values[30]	auto[1]	auto[0]	auto[1]	131047	1			T22	5		T16	1		T18	1
all_values[30]	auto[1]	auto[1]	auto[1]	129928	1			T16	4		T18	2		T103	3
all_values[31]	auto[0]	auto[0]	auto[0]	3207439	1			T21	2		T22	10		T1	5
all_values[31]	auto[0]	auto[0]	auto[1]	9168197	1			T21	1		T22	2		T1	6
all_values[31]	auto[0]	auto[1]	auto[0]	963264	1			T22	4		T11	4		T12	2
all_values[31]	auto[0]	auto[1]	auto[1]	9212348	1			T22	3		T1	13		T11	2
all_values[31]	auto[1]	auto[0]	auto[1]	130535	1			T22	2		T16	3		T18	2
all_values[31]	auto[1]	auto[1]	auto[1]	130292	1			T16	3		T18	3		T103	2

User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins

NAME	COUNT	STATUS
test_1_state_0	0	Illegal