Unified Coverage Report :: Group :: gpio_env_pkg::gpio_env_cov::data_out_data_oe_data_in_cross_cg

Group : gpio_env_pkg::gpio_env_cov::data_out_data_oe_data_in_cross_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_gpio_env_0.1/gpio_env_cov.sv

---

Summary for Group gpio_env_pkg::gpio_env_cov::data_out_data_oe_data_in_cross_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	192	0	192	100.00

Variables for Group gpio_env_pkg::gpio_env_cov::data_out_data_oe_data_in_cross_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_pin	32	0	32	100.00	100	1	1	0
data_in	2	0	2	100.00	100	1	1	2
data_oe	2	0	2	100.00	100	1	1	2
data_out	2	0	2	100.00	100	1	1	2

Crosses for Group gpio_env_pkg::gpio_env_cov::data_out_data_oe_data_in_cross_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_cross_all	192	0	192	100.00	100	1	1	0

Summary for Variable cp_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	32	0	32	100.00

User Defined Bins for cp_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
bins_for_gpio_bits[0]	22434776	1			T21	3		T22	1		T1	24
bins_for_gpio_bits[1]	22434776	1			T21	3		T22	1		T1	24
bins_for_gpio_bits[2]	22434776	1			T21	3		T22	1		T1	24
bins_for_gpio_bits[3]	22434776	1			T21	3		T22	1		T1	24
bins_for_gpio_bits[4]	22434776	1			T21	3		T22	1		T1	24
bins_for_gpio_bits[5]	22434776	1			T21	3		T22	1		T1	24
bins_for_gpio_bits[6]	22434776	1			T21	3		T22	1		T1	24
bins_for_gpio_bits[7]	22434776	1			T21	3		T22	1		T1	24
bins_for_gpio_bits[8]	22434776	1			T21	3		T22	1		T1	24
bins_for_gpio_bits[9]	22434776	1			T21	3		T22	1		T1	24
bins_for_gpio_bits[10]	22434776	1			T21	3		T22	1		T1	24
bins_for_gpio_bits[11]	22434776	1			T21	3		T22	1		T1	24
bins_for_gpio_bits[12]	22434776	1			T21	3		T22	1		T1	24
bins_for_gpio_bits[13]	22434776	1			T21	3		T22	1		T1	24
bins_for_gpio_bits[14]	22434776	1			T21	3		T22	1		T1	24
bins_for_gpio_bits[15]	22434776	1			T21	3		T22	1		T1	24
bins_for_gpio_bits[16]	22434776	1			T21	3		T22	1		T1	24
bins_for_gpio_bits[17]	22434776	1			T21	3		T22	1		T1	24
bins_for_gpio_bits[18]	22434776	1			T21	3		T22	1		T1	24
bins_for_gpio_bits[19]	22434776	1			T21	3		T22	1		T1	24
bins_for_gpio_bits[20]	22434776	1			T21	3		T22	1		T1	24
bins_for_gpio_bits[21]	22434776	1			T21	3		T22	1		T1	24
bins_for_gpio_bits[22]	22434776	1			T21	3		T22	1		T1	24
bins_for_gpio_bits[23]	22434776	1			T21	3		T22	1		T1	24
bins_for_gpio_bits[24]	22434776	1			T21	3		T22	1		T1	24
bins_for_gpio_bits[25]	22434776	1			T21	3		T22	1		T1	24
bins_for_gpio_bits[26]	22434776	1			T21	3		T22	1		T1	24
bins_for_gpio_bits[27]	22434776	1			T21	3		T22	1		T1	24
bins_for_gpio_bits[28]	22434776	1			T21	3		T22	1		T1	24
bins_for_gpio_bits[29]	22434776	1			T21	3		T22	1		T1	24
bins_for_gpio_bits[30]	22434776	1			T21	3		T22	1		T1	24
bins_for_gpio_bits[31]	22434776	1			T21	3		T22	1		T1	24

---

Summary for Variable data_in

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for data_in

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

439807272

1

T21

96

T22

32

T1

768

auto[1]

278105560

1

T39

6793

T40

4032

T41

7462

---

Summary for Variable data_oe

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for data_oe

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

570382303

1

T21

96

T22

32

T1

768

auto[1]

147530529

1

T39

8660

T40

6798

T41

3039

---

Summary for Variable data_out

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for data_out

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

527003631

1

T21

96

T22

32

T1

768

auto[1]

190909201

1

T39

8546

T40

6776

T41

2930

---

Summary for Cross cp_cross_all

Samples crossed: cp_pin data_out data_oe data_in

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	192	0	192	100.00
Automatically Generated Cross Bins	192	0	192	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cp_cross_all

Bins

cp_pin	data_out	data_oe	data_in	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
bins_for_gpio_bits[0]	auto[0]	auto[0]	auto[0]	8346779	1			T21	3		T22	1		T1	24
bins_for_gpio_bits[0]	auto[0]	auto[0]	auto[1]	5800929	1			T39	69		T40	19		T41	146
bins_for_gpio_bits[0]	auto[0]	auto[1]	auto[0]	2318091	1			T39	148		T40	126		T41	49
bins_for_gpio_bits[0]	auto[1]	auto[0]	auto[0]	3072058	1			T39	131		T40	97		T51	34
bins_for_gpio_bits[0]	auto[1]	auto[0]	auto[1]	596910	1			T41	40		T50	78		T53	124
bins_for_gpio_bits[0]	auto[1]	auto[1]	auto[1]	2300009	1			T39	148		T40	90		T41	48
bins_for_gpio_bits[1]	auto[0]	auto[0]	auto[0]	8360872	1			T21	3		T22	1		T1	24
bins_for_gpio_bits[1]	auto[0]	auto[0]	auto[1]	5792607	1			T39	69		T40	20		T41	148
bins_for_gpio_bits[1]	auto[0]	auto[1]	auto[0]	2323593	1			T39	154		T40	106		T41	36
bins_for_gpio_bits[1]	auto[1]	auto[0]	auto[0]	3061989	1			T39	142		T40	78		T51	28
bins_for_gpio_bits[1]	auto[1]	auto[0]	auto[1]	597508	1			T41	47		T50	86		T53	108
bins_for_gpio_bits[1]	auto[1]	auto[1]	auto[1]	2298207	1			T39	110		T40	110		T41	64
bins_for_gpio_bits[2]	auto[0]	auto[0]	auto[0]	8349450	1			T21	3		T22	1		T1	24
bins_for_gpio_bits[2]	auto[0]	auto[0]	auto[1]	5796172	1			T39	81		T40	19		T41	136
bins_for_gpio_bits[2]	auto[0]	auto[1]	auto[0]	2323429	1			T39	144		T40	93		T41	44
bins_for_gpio_bits[2]	auto[1]	auto[0]	auto[0]	3070086	1			T39	128		T40	120		T51	41
bins_for_gpio_bits[2]	auto[1]	auto[0]	auto[1]	596045	1			T41	42		T50	68		T53	120
bins_for_gpio_bits[2]	auto[1]	auto[1]	auto[1]	2299594	1			T39	140		T40	104		T41	49
bins_for_gpio_bits[3]	auto[0]	auto[0]	auto[0]	8347010	1			T21	3		T22	1		T1	24
bins_for_gpio_bits[3]	auto[0]	auto[0]	auto[1]	5792355	1			T39	73		T40	20		T41	155
bins_for_gpio_bits[3]	auto[0]	auto[1]	auto[0]	2320995	1			T39	121		T40	94		T41	44
bins_for_gpio_bits[3]	auto[1]	auto[0]	auto[0]	3065981	1			T39	124		T40	104		T51	38
bins_for_gpio_bits[3]	auto[1]	auto[0]	auto[1]	601206	1			T41	40		T50	76		T53	100
bins_for_gpio_bits[3]	auto[1]	auto[1]	auto[1]	2307229	1			T39	136		T40	115		T41	40
bins_for_gpio_bits[4]	auto[0]	auto[0]	auto[0]	8346159	1			T21	3		T22	1		T1	24
bins_for_gpio_bits[4]	auto[0]	auto[0]	auto[1]	5799728	1			T39	75		T40	21		T41	138
bins_for_gpio_bits[4]	auto[0]	auto[1]	auto[0]	2317231	1			T39	156		T40	88		T41	48
bins_for_gpio_bits[4]	auto[1]	auto[0]	auto[0]	3074954	1			T39	83		T40	104		T51	34
bins_for_gpio_bits[4]	auto[1]	auto[0]	auto[1]	596275	1			T41	50		T50	81		T53	126
bins_for_gpio_bits[4]	auto[1]	auto[1]	auto[1]	2300429	1			T39	128		T40	100		T41	45
bins_for_gpio_bits[5]	auto[0]	auto[0]	auto[0]	8344899	1			T21	3		T22	1		T1	24
bins_for_gpio_bits[5]	auto[0]	auto[0]	auto[1]	5805640	1			T39	79		T40	15		T41	134
bins_for_gpio_bits[5]	auto[0]	auto[1]	auto[0]	2322671	1			T39	136		T40	125		T41	51
bins_for_gpio_bits[5]	auto[1]	auto[0]	auto[0]	3068256	1			T39	119		T40	84		T51	28
bins_for_gpio_bits[5]	auto[1]	auto[0]	auto[1]	596311	1			T41	50		T50	118		T53	104
bins_for_gpio_bits[5]	auto[1]	auto[1]	auto[1]	2296999	1			T39	104		T40	112		T41	50
bins_for_gpio_bits[6]	auto[0]	auto[0]	auto[0]	8364087	1			T21	3		T22	1		T1	24
bins_for_gpio_bits[6]	auto[0]	auto[0]	auto[1]	5798069	1			T39	79		T40	14		T41	131
bins_for_gpio_bits[6]	auto[0]	auto[1]	auto[0]	2316596	1			T39	138		T40	100		T41	56
bins_for_gpio_bits[6]	auto[1]	auto[0]	auto[0]	3064550	1			T39	136		T40	103		T51	23
bins_for_gpio_bits[6]	auto[1]	auto[0]	auto[1]	597113	1			T41	40		T50	74		T53	90
bins_for_gpio_bits[6]	auto[1]	auto[1]	auto[1]	2294361	1			T39	135		T40	88		T41	60
bins_for_gpio_bits[7]	auto[0]	auto[0]	auto[0]	8350728	1			T21	3		T22	1		T1	24
bins_for_gpio_bits[7]	auto[0]	auto[0]	auto[1]	5802037	1			T39	80		T40	23		T41	121
bins_for_gpio_bits[7]	auto[0]	auto[1]	auto[0]	2320834	1			T39	132		T40	108		T41	52
bins_for_gpio_bits[7]	auto[1]	auto[0]	auto[0]	3065510	1			T39	126		T40	122		T51	34
bins_for_gpio_bits[7]	auto[1]	auto[0]	auto[1]	598490	1			T41	31		T50	74		T53	118
bins_for_gpio_bits[7]	auto[1]	auto[1]	auto[1]	2297177	1			T39	161		T40	97		T41	64
bins_for_gpio_bits[8]	auto[0]	auto[0]	auto[0]	8356793	1			T21	3		T22	1		T1	24
bins_for_gpio_bits[8]	auto[0]	auto[0]	auto[1]	5789160	1			T39	74		T40	16		T41	141
bins_for_gpio_bits[8]	auto[0]	auto[1]	auto[0]	2322016	1			T39	154		T40	92		T41	44
bins_for_gpio_bits[8]	auto[1]	auto[0]	auto[0]	3068908	1			T39	138		T40	123		T51	28
bins_for_gpio_bits[8]	auto[1]	auto[0]	auto[1]	598351	1			T41	44		T50	46		T53	124
bins_for_gpio_bits[8]	auto[1]	auto[1]	auto[1]	2299548	1			T39	134		T40	92		T41	36
bins_for_gpio_bits[9]	auto[0]	auto[0]	auto[0]	8351205	1			T21	3		T22	1		T1	24
bins_for_gpio_bits[9]	auto[0]	auto[0]	auto[1]	5789132	1			T39	72		T40	22		T41	129
bins_for_gpio_bits[9]	auto[0]	auto[1]	auto[0]	2313391	1			T39	138		T40	114		T41	60
bins_for_gpio_bits[9]	auto[1]	auto[0]	auto[0]	3074972	1			T39	121		T40	98		T51	30
bins_for_gpio_bits[9]	auto[1]	auto[0]	auto[1]	598271	1			T41	32		T50	84		T53	112
bins_for_gpio_bits[9]	auto[1]	auto[1]	auto[1]	2307805	1			T39	146		T40	90		T41	52
bins_for_gpio_bits[10]	auto[0]	auto[0]	auto[0]	8360892	1			T21	3		T22	1		T1	24
bins_for_gpio_bits[10]	auto[0]	auto[0]	auto[1]	5784878	1			T39	73		T40	24		T41	129
bins_for_gpio_bits[10]	auto[0]	auto[1]	auto[0]	2314874	1			T39	124		T40	119		T41	44
bins_for_gpio_bits[10]	auto[1]	auto[0]	auto[0]	3075446	1			T39	138		T40	94		T51	43
bins_for_gpio_bits[10]	auto[1]	auto[0]	auto[1]	600692	1			T41	44		T50	104		T53	134
bins_for_gpio_bits[10]	auto[1]	auto[1]	auto[1]	2297994	1			T39	133		T40	98		T41	52
bins_for_gpio_bits[11]	auto[0]	auto[0]	auto[0]	8356524	1			T21	3		T22	1		T1	24
bins_for_gpio_bits[11]	auto[0]	auto[0]	auto[1]	5795207	1			T39	70		T40	21		T41	147
bins_for_gpio_bits[11]	auto[0]	auto[1]	auto[0]	2318160	1			T39	103		T40	102		T41	20
bins_for_gpio_bits[11]	auto[1]	auto[0]	auto[0]	3065593	1			T39	134		T40	110		T51	39
bins_for_gpio_bits[11]	auto[1]	auto[0]	auto[1]	599919	1			T41	59		T50	78		T53	72
bins_for_gpio_bits[11]	auto[1]	auto[1]	auto[1]	2299373	1			T39	170		T40	110		T41	52
bins_for_gpio_bits[12]	auto[0]	auto[0]	auto[0]	8349502	1			T21	3		T22	1		T1	24
bins_for_gpio_bits[12]	auto[0]	auto[0]	auto[1]	5803618	1			T39	70		T40	16		T41	162
bins_for_gpio_bits[12]	auto[0]	auto[1]	auto[0]	2320222	1			T39	134		T40	114		T41	58
bins_for_gpio_bits[12]	auto[1]	auto[0]	auto[0]	3067495	1			T39	133		T40	116		T51	32
bins_for_gpio_bits[12]	auto[1]	auto[0]	auto[1]	598288	1			T41	32		T50	106		T53	114
bins_for_gpio_bits[12]	auto[1]	auto[1]	auto[1]	2295651	1			T39	150		T40	83		T41	39
bins_for_gpio_bits[13]	auto[0]	auto[0]	auto[0]	8348794	1			T21	3		T22	1		T1	24
bins_for_gpio_bits[13]	auto[0]	auto[0]	auto[1]	5794919	1			T39	84		T40	17		T41	123
bins_for_gpio_bits[13]	auto[0]	auto[1]	auto[0]	2316686	1			T39	118		T40	73		T41	42
bins_for_gpio_bits[13]	auto[1]	auto[0]	auto[0]	3072492	1			T39	173		T40	108		T51	22
bins_for_gpio_bits[13]	auto[1]	auto[0]	auto[1]	597041	1			T41	45		T50	87		T53	108
bins_for_gpio_bits[13]	auto[1]	auto[1]	auto[1]	2304844	1			T39	102		T40	132		T41	70
bins_for_gpio_bits[14]	auto[0]	auto[0]	auto[0]	8344066	1			T21	3		T22	1		T1	24
bins_for_gpio_bits[14]	auto[0]	auto[0]	auto[1]	5806450	1			T39	85		T40	14		T41	123
bins_for_gpio_bits[14]	auto[0]	auto[1]	auto[0]	2315611	1			T39	169		T40	76		T41	53
bins_for_gpio_bits[14]	auto[1]	auto[0]	auto[0]	3073006	1			T39	104		T40	115		T51	19
bins_for_gpio_bits[14]	auto[1]	auto[0]	auto[1]	596298	1			T41	52		T50	86		T53	96
bins_for_gpio_bits[14]	auto[1]	auto[1]	auto[1]	2299345	1			T39	116		T40	128		T41	44
bins_for_gpio_bits[15]	auto[0]	auto[0]	auto[0]	8342398	1			T21	3		T22	1		T1	24
bins_for_gpio_bits[15]	auto[0]	auto[0]	auto[1]	5797691	1			T39	63		T40	20		T41	144
bins_for_gpio_bits[15]	auto[0]	auto[1]	auto[0]	2318373	1			T39	119		T40	126		T41	53
bins_for_gpio_bits[15]	auto[1]	auto[0]	auto[0]	3070829	1			T39	138		T40	70		T51	44
bins_for_gpio_bits[15]	auto[1]	auto[0]	auto[1]	598716	1			T41	28		T50	87		T53	120
bins_for_gpio_bits[15]	auto[1]	auto[1]	auto[1]	2306769	1			T39	130		T40	118		T41	44
bins_for_gpio_bits[16]	auto[0]	auto[0]	auto[0]	8369224	1			T21	3		T22	1		T1	24
bins_for_gpio_bits[16]	auto[0]	auto[0]	auto[1]	5799240	1			T39	76		T40	18		T41	145
bins_for_gpio_bits[16]	auto[0]	auto[1]	auto[0]	2316392	1			T39	130		T40	92		T41	54
bins_for_gpio_bits[16]	auto[1]	auto[0]	auto[0]	3068567	1			T39	122		T40	115		T51	25
bins_for_gpio_bits[16]	auto[1]	auto[0]	auto[1]	595726	1			T41	41		T50	98		T53	124
bins_for_gpio_bits[16]	auto[1]	auto[1]	auto[1]	2285627	1			T39	170		T40	120		T41	34
bins_for_gpio_bits[17]	auto[0]	auto[0]	auto[0]	8359759	1			T21	3		T22	1		T1	24
bins_for_gpio_bits[17]	auto[0]	auto[0]	auto[1]	5799864	1			T39	82		T40	20		T41	164
bins_for_gpio_bits[17]	auto[0]	auto[1]	auto[0]	2317892	1			T39	130		T40	124		T41	40
bins_for_gpio_bits[17]	auto[1]	auto[0]	auto[0]	3074497	1			T39	108		T40	107		T51	16
bins_for_gpio_bits[17]	auto[1]	auto[0]	auto[1]	598817	1			T41	46		T50	77		T53	140
bins_for_gpio_bits[17]	auto[1]	auto[1]	auto[1]	2283947	1			T39	151		T40	116		T41	33
bins_for_gpio_bits[18]	auto[0]	auto[0]	auto[0]	8369883	1			T21	3		T22	1		T1	24
bins_for_gpio_bits[18]	auto[0]	auto[0]	auto[1]	5794947	1			T39	75		T40	17		T41	146
bins_for_gpio_bits[18]	auto[0]	auto[1]	auto[0]	2307273	1			T39	138		T40	132		T41	46
bins_for_gpio_bits[18]	auto[1]	auto[0]	auto[0]	3076629	1			T39	125		T40	102		T51	34
bins_for_gpio_bits[18]	auto[1]	auto[0]	auto[1]	600802	1			T41	56		T50	82		T53	110
bins_for_gpio_bits[18]	auto[1]	auto[1]	auto[1]	2285242	1			T39	114		T40	101		T41	39
bins_for_gpio_bits[19]	auto[0]	auto[0]	auto[0]	8358321	1			T21	3		T22	1		T1	24
bins_for_gpio_bits[19]	auto[0]	auto[0]	auto[1]	5798085	1			T39	66		T40	15		T41	128
bins_for_gpio_bits[19]	auto[0]	auto[1]	auto[0]	2300683	1			T39	163		T40	110		T41	80
bins_for_gpio_bits[19]	auto[1]	auto[0]	auto[0]	3084714	1			T39	122		T40	88		T51	38
bins_for_gpio_bits[19]	auto[1]	auto[0]	auto[1]	599967	1			T41	32		T50	98		T53	108
bins_for_gpio_bits[19]	auto[1]	auto[1]	auto[1]	2293006	1			T39	114		T40	115		T41	36
bins_for_gpio_bits[20]	auto[0]	auto[0]	auto[0]	8364228	1			T21	3		T22	1		T1	24
bins_for_gpio_bits[20]	auto[0]	auto[0]	auto[1]	5796023	1			T39	84		T40	16		T41	153
bins_for_gpio_bits[20]	auto[0]	auto[1]	auto[0]	2315025	1			T39	134		T40	84		T41	65
bins_for_gpio_bits[20]	auto[1]	auto[0]	auto[0]	3067206	1			T39	129		T40	132		T51	34
bins_for_gpio_bits[20]	auto[1]	auto[0]	auto[1]	597791	1			T41	20		T50	72		T53	118
bins_for_gpio_bits[20]	auto[1]	auto[1]	auto[1]	2294503	1			T39	158		T40	100		T41	36
bins_for_gpio_bits[21]	auto[0]	auto[0]	auto[0]	8354838	1			T21	3		T22	1		T1	24
bins_for_gpio_bits[21]	auto[0]	auto[0]	auto[1]	5804795	1			T39	84		T40	17		T41	139
bins_for_gpio_bits[21]	auto[0]	auto[1]	auto[0]	2311410	1			T39	156		T40	119		T41	30
bins_for_gpio_bits[21]	auto[1]	auto[0]	auto[0]	3081667	1			T39	90		T40	110		T51	20
bins_for_gpio_bits[21]	auto[1]	auto[0]	auto[1]	598533	1			T41	50		T50	106		T53	104
bins_for_gpio_bits[21]	auto[1]	auto[1]	auto[1]	2283533	1			T39	141		T40	122		T41	54
bins_for_gpio_bits[22]	auto[0]	auto[0]	auto[0]	8351406	1			T21	3		T22	1		T1	24
bins_for_gpio_bits[22]	auto[0]	auto[0]	auto[1]	5800034	1			T39	74		T40	22		T41	166
bins_for_gpio_bits[22]	auto[0]	auto[1]	auto[0]	2311047	1			T39	136		T40	92		T41	54
bins_for_gpio_bits[22]	auto[1]	auto[0]	auto[0]	3085782	1			T39	106		T40	122		T51	30
bins_for_gpio_bits[22]	auto[1]	auto[0]	auto[1]	597172	1			T41	38		T50	82		T53	110
bins_for_gpio_bits[22]	auto[1]	auto[1]	auto[1]	2289335	1			T39	149		T40	113		T41	34
bins_for_gpio_bits[23]	auto[0]	auto[0]	auto[0]	8360052	1			T21	3		T22	1		T1	24
bins_for_gpio_bits[23]	auto[0]	auto[0]	auto[1]	5801092	1			T39	83		T40	21		T41	141
bins_for_gpio_bits[23]	auto[0]	auto[1]	auto[0]	2315994	1			T39	123		T40	110		T41	69
bins_for_gpio_bits[23]	auto[1]	auto[0]	auto[0]	3065283	1			T39	146		T40	98		T51	32
bins_for_gpio_bits[23]	auto[1]	auto[0]	auto[1]	602074	1			T41	32		T50	96		T53	114
bins_for_gpio_bits[23]	auto[1]	auto[1]	auto[1]	2290281	1			T39	166		T40	114		T41	44
bins_for_gpio_bits[24]	auto[0]	auto[0]	auto[0]	8353432	1			T21	3		T22	1		T1	24
bins_for_gpio_bits[24]	auto[0]	auto[0]	auto[1]	5799594	1			T39	79		T40	26		T41	143
bins_for_gpio_bits[24]	auto[0]	auto[1]	auto[0]	2314913	1			T39	132		T40	106		T41	27
bins_for_gpio_bits[24]	auto[1]	auto[0]	auto[0]	3072502	1			T39	162		T40	90		T51	35
bins_for_gpio_bits[24]	auto[1]	auto[0]	auto[1]	598291	1			T41	42		T50	90		T53	145
bins_for_gpio_bits[24]	auto[1]	auto[1]	auto[1]	2296044	1			T39	113		T40	122		T41	74
bins_for_gpio_bits[25]	auto[0]	auto[0]	auto[0]	8367016	1			T21	3		T22	1		T1	24
bins_for_gpio_bits[25]	auto[0]	auto[0]	auto[1]	5790565	1			T39	84		T40	17		T41	144
bins_for_gpio_bits[25]	auto[0]	auto[1]	auto[0]	2309597	1			T39	140		T40	129		T41	50
bins_for_gpio_bits[25]	auto[1]	auto[0]	auto[0]	3076739	1			T39	124		T40	88		T51	34
bins_for_gpio_bits[25]	auto[1]	auto[0]	auto[1]	600316	1			T41	38		T50	86		T53	112
bins_for_gpio_bits[25]	auto[1]	auto[1]	auto[1]	2290543	1			T39	180		T40	108		T41	50
bins_for_gpio_bits[26]	auto[0]	auto[0]	auto[0]	8353156	1			T21	3		T22	1		T1	24
bins_for_gpio_bits[26]	auto[0]	auto[0]	auto[1]	5804628	1			T39	82		T40	22		T41	156
bins_for_gpio_bits[26]	auto[0]	auto[1]	auto[0]	2314355	1			T39	120		T40	92		T41	52
bins_for_gpio_bits[26]	auto[1]	auto[0]	auto[0]	3073614	1			T39	138		T40	126		T51	26
bins_for_gpio_bits[26]	auto[1]	auto[0]	auto[1]	598673	1			T41	44		T50	90		T53	115
bins_for_gpio_bits[26]	auto[1]	auto[1]	auto[1]	2290350	1			T39	157		T40	97		T41	36
bins_for_gpio_bits[27]	auto[0]	auto[0]	auto[0]	8361744	1			T21	3		T22	1		T1	24
bins_for_gpio_bits[27]	auto[0]	auto[0]	auto[1]	5795430	1			T39	76		T40	19		T41	146
bins_for_gpio_bits[27]	auto[0]	auto[1]	auto[0]	2315258	1			T39	118		T40	113		T41	36
bins_for_gpio_bits[27]	auto[1]	auto[0]	auto[0]	3071883	1			T39	156		T40	100		T51	34
bins_for_gpio_bits[27]	auto[1]	auto[0]	auto[1]	600469	1			T41	55		T50	92		T53	131
bins_for_gpio_bits[27]	auto[1]	auto[1]	auto[1]	2289992	1			T39	131		T40	112		T41	48
bins_for_gpio_bits[28]	auto[0]	auto[0]	auto[0]	8360997	1			T21	3		T22	1		T1	24
bins_for_gpio_bits[28]	auto[0]	auto[0]	auto[1]	5801704	1			T39	81		T40	19		T41	119
bins_for_gpio_bits[28]	auto[0]	auto[1]	auto[0]	2313593	1			T39	120		T40	134		T41	36
bins_for_gpio_bits[28]	auto[1]	auto[0]	auto[0]	3072480	1			T39	144		T40	93		T51	14
bins_for_gpio_bits[28]	auto[1]	auto[0]	auto[1]	595830	1			T41	59		T50	106		T53	106
bins_for_gpio_bits[28]	auto[1]	auto[1]	auto[1]	2290172	1			T39	104		T40	114		T41	68
bins_for_gpio_bits[29]	auto[0]	auto[0]	auto[0]	8363711	1			T21	3		T22	1		T1	24
bins_for_gpio_bits[29]	auto[0]	auto[0]	auto[1]	5789622	1			T39	84		T40	17		T41	151
bins_for_gpio_bits[29]	auto[0]	auto[1]	auto[0]	2313159	1			T39	131		T40	80		T41	51
bins_for_gpio_bits[29]	auto[1]	auto[0]	auto[0]	3078325	1			T39	166		T40	127		T51	38
bins_for_gpio_bits[29]	auto[1]	auto[0]	auto[1]	601239	1			T41	42		T50	55		T53	106
bins_for_gpio_bits[29]	auto[1]	auto[1]	auto[1]	2288720	1			T39	122		T40	116		T41	42
bins_for_gpio_bits[30]	auto[0]	auto[0]	auto[0]	8359595	1			T21	3		T22	1		T1	24
bins_for_gpio_bits[30]	auto[0]	auto[0]	auto[1]	5795519	1			T39	84		T40	22		T41	137
bins_for_gpio_bits[30]	auto[0]	auto[1]	auto[0]	2309599	1			T39	134		T40	96		T41	34
bins_for_gpio_bits[30]	auto[1]	auto[0]	auto[0]	3081537	1			T39	157		T40	92		T51	26
bins_for_gpio_bits[30]	auto[1]	auto[0]	auto[1]	597334	1			T41	48		T50	72		T53	123
bins_for_gpio_bits[30]	auto[1]	auto[1]	auto[1]	2291192	1			T39	98		T40	100		T41	63
bins_for_gpio_bits[31]	auto[0]	auto[0]	auto[0]	8355945	1			T21	3		T22	1		T1	24
bins_for_gpio_bits[31]	auto[0]	auto[0]	auto[1]	5802799	1			T39	76		T40	18		T41	147
bins_for_gpio_bits[31]	auto[0]	auto[1]	auto[0]	2308670	1			T39	140		T40	104		T41	20
bins_for_gpio_bits[31]	auto[1]	auto[0]	auto[0]	3082624	1			T39	156		T40	115		T51	28
bins_for_gpio_bits[31]	auto[1]	auto[0]	auto[1]	599663	1			T41	70		T50	66		T53	102
bins_for_gpio_bits[31]	auto[1]	auto[1]	auto[1]	2285075	1			T39	116		T40	88		T41	41

User Defined Cross Bins for cp_cross_all

Excluded/Illegal bins

NAME	COUNT	STATUS
data_oe_1_data_out_0_data_in_1	0	Illegal
data_oe_1_data_out_1_data_in_0	0	Illegal