Unified Coverage Report :: Group :: gpio_env_pkg::gpio_env_cov::gpio_pins_data_in_cross_cg

Group : gpio_env_pkg::gpio_env_cov::gpio_pins_data_in_cross_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_gpio_env_0.1/gpio_env_cov.sv

---

Summary for Group gpio_env_pkg::gpio_env_cov::gpio_pins_data_in_cross_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	36	0	36	100.00
Crosses	128	0	128	100.00

Variables for Group gpio_env_pkg::gpio_env_cov::gpio_pins_data_in_cross_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_pin	32	0	32	100.00	100	1	1	0
data_in	2	0	2	100.00	100	1	1	2
gpio_value	2	0	2	100.00	100	1	1	2

Crosses for Group gpio_env_pkg::gpio_env_cov::gpio_pins_data_in_cross_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_cross_pins_data_in	128	0	128	100.00	100	1	1	0

Summary for Variable cp_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	32	0	32	100.00

User Defined Bins for cp_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
bins_for_gpio_bits[0]	22434776	1			T21	3		T22	1		T1	24
bins_for_gpio_bits[1]	22434776	1			T21	3		T22	1		T1	24
bins_for_gpio_bits[2]	22434776	1			T21	3		T22	1		T1	24
bins_for_gpio_bits[3]	22434776	1			T21	3		T22	1		T1	24
bins_for_gpio_bits[4]	22434776	1			T21	3		T22	1		T1	24
bins_for_gpio_bits[5]	22434776	1			T21	3		T22	1		T1	24
bins_for_gpio_bits[6]	22434776	1			T21	3		T22	1		T1	24
bins_for_gpio_bits[7]	22434776	1			T21	3		T22	1		T1	24
bins_for_gpio_bits[8]	22434776	1			T21	3		T22	1		T1	24
bins_for_gpio_bits[9]	22434776	1			T21	3		T22	1		T1	24
bins_for_gpio_bits[10]	22434776	1			T21	3		T22	1		T1	24
bins_for_gpio_bits[11]	22434776	1			T21	3		T22	1		T1	24
bins_for_gpio_bits[12]	22434776	1			T21	3		T22	1		T1	24
bins_for_gpio_bits[13]	22434776	1			T21	3		T22	1		T1	24
bins_for_gpio_bits[14]	22434776	1			T21	3		T22	1		T1	24
bins_for_gpio_bits[15]	22434776	1			T21	3		T22	1		T1	24
bins_for_gpio_bits[16]	22434776	1			T21	3		T22	1		T1	24
bins_for_gpio_bits[17]	22434776	1			T21	3		T22	1		T1	24
bins_for_gpio_bits[18]	22434776	1			T21	3		T22	1		T1	24
bins_for_gpio_bits[19]	22434776	1			T21	3		T22	1		T1	24
bins_for_gpio_bits[20]	22434776	1			T21	3		T22	1		T1	24
bins_for_gpio_bits[21]	22434776	1			T21	3		T22	1		T1	24
bins_for_gpio_bits[22]	22434776	1			T21	3		T22	1		T1	24
bins_for_gpio_bits[23]	22434776	1			T21	3		T22	1		T1	24
bins_for_gpio_bits[24]	22434776	1			T21	3		T22	1		T1	24
bins_for_gpio_bits[25]	22434776	1			T21	3		T22	1		T1	24
bins_for_gpio_bits[26]	22434776	1			T21	3		T22	1		T1	24
bins_for_gpio_bits[27]	22434776	1			T21	3		T22	1		T1	24
bins_for_gpio_bits[28]	22434776	1			T21	3		T22	1		T1	24
bins_for_gpio_bits[29]	22434776	1			T21	3		T22	1		T1	24
bins_for_gpio_bits[30]	22434776	1			T21	3		T22	1		T1	24
bins_for_gpio_bits[31]	22434776	1			T21	3		T22	1		T1	24

---

Summary for Variable data_in

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for data_in

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

439807272

1

T21

96

T22

32

T1

768

auto[1]

278105560

1

T39

6793

T40

4032

T41

7462

---

Summary for Variable gpio_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for gpio_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

439801301

1

T21

89

T22

32

T1

627

auto[1]

278111531

1

T21

7

T1

141

T11

164

---

Summary for Cross cp_cross_pins_data_in

Samples crossed: cp_pin gpio_value data_in

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	128	0	128	100.00

Automatically Generated Cross Bins for cp_cross_pins_data_in

Bins

cp_pin	gpio_value	data_in	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
bins_for_gpio_bits[0]	auto[0]	auto[0]	13325404	1			T21	3		T22	1		T1	22
bins_for_gpio_bits[0]	auto[0]	auto[1]	411319	1			T39	37		T40	24		T41	14
bins_for_gpio_bits[0]	auto[1]	auto[0]	411524	1			T1	2		T11	7		T12	1
bins_for_gpio_bits[0]	auto[1]	auto[1]	8286529	1			T39	180		T40	85		T41	220
bins_for_gpio_bits[1]	auto[0]	auto[0]	13335105	1			T21	2		T22	1		T1	15
bins_for_gpio_bits[1]	auto[0]	auto[1]	411176	1			T39	36		T40	25		T41	10
bins_for_gpio_bits[1]	auto[1]	auto[0]	411349	1			T21	1		T1	9		T11	4
bins_for_gpio_bits[1]	auto[1]	auto[1]	8277146	1			T39	143		T40	105		T41	249
bins_for_gpio_bits[2]	auto[0]	auto[0]	13331460	1			T21	2		T22	1		T1	24
bins_for_gpio_bits[2]	auto[0]	auto[1]	411354	1			T39	31		T40	23		T41	11
bins_for_gpio_bits[2]	auto[1]	auto[0]	411505	1			T21	1		T11	4		T12	2
bins_for_gpio_bits[2]	auto[1]	auto[1]	8280457	1			T39	190		T40	100		T41	216
bins_for_gpio_bits[3]	auto[0]	auto[0]	13322528	1			T21	2		T22	1		T1	24
bins_for_gpio_bits[3]	auto[0]	auto[1]	411211	1			T39	35		T40	28		T41	10
bins_for_gpio_bits[3]	auto[1]	auto[0]	411458	1			T21	1		T11	8		T12	2
bins_for_gpio_bits[3]	auto[1]	auto[1]	8289579	1			T39	174		T40	107		T41	225
bins_for_gpio_bits[4]	auto[0]	auto[0]	13327264	1			T21	3		T22	1		T1	14
bins_for_gpio_bits[4]	auto[0]	auto[1]	410897	1			T39	36		T40	26		T41	12
bins_for_gpio_bits[4]	auto[1]	auto[0]	411080	1			T1	10		T11	2		T12	3
bins_for_gpio_bits[4]	auto[1]	auto[1]	8285535	1			T39	167		T40	95		T41	221
bins_for_gpio_bits[5]	auto[0]	auto[0]	13325220	1			T21	3		T22	1		T1	15
bins_for_gpio_bits[5]	auto[0]	auto[1]	410383	1			T39	26		T40	31		T41	10
bins_for_gpio_bits[5]	auto[1]	auto[0]	410606	1			T1	9		T11	8		T12	1
bins_for_gpio_bits[5]	auto[1]	auto[1]	8288567	1			T39	157		T40	96		T41	224
bins_for_gpio_bits[6]	auto[0]	auto[0]	13335116	1			T21	2		T22	1		T1	18
bins_for_gpio_bits[6]	auto[0]	auto[1]	409992	1			T39	32		T40	25		T41	11
bins_for_gpio_bits[6]	auto[1]	auto[0]	410117	1			T21	1		T1	6		T11	6
bins_for_gpio_bits[6]	auto[1]	auto[1]	8279551	1			T39	182		T40	77		T41	220
bins_for_gpio_bits[7]	auto[0]	auto[0]	13326505	1			T21	2		T22	1		T1	24
bins_for_gpio_bits[7]	auto[0]	auto[1]	410388	1			T39	34		T40	25		T41	16
bins_for_gpio_bits[7]	auto[1]	auto[0]	410567	1			T21	1		T11	5		T12	3
bins_for_gpio_bits[7]	auto[1]	auto[1]	8287316	1			T39	207		T40	95		T41	200
bins_for_gpio_bits[8]	auto[0]	auto[0]	13336246	1			T21	3		T22	1		T1	17
bins_for_gpio_bits[8]	auto[0]	auto[1]	411281	1			T39	31		T40	19		T41	12
bins_for_gpio_bits[8]	auto[1]	auto[0]	411471	1			T1	7		T11	8		T12	3
bins_for_gpio_bits[8]	auto[1]	auto[1]	8275778	1			T39	177		T40	89		T41	209
bins_for_gpio_bits[9]	auto[0]	auto[0]	13327705	1			T21	2		T22	1		T1	16
bins_for_gpio_bits[9]	auto[0]	auto[1]	411681	1			T39	39		T40	25		T41	13
bins_for_gpio_bits[9]	auto[1]	auto[0]	411863	1			T21	1		T1	8		T11	3
bins_for_gpio_bits[9]	auto[1]	auto[1]	8283527	1			T39	179		T40	87		T41	200
bins_for_gpio_bits[10]	auto[0]	auto[0]	13339698	1			T21	3		T22	1		T1	10
bins_for_gpio_bits[10]	auto[0]	auto[1]	411315	1			T39	37		T40	30		T41	11
bins_for_gpio_bits[10]	auto[1]	auto[0]	411514	1			T1	14		T11	9		T2	7
bins_for_gpio_bits[10]	auto[1]	auto[1]	8272249	1			T39	169		T40	92		T41	214
bins_for_gpio_bits[11]	auto[0]	auto[0]	13329514	1			T21	3		T22	1		T1	13
bins_for_gpio_bits[11]	auto[0]	auto[1]	410565	1			T39	31		T40	29		T41	7
bins_for_gpio_bits[11]	auto[1]	auto[0]	410763	1			T1	11		T11	6		T12	4
bins_for_gpio_bits[11]	auto[1]	auto[1]	8283934	1			T39	209		T40	102		T41	251
bins_for_gpio_bits[12]	auto[0]	auto[0]	13326673	1			T21	3		T22	1		T1	24
bins_for_gpio_bits[12]	auto[0]	auto[1]	410368	1			T39	36		T40	24		T41	14
bins_for_gpio_bits[12]	auto[1]	auto[0]	410546	1			T11	5		T12	2		T2	13
bins_for_gpio_bits[12]	auto[1]	auto[1]	8287189	1			T39	184		T40	75		T41	219
bins_for_gpio_bits[13]	auto[0]	auto[0]	13326290	1			T21	3		T22	1		T1	21
bins_for_gpio_bits[13]	auto[0]	auto[1]	411498	1			T39	33		T40	29		T41	12
bins_for_gpio_bits[13]	auto[1]	auto[0]	411682	1			T1	3		T11	2		T12	1
bins_for_gpio_bits[13]	auto[1]	auto[1]	8285306	1			T39	153		T40	120		T41	226
bins_for_gpio_bits[14]	auto[0]	auto[0]	13321251	1			T21	3		T22	1		T1	24
bins_for_gpio_bits[14]	auto[0]	auto[1]	411250	1			T39	32		T40	22		T41	14
bins_for_gpio_bits[14]	auto[1]	auto[0]	411432	1			T11	5		T12	2		T2	4
bins_for_gpio_bits[14]	auto[1]	auto[1]	8290843	1			T39	169		T40	120		T41	205
bins_for_gpio_bits[15]	auto[0]	auto[0]	13319904	1			T21	3		T22	1		T1	24
bins_for_gpio_bits[15]	auto[0]	auto[1]	411513	1			T39	34		T40	23		T41	15
bins_for_gpio_bits[15]	auto[1]	auto[0]	411696	1			T11	7		T12	4		T2	12
bins_for_gpio_bits[15]	auto[1]	auto[1]	8291663	1			T39	159		T40	115		T41	201
bins_for_gpio_bits[16]	auto[0]	auto[0]	13343205	1			T21	3		T22	1		T1	24
bins_for_gpio_bits[16]	auto[0]	auto[1]	410820	1			T39	36		T40	28		T41	13
bins_for_gpio_bits[16]	auto[1]	auto[0]	410978	1			T11	7		T12	2		T2	17
bins_for_gpio_bits[16]	auto[1]	auto[1]	8269773	1			T39	210		T40	110		T41	207
bins_for_gpio_bits[17]	auto[0]	auto[0]	13341875	1			T21	3		T22	1		T1	24
bins_for_gpio_bits[17]	auto[0]	auto[1]	410075	1			T39	30		T40	27		T41	14
bins_for_gpio_bits[17]	auto[1]	auto[0]	410273	1			T11	4		T12	5		T2	13
bins_for_gpio_bits[17]	auto[1]	auto[1]	8272553	1			T39	203		T40	109		T41	229
bins_for_gpio_bits[18]	auto[0]	auto[0]	13344435	1			T21	3		T22	1		T1	13
bins_for_gpio_bits[18]	auto[0]	auto[1]	409148	1			T39	36		T40	24		T41	10
bins_for_gpio_bits[18]	auto[1]	auto[0]	409350	1			T1	11		T11	5		T12	3
bins_for_gpio_bits[18]	auto[1]	auto[1]	8271843	1			T39	153		T40	94		T41	231
bins_for_gpio_bits[19]	auto[0]	auto[0]	13332848	1			T21	3		T22	1		T1	14
bins_for_gpio_bits[19]	auto[0]	auto[1]	410671	1			T39	30		T40	30		T41	15
bins_for_gpio_bits[19]	auto[1]	auto[0]	410870	1			T1	10		T11	5		T12	2
bins_for_gpio_bits[19]	auto[1]	auto[1]	8280387	1			T39	150		T40	100		T41	181
bins_for_gpio_bits[20]	auto[0]	auto[0]	13334850	1			T21	3		T22	1		T1	21
bins_for_gpio_bits[20]	auto[0]	auto[1]	411443	1			T39	36		T40	28		T41	15
bins_for_gpio_bits[20]	auto[1]	auto[0]	411609	1			T1	3		T11	5		T12	1
bins_for_gpio_bits[20]	auto[1]	auto[1]	8276874	1			T39	206		T40	88		T41	194
bins_for_gpio_bits[21]	auto[0]	auto[0]	13337262	1			T21	3		T22	1		T1	15
bins_for_gpio_bits[21]	auto[0]	auto[1]	410473	1			T39	30		T40	28		T41	11
bins_for_gpio_bits[21]	auto[1]	auto[0]	410653	1			T1	9		T11	5		T12	5
bins_for_gpio_bits[21]	auto[1]	auto[1]	8276388	1			T39	195		T40	111		T41	232
bins_for_gpio_bits[22]	auto[0]	auto[0]	13337677	1			T21	3		T22	1		T1	14
bins_for_gpio_bits[22]	auto[0]	auto[1]	410329	1			T39	28		T40	32		T41	12
bins_for_gpio_bits[22]	auto[1]	auto[0]	410558	1			T1	10		T11	5		T12	5
bins_for_gpio_bits[22]	auto[1]	auto[1]	8276212	1			T39	195		T40	103		T41	226
bins_for_gpio_bits[23]	auto[0]	auto[0]	13330437	1			T21	3		T22	1		T1	24
bins_for_gpio_bits[23]	auto[0]	auto[1]	410733	1			T39	37		T40	30		T41	14
bins_for_gpio_bits[23]	auto[1]	auto[0]	410892	1			T11	3		T12	3		T15	2
bins_for_gpio_bits[23]	auto[1]	auto[1]	8282714	1			T39	212		T40	105		T41	203
bins_for_gpio_bits[24]	auto[0]	auto[0]	13328644	1			T21	2		T22	1		T1	15
bins_for_gpio_bits[24]	auto[0]	auto[1]	412000	1			T39	30		T40	26		T41	12
bins_for_gpio_bits[24]	auto[1]	auto[0]	412203	1			T21	1		T1	9		T11	3
bins_for_gpio_bits[24]	auto[1]	auto[1]	8281929	1			T39	162		T40	122		T41	247
bins_for_gpio_bits[25]	auto[0]	auto[0]	13342380	1			T21	3		T22	1		T1	23
bins_for_gpio_bits[25]	auto[0]	auto[1]	410776	1			T39	36		T40	32		T41	11
bins_for_gpio_bits[25]	auto[1]	auto[0]	410972	1			T1	1		T11	7		T12	3
bins_for_gpio_bits[25]	auto[1]	auto[1]	8270648	1			T39	228		T40	93		T41	221
bins_for_gpio_bits[26]	auto[0]	auto[0]	13330946	1			T21	3		T22	1		T1	24
bins_for_gpio_bits[26]	auto[0]	auto[1]	410019	1			T39	33		T40	26		T41	14
bins_for_gpio_bits[26]	auto[1]	auto[0]	410179	1			T11	4		T2	10		T14	1
bins_for_gpio_bits[26]	auto[1]	auto[1]	8283632	1			T39	206		T40	93		T41	222
bins_for_gpio_bits[27]	auto[0]	auto[0]	13338091	1			T21	3		T22	1		T1	24
bins_for_gpio_bits[27]	auto[0]	auto[1]	410602	1			T39	30		T40	27		T41	10
bins_for_gpio_bits[27]	auto[1]	auto[0]	410794	1			T11	5		T12	2		T2	2
bins_for_gpio_bits[27]	auto[1]	auto[1]	8275289	1			T39	177		T40	104		T41	239
bins_for_gpio_bits[28]	auto[0]	auto[0]	13336339	1			T21	3		T22	1		T1	23
bins_for_gpio_bits[28]	auto[0]	auto[1]	410522	1			T39	28		T40	29		T41	9
bins_for_gpio_bits[28]	auto[1]	auto[0]	410731	1			T1	1		T11	4		T12	2
bins_for_gpio_bits[28]	auto[1]	auto[1]	8277184	1			T39	157		T40	104		T41	237
bins_for_gpio_bits[29]	auto[0]	auto[0]	13343669	1			T21	3		T22	1		T1	24
bins_for_gpio_bits[29]	auto[0]	auto[1]	411352	1			T39	35		T40	29		T41	12
bins_for_gpio_bits[29]	auto[1]	auto[0]	411526	1			T12	2		T2	11		T14	1
bins_for_gpio_bits[29]	auto[1]	auto[1]	8268229	1			T39	171		T40	104		T41	223
bins_for_gpio_bits[30]	auto[0]	auto[0]	13339832	1			T21	3		T22	1		T1	24
bins_for_gpio_bits[30]	auto[0]	auto[1]	410710	1			T39	29		T40	29		T41	8
bins_for_gpio_bits[30]	auto[1]	auto[0]	410899	1			T11	8		T12	3		T2	7
bins_for_gpio_bits[30]	auto[1]	auto[1]	8273335	1			T39	153		T40	93		T41	240
bins_for_gpio_bits[31]	auto[0]	auto[0]	13336842	1			T21	3		T22	1		T1	16
bins_for_gpio_bits[31]	auto[0]	auto[1]	410222	1			T39	33		T40	24		T41	7
bins_for_gpio_bits[31]	auto[1]	auto[0]	410397	1			T1	8		T11	5		T12	2
bins_for_gpio_bits[31]	auto[1]	auto[1]	8277315	1			T39	159		T40	82		T41	251