Summary for Variable intr_en
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
12540482 |
1 |
|
|
T21 |
2 |
|
T22 |
12 |
|
T1 |
5 |
auto[1] |
10271593 |
1 |
|
|
T21 |
1 |
|
T22 |
9 |
|
T1 |
19 |
Summary for Variable intr_state
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
21486677 |
1 |
|
|
T21 |
3 |
|
T22 |
21 |
|
T1 |
24 |
auto[1] |
1325398 |
1 |
|
|
T2 |
3 |
|
T79 |
2 |
|
T106 |
1 |
Summary for Variable type_ctrl_en
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
12564207 |
1 |
|
|
T21 |
3 |
|
T22 |
21 |
|
T1 |
6 |
auto[1] |
10247868 |
1 |
|
|
T1 |
18 |
|
T11 |
3 |
|
T12 |
2 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
TOTAL |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[1] |
auto[0] |
auto[0] |
4467323 |
1 |
|
|
T11 |
1 |
|
T12 |
1 |
|
T2 |
7 |
auto[1] |
auto[0] |
auto[1] |
661969 |
1 |
|
|
T2 |
1 |
|
T48 |
1621 |
|
T104 |
78 |
auto[1] |
auto[1] |
auto[0] |
4455147 |
1 |
|
|
T1 |
18 |
|
T11 |
2 |
|
T12 |
1 |
auto[1] |
auto[1] |
auto[1] |
663429 |
1 |
|
|
T2 |
2 |
|
T79 |
2 |
|
T106 |
1 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
NAME | COUNT | STATUS |
intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
12576126 |
1 |
|
|
T21 |
3 |
|
T22 |
12 |
|
T1 |
5 |
auto[1] |
10235949 |
1 |
|
|
T22 |
9 |
|
T1 |
19 |
|
T11 |
6 |
Summary for Variable intr_state
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
21481908 |
1 |
|
|
T21 |
3 |
|
T22 |
21 |
|
T1 |
19 |
auto[1] |
1330167 |
1 |
|
|
T1 |
5 |
|
T78 |
1 |
|
T79 |
1 |
Summary for Variable type_ctrl_en
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
12534140 |
1 |
|
|
T21 |
2 |
|
T22 |
21 |
|
T1 |
6 |
auto[1] |
10277935 |
1 |
|
|
T21 |
1 |
|
T1 |
18 |
|
T11 |
5 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
TOTAL |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[1] |
auto[0] |
auto[0] |
4493642 |
1 |
|
|
T21 |
1 |
|
T11 |
2 |
|
T12 |
1 |
auto[1] |
auto[0] |
auto[1] |
668086 |
1 |
|
|
T78 |
1 |
|
T79 |
1 |
|
T80 |
6 |
auto[1] |
auto[1] |
auto[0] |
4454126 |
1 |
|
|
T1 |
13 |
|
T11 |
3 |
|
T12 |
1 |
auto[1] |
auto[1] |
auto[1] |
662081 |
1 |
|
|
T1 |
5 |
|
T80 |
2 |
|
T86 |
1 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
NAME | COUNT | STATUS |
intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
12529458 |
1 |
|
|
T21 |
2 |
|
T22 |
7 |
|
T1 |
11 |
auto[1] |
10282617 |
1 |
|
|
T21 |
1 |
|
T22 |
14 |
|
T1 |
13 |
Summary for Variable intr_state
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
21484837 |
1 |
|
|
T21 |
3 |
|
T22 |
21 |
|
T1 |
19 |
auto[1] |
1327238 |
1 |
|
|
T1 |
5 |
|
T79 |
1 |
|
T80 |
3 |
Summary for Variable type_ctrl_en
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
12548079 |
1 |
|
|
T21 |
3 |
|
T22 |
21 |
|
T1 |
6 |
auto[1] |
10263996 |
1 |
|
|
T1 |
18 |
|
T11 |
5 |
|
T12 |
2 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
TOTAL |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[1] |
auto[0] |
auto[0] |
4459891 |
1 |
|
|
T1 |
5 |
|
T11 |
4 |
|
T12 |
1 |
auto[1] |
auto[0] |
auto[1] |
661714 |
1 |
|
|
T89 |
2 |
|
T48 |
1430 |
|
T104 |
105 |
auto[1] |
auto[1] |
auto[0] |
4476867 |
1 |
|
|
T1 |
8 |
|
T11 |
1 |
|
T12 |
1 |
auto[1] |
auto[1] |
auto[1] |
665524 |
1 |
|
|
T1 |
5 |
|
T79 |
1 |
|
T80 |
3 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
NAME | COUNT | STATUS |
intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
12528187 |
1 |
|
|
T21 |
3 |
|
T22 |
15 |
|
T1 |
24 |
auto[1] |
10283888 |
1 |
|
|
T22 |
6 |
|
T11 |
7 |
|
T12 |
6 |
Summary for Variable intr_state
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
21494309 |
1 |
|
|
T21 |
3 |
|
T22 |
21 |
|
T1 |
19 |
auto[1] |
1317766 |
1 |
|
|
T1 |
5 |
|
T2 |
2 |
|
T7 |
1 |
Summary for Variable type_ctrl_en
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
12602466 |
1 |
|
|
T21 |
3 |
|
T22 |
21 |
|
T1 |
6 |
auto[1] |
10209609 |
1 |
|
|
T1 |
18 |
|
T11 |
4 |
|
T12 |
6 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
TOTAL |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[1] |
auto[0] |
auto[0] |
4446716 |
1 |
|
|
T1 |
13 |
|
T11 |
2 |
|
T12 |
3 |
auto[1] |
auto[0] |
auto[1] |
656839 |
1 |
|
|
T1 |
5 |
|
T2 |
2 |
|
T48 |
1770 |
auto[1] |
auto[1] |
auto[0] |
4445127 |
1 |
|
|
T11 |
2 |
|
T12 |
3 |
|
T23 |
3 |
auto[1] |
auto[1] |
auto[1] |
660927 |
1 |
|
|
T7 |
1 |
|
T80 |
2 |
|
T48 |
1581 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
NAME | COUNT | STATUS |
intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
12558854 |
1 |
|
|
T21 |
3 |
|
T22 |
6 |
|
T1 |
8 |
auto[1] |
10253221 |
1 |
|
|
T22 |
15 |
|
T1 |
16 |
|
T11 |
7 |
Summary for Variable intr_state
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
21489230 |
1 |
|
|
T21 |
3 |
|
T22 |
21 |
|
T1 |
24 |
auto[1] |
1322845 |
1 |
|
|
T2 |
4 |
|
T15 |
2 |
|
T80 |
1 |
Summary for Variable type_ctrl_en
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
12576190 |
1 |
|
|
T21 |
2 |
|
T22 |
21 |
|
T1 |
5 |
auto[1] |
10235885 |
1 |
|
|
T21 |
1 |
|
T1 |
19 |
|
T11 |
6 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
TOTAL |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[1] |
auto[0] |
auto[0] |
4471521 |
1 |
|
|
T21 |
1 |
|
T1 |
6 |
|
T11 |
4 |
auto[1] |
auto[0] |
auto[1] |
663829 |
1 |
|
|
T15 |
2 |
|
T80 |
1 |
|
T81 |
1 |
auto[1] |
auto[1] |
auto[0] |
4441519 |
1 |
|
|
T1 |
13 |
|
T11 |
2 |
|
T12 |
2 |
auto[1] |
auto[1] |
auto[1] |
659016 |
1 |
|
|
T2 |
4 |
|
T86 |
1 |
|
T48 |
1688 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
NAME | COUNT | STATUS |
intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
12586225 |
1 |
|
|
T21 |
3 |
|
T22 |
4 |
|
T1 |
5 |
auto[1] |
10225850 |
1 |
|
|
T22 |
17 |
|
T1 |
19 |
|
T11 |
4 |
Summary for Variable intr_state
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
21488303 |
1 |
|
|
T21 |
3 |
|
T22 |
21 |
|
T1 |
24 |
auto[1] |
1323772 |
1 |
|
|
T2 |
1 |
|
T102 |
2 |
|
T83 |
1 |
Summary for Variable type_ctrl_en
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
12553410 |
1 |
|
|
T21 |
3 |
|
T22 |
21 |
|
T1 |
5 |
auto[1] |
10258665 |
1 |
|
|
T1 |
19 |
|
T11 |
6 |
|
T12 |
2 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
TOTAL |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[1] |
auto[0] |
auto[0] |
4501002 |
1 |
|
|
T11 |
6 |
|
T12 |
2 |
|
T2 |
17 |
auto[1] |
auto[0] |
auto[1] |
668665 |
1 |
|
|
T2 |
1 |
|
T102 |
2 |
|
T48 |
1653 |
auto[1] |
auto[1] |
auto[0] |
4433891 |
1 |
|
|
T1 |
19 |
|
T23 |
3 |
|
T5 |
2 |
auto[1] |
auto[1] |
auto[1] |
655107 |
1 |
|
|
T83 |
1 |
|
T107 |
1 |
|
T48 |
1543 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
NAME | COUNT | STATUS |
intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
12535135 |
1 |
|
|
T21 |
2 |
|
T22 |
13 |
|
T1 |
24 |
auto[1] |
10276940 |
1 |
|
|
T21 |
1 |
|
T22 |
8 |
|
T11 |
7 |
Summary for Variable intr_state
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
21478157 |
1 |
|
|
T21 |
3 |
|
T22 |
21 |
|
T1 |
24 |
auto[1] |
1333918 |
1 |
|
|
T100 |
1 |
|
T79 |
2 |
|
T89 |
3 |
Summary for Variable type_ctrl_en
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
12514236 |
1 |
|
|
T21 |
3 |
|
T22 |
21 |
|
T1 |
5 |
auto[1] |
10297839 |
1 |
|
|
T1 |
19 |
|
T12 |
3 |
|
T2 |
26 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
TOTAL |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[1] |
auto[0] |
auto[0] |
4491529 |
1 |
|
|
T1 |
19 |
|
T12 |
1 |
|
T23 |
9 |
auto[1] |
auto[0] |
auto[1] |
670278 |
1 |
|
|
T79 |
2 |
|
T89 |
3 |
|
T48 |
1464 |
auto[1] |
auto[1] |
auto[0] |
4472392 |
1 |
|
|
T12 |
2 |
|
T2 |
26 |
|
T14 |
1 |
auto[1] |
auto[1] |
auto[1] |
663640 |
1 |
|
|
T100 |
1 |
|
T48 |
1798 |
|
T104 |
74 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
NAME | COUNT | STATUS |
intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
12559984 |
1 |
|
|
T21 |
3 |
|
T22 |
10 |
|
T1 |
5 |
auto[1] |
10252091 |
1 |
|
|
T22 |
11 |
|
T1 |
19 |
|
T11 |
8 |
Summary for Variable intr_state
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
21486614 |
1 |
|
|
T21 |
3 |
|
T22 |
21 |
|
T1 |
24 |
auto[1] |
1325461 |
1 |
|
|
T101 |
1 |
|
T79 |
1 |
|
T80 |
4 |
Summary for Variable type_ctrl_en
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
12562069 |
1 |
|
|
T21 |
3 |
|
T22 |
21 |
|
T1 |
23 |
auto[1] |
10250006 |
1 |
|
|
T1 |
1 |
|
T11 |
3 |
|
T12 |
5 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
TOTAL |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[1] |
auto[0] |
auto[0] |
4464431 |
1 |
|
|
T11 |
2 |
|
T12 |
5 |
|
T23 |
5 |
auto[1] |
auto[0] |
auto[1] |
663048 |
1 |
|
|
T101 |
1 |
|
T79 |
1 |
|
T80 |
4 |
auto[1] |
auto[1] |
auto[0] |
4460114 |
1 |
|
|
T1 |
1 |
|
T11 |
1 |
|
T23 |
5 |
auto[1] |
auto[1] |
auto[1] |
662413 |
1 |
|
|
T48 |
1560 |
|
T104 |
78 |
|
T49 |
2592 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
NAME | COUNT | STATUS |
intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
12509837 |
1 |
|
|
T21 |
3 |
|
T22 |
17 |
|
T1 |
18 |
auto[1] |
10302238 |
1 |
|
|
T22 |
4 |
|
T1 |
6 |
|
T11 |
10 |
Summary for Variable intr_state
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
21489959 |
1 |
|
|
T21 |
3 |
|
T22 |
21 |
|
T1 |
24 |
auto[1] |
1322116 |
1 |
|
|
T2 |
1 |
|
T107 |
2 |
|
T48 |
3043 |
Summary for Variable type_ctrl_en
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
12587816 |
1 |
|
|
T21 |
2 |
|
T22 |
21 |
|
T1 |
6 |
auto[1] |
10224259 |
1 |
|
|
T21 |
1 |
|
T1 |
18 |
|
T11 |
7 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
TOTAL |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[1] |
auto[0] |
auto[0] |
4434685 |
1 |
|
|
T21 |
1 |
|
T1 |
13 |
|
T11 |
4 |
auto[1] |
auto[0] |
auto[1] |
657415 |
1 |
|
|
T107 |
2 |
|
T48 |
1442 |
|
T104 |
71 |
auto[1] |
auto[1] |
auto[0] |
4467458 |
1 |
|
|
T1 |
5 |
|
T11 |
3 |
|
T12 |
1 |
auto[1] |
auto[1] |
auto[1] |
664701 |
1 |
|
|
T2 |
1 |
|
T48 |
1601 |
|
T104 |
92 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
NAME | COUNT | STATUS |
intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
12543309 |
1 |
|
|
T21 |
3 |
|
T22 |
16 |
|
T1 |
8 |
auto[1] |
10268766 |
1 |
|
|
T22 |
5 |
|
T1 |
16 |
|
T11 |
6 |
Summary for Variable intr_state
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
21481523 |
1 |
|
|
T21 |
3 |
|
T22 |
21 |
|
T1 |
24 |
auto[1] |
1330552 |
1 |
|
|
T2 |
6 |
|
T5 |
1 |
|
T7 |
1 |
Summary for Variable type_ctrl_en
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
12514302 |
1 |
|
|
T21 |
2 |
|
T22 |
21 |
|
T1 |
5 |
auto[1] |
10297773 |
1 |
|
|
T21 |
1 |
|
T1 |
19 |
|
T11 |
4 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
TOTAL |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[1] |
auto[0] |
auto[0] |
4478670 |
1 |
|
|
T21 |
1 |
|
T1 |
6 |
|
T11 |
3 |
auto[1] |
auto[0] |
auto[1] |
664222 |
1 |
|
|
T2 |
6 |
|
T7 |
1 |
|
T48 |
1460 |
auto[1] |
auto[1] |
auto[0] |
4488551 |
1 |
|
|
T1 |
13 |
|
T11 |
1 |
|
T12 |
3 |
auto[1] |
auto[1] |
auto[1] |
666330 |
1 |
|
|
T5 |
1 |
|
T102 |
2 |
|
T83 |
1 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
NAME | COUNT | STATUS |
intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
12520309 |
1 |
|
|
T21 |
3 |
|
T22 |
3 |
|
T1 |
18 |
auto[1] |
10291766 |
1 |
|
|
T22 |
18 |
|
T1 |
6 |
|
T11 |
8 |
Summary for Variable intr_state
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
21488154 |
1 |
|
|
T21 |
3 |
|
T22 |
21 |
|
T1 |
18 |
auto[1] |
1323921 |
1 |
|
|
T1 |
6 |
|
T2 |
4 |
|
T79 |
2 |
Summary for Variable type_ctrl_en
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
12557859 |
1 |
|
|
T21 |
3 |
|
T22 |
21 |
|
T1 |
5 |
auto[1] |
10254216 |
1 |
|
|
T1 |
19 |
|
T11 |
4 |
|
T12 |
3 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
TOTAL |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[1] |
auto[0] |
auto[0] |
4445543 |
1 |
|
|
T1 |
9 |
|
T11 |
2 |
|
T12 |
2 |
auto[1] |
auto[0] |
auto[1] |
657510 |
1 |
|
|
T1 |
4 |
|
T2 |
1 |
|
T79 |
2 |
auto[1] |
auto[1] |
auto[0] |
4484752 |
1 |
|
|
T1 |
4 |
|
T11 |
2 |
|
T12 |
1 |
auto[1] |
auto[1] |
auto[1] |
666411 |
1 |
|
|
T1 |
2 |
|
T2 |
3 |
|
T86 |
1 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
NAME | COUNT | STATUS |
intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
12593950 |
1 |
|
|
T21 |
2 |
|
T22 |
12 |
|
T1 |
2 |
auto[1] |
10218125 |
1 |
|
|
T21 |
1 |
|
T22 |
9 |
|
T1 |
22 |
Summary for Variable intr_state
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
21480038 |
1 |
|
|
T21 |
3 |
|
T22 |
21 |
|
T1 |
24 |
auto[1] |
1332037 |
1 |
|
|
T2 |
1 |
|
T15 |
1 |
|
T5 |
1 |
Summary for Variable type_ctrl_en
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
12522296 |
1 |
|
|
T21 |
3 |
|
T22 |
21 |
|
T1 |
24 |
auto[1] |
10289779 |
1 |
|
|
T11 |
7 |
|
T12 |
3 |
|
T2 |
20 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
TOTAL |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[1] |
auto[0] |
auto[0] |
4502335 |
1 |
|
|
T11 |
4 |
|
T2 |
7 |
|
T14 |
1 |
auto[1] |
auto[0] |
auto[1] |
670341 |
1 |
|
|
T2 |
1 |
|
T15 |
1 |
|
T5 |
1 |
auto[1] |
auto[1] |
auto[0] |
4455407 |
1 |
|
|
T11 |
3 |
|
T12 |
3 |
|
T2 |
12 |
auto[1] |
auto[1] |
auto[1] |
661696 |
1 |
|
|
T80 |
7 |
|
T84 |
1 |
|
T48 |
1625 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
NAME | COUNT | STATUS |
intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
12525090 |
1 |
|
|
T21 |
3 |
|
T22 |
8 |
|
T1 |
2 |
auto[1] |
10286985 |
1 |
|
|
T22 |
13 |
|
T1 |
22 |
|
T11 |
5 |
Summary for Variable intr_state
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
21477902 |
1 |
|
|
T21 |
3 |
|
T22 |
21 |
|
T1 |
24 |
auto[1] |
1334173 |
1 |
|
|
T2 |
2 |
|
T5 |
1 |
|
T83 |
1 |
Summary for Variable type_ctrl_en
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
12491938 |
1 |
|
|
T21 |
3 |
|
T22 |
21 |
|
T1 |
23 |
auto[1] |
10320137 |
1 |
|
|
T1 |
1 |
|
T11 |
3 |
|
T12 |
5 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
TOTAL |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[1] |
auto[0] |
auto[0] |
4487016 |
1 |
|
|
T11 |
2 |
|
T12 |
3 |
|
T14 |
1 |
auto[1] |
auto[0] |
auto[1] |
666031 |
1 |
|
|
T83 |
1 |
|
T48 |
1457 |
|
T104 |
97 |
auto[1] |
auto[1] |
auto[0] |
4498948 |
1 |
|
|
T1 |
1 |
|
T11 |
1 |
|
T12 |
2 |
auto[1] |
auto[1] |
auto[1] |
668142 |
1 |
|
|
T2 |
2 |
|
T5 |
1 |
|
T106 |
1 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
NAME | COUNT | STATUS |
intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
12490659 |
1 |
|
|
T21 |
2 |
|
T22 |
12 |
|
T1 |
2 |
auto[1] |
10321416 |
1 |
|
|
T21 |
1 |
|
T22 |
9 |
|
T1 |
22 |
Summary for Variable intr_state
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
21480372 |
1 |
|
|
T21 |
3 |
|
T22 |
21 |
|
T1 |
24 |
auto[1] |
1331703 |
1 |
|
|
T2 |
7 |
|
T15 |
1 |
|
T100 |
1 |
Summary for Variable type_ctrl_en
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
12512420 |
1 |
|
|
T21 |
2 |
|
T22 |
21 |
|
T1 |
23 |
auto[1] |
10299655 |
1 |
|
|
T21 |
1 |
|
T1 |
1 |
|
T11 |
6 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
TOTAL |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[1] |
auto[0] |
auto[0] |
4458367 |
1 |
|
|
T11 |
4 |
|
T12 |
1 |
|
T14 |
1 |
auto[1] |
auto[0] |
auto[1] |
660812 |
1 |
|
|
T15 |
1 |
|
T101 |
1 |
|
T81 |
1 |
auto[1] |
auto[1] |
auto[0] |
4509585 |
1 |
|
|
T21 |
1 |
|
T1 |
1 |
|
T11 |
2 |
auto[1] |
auto[1] |
auto[1] |
670891 |
1 |
|
|
T2 |
7 |
|
T100 |
1 |
|
T80 |
5 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
NAME | COUNT | STATUS |
intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
12563839 |
1 |
|
|
T21 |
3 |
|
T22 |
12 |
|
T1 |
21 |
auto[1] |
10248236 |
1 |
|
|
T22 |
9 |
|
T1 |
3 |
|
T11 |
6 |
Summary for Variable intr_state
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
21478676 |
1 |
|
|
T21 |
3 |
|
T22 |
21 |
|
T1 |
24 |
auto[1] |
1333399 |
1 |
|
|
T2 |
6 |
|
T100 |
1 |
|
T79 |
2 |
Summary for Variable type_ctrl_en
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
12498392 |
1 |
|
|
T21 |
2 |
|
T22 |
21 |
|
T1 |
24 |
auto[1] |
10313683 |
1 |
|
|
T21 |
1 |
|
T11 |
3 |
|
T12 |
2 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
TOTAL |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[1] |
auto[0] |
auto[0] |
4511645 |
1 |
|
|
T21 |
1 |
|
T11 |
1 |
|
T12 |
2 |
auto[1] |
auto[0] |
auto[1] |
670359 |
1 |
|
|
T100 |
1 |
|
T88 |
1 |
|
T83 |
1 |
auto[1] |
auto[1] |
auto[0] |
4468639 |
1 |
|
|
T11 |
2 |
|
T2 |
20 |
|
T15 |
1 |
auto[1] |
auto[1] |
auto[1] |
663040 |
1 |
|
|
T2 |
6 |
|
T79 |
2 |
|
T107 |
1 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
NAME | COUNT | STATUS |
intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
12549044 |
1 |
|
|
T21 |
3 |
|
T22 |
13 |
|
T1 |
15 |
auto[1] |
10263031 |
1 |
|
|
T22 |
8 |
|
T1 |
9 |
|
T11 |
8 |
Summary for Variable intr_state
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
21491139 |
1 |
|
|
T21 |
3 |
|
T22 |
21 |
|
T1 |
24 |
auto[1] |
1320936 |
1 |
|
|
T78 |
2 |
|
T101 |
1 |
|
T79 |
2 |
Summary for Variable type_ctrl_en
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
12574502 |
1 |
|
|
T21 |
2 |
|
T22 |
21 |
|
T1 |
24 |
auto[1] |
10237573 |
1 |
|
|
T21 |
1 |
|
T11 |
3 |
|
T12 |
3 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
TOTAL |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[1] |
auto[0] |
auto[0] |
4476834 |
1 |
|
|
T21 |
1 |
|
T11 |
2 |
|
T12 |
1 |
auto[1] |
auto[0] |
auto[1] |
663709 |
1 |
|
|
T101 |
1 |
|
T80 |
1 |
|
T88 |
1 |
auto[1] |
auto[1] |
auto[0] |
4439803 |
1 |
|
|
T11 |
1 |
|
T12 |
2 |
|
T15 |
1 |
auto[1] |
auto[1] |
auto[1] |
657227 |
1 |
|
|
T78 |
2 |
|
T79 |
2 |
|
T106 |
2 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
NAME | COUNT | STATUS |
intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
12505962 |
1 |
|
|
T21 |
3 |
|
T22 |
7 |
|
T1 |
2 |
auto[1] |
10306113 |
1 |
|
|
T22 |
14 |
|
T1 |
22 |
|
T11 |
7 |
Summary for Variable intr_state
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
21491448 |
1 |
|
|
T21 |
3 |
|
T22 |
21 |
|
T1 |
24 |
auto[1] |
1320627 |
1 |
|
|
T15 |
1 |
|
T5 |
1 |
|
T7 |
1 |
Summary for Variable type_ctrl_en
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
12570165 |
1 |
|
|
T21 |
2 |
|
T22 |
21 |
|
T1 |
6 |
auto[1] |
10241910 |
1 |
|
|
T21 |
1 |
|
T1 |
18 |
|
T11 |
7 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
TOTAL |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[1] |
auto[0] |
auto[0] |
4449794 |
1 |
|
|
T21 |
1 |
|
T11 |
5 |
|
T15 |
3 |
auto[1] |
auto[0] |
auto[1] |
658644 |
1 |
|
|
T15 |
1 |
|
T7 |
1 |
|
T80 |
2 |
auto[1] |
auto[1] |
auto[0] |
4471489 |
1 |
|
|
T1 |
18 |
|
T11 |
2 |
|
T12 |
2 |
auto[1] |
auto[1] |
auto[1] |
661983 |
1 |
|
|
T5 |
1 |
|
T80 |
4 |
|
T89 |
2 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
NAME | COUNT | STATUS |
intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
12505435 |
1 |
|
|
T21 |
2 |
|
T22 |
11 |
|
T1 |
24 |
auto[1] |
10306640 |
1 |
|
|
T21 |
1 |
|
T22 |
10 |
|
T11 |
8 |
Summary for Variable intr_state
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
21479458 |
1 |
|
|
T21 |
3 |
|
T22 |
21 |
|
T1 |
19 |
auto[1] |
1332617 |
1 |
|
|
T1 |
5 |
|
T2 |
2 |
|
T15 |
1 |
Summary for Variable type_ctrl_en
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
12522038 |
1 |
|
|
T21 |
3 |
|
T22 |
21 |
|
T1 |
6 |
auto[1] |
10290037 |
1 |
|
|
T1 |
18 |
|
T11 |
4 |
|
T12 |
6 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
TOTAL |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[1] |
auto[0] |
auto[0] |
4447894 |
1 |
|
|
T1 |
13 |
|
T11 |
2 |
|
T12 |
5 |
auto[1] |
auto[0] |
auto[1] |
660093 |
1 |
|
|
T1 |
5 |
|
T2 |
2 |
|
T88 |
1 |
auto[1] |
auto[1] |
auto[0] |
4509526 |
1 |
|
|
T11 |
2 |
|
T12 |
1 |
|
T2 |
8 |
auto[1] |
auto[1] |
auto[1] |
672524 |
1 |
|
|
T15 |
1 |
|
T84 |
1 |
|
T107 |
4 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
NAME | COUNT | STATUS |
intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
12493924 |
1 |
|
|
T21 |
2 |
|
T22 |
7 |
|
T1 |
24 |
auto[1] |
10318151 |
1 |
|
|
T21 |
1 |
|
T22 |
14 |
|
T11 |
6 |
Summary for Variable intr_state
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
21489756 |
1 |
|
|
T21 |
3 |
|
T22 |
21 |
|
T1 |
24 |
auto[1] |
1322319 |
1 |
|
|
T2 |
5 |
|
T100 |
1 |
|
T79 |
2 |
Summary for Variable type_ctrl_en
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
12579344 |
1 |
|
|
T21 |
3 |
|
T22 |
21 |
|
T1 |
23 |
auto[1] |
10232731 |
1 |
|
|
T1 |
1 |
|
T11 |
4 |
|
T12 |
3 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
TOTAL |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[1] |
auto[0] |
auto[0] |
4448751 |
1 |
|
|
T1 |
1 |
|
T11 |
3 |
|
T12 |
2 |
auto[1] |
auto[0] |
auto[1] |
660295 |
1 |
|
|
T2 |
5 |
|
T81 |
1 |
|
T88 |
2 |
auto[1] |
auto[1] |
auto[0] |
4461661 |
1 |
|
|
T11 |
1 |
|
T12 |
1 |
|
T23 |
3 |
auto[1] |
auto[1] |
auto[1] |
662024 |
1 |
|
|
T100 |
1 |
|
T79 |
2 |
|
T84 |
1 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
NAME | COUNT | STATUS |
intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
12558538 |
1 |
|
|
T21 |
2 |
|
T22 |
9 |
|
T1 |
18 |
auto[1] |
10253537 |
1 |
|
|
T21 |
1 |
|
T22 |
12 |
|
T1 |
6 |