Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
12563839 |
1 |
|
|
T21 |
3 |
|
T22 |
12 |
|
T1 |
21 |
| auto[1] |
10248236 |
1 |
|
|
T22 |
9 |
|
T1 |
3 |
|
T11 |
6 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
21489687 |
1 |
|
|
T21 |
3 |
|
T22 |
21 |
|
T1 |
21 |
| auto[1] |
1322388 |
1 |
|
|
T1 |
3 |
|
T11 |
1 |
|
T12 |
1 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
12563108 |
1 |
|
|
T21 |
2 |
|
T22 |
21 |
|
T1 |
6 |
| auto[1] |
10248967 |
1 |
|
|
T21 |
1 |
|
T1 |
18 |
|
T11 |
6 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
4487458 |
1 |
|
|
T21 |
1 |
|
T1 |
15 |
|
T11 |
3 |
| auto[1] |
auto[0] |
auto[1] |
665627 |
1 |
|
|
T1 |
3 |
|
T11 |
1 |
|
T12 |
1 |
| auto[1] |
auto[1] |
auto[0] |
4439121 |
1 |
|
|
T11 |
2 |
|
T12 |
1 |
|
T2 |
13 |
| auto[1] |
auto[1] |
auto[1] |
656761 |
1 |
|
|
T2 |
2 |
|
T101 |
1 |
|
T109 |
1 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
12549044 |
1 |
|
|
T21 |
3 |
|
T22 |
13 |
|
T1 |
15 |
| auto[1] |
10263031 |
1 |
|
|
T22 |
8 |
|
T1 |
9 |
|
T11 |
8 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
21481945 |
1 |
|
|
T21 |
3 |
|
T22 |
21 |
|
T1 |
24 |
| auto[1] |
1330130 |
1 |
|
|
T11 |
1 |
|
T12 |
4 |
|
T14 |
1 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
12521200 |
1 |
|
|
T21 |
3 |
|
T22 |
21 |
|
T1 |
23 |
| auto[1] |
10290875 |
1 |
|
|
T1 |
1 |
|
T11 |
7 |
|
T12 |
6 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
4485013 |
1 |
|
|
T11 |
3 |
|
T12 |
1 |
|
T2 |
20 |
| auto[1] |
auto[0] |
auto[1] |
665521 |
1 |
|
|
T12 |
1 |
|
T14 |
1 |
|
T23 |
3 |
| auto[1] |
auto[1] |
auto[0] |
4475732 |
1 |
|
|
T1 |
1 |
|
T11 |
3 |
|
T12 |
1 |
| auto[1] |
auto[1] |
auto[1] |
664609 |
1 |
|
|
T11 |
1 |
|
T12 |
3 |
|
T23 |
1 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
12505962 |
1 |
|
|
T21 |
3 |
|
T22 |
7 |
|
T1 |
2 |
| auto[1] |
10306113 |
1 |
|
|
T22 |
14 |
|
T1 |
22 |
|
T11 |
7 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
21487680 |
1 |
|
|
T21 |
3 |
|
T22 |
21 |
|
T1 |
24 |
| auto[1] |
1324395 |
1 |
|
|
T11 |
2 |
|
T12 |
2 |
|
T23 |
2 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
12551165 |
1 |
|
|
T21 |
3 |
|
T22 |
21 |
|
T1 |
5 |
| auto[1] |
10260910 |
1 |
|
|
T1 |
19 |
|
T11 |
4 |
|
T12 |
4 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
4452873 |
1 |
|
|
T11 |
2 |
|
T12 |
1 |
|
T2 |
12 |
| auto[1] |
auto[0] |
auto[1] |
659829 |
1 |
|
|
T11 |
1 |
|
T12 |
2 |
|
T23 |
1 |
| auto[1] |
auto[1] |
auto[0] |
4483642 |
1 |
|
|
T1 |
19 |
|
T12 |
1 |
|
T2 |
7 |
| auto[1] |
auto[1] |
auto[1] |
664566 |
1 |
|
|
T11 |
1 |
|
T23 |
1 |
|
T5 |
1 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
12505435 |
1 |
|
|
T21 |
2 |
|
T22 |
11 |
|
T1 |
24 |
| auto[1] |
10306640 |
1 |
|
|
T21 |
1 |
|
T22 |
10 |
|
T11 |
8 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
21489478 |
1 |
|
|
T21 |
2 |
|
T22 |
21 |
|
T1 |
24 |
| auto[1] |
1322597 |
1 |
|
|
T21 |
1 |
|
T11 |
1 |
|
T12 |
2 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
12575806 |
1 |
|
|
T21 |
2 |
|
T22 |
21 |
|
T1 |
24 |
| auto[1] |
10236269 |
1 |
|
|
T21 |
1 |
|
T11 |
6 |
|
T12 |
6 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
4442015 |
1 |
|
|
T11 |
2 |
|
T12 |
3 |
|
T2 |
17 |
| auto[1] |
auto[0] |
auto[1] |
659346 |
1 |
|
|
T11 |
1 |
|
T12 |
1 |
|
T2 |
2 |
| auto[1] |
auto[1] |
auto[0] |
4471657 |
1 |
|
|
T11 |
3 |
|
T12 |
1 |
|
T2 |
8 |
| auto[1] |
auto[1] |
auto[1] |
663251 |
1 |
|
|
T21 |
1 |
|
T12 |
1 |
|
T15 |
1 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
12493924 |
1 |
|
|
T21 |
2 |
|
T22 |
7 |
|
T1 |
24 |
| auto[1] |
10318151 |
1 |
|
|
T21 |
1 |
|
T22 |
14 |
|
T11 |
6 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
21487369 |
1 |
|
|
T21 |
3 |
|
T22 |
21 |
|
T1 |
24 |
| auto[1] |
1324706 |
1 |
|
|
T11 |
1 |
|
T12 |
3 |
|
T23 |
1 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
12558689 |
1 |
|
|
T21 |
2 |
|
T22 |
21 |
|
T1 |
6 |
| auto[1] |
10253386 |
1 |
|
|
T21 |
1 |
|
T1 |
18 |
|
T11 |
6 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
4452717 |
1 |
|
|
T1 |
18 |
|
T11 |
3 |
|
T12 |
3 |
| auto[1] |
auto[0] |
auto[1] |
660460 |
1 |
|
|
T11 |
1 |
|
T12 |
2 |
|
T23 |
1 |
| auto[1] |
auto[1] |
auto[0] |
4475963 |
1 |
|
|
T21 |
1 |
|
T11 |
2 |
|
T23 |
5 |
| auto[1] |
auto[1] |
auto[1] |
664246 |
1 |
|
|
T12 |
1 |
|
T9 |
1 |
|
T10 |
1 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
12558538 |
1 |
|
|
T21 |
2 |
|
T22 |
9 |
|
T1 |
18 |
| auto[1] |
10253537 |
1 |
|
|
T21 |
1 |
|
T22 |
12 |
|
T1 |
6 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
21475578 |
1 |
|
|
T21 |
3 |
|
T22 |
21 |
|
T1 |
24 |
| auto[1] |
1336497 |
1 |
|
|
T11 |
1 |
|
T2 |
1 |
|
T23 |
3 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
12493643 |
1 |
|
|
T21 |
2 |
|
T22 |
21 |
|
T1 |
5 |
| auto[1] |
10318432 |
1 |
|
|
T21 |
1 |
|
T1 |
19 |
|
T11 |
5 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
4497412 |
1 |
|
|
T1 |
13 |
|
T11 |
2 |
|
T12 |
2 |
| auto[1] |
auto[0] |
auto[1] |
669135 |
1 |
|
|
T11 |
1 |
|
T23 |
2 |
|
T4 |
1 |
| auto[1] |
auto[1] |
auto[0] |
4484523 |
1 |
|
|
T21 |
1 |
|
T1 |
6 |
|
T11 |
2 |
| auto[1] |
auto[1] |
auto[1] |
667362 |
1 |
|
|
T2 |
1 |
|
T23 |
1 |
|
T5 |
1 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
12540130 |
1 |
|
|
T21 |
3 |
|
T22 |
11 |
|
T1 |
21 |
| auto[1] |
10271945 |
1 |
|
|
T22 |
10 |
|
T1 |
3 |
|
T11 |
8 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
21491461 |
1 |
|
|
T21 |
3 |
|
T22 |
21 |
|
T1 |
24 |
| auto[1] |
1320614 |
1 |
|
|
T2 |
2 |
|
T23 |
4 |
|
T29 |
1 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
12591813 |
1 |
|
|
T21 |
2 |
|
T22 |
21 |
|
T1 |
6 |
| auto[1] |
10220262 |
1 |
|
|
T21 |
1 |
|
T1 |
18 |
|
T11 |
5 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
4441070 |
1 |
|
|
T21 |
1 |
|
T1 |
18 |
|
T11 |
1 |
| auto[1] |
auto[0] |
auto[1] |
658257 |
1 |
|
|
T2 |
2 |
|
T23 |
3 |
|
T9 |
1 |
| auto[1] |
auto[1] |
auto[0] |
4458578 |
1 |
|
|
T11 |
4 |
|
T12 |
1 |
|
T23 |
4 |
| auto[1] |
auto[1] |
auto[1] |
662357 |
1 |
|
|
T23 |
1 |
|
T29 |
1 |
|
T78 |
3 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
12541902 |
1 |
|
|
T21 |
2 |
|
T22 |
18 |
|
T1 |
21 |
| auto[1] |
10270173 |
1 |
|
|
T21 |
1 |
|
T22 |
3 |
|
T1 |
3 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
21480477 |
1 |
|
|
T21 |
3 |
|
T22 |
21 |
|
T1 |
24 |
| auto[1] |
1331598 |
1 |
|
|
T11 |
1 |
|
T2 |
6 |
|
T23 |
4 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
12517238 |
1 |
|
|
T21 |
3 |
|
T22 |
21 |
|
T1 |
24 |
| auto[1] |
10294837 |
1 |
|
|
T11 |
5 |
|
T12 |
2 |
|
T2 |
19 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
4486972 |
1 |
|
|
T11 |
2 |
|
T12 |
2 |
|
T2 |
4 |
| auto[1] |
auto[0] |
auto[1] |
665806 |
1 |
|
|
T11 |
1 |
|
T2 |
3 |
|
T23 |
3 |
| auto[1] |
auto[1] |
auto[0] |
4476267 |
1 |
|
|
T11 |
2 |
|
T2 |
9 |
|
T23 |
4 |
| auto[1] |
auto[1] |
auto[1] |
665792 |
1 |
|
|
T2 |
3 |
|
T23 |
1 |
|
T107 |
1 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
12528989 |
1 |
|
|
T21 |
2 |
|
T22 |
15 |
|
T1 |
24 |
| auto[1] |
10283086 |
1 |
|
|
T21 |
1 |
|
T22 |
6 |
|
T11 |
6 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
21479276 |
1 |
|
|
T21 |
3 |
|
T22 |
21 |
|
T1 |
24 |
| auto[1] |
1332799 |
1 |
|
|
T12 |
2 |
|
T23 |
2 |
|
T29 |
2 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
12522832 |
1 |
|
|
T21 |
3 |
|
T22 |
21 |
|
T1 |
6 |
| auto[1] |
10289243 |
1 |
|
|
T1 |
18 |
|
T11 |
6 |
|
T12 |
4 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
4492209 |
1 |
|
|
T1 |
18 |
|
T11 |
4 |
|
T12 |
1 |
| auto[1] |
auto[0] |
auto[1] |
669595 |
1 |
|
|
T12 |
1 |
|
T23 |
2 |
|
T29 |
2 |
| auto[1] |
auto[1] |
auto[0] |
4464235 |
1 |
|
|
T11 |
2 |
|
T12 |
1 |
|
T15 |
2 |
| auto[1] |
auto[1] |
auto[1] |
663204 |
1 |
|
|
T12 |
1 |
|
T6 |
1 |
|
T101 |
2 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
12533045 |
1 |
|
|
T21 |
3 |
|
T22 |
12 |
|
T1 |
11 |
| auto[1] |
10279030 |
1 |
|
|
T22 |
9 |
|
T1 |
13 |
|
T11 |
5 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
21485824 |
1 |
|
|
T21 |
2 |
|
T22 |
21 |
|
T1 |
24 |
| auto[1] |
1326251 |
1 |
|
|
T21 |
1 |
|
T11 |
2 |
|
T12 |
1 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
12556916 |
1 |
|
|
T21 |
2 |
|
T22 |
21 |
|
T1 |
6 |
| auto[1] |
10255159 |
1 |
|
|
T21 |
1 |
|
T1 |
18 |
|
T11 |
5 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
4473825 |
1 |
|
|
T1 |
5 |
|
T11 |
3 |
|
T12 |
2 |
| auto[1] |
auto[0] |
auto[1] |
665083 |
1 |
|
|
T21 |
1 |
|
T11 |
1 |
|
T12 |
1 |
| auto[1] |
auto[1] |
auto[0] |
4455083 |
1 |
|
|
T1 |
13 |
|
T12 |
2 |
|
T2 |
16 |
| auto[1] |
auto[1] |
auto[1] |
661168 |
1 |
|
|
T11 |
1 |
|
T2 |
4 |
|
T15 |
1 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
12477583 |
1 |
|
|
T21 |
2 |
|
T22 |
20 |
|
T1 |
2 |
| auto[1] |
10334492 |
1 |
|
|
T21 |
1 |
|
T22 |
1 |
|
T1 |
22 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
21482661 |
1 |
|
|
T21 |
3 |
|
T22 |
21 |
|
T1 |
24 |
| auto[1] |
1329414 |
1 |
|
|
T11 |
3 |
|
T12 |
2 |
|
T2 |
3 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
12537024 |
1 |
|
|
T21 |
2 |
|
T22 |
21 |
|
T1 |
23 |
| auto[1] |
10275051 |
1 |
|
|
T21 |
1 |
|
T1 |
1 |
|
T11 |
7 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
4442861 |
1 |
|
|
T11 |
4 |
|
T12 |
1 |
|
T14 |
1 |
| auto[1] |
auto[0] |
auto[1] |
658760 |
1 |
|
|
T11 |
1 |
|
T14 |
1 |
|
T15 |
1 |
| auto[1] |
auto[1] |
auto[0] |
4502776 |
1 |
|
|
T21 |
1 |
|
T1 |
1 |
|
T12 |
1 |
| auto[1] |
auto[1] |
auto[1] |
670654 |
1 |
|
|
T11 |
2 |
|
T12 |
2 |
|
T2 |
3 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
12506171 |
1 |
|
|
T21 |
3 |
|
T22 |
14 |
|
T1 |
11 |
| auto[1] |
10305904 |
1 |
|
|
T22 |
7 |
|
T1 |
13 |
|
T11 |
6 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
21482260 |
1 |
|
|
T21 |
3 |
|
T22 |
21 |
|
T1 |
24 |
| auto[1] |
1329815 |
1 |
|
|
T11 |
1 |
|
T12 |
1 |
|
T23 |
2 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
12535005 |
1 |
|
|
T21 |
3 |
|
T22 |
21 |
|
T1 |
23 |
| auto[1] |
10277070 |
1 |
|
|
T1 |
1 |
|
T11 |
4 |
|
T12 |
2 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
4478219 |
1 |
|
|
T1 |
1 |
|
T11 |
1 |
|
T12 |
1 |
| auto[1] |
auto[0] |
auto[1] |
665570 |
1 |
|
|
T11 |
1 |
|
T23 |
2 |
|
T101 |
2 |
| auto[1] |
auto[1] |
auto[0] |
4469036 |
1 |
|
|
T11 |
2 |
|
T14 |
2 |
|
T15 |
1 |
| auto[1] |
auto[1] |
auto[1] |
664245 |
1 |
|
|
T12 |
1 |
|
T29 |
1 |
|
T6 |
1 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
12500518 |
1 |
|
|
T21 |
2 |
|
T22 |
14 |
|
T1 |
21 |
| auto[1] |
10311557 |
1 |
|
|
T21 |
1 |
|
T22 |
7 |
|
T1 |
3 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
21484568 |
1 |
|
|
T21 |
3 |
|
T22 |
21 |
|
T1 |
20 |
| auto[1] |
1327507 |
1 |
|
|
T1 |
4 |
|
T12 |
1 |
|
T23 |
1 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
12548851 |
1 |
|
|
T21 |
3 |
|
T22 |
21 |
|
T1 |
5 |
| auto[1] |
10263224 |
1 |
|
|
T1 |
19 |
|
T11 |
5 |
|
T12 |
5 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
4460989 |
1 |
|
|
T1 |
15 |
|
T11 |
4 |
|
T12 |
2 |
| auto[1] |
auto[0] |
auto[1] |
661109 |
1 |
|
|
T1 |
4 |
|
T9 |
2 |
|
T79 |
3 |
| auto[1] |
auto[1] |
auto[0] |
4474728 |
1 |
|
|
T11 |
1 |
|
T12 |
2 |
|
T15 |
2 |
| auto[1] |
auto[1] |
auto[1] |
666398 |
1 |
|
|
T12 |
1 |
|
T23 |
1 |
|
T29 |
1 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
12531434 |
1 |
|
|
T21 |
3 |
|
T22 |
10 |
|
T1 |
11 |
| auto[1] |
10280641 |
1 |
|
|
T22 |
11 |
|
T1 |
13 |
|
T11 |
5 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
21479130 |
1 |
|
|
T21 |
3 |
|
T22 |
21 |
|
T1 |
19 |
| auto[1] |
1332945 |
1 |
|
|
T1 |
5 |
|
T11 |
3 |
|
T2 |
5 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
12500979 |
1 |
|
|
T21 |
2 |
|
T22 |
21 |
|
T1 |
6 |
| auto[1] |
10311096 |
1 |
|
|
T21 |
1 |
|
T1 |
18 |
|
T11 |
8 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
4476277 |
1 |
|
|
T21 |
1 |
|
T1 |
4 |
|
T11 |
4 |
| auto[1] |
auto[0] |
auto[1] |
664746 |
1 |
|
|
T1 |
1 |
|
T11 |
3 |
|
T2 |
1 |
| auto[1] |
auto[1] |
auto[0] |
4501874 |
1 |
|
|
T1 |
9 |
|
T11 |
1 |
|
T12 |
2 |
| auto[1] |
auto[1] |
auto[1] |
668199 |
1 |
|
|
T1 |
4 |
|
T2 |
4 |
|
T15 |
1 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
12563851 |
1 |
|
|
T21 |
3 |
|
T22 |
11 |
|
T1 |
21 |
| auto[1] |
10248224 |
1 |
|
|
T22 |
10 |
|
T1 |
3 |
|
T11 |
7 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
21478295 |
1 |
|
|
T21 |
3 |
|
T22 |
21 |
|
T1 |
21 |
| auto[1] |
1333780 |
1 |
|
|
T1 |
3 |
|
T12 |
2 |
|
T14 |
1 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
12514404 |
1 |
|
|
T21 |
3 |
|
T22 |
21 |
|
T1 |
5 |
| auto[1] |
10297671 |
1 |
|
|
T1 |
19 |
|
T11 |
5 |
|
T12 |
3 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
4497423 |
1 |
|
|
T1 |
16 |
|
T11 |
4 |
|
T12 |
1 |
| auto[1] |
auto[0] |
auto[1] |
669820 |
1 |
|
|
T1 |
3 |
|
T12 |
2 |
|
T23 |
1 |
| auto[1] |
auto[1] |
auto[0] |
4466468 |
1 |
|
|
T11 |
1 |
|
T14 |
1 |
|
T23 |
2 |
| auto[1] |
auto[1] |
auto[1] |
663960 |
1 |
|
|
T14 |
1 |
|
T23 |
1 |
|
T9 |
1 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |