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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
99.61 99.06 99.10 100.00 99.80 99.68 100.00


Total test records in report: 970
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T764 /workspace/coverage/default/13.gpio_random_long_reg_writes_reg_reads.4140812305 Dec 24 01:10:30 PM PST 23 Dec 24 01:10:40 PM PST 23 7872687055 ps
T765 /workspace/coverage/default/10.gpio_random_long_reg_writes_reg_reads.1245720096 Dec 24 01:10:18 PM PST 23 Dec 24 01:10:25 PM PST 23 1120586738 ps
T766 /workspace/coverage/default/20.gpio_rand_intr_trigger.1943203750 Dec 24 01:10:43 PM PST 23 Dec 24 01:10:54 PM PST 23 953223586 ps
T767 /workspace/coverage/default/9.gpio_random_dout_din_no_pullup_pulldown.3150209052 Dec 24 01:10:13 PM PST 23 Dec 24 01:10:19 PM PST 23 109754254 ps
T768 /workspace/coverage/default/37.gpio_filter_stress.2305985806 Dec 24 01:11:07 PM PST 23 Dec 24 01:11:28 PM PST 23 343754167 ps
T769 /workspace/coverage/default/14.gpio_full_random.391168108 Dec 24 01:10:15 PM PST 23 Dec 24 01:10:21 PM PST 23 316878119 ps
T770 /workspace/coverage/default/20.gpio_random_long_reg_writes_reg_reads.2909179362 Dec 24 01:10:32 PM PST 23 Dec 24 01:10:40 PM PST 23 366143684 ps
T771 /workspace/coverage/default/12.gpio_rand_intr_trigger.1470822617 Dec 24 01:10:43 PM PST 23 Dec 24 01:10:54 PM PST 23 68309182 ps
T772 /workspace/coverage/default/29.gpio_stress_all_with_rand_reset.1009920022 Dec 24 01:10:45 PM PST 23 Dec 24 01:30:15 PM PST 23 362204650669 ps
T773 /workspace/coverage/default/32.gpio_stress_all.4069210528 Dec 24 01:10:54 PM PST 23 Dec 24 01:13:39 PM PST 23 26414899115 ps
T774 /workspace/coverage/default/10.gpio_filter_stress.535126924 Dec 24 01:10:26 PM PST 23 Dec 24 01:11:04 PM PST 23 785794955 ps
T775 /workspace/coverage/default/33.gpio_stress_all_with_rand_reset.4055652457 Dec 24 01:10:46 PM PST 23 Dec 24 01:15:05 PM PST 23 62695462691 ps
T776 /workspace/coverage/default/0.gpio_intr_with_filter_rand_intr_event.3825634925 Dec 24 01:09:50 PM PST 23 Dec 24 01:09:57 PM PST 23 138202249 ps
T777 /workspace/coverage/default/12.gpio_intr_rand_pgm.151027685 Dec 24 01:10:41 PM PST 23 Dec 24 01:10:49 PM PST 23 75119425 ps
T778 /workspace/coverage/default/21.gpio_smoke_no_pullup_pulldown.1700492440 Dec 24 01:10:36 PM PST 23 Dec 24 01:10:43 PM PST 23 235404534 ps
T779 /workspace/coverage/default/5.gpio_stress_all_with_rand_reset.728330778 Dec 24 01:10:18 PM PST 23 Dec 24 01:27:41 PM PST 23 150092380764 ps
T780 /workspace/coverage/default/39.gpio_random_long_reg_writes_reg_reads.2181009256 Dec 24 01:11:09 PM PST 23 Dec 24 01:11:19 PM PST 23 201343760 ps
T781 /workspace/coverage/default/30.gpio_stress_all.3244260695 Dec 24 01:10:52 PM PST 23 Dec 24 01:13:44 PM PST 23 25944815574 ps
T782 /workspace/coverage/default/42.gpio_random_dout_din.3627450551 Dec 24 01:11:12 PM PST 23 Dec 24 01:11:21 PM PST 23 678285874 ps
T783 /workspace/coverage/default/5.gpio_alert_test.1683725558 Dec 24 01:10:03 PM PST 23 Dec 24 01:10:08 PM PST 23 14541130 ps
T784 /workspace/coverage/default/4.gpio_random_dout_din.3812787937 Dec 24 01:10:35 PM PST 23 Dec 24 01:10:40 PM PST 23 22311184 ps
T785 /workspace/coverage/default/8.gpio_random_dout_din_no_pullup_pulldown.3348591850 Dec 24 01:10:04 PM PST 23 Dec 24 01:10:09 PM PST 23 51671498 ps
T786 /workspace/coverage/default/35.gpio_filter_stress.1171211387 Dec 24 01:11:18 PM PST 23 Dec 24 01:11:42 PM PST 23 894552153 ps
T787 /workspace/coverage/default/16.gpio_random_dout_din_no_pullup_pulldown.2215882679 Dec 24 01:10:41 PM PST 23 Dec 24 01:10:50 PM PST 23 104917102 ps
T788 /workspace/coverage/default/36.gpio_random_dout_din.3713974269 Dec 24 01:10:58 PM PST 23 Dec 24 01:11:10 PM PST 23 75081265 ps
T789 /workspace/coverage/default/13.gpio_dout_din_regs_random_rw.549060702 Dec 24 01:10:31 PM PST 23 Dec 24 01:10:34 PM PST 23 47162577 ps
T790 /workspace/coverage/default/20.gpio_stress_all_with_rand_reset.3827341713 Dec 24 01:10:33 PM PST 23 Dec 24 01:51:47 PM PST 23 89902595631 ps
T791 /workspace/coverage/default/27.gpio_intr_with_filter_rand_intr_event.1031114122 Dec 24 01:10:55 PM PST 23 Dec 24 01:11:08 PM PST 23 107804285 ps
T792 /workspace/coverage/default/10.gpio_stress_all.1250483223 Dec 24 01:10:21 PM PST 23 Dec 24 01:11:09 PM PST 23 1647022541 ps
T793 /workspace/coverage/default/32.gpio_intr_rand_pgm.3126057389 Dec 24 01:10:48 PM PST 23 Dec 24 01:10:59 PM PST 23 103458640 ps
T794 /workspace/coverage/default/40.gpio_stress_all_with_rand_reset.3913700183 Dec 24 01:11:13 PM PST 23 Dec 24 01:37:34 PM PST 23 380559715401 ps
T795 /workspace/coverage/default/4.gpio_rand_intr_trigger.3250621925 Dec 24 01:10:19 PM PST 23 Dec 24 01:10:24 PM PST 23 144713119 ps
T796 /workspace/coverage/default/11.gpio_intr_with_filter_rand_intr_event.1775145434 Dec 24 01:10:17 PM PST 23 Dec 24 01:10:24 PM PST 23 207263592 ps
T797 /workspace/coverage/default/24.gpio_random_dout_din_no_pullup_pulldown.2978854551 Dec 24 01:10:34 PM PST 23 Dec 24 01:10:39 PM PST 23 55113188 ps
T798 /workspace/coverage/default/8.gpio_filter_stress.651860464 Dec 24 01:10:04 PM PST 23 Dec 24 01:10:24 PM PST 23 2399710702 ps
T799 /workspace/coverage/default/28.gpio_smoke.328528709 Dec 24 01:10:45 PM PST 23 Dec 24 01:10:57 PM PST 23 188523100 ps
T800 /workspace/coverage/default/12.gpio_full_random.2971542566 Dec 24 01:10:30 PM PST 23 Dec 24 01:10:40 PM PST 23 63772794 ps
T801 /workspace/coverage/default/19.gpio_intr_with_filter_rand_intr_event.2492993171 Dec 24 01:10:51 PM PST 23 Dec 24 01:11:03 PM PST 23 52228238 ps
T802 /workspace/coverage/default/2.gpio_random_long_reg_writes_reg_reads.2598402618 Dec 24 01:10:33 PM PST 23 Dec 24 01:10:39 PM PST 23 118995182 ps
T803 /workspace/coverage/default/43.gpio_intr_with_filter_rand_intr_event.3757757261 Dec 24 01:11:27 PM PST 23 Dec 24 01:11:35 PM PST 23 313006133 ps
T804 /workspace/coverage/default/7.gpio_intr_rand_pgm.1961611880 Dec 24 01:10:20 PM PST 23 Dec 24 01:10:28 PM PST 23 51256794 ps
T805 /workspace/coverage/default/37.gpio_rand_intr_trigger.3118815671 Dec 24 01:10:43 PM PST 23 Dec 24 01:10:54 PM PST 23 67984696 ps
T806 /workspace/coverage/default/25.gpio_random_dout_din.3683980220 Dec 24 01:10:33 PM PST 23 Dec 24 01:10:38 PM PST 23 161285082 ps
T807 /workspace/coverage/default/48.gpio_alert_test.2362065699 Dec 24 01:11:30 PM PST 23 Dec 24 01:11:38 PM PST 23 12376106 ps
T808 /workspace/coverage/default/35.gpio_dout_din_regs_random_rw.2039261983 Dec 24 01:10:54 PM PST 23 Dec 24 01:11:06 PM PST 23 36317345 ps
T809 /workspace/coverage/default/30.gpio_full_random.3928100780 Dec 24 01:10:43 PM PST 23 Dec 24 01:10:53 PM PST 23 53892505 ps
T810 /workspace/coverage/default/35.gpio_intr_with_filter_rand_intr_event.3041016099 Dec 24 01:10:53 PM PST 23 Dec 24 01:11:08 PM PST 23 339996531 ps
T811 /workspace/coverage/default/25.gpio_smoke_no_pullup_pulldown.1109190551 Dec 24 01:10:43 PM PST 23 Dec 24 01:10:53 PM PST 23 112097656 ps
T812 /workspace/coverage/default/20.gpio_filter_stress.963915231 Dec 24 01:10:37 PM PST 23 Dec 24 01:10:50 PM PST 23 163564513 ps
T813 /workspace/coverage/default/4.gpio_intr_rand_pgm.3361497617 Dec 24 01:10:39 PM PST 23 Dec 24 01:10:47 PM PST 23 283545912 ps
T814 /workspace/coverage/default/13.gpio_rand_intr_trigger.3981602226 Dec 24 01:10:31 PM PST 23 Dec 24 01:10:37 PM PST 23 551545319 ps
T815 /workspace/coverage/default/32.gpio_full_random.331559568 Dec 24 01:10:49 PM PST 23 Dec 24 01:11:00 PM PST 23 311765135 ps
T816 /workspace/coverage/default/24.gpio_full_random.1634972780 Dec 24 01:10:33 PM PST 23 Dec 24 01:10:37 PM PST 23 70309467 ps
T817 /workspace/coverage/default/47.gpio_filter_stress.176005925 Dec 24 01:11:34 PM PST 23 Dec 24 01:11:49 PM PST 23 657968002 ps
T58 /workspace/coverage/default/3.gpio_sec_cm.491693675 Dec 24 01:10:22 PM PST 23 Dec 24 01:10:27 PM PST 23 407328446 ps
T818 /workspace/coverage/default/35.gpio_random_dout_din_no_pullup_pulldown.1785636760 Dec 24 01:10:56 PM PST 23 Dec 24 01:11:08 PM PST 23 182434329 ps
T819 /workspace/coverage/default/17.gpio_smoke.3973533265 Dec 24 01:10:37 PM PST 23 Dec 24 01:10:43 PM PST 23 59129122 ps
T820 /workspace/coverage/default/33.gpio_intr_rand_pgm.490123187 Dec 24 01:10:53 PM PST 23 Dec 24 01:11:05 PM PST 23 251956140 ps
T821 /workspace/coverage/default/37.gpio_random_long_reg_writes_reg_reads.1272475253 Dec 24 01:10:59 PM PST 23 Dec 24 01:11:15 PM PST 23 70993033 ps
T822 /workspace/coverage/default/2.gpio_random_dout_din.3633672837 Dec 24 01:10:03 PM PST 23 Dec 24 01:10:07 PM PST 23 90496776 ps
T823 /workspace/coverage/default/36.gpio_random_long_reg_writes_reg_reads.2678559813 Dec 24 01:10:47 PM PST 23 Dec 24 01:11:03 PM PST 23 108534622 ps
T824 /workspace/coverage/default/15.gpio_random_long_reg_writes_reg_reads.123142727 Dec 24 01:10:23 PM PST 23 Dec 24 01:10:32 PM PST 23 832730272 ps
T825 /workspace/coverage/default/48.gpio_random_dout_din.1271994258 Dec 24 01:11:53 PM PST 23 Dec 24 01:12:02 PM PST 23 25634396 ps
T826 /workspace/coverage/default/26.gpio_intr_with_filter_rand_intr_event.46953784 Dec 24 01:10:40 PM PST 23 Dec 24 01:10:51 PM PST 23 93608355 ps
T827 /workspace/coverage/default/6.gpio_smoke.1677286220 Dec 24 01:10:01 PM PST 23 Dec 24 01:10:06 PM PST 23 367972996 ps
T828 /workspace/coverage/default/24.gpio_random_dout_din.4197385434 Dec 24 01:10:55 PM PST 23 Dec 24 01:11:07 PM PST 23 100365689 ps
T829 /workspace/coverage/default/10.gpio_smoke.30645653 Dec 24 01:10:10 PM PST 23 Dec 24 01:10:16 PM PST 23 32019825 ps
T830 /workspace/coverage/default/45.gpio_stress_all.3121131304 Dec 24 01:11:32 PM PST 23 Dec 24 01:13:47 PM PST 23 17161442736 ps
T831 /workspace/coverage/default/11.gpio_stress_all.4151781200 Dec 24 01:10:41 PM PST 23 Dec 24 01:12:15 PM PST 23 36494756105 ps
T832 /workspace/coverage/default/1.gpio_smoke_no_pullup_pulldown.1950881291 Dec 24 01:09:54 PM PST 23 Dec 24 01:09:59 PM PST 23 306627703 ps
T833 /workspace/coverage/default/6.gpio_stress_all.847345254 Dec 24 01:10:12 PM PST 23 Dec 24 01:12:00 PM PST 23 7063821882 ps
T834 /workspace/coverage/default/25.gpio_stress_all_with_rand_reset.1397124138 Dec 24 01:10:42 PM PST 23 Dec 24 01:24:40 PM PST 23 301287018271 ps
T835 /workspace/coverage/default/9.gpio_stress_all.2640916062 Dec 24 01:10:04 PM PST 23 Dec 24 01:13:22 PM PST 23 74395902375 ps
T836 /workspace/coverage/default/43.gpio_rand_intr_trigger.2016663943 Dec 24 01:11:05 PM PST 23 Dec 24 01:11:17 PM PST 23 103300479 ps
T837 /workspace/coverage/default/31.gpio_filter_stress.2735459077 Dec 24 01:10:51 PM PST 23 Dec 24 01:11:09 PM PST 23 159103248 ps
T838 /workspace/coverage/default/10.gpio_rand_intr_trigger.2396060580 Dec 24 01:10:09 PM PST 23 Dec 24 01:10:18 PM PST 23 230360367 ps
T839 /workspace/coverage/default/42.gpio_rand_intr_trigger.106811114 Dec 24 01:10:56 PM PST 23 Dec 24 01:11:10 PM PST 23 1001474230 ps
T840 /workspace/coverage/default/30.gpio_rand_intr_trigger.2444215961 Dec 24 01:10:42 PM PST 23 Dec 24 01:10:53 PM PST 23 101150198 ps
T841 /workspace/coverage/default/42.gpio_stress_all_with_rand_reset.368893502 Dec 24 01:10:59 PM PST 23 Dec 24 01:17:00 PM PST 23 52816345640 ps
T842 /workspace/coverage/default/22.gpio_rand_intr_trigger.2284074652 Dec 24 01:10:37 PM PST 23 Dec 24 01:10:45 PM PST 23 212997493 ps
T843 /workspace/coverage/default/0.gpio_stress_all_with_rand_reset.1236905419 Dec 24 01:10:04 PM PST 23 Dec 24 01:25:01 PM PST 23 262906845030 ps
T844 /workspace/coverage/default/34.gpio_alert_test.3206221613 Dec 24 01:10:39 PM PST 23 Dec 24 01:10:47 PM PST 23 94013358 ps
T845 /workspace/coverage/default/2.gpio_smoke_no_pullup_pulldown.3719052537 Dec 24 01:10:07 PM PST 23 Dec 24 01:10:14 PM PST 23 333064805 ps
T846 /workspace/coverage/default/47.gpio_random_long_reg_writes_reg_reads.4181948640 Dec 24 01:11:38 PM PST 23 Dec 24 01:11:56 PM PST 23 1032170234 ps
T847 /workspace/coverage/default/5.gpio_smoke_no_pullup_pulldown.1264648971 Dec 24 01:10:10 PM PST 23 Dec 24 01:10:17 PM PST 23 148745811 ps
T848 /workspace/coverage/default/5.gpio_smoke.1178366217 Dec 24 01:10:05 PM PST 23 Dec 24 01:10:10 PM PST 23 54165404 ps
T849 /workspace/coverage/default/16.gpio_alert_test.3776205848 Dec 24 01:10:41 PM PST 23 Dec 24 01:10:49 PM PST 23 11447387 ps
T850 /workspace/coverage/default/6.gpio_dout_din_regs_random_rw.2488098423 Dec 24 01:10:08 PM PST 23 Dec 24 01:10:15 PM PST 23 25587589 ps
T851 /workspace/coverage/default/31.gpio_random_long_reg_writes_reg_reads.2161527947 Dec 24 01:10:43 PM PST 23 Dec 24 01:10:56 PM PST 23 265851781 ps
T852 /workspace/coverage/default/1.gpio_stress_all_with_rand_reset.1025967541 Dec 24 01:09:50 PM PST 23 Dec 24 01:33:20 PM PST 23 96454441211 ps
T853 /workspace/coverage/default/32.gpio_intr_with_filter_rand_intr_event.425010505 Dec 24 01:10:39 PM PST 23 Dec 24 01:10:48 PM PST 23 96640688 ps
T854 /workspace/coverage/default/39.gpio_intr_rand_pgm.777013185 Dec 24 01:10:58 PM PST 23 Dec 24 01:11:12 PM PST 23 23600221 ps
T855 /workspace/coverage/default/21.gpio_stress_all.2770993589 Dec 24 01:10:39 PM PST 23 Dec 24 01:13:12 PM PST 23 13932049646 ps
T856 /workspace/coverage/default/7.gpio_intr_with_filter_rand_intr_event.1686519519 Dec 24 01:10:18 PM PST 23 Dec 24 01:10:25 PM PST 23 226168536 ps
T857 /workspace/coverage/default/0.gpio_filter_stress.2923211777 Dec 24 01:10:06 PM PST 23 Dec 24 01:10:35 PM PST 23 2934624063 ps
T858 /workspace/coverage/default/46.gpio_random_dout_din_no_pullup_pulldown.627908876 Dec 24 01:11:35 PM PST 23 Dec 24 01:11:47 PM PST 23 67766691 ps
T859 /workspace/coverage/default/2.gpio_intr_rand_pgm.1442946647 Dec 24 01:10:20 PM PST 23 Dec 24 01:10:24 PM PST 23 112760786 ps
T860 /workspace/coverage/default/18.gpio_random_dout_din.2740161491 Dec 24 01:10:43 PM PST 23 Dec 24 01:10:53 PM PST 23 51579479 ps
T861 /workspace/coverage/default/29.gpio_rand_intr_trigger.4063293656 Dec 24 01:10:42 PM PST 23 Dec 24 01:10:53 PM PST 23 104477950 ps
T862 /workspace/coverage/default/41.gpio_rand_intr_trigger.1672257784 Dec 24 01:11:04 PM PST 23 Dec 24 01:11:16 PM PST 23 195909007 ps
T87 /workspace/coverage/default/11.gpio_stress_all_with_rand_reset.815361556 Dec 24 01:10:37 PM PST 23 Dec 24 01:15:35 PM PST 23 87140798621 ps
T863 /workspace/coverage/default/41.gpio_random_long_reg_writes_reg_reads.3097072122 Dec 24 01:11:00 PM PST 23 Dec 24 01:11:16 PM PST 23 906432203 ps
T864 /workspace/coverage/default/2.gpio_dout_din_regs_random_rw.915220934 Dec 24 01:10:03 PM PST 23 Dec 24 01:10:08 PM PST 23 97551099 ps
T865 /workspace/coverage/default/2.gpio_full_random.1328756073 Dec 24 01:10:02 PM PST 23 Dec 24 01:10:06 PM PST 23 195946222 ps
T866 /workspace/coverage/default/29.gpio_intr_rand_pgm.2165853306 Dec 24 01:11:03 PM PST 23 Dec 24 01:11:16 PM PST 23 59189078 ps
T867 /workspace/coverage/default/27.gpio_stress_all.1446316862 Dec 24 01:11:03 PM PST 23 Dec 24 01:13:39 PM PST 23 57768163055 ps
T868 /workspace/coverage/default/1.gpio_filter_stress.3870826863 Dec 24 01:10:00 PM PST 23 Dec 24 01:10:26 PM PST 23 8210879518 ps
T869 /workspace/coverage/default/7.gpio_dout_din_regs_random_rw.2506240284 Dec 24 01:10:06 PM PST 23 Dec 24 01:10:13 PM PST 23 107868735 ps
T870 /workspace/coverage/default/29.gpio_stress_all.1925168179 Dec 24 01:10:39 PM PST 23 Dec 24 01:11:15 PM PST 23 24108292610 ps
T871 /workspace/coverage/default/9.gpio_alert_test.637905959 Dec 24 01:10:04 PM PST 23 Dec 24 01:10:08 PM PST 23 30196487 ps
T872 /workspace/coverage/default/27.gpio_dout_din_regs_random_rw.1162075201 Dec 24 01:10:43 PM PST 23 Dec 24 01:10:54 PM PST 23 70798877 ps
T873 /workspace/coverage/default/21.gpio_dout_din_regs_random_rw.2862368718 Dec 24 01:10:53 PM PST 23 Dec 24 01:11:04 PM PST 23 162838554 ps
T874 /workspace/coverage/default/34.gpio_random_dout_din.3247962025 Dec 24 01:10:47 PM PST 23 Dec 24 01:10:59 PM PST 23 338984842 ps
T875 /workspace/coverage/default/30.gpio_smoke.686859216 Dec 24 01:10:43 PM PST 23 Dec 24 01:10:53 PM PST 23 34080092 ps
T876 /workspace/coverage/default/28.gpio_stress_all_with_rand_reset.3870677542 Dec 24 01:10:41 PM PST 23 Dec 24 01:18:38 PM PST 23 28648940909 ps
T877 /workspace/coverage/default/25.gpio_intr_with_filter_rand_intr_event.2988183671 Dec 24 01:10:35 PM PST 23 Dec 24 01:10:42 PM PST 23 64584901 ps
T878 /workspace/coverage/default/45.gpio_random_dout_din.3515618378 Dec 24 01:11:19 PM PST 23 Dec 24 01:11:28 PM PST 23 44520171 ps
T879 /workspace/coverage/default/23.gpio_filter_stress.854253092 Dec 24 01:10:37 PM PST 23 Dec 24 01:10:55 PM PST 23 1401112271 ps
T880 /workspace/coverage/default/42.gpio_dout_din_regs_random_rw.2918192610 Dec 24 01:11:02 PM PST 23 Dec 24 01:11:14 PM PST 23 30219550 ps
T881 /workspace/coverage/default/41.gpio_intr_with_filter_rand_intr_event.1685220103 Dec 24 01:11:15 PM PST 23 Dec 24 01:11:25 PM PST 23 69538745 ps
T882 /workspace/coverage/default/20.gpio_intr_with_filter_rand_intr_event.3310869870 Dec 24 01:10:27 PM PST 23 Dec 24 01:10:32 PM PST 23 67899718 ps
T883 /workspace/coverage/default/34.gpio_intr_rand_pgm.520958399 Dec 24 01:10:53 PM PST 23 Dec 24 01:11:05 PM PST 23 36308767 ps
T884 /workspace/coverage/default/37.gpio_intr_with_filter_rand_intr_event.672901830 Dec 24 01:10:49 PM PST 23 Dec 24 01:11:03 PM PST 23 92639015 ps
T885 /workspace/coverage/default/26.gpio_dout_din_regs_random_rw.3037424109 Dec 24 01:10:59 PM PST 23 Dec 24 01:11:13 PM PST 23 172741872 ps
T886 /workspace/coverage/default/22.gpio_random_long_reg_writes_reg_reads.2983801442 Dec 24 01:10:28 PM PST 23 Dec 24 01:10:32 PM PST 23 56872292 ps
T887 /workspace/coverage/cover_reg_top/8.gpio_csr_rw.963750800 Dec 24 01:42:40 PM PST 23 Dec 24 01:42:53 PM PST 23 15178982 ps
T94 /workspace/coverage/cover_reg_top/4.gpio_csr_hw_reset.790968444 Dec 24 01:41:52 PM PST 23 Dec 24 01:41:56 PM PST 23 20415773 ps
T888 /workspace/coverage/cover_reg_top/6.gpio_csr_mem_rw_with_rand_reset.2449614469 Dec 24 01:42:19 PM PST 23 Dec 24 01:42:22 PM PST 23 26625509 ps
T889 /workspace/coverage/cover_reg_top/13.gpio_intr_test.1668168483 Dec 24 01:41:53 PM PST 23 Dec 24 01:41:59 PM PST 23 12843065 ps
T890 /workspace/coverage/cover_reg_top/19.gpio_tl_errors.1112458097 Dec 24 01:41:57 PM PST 23 Dec 24 01:42:05 PM PST 23 99431560 ps
T891 /workspace/coverage/cover_reg_top/13.gpio_csr_rw.3978094873 Dec 24 01:41:51 PM PST 23 Dec 24 01:41:53 PM PST 23 37121296 ps
T892 /workspace/coverage/cover_reg_top/3.gpio_csr_hw_reset.4064806428 Dec 24 01:42:39 PM PST 23 Dec 24 01:42:53 PM PST 23 39507386 ps
T893 /workspace/coverage/cover_reg_top/16.gpio_tl_errors.973271980 Dec 24 01:41:53 PM PST 23 Dec 24 01:42:00 PM PST 23 63942799 ps
T894 /workspace/coverage/cover_reg_top/11.gpio_csr_mem_rw_with_rand_reset.579711397 Dec 24 01:42:48 PM PST 23 Dec 24 01:43:12 PM PST 23 29323065 ps
T895 /workspace/coverage/cover_reg_top/0.gpio_csr_aliasing.2891438266 Dec 24 01:41:55 PM PST 23 Dec 24 01:42:02 PM PST 23 50099602 ps
T896 /workspace/coverage/cover_reg_top/18.gpio_tl_errors.3232576977 Dec 24 01:41:55 PM PST 23 Dec 24 01:42:02 PM PST 23 25150196 ps
T897 /workspace/coverage/cover_reg_top/1.gpio_same_csr_outstanding.599560361 Dec 24 01:41:55 PM PST 23 Dec 24 01:42:02 PM PST 23 45940113 ps
T898 /workspace/coverage/cover_reg_top/7.gpio_same_csr_outstanding.335068536 Dec 24 01:41:57 PM PST 23 Dec 24 01:42:04 PM PST 23 117027376 ps
T899 /workspace/coverage/cover_reg_top/17.gpio_intr_test.131690913 Dec 24 01:41:55 PM PST 23 Dec 24 01:42:02 PM PST 23 111982312 ps
T900 /workspace/coverage/cover_reg_top/10.gpio_tl_errors.2168655565 Dec 24 01:42:47 PM PST 23 Dec 24 01:43:09 PM PST 23 65689504 ps
T901 /workspace/coverage/cover_reg_top/17.gpio_same_csr_outstanding.3481648858 Dec 24 01:42:40 PM PST 23 Dec 24 01:42:53 PM PST 23 46152376 ps
T902 /workspace/coverage/cover_reg_top/5.gpio_tl_intg_err.456114980 Dec 24 01:42:36 PM PST 23 Dec 24 01:42:43 PM PST 23 184129024 ps
T903 /workspace/coverage/cover_reg_top/3.gpio_csr_bit_bash.2303582622 Dec 24 01:42:48 PM PST 23 Dec 24 01:43:12 PM PST 23 537856030 ps
T95 /workspace/coverage/cover_reg_top/0.gpio_csr_rw.266933068 Dec 24 01:41:53 PM PST 23 Dec 24 01:41:57 PM PST 23 13425959 ps
T904 /workspace/coverage/cover_reg_top/28.gpio_intr_test.757081544 Dec 24 01:42:16 PM PST 23 Dec 24 01:42:19 PM PST 23 14699642 ps
T96 /workspace/coverage/cover_reg_top/16.gpio_csr_rw.2282989959 Dec 24 01:42:39 PM PST 23 Dec 24 01:42:53 PM PST 23 17983634 ps
T905 /workspace/coverage/cover_reg_top/11.gpio_intr_test.3805707456 Dec 24 01:42:52 PM PST 23 Dec 24 01:43:15 PM PST 23 32553989 ps
T906 /workspace/coverage/cover_reg_top/5.gpio_tl_errors.247291532 Dec 24 01:42:37 PM PST 23 Dec 24 01:42:45 PM PST 23 183612596 ps
T907 /workspace/coverage/cover_reg_top/49.gpio_intr_test.2243636168 Dec 24 01:41:55 PM PST 23 Dec 24 01:42:02 PM PST 23 16478856 ps
T908 /workspace/coverage/cover_reg_top/4.gpio_intr_test.3207227213 Dec 24 01:41:52 PM PST 23 Dec 24 01:41:56 PM PST 23 32052666 ps
T909 /workspace/coverage/cover_reg_top/32.gpio_intr_test.3830308888 Dec 24 01:41:53 PM PST 23 Dec 24 01:41:59 PM PST 23 18089481 ps
T910 /workspace/coverage/cover_reg_top/18.gpio_csr_mem_rw_with_rand_reset.2531240121 Dec 24 01:41:52 PM PST 23 Dec 24 01:41:57 PM PST 23 17528351 ps
T911 /workspace/coverage/cover_reg_top/3.gpio_intr_test.1856042887 Dec 24 01:42:40 PM PST 23 Dec 24 01:42:53 PM PST 23 33493761 ps
T912 /workspace/coverage/cover_reg_top/6.gpio_tl_errors.2309683273 Dec 24 01:42:16 PM PST 23 Dec 24 01:42:21 PM PST 23 1116085231 ps
T913 /workspace/coverage/cover_reg_top/45.gpio_intr_test.276087019 Dec 24 01:41:54 PM PST 23 Dec 24 01:42:01 PM PST 23 18138004 ps
T914 /workspace/coverage/cover_reg_top/4.gpio_csr_bit_bash.4169448835 Dec 24 01:41:35 PM PST 23 Dec 24 01:41:40 PM PST 23 1495214876 ps
T915 /workspace/coverage/cover_reg_top/39.gpio_intr_test.17380874 Dec 24 01:41:47 PM PST 23 Dec 24 01:41:49 PM PST 23 53482176 ps
T916 /workspace/coverage/cover_reg_top/0.gpio_intr_test.2581161857 Dec 24 01:41:34 PM PST 23 Dec 24 01:41:36 PM PST 23 15632994 ps
T917 /workspace/coverage/cover_reg_top/8.gpio_csr_mem_rw_with_rand_reset.669727322 Dec 24 01:42:41 PM PST 23 Dec 24 01:42:53 PM PST 23 85143979 ps
T918 /workspace/coverage/cover_reg_top/18.gpio_intr_test.2282925140 Dec 24 01:41:52 PM PST 23 Dec 24 01:41:56 PM PST 23 25953942 ps
T85 /workspace/coverage/cover_reg_top/17.gpio_csr_rw.199516682 Dec 24 01:42:44 PM PST 23 Dec 24 01:43:04 PM PST 23 17186068 ps
T33 /workspace/coverage/cover_reg_top/8.gpio_tl_intg_err.3078333471 Dec 24 01:42:41 PM PST 23 Dec 24 01:42:53 PM PST 23 451944395 ps
T919 /workspace/coverage/cover_reg_top/25.gpio_intr_test.2762330839 Dec 24 01:41:53 PM PST 23 Dec 24 01:41:59 PM PST 23 13486810 ps
T920 /workspace/coverage/cover_reg_top/12.gpio_same_csr_outstanding.2753165863 Dec 24 01:42:51 PM PST 23 Dec 24 01:43:14 PM PST 23 213672429 ps
T921 /workspace/coverage/cover_reg_top/17.gpio_csr_mem_rw_with_rand_reset.3164930946 Dec 24 01:42:43 PM PST 23 Dec 24 01:43:01 PM PST 23 29802861 ps
T922 /workspace/coverage/cover_reg_top/6.gpio_intr_test.3702145594 Dec 24 01:42:38 PM PST 23 Dec 24 01:42:53 PM PST 23 98381482 ps
T97 /workspace/coverage/cover_reg_top/1.gpio_csr_rw.564391377 Dec 24 01:42:36 PM PST 23 Dec 24 01:42:43 PM PST 23 52068518 ps
T923 /workspace/coverage/cover_reg_top/1.gpio_intr_test.2914184743 Dec 24 01:41:56 PM PST 23 Dec 24 01:42:02 PM PST 23 58919503 ps
T924 /workspace/coverage/cover_reg_top/14.gpio_tl_errors.410759216 Dec 24 01:41:54 PM PST 23 Dec 24 01:42:02 PM PST 23 325466604 ps
T925 /workspace/coverage/cover_reg_top/8.gpio_tl_errors.1490418418 Dec 24 01:42:31 PM PST 23 Dec 24 01:42:35 PM PST 23 125430507 ps
T926 /workspace/coverage/cover_reg_top/5.gpio_intr_test.2453694289 Dec 24 01:41:50 PM PST 23 Dec 24 01:41:52 PM PST 23 14003648 ps
T927 /workspace/coverage/cover_reg_top/14.gpio_same_csr_outstanding.3302238664 Dec 24 01:41:51 PM PST 23 Dec 24 01:41:54 PM PST 23 18222402 ps
T928 /workspace/coverage/cover_reg_top/4.gpio_csr_mem_rw_with_rand_reset.1360191002 Dec 24 01:42:49 PM PST 23 Dec 24 01:43:13 PM PST 23 28938131 ps
T929 /workspace/coverage/cover_reg_top/43.gpio_intr_test.3688390090 Dec 24 01:41:52 PM PST 23 Dec 24 01:41:57 PM PST 23 19498604 ps
T98 /workspace/coverage/cover_reg_top/1.gpio_csr_bit_bash.1213647981 Dec 24 01:42:02 PM PST 23 Dec 24 01:42:08 PM PST 23 67821754 ps
T930 /workspace/coverage/cover_reg_top/15.gpio_tl_errors.3910700476 Dec 24 01:41:58 PM PST 23 Dec 24 01:42:05 PM PST 23 145942953 ps
T36 /workspace/coverage/cover_reg_top/0.gpio_tl_intg_err.1310119138 Dec 24 01:41:54 PM PST 23 Dec 24 01:42:02 PM PST 23 501351759 ps
T931 /workspace/coverage/cover_reg_top/19.gpio_csr_mem_rw_with_rand_reset.1151473682 Dec 24 01:41:50 PM PST 23 Dec 24 01:41:52 PM PST 23 23881203 ps
T932 /workspace/coverage/cover_reg_top/14.gpio_csr_mem_rw_with_rand_reset.1055519470 Dec 24 01:42:18 PM PST 23 Dec 24 01:42:21 PM PST 23 25106130 ps
T933 /workspace/coverage/cover_reg_top/4.gpio_tl_intg_err.1094334730 Dec 24 01:42:48 PM PST 23 Dec 24 01:43:10 PM PST 23 280383154 ps
T934 /workspace/coverage/cover_reg_top/7.gpio_intr_test.2964190946 Dec 24 01:41:58 PM PST 23 Dec 24 01:42:05 PM PST 23 18288287 ps
T935 /workspace/coverage/cover_reg_top/2.gpio_tl_errors.3861962238 Dec 24 01:42:43 PM PST 23 Dec 24 01:43:02 PM PST 23 425403476 ps
T936 /workspace/coverage/cover_reg_top/34.gpio_intr_test.4266760379 Dec 24 01:41:50 PM PST 23 Dec 24 01:41:52 PM PST 23 30471165 ps
T937 /workspace/coverage/cover_reg_top/18.gpio_csr_rw.3193041085 Dec 24 01:42:13 PM PST 23 Dec 24 01:42:15 PM PST 23 38724222 ps
T938 /workspace/coverage/cover_reg_top/7.gpio_tl_intg_err.2307187912 Dec 24 01:41:57 PM PST 23 Dec 24 01:42:04 PM PST 23 181142085 ps
T939 /workspace/coverage/cover_reg_top/29.gpio_intr_test.3879797839 Dec 24 01:41:52 PM PST 23 Dec 24 01:41:57 PM PST 23 34365778 ps
T940 /workspace/coverage/cover_reg_top/12.gpio_tl_intg_err.2055814289 Dec 24 01:41:54 PM PST 23 Dec 24 01:42:00 PM PST 23 167872276 ps
T941 /workspace/coverage/cover_reg_top/33.gpio_intr_test.212760613 Dec 24 01:41:55 PM PST 23 Dec 24 01:42:01 PM PST 23 22290002 ps
T942 /workspace/coverage/cover_reg_top/2.gpio_tl_intg_err.258142196 Dec 24 01:42:44 PM PST 23 Dec 24 01:43:04 PM PST 23 1298382280 ps
T38 /workspace/coverage/cover_reg_top/13.gpio_tl_intg_err.2901138131 Dec 24 01:41:50 PM PST 23 Dec 24 01:41:52 PM PST 23 358886589 ps
T943 /workspace/coverage/cover_reg_top/0.gpio_csr_mem_rw_with_rand_reset.2930819868 Dec 24 01:41:58 PM PST 23 Dec 24 01:42:05 PM PST 23 72085370 ps
T944 /workspace/coverage/cover_reg_top/10.gpio_same_csr_outstanding.3056887252 Dec 24 01:42:41 PM PST 23 Dec 24 01:42:53 PM PST 23 119672477 ps
T945 /workspace/coverage/cover_reg_top/38.gpio_intr_test.4212706767 Dec 24 01:41:51 PM PST 23 Dec 24 01:41:54 PM PST 23 12466457 ps
T946 /workspace/coverage/cover_reg_top/14.gpio_tl_intg_err.1939214048 Dec 24 01:41:55 PM PST 23 Dec 24 01:42:02 PM PST 23 84962243 ps
T947 /workspace/coverage/cover_reg_top/7.gpio_tl_errors.2920611494 Dec 24 01:42:42 PM PST 23 Dec 24 01:42:54 PM PST 23 436337062 ps
T948 /workspace/coverage/cover_reg_top/0.gpio_csr_hw_reset.4183849455 Dec 24 01:42:35 PM PST 23 Dec 24 01:42:39 PM PST 23 199093748 ps
T949 /workspace/coverage/cover_reg_top/8.gpio_intr_test.2785496381 Dec 24 01:42:44 PM PST 23 Dec 24 01:43:05 PM PST 23 15159524 ps
T950 /workspace/coverage/cover_reg_top/2.gpio_csr_rw.168523961 Dec 24 01:42:39 PM PST 23 Dec 24 01:42:53 PM PST 23 64261912 ps
T951 /workspace/coverage/cover_reg_top/0.gpio_tl_errors.115818939 Dec 24 01:41:54 PM PST 23 Dec 24 01:42:03 PM PST 23 416412636 ps
T952 /workspace/coverage/cover_reg_top/22.gpio_intr_test.934112271 Dec 24 01:41:53 PM PST 23 Dec 24 01:41:59 PM PST 23 20480516 ps
T953 /workspace/coverage/cover_reg_top/8.gpio_same_csr_outstanding.1988083691 Dec 24 01:42:02 PM PST 23 Dec 24 01:42:07 PM PST 23 65555551 ps
T954 /workspace/coverage/cover_reg_top/42.gpio_intr_test.3929912488 Dec 24 01:41:48 PM PST 23 Dec 24 01:41:50 PM PST 23 11685082 ps
T955 /workspace/coverage/cover_reg_top/19.gpio_intr_test.3413966138 Dec 24 01:41:54 PM PST 23 Dec 24 01:42:00 PM PST 23 32345541 ps
T34 /workspace/coverage/cover_reg_top/1.gpio_tl_intg_err.3672029505 Dec 24 01:41:58 PM PST 23 Dec 24 01:42:06 PM PST 23 164930803 ps
T956 /workspace/coverage/cover_reg_top/46.gpio_intr_test.1233269825 Dec 24 01:41:57 PM PST 23 Dec 24 01:42:03 PM PST 23 25285182 ps
T957 /workspace/coverage/cover_reg_top/26.gpio_intr_test.1929061257 Dec 24 01:41:51 PM PST 23 Dec 24 01:41:54 PM PST 23 24905357 ps
T105 /workspace/coverage/cover_reg_top/3.gpio_tl_intg_err.2453797750 Dec 24 01:42:47 PM PST 23 Dec 24 01:43:07 PM PST 23 443834804 ps
T958 /workspace/coverage/cover_reg_top/20.gpio_intr_test.2847975687 Dec 24 01:41:53 PM PST 23 Dec 24 01:41:59 PM PST 23 43485935 ps
T959 /workspace/coverage/cover_reg_top/3.gpio_tl_errors.3338348562 Dec 24 01:42:38 PM PST 23 Dec 24 01:42:54 PM PST 23 54142453 ps
T960 /workspace/coverage/cover_reg_top/41.gpio_intr_test.2958460775 Dec 24 01:41:55 PM PST 23 Dec 24 01:42:02 PM PST 23 43391216 ps
T961 /workspace/coverage/cover_reg_top/10.gpio_intr_test.1308374405 Dec 24 01:42:40 PM PST 23 Dec 24 01:42:53 PM PST 23 35923394 ps
T962 /workspace/coverage/cover_reg_top/21.gpio_intr_test.1006553168 Dec 24 01:42:35 PM PST 23 Dec 24 01:42:39 PM PST 23 35051140 ps
T963 /workspace/coverage/cover_reg_top/30.gpio_intr_test.2649586647 Dec 24 01:42:17 PM PST 23 Dec 24 01:42:20 PM PST 23 12721498 ps
T964 /workspace/coverage/cover_reg_top/11.gpio_tl_intg_err.2060534797 Dec 24 01:42:43 PM PST 23 Dec 24 01:43:00 PM PST 23 178902180 ps
T965 /workspace/coverage/cover_reg_top/7.gpio_csr_rw.2615892820 Dec 24 01:41:52 PM PST 23 Dec 24 01:41:56 PM PST 23 35002575 ps
T966 /workspace/coverage/cover_reg_top/24.gpio_intr_test.722905617 Dec 24 01:41:55 PM PST 23 Dec 24 01:42:02 PM PST 23 39809246 ps
T967 /workspace/coverage/cover_reg_top/16.gpio_same_csr_outstanding.2090469673 Dec 24 01:42:41 PM PST 23 Dec 24 01:42:53 PM PST 23 26445867 ps
T968 /workspace/coverage/cover_reg_top/0.gpio_csr_bit_bash.1574148814 Dec 24 01:41:53 PM PST 23 Dec 24 01:42:00 PM PST 23 351782645 ps
T969 /workspace/coverage/cover_reg_top/3.gpio_csr_rw.3718985963 Dec 24 01:42:37 PM PST 23 Dec 24 01:42:43 PM PST 23 16824803 ps
T970 /workspace/coverage/cover_reg_top/12.gpio_csr_mem_rw_with_rand_reset.309769320 Dec 24 01:42:47 PM PST 23 Dec 24 01:43:06 PM PST 23 31384966 ps

Test location /workspace/coverage/cover_reg_top/16.gpio_tl_intg_err.2010634801
Short name T11
Test name
Test status
Simulation time 157847708 ps
CPU time 1.15 seconds
Started Dec 24 01:41:57 PM PST 23
Finished Dec 24 01:42:04 PM PST 23
Peak memory 198300 kb
Host smart-0f8049b5-d384-4dd4-9dca-53f338f1c765
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2010634801 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 16.gpio_tl_intg_err.2010634801
Directory /workspace/16.gpio_tl_intg_err/latest

Test location /workspace/coverage/en_cdc_prims/31.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1967892860
Short name T56
Test name
Test status
Simulation time 103975930 ps
CPU time 1.44 seconds
Started Dec 24 12:34:10 PM PST 23
Finished Dec 24 12:34:48 PM PST 23
Peak memory 196404 kb
Host smart-f7e075eb-bee6-4c63-a017-16bb1b280ea4
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1967892860 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 31.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.1967892860
Directory /workspace/31.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/default/26.gpio_full_random.2645623222
Short name T42
Test name
Test status
Simulation time 237907845 ps
CPU time 0.97 seconds
Started Dec 24 01:10:34 PM PST 23
Finished Dec 24 01:10:39 PM PST 23
Peak memory 197796 kb
Host smart-8b4c455c-ce54-4344-9060-2197a990744c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2645623222 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_full_random.2645623222
Directory /workspace/26.gpio_full_random/latest

Test location /workspace/coverage/default/12.gpio_intr_with_filter_rand_intr_event.295763143
Short name T344
Test name
Test status
Simulation time 310102237 ps
CPU time 3.34 seconds
Started Dec 24 01:10:28 PM PST 23
Finished Dec 24 01:10:34 PM PST 23
Peak memory 198252 kb
Host smart-6fc1774e-5100-4a1f-9fba-09fe4d83f5f7
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=295763143 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 12.gpio_intr_with_filter_rand_intr_event.295763143
Directory /workspace/12.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/cover_reg_top/11.gpio_tl_errors.4188160116
Short name T27
Test name
Test status
Simulation time 23876067 ps
CPU time 1.23 seconds
Started Dec 24 01:42:49 PM PST 23
Finished Dec 24 01:43:14 PM PST 23
Peak memory 198392 kb
Host smart-d25dd39d-12f5-49f2-a0e2-eabb48e4e025
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4188160116 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.gpio_tl_errors.4188160116
Directory /workspace/11.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.gpio_csr_rw.4239255295
Short name T5
Test name
Test status
Simulation time 73993849 ps
CPU time 0.61 seconds
Started Dec 24 01:42:15 PM PST 23
Finished Dec 24 01:42:16 PM PST 23
Peak memory 195240 kb
Host smart-f2eb6a11-c099-4321-a7c1-a1cb8925ae7e
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4239255295 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.gpi
o_csr_rw.4239255295
Directory /workspace/14.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.gpio_csr_mem_rw_with_rand_reset.1530212536
Short name T14
Test name
Test status
Simulation time 26867275 ps
CPU time 1.23 seconds
Started Dec 24 01:42:40 PM PST 23
Finished Dec 24 01:42:53 PM PST 23
Peak memory 198480 kb
Host smart-66635c4a-7951-42db-b425-7bfee46555fc
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1530212536 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.gpio_csr_mem_rw_with_rand_reset.1530212536
Directory /workspace/16.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.gpio_intr_test.2973118945
Short name T103
Test name
Test status
Simulation time 12920959 ps
CPU time 0.67 seconds
Started Dec 24 01:42:19 PM PST 23
Finished Dec 24 01:42:22 PM PST 23
Peak memory 194088 kb
Host smart-71337054-8549-419a-9fc1-e8ac45ccb34c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2973118945 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.gpio_intr_test.2973118945
Directory /workspace/2.gpio_intr_test/latest

Test location /workspace/coverage/default/46.gpio_stress_all.489692934
Short name T48
Test name
Test status
Simulation time 41682578008 ps
CPU time 115.41 seconds
Started Dec 24 01:11:47 PM PST 23
Finished Dec 24 01:13:52 PM PST 23
Peak memory 198096 kb
Host smart-9ed43483-d225-4316-ad6c-4d0b2fc383ff
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=489692934 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.g
pio_stress_all.489692934
Directory /workspace/46.gpio_stress_all/latest

Test location /workspace/coverage/default/1.gpio_sec_cm.3795768876
Short name T24
Test name
Test status
Simulation time 178340916 ps
CPU time 0.91 seconds
Started Dec 24 01:10:09 PM PST 23
Finished Dec 24 01:10:21 PM PST 23
Peak memory 213564 kb
Host smart-1c3d4789-aec7-4aee-8493-65eb3da5c780
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3795768876 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_sec_cm.3795768876
Directory /workspace/1.gpio_sec_cm/latest

Test location /workspace/coverage/cover_reg_top/15.gpio_tl_intg_err.1536367957
Short name T29
Test name
Test status
Simulation time 135037501 ps
CPU time 1.14 seconds
Started Dec 24 01:41:55 PM PST 23
Finished Dec 24 01:42:02 PM PST 23
Peak memory 198376 kb
Host smart-8315ce9c-44ca-4b17-b3d0-1e436db6b090
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1536367957 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 15.gpio_tl_intg_err.1536367957
Directory /workspace/15.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.gpio_same_csr_outstanding.4245238943
Short name T2
Test name
Test status
Simulation time 159836354 ps
CPU time 0.94 seconds
Started Dec 24 01:41:52 PM PST 23
Finished Dec 24 01:41:57 PM PST 23
Peak memory 197560 kb
Host smart-8ca72318-b5ac-45a1-aa6a-88fe928ce03c
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4245238943 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 19.gpio_same_csr_outstanding.4245238943
Directory /workspace/19.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/en_cdc_prims/0.gpio_smoke_en_cdc_prim.3090454854
Short name T136
Test name
Test status
Simulation time 152268644 ps
CPU time 0.79 seconds
Started Dec 24 12:34:00 PM PST 23
Finished Dec 24 12:34:38 PM PST 23
Peak memory 195064 kb
Host smart-f029d16f-484d-478b-8dce-1fe9fd06ded1
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3090454854 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 0.gpio_smoke_en_cdc_prim.3090454854
Directory /workspace/0.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/default/11.gpio_alert_test.1780857134
Short name T46
Test name
Test status
Simulation time 14357415 ps
CPU time 0.56 seconds
Started Dec 24 01:10:44 PM PST 23
Finished Dec 24 01:10:54 PM PST 23
Peak memory 193968 kb
Host smart-32d9b870-9d99-42ec-a966-a9ff3c9ccefe
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1780857134 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_alert_test.1780857134
Directory /workspace/11.gpio_alert_test/latest

Test location /workspace/coverage/cover_reg_top/17.gpio_tl_intg_err.2869488327
Short name T9
Test name
Test status
Simulation time 548527529 ps
CPU time 1.54 seconds
Started Dec 24 01:41:51 PM PST 23
Finished Dec 24 01:41:55 PM PST 23
Peak memory 198216 kb
Host smart-3f5da3bd-ab94-4a85-992c-1bbfd4a57f62
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2869488327 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 17.gpio_tl_intg_err.2869488327
Directory /workspace/17.gpio_tl_intg_err/latest

Test location /workspace/coverage/default/12.gpio_stress_all_with_rand_reset.904972397
Short name T372
Test name
Test status
Simulation time 66624432098 ps
CPU time 1006.67 seconds
Started Dec 24 01:10:15 PM PST 23
Finished Dec 24 01:27:06 PM PST 23
Peak memory 198372 kb
Host smart-f50410e1-bc55-4b87-ac97-09cbd1dccc3d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=904972397 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_stress_all_with_rand_reset.904972397
Directory /workspace/12.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.gpio_intr_test.2802316042
Short name T116
Test name
Test status
Simulation time 18843604 ps
CPU time 0.63 seconds
Started Dec 24 01:42:38 PM PST 23
Finished Dec 24 01:42:47 PM PST 23
Peak memory 194052 kb
Host smart-dc950e39-9259-42a0-a7ff-8009c91a92af
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2802316042 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.gpio_intr_test.2802316042
Directory /workspace/14.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.gpio_csr_aliasing.2891438266
Short name T895
Test name
Test status
Simulation time 50099602 ps
CPU time 0.66 seconds
Started Dec 24 01:41:55 PM PST 23
Finished Dec 24 01:42:02 PM PST 23
Peak memory 194392 kb
Host smart-bc157b11-ebfb-43c0-9e34-919e7491898e
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2891438266 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM
_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name
0.gpio_csr_aliasing.2891438266
Directory /workspace/0.gpio_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.gpio_csr_bit_bash.1574148814
Short name T968
Test name
Test status
Simulation time 351782645 ps
CPU time 1.53 seconds
Started Dec 24 01:41:53 PM PST 23
Finished Dec 24 01:42:00 PM PST 23
Peak memory 198240 kb
Host smart-195ec3f8-3b62-4582-8419-c0b395ca5d9f
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1574148814 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.gpio_csr_bit_bash.1574148814
Directory /workspace/0.gpio_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.gpio_csr_hw_reset.4183849455
Short name T948
Test name
Test status
Simulation time 199093748 ps
CPU time 0.59 seconds
Started Dec 24 01:42:35 PM PST 23
Finished Dec 24 01:42:39 PM PST 23
Peak memory 194648 kb
Host smart-0e443fb2-26ee-4ccd-abdc-ee13e4fc55ba
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4183849455 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.gpio_csr_hw_reset.4183849455
Directory /workspace/0.gpio_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.gpio_csr_mem_rw_with_rand_reset.2930819868
Short name T943
Test name
Test status
Simulation time 72085370 ps
CPU time 0.8 seconds
Started Dec 24 01:41:58 PM PST 23
Finished Dec 24 01:42:05 PM PST 23
Peak memory 198204 kb
Host smart-17c5c08e-0fd0-430b-a2eb-7de01aafd5c5
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2930819868 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.gpio_csr_mem_rw_with_rand_reset.2930819868
Directory /workspace/0.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.gpio_csr_rw.266933068
Short name T95
Test name
Test status
Simulation time 13425959 ps
CPU time 0.58 seconds
Started Dec 24 01:41:53 PM PST 23
Finished Dec 24 01:41:57 PM PST 23
Peak memory 195228 kb
Host smart-a49e9a0f-b792-4660-9d13-7f940c010cf1
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=266933068 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_S
EQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.gpio_
csr_rw.266933068
Directory /workspace/0.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.gpio_intr_test.2581161857
Short name T916
Test name
Test status
Simulation time 15632994 ps
CPU time 0.58 seconds
Started Dec 24 01:41:34 PM PST 23
Finished Dec 24 01:41:36 PM PST 23
Peak memory 194816 kb
Host smart-2fe01e2b-4064-4836-91a8-e8d780f741b6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2581161857 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.gpio_intr_test.2581161857
Directory /workspace/0.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.gpio_same_csr_outstanding.1585853189
Short name T80
Test name
Test status
Simulation time 112113756 ps
CPU time 0.77 seconds
Started Dec 24 01:41:52 PM PST 23
Finished Dec 24 01:41:57 PM PST 23
Peak memory 197192 kb
Host smart-765a809a-b10f-40da-b342-0cd0d7f00a1b
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1585853189 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 0.gpio_same_csr_outstanding.1585853189
Directory /workspace/0.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.gpio_tl_errors.115818939
Short name T951
Test name
Test status
Simulation time 416412636 ps
CPU time 2.26 seconds
Started Dec 24 01:41:54 PM PST 23
Finished Dec 24 01:42:03 PM PST 23
Peak memory 198236 kb
Host smart-be785481-6b16-4402-b47c-784ffa6095b1
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=115818939 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.gpio_tl_errors.115818939
Directory /workspace/0.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.gpio_tl_intg_err.1310119138
Short name T36
Test name
Test status
Simulation time 501351759 ps
CPU time 1.38 seconds
Started Dec 24 01:41:54 PM PST 23
Finished Dec 24 01:42:02 PM PST 23
Peak memory 198396 kb
Host smart-7e29b24b-0218-4dc0-8106-51f69841d415
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1310119138 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 0.gpio_tl_intg_err.1310119138
Directory /workspace/0.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.gpio_csr_aliasing.3636857018
Short name T7
Test name
Test status
Simulation time 52879169 ps
CPU time 0.73 seconds
Started Dec 24 01:42:01 PM PST 23
Finished Dec 24 01:42:07 PM PST 23
Peak memory 195872 kb
Host smart-41cf1071-1943-463e-9cd1-773a742853d7
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3636857018 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM
_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name
1.gpio_csr_aliasing.3636857018
Directory /workspace/1.gpio_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.gpio_csr_bit_bash.1213647981
Short name T98
Test name
Test status
Simulation time 67821754 ps
CPU time 1.3 seconds
Started Dec 24 01:42:02 PM PST 23
Finished Dec 24 01:42:08 PM PST 23
Peak memory 196656 kb
Host smart-62c80408-2740-4753-a870-d8cbe20a3fc0
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1213647981 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.gpio_csr_bit_bash.1213647981
Directory /workspace/1.gpio_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.gpio_csr_hw_reset.2838939046
Short name T3
Test name
Test status
Simulation time 15204954 ps
CPU time 0.65 seconds
Started Dec 24 01:41:57 PM PST 23
Finished Dec 24 01:42:04 PM PST 23
Peak memory 194704 kb
Host smart-856e32a9-60d1-4226-9e6c-64b272e78fba
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2838939046 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.gpio_csr_hw_reset.2838939046
Directory /workspace/1.gpio_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.gpio_csr_mem_rw_with_rand_reset.125080376
Short name T8
Test name
Test status
Simulation time 25242602 ps
CPU time 0.87 seconds
Started Dec 24 01:42:39 PM PST 23
Finished Dec 24 01:42:53 PM PST 23
Peak memory 198224 kb
Host smart-f2c5acbf-60f8-4e90-ada3-44c8e4e6c4b1
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=125080376 -asser
t nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage
/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.gpio_csr_mem_rw_with_rand_reset.125080376
Directory /workspace/1.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.gpio_csr_rw.564391377
Short name T97
Test name
Test status
Simulation time 52068518 ps
CPU time 0.63 seconds
Started Dec 24 01:42:36 PM PST 23
Finished Dec 24 01:42:43 PM PST 23
Peak memory 195588 kb
Host smart-f1cf74d3-ded8-4040-90a5-e8ad1a6086b2
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=564391377 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_S
EQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.gpio_
csr_rw.564391377
Directory /workspace/1.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.gpio_intr_test.2914184743
Short name T923
Test name
Test status
Simulation time 58919503 ps
CPU time 0.61 seconds
Started Dec 24 01:41:56 PM PST 23
Finished Dec 24 01:42:02 PM PST 23
Peak memory 194740 kb
Host smart-4244553e-fae7-4d81-829d-d3fae454437d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2914184743 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.gpio_intr_test.2914184743
Directory /workspace/1.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.gpio_same_csr_outstanding.599560361
Short name T897
Test name
Test status
Simulation time 45940113 ps
CPU time 0.65 seconds
Started Dec 24 01:41:55 PM PST 23
Finished Dec 24 01:42:02 PM PST 23
Peak memory 195800 kb
Host smart-ad20ff48-e370-430a-9ddf-064210e61dd6
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=599560361 -assert nopostproc +UVM_TESTNAME=gpio_bas
e_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul
l -cm_name 1.gpio_same_csr_outstanding.599560361
Directory /workspace/1.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.gpio_tl_errors.1188468157
Short name T75
Test name
Test status
Simulation time 256301595 ps
CPU time 2.8 seconds
Started Dec 24 01:42:02 PM PST 23
Finished Dec 24 01:42:09 PM PST 23
Peak memory 198196 kb
Host smart-10143ff7-e6c3-46d8-a0bb-eb13ec8815ff
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1188468157 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.gpio_tl_errors.1188468157
Directory /workspace/1.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.gpio_tl_intg_err.3672029505
Short name T34
Test name
Test status
Simulation time 164930803 ps
CPU time 1.2 seconds
Started Dec 24 01:41:58 PM PST 23
Finished Dec 24 01:42:06 PM PST 23
Peak memory 198368 kb
Host smart-c3862162-d4f4-4dc1-a136-9bb7d14ca4ec
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3672029505 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 1.gpio_tl_intg_err.3672029505
Directory /workspace/1.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.gpio_csr_mem_rw_with_rand_reset.152135083
Short name T124
Test name
Test status
Simulation time 13933851 ps
CPU time 0.68 seconds
Started Dec 24 01:42:48 PM PST 23
Finished Dec 24 01:43:11 PM PST 23
Peak memory 197256 kb
Host smart-27f3043e-64a9-4fc5-8b7f-222859aac4ba
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=152135083 -asser
t nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage
/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.gpio_csr_mem_rw_with_rand_reset.152135083
Directory /workspace/10.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.gpio_csr_rw.2748024112
Short name T108
Test name
Test status
Simulation time 38752053 ps
CPU time 0.6 seconds
Started Dec 24 01:42:40 PM PST 23
Finished Dec 24 01:42:53 PM PST 23
Peak memory 194964 kb
Host smart-8aeb2350-0449-4249-a22a-c28cffb7a048
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2748024112 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.gpi
o_csr_rw.2748024112
Directory /workspace/10.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.gpio_intr_test.1308374405
Short name T961
Test name
Test status
Simulation time 35923394 ps
CPU time 0.59 seconds
Started Dec 24 01:42:40 PM PST 23
Finished Dec 24 01:42:53 PM PST 23
Peak memory 194688 kb
Host smart-11656827-66c0-47f6-9b66-8b1ca8e62bca
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1308374405 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.gpio_intr_test.1308374405
Directory /workspace/10.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.gpio_same_csr_outstanding.3056887252
Short name T944
Test name
Test status
Simulation time 119672477 ps
CPU time 0.76 seconds
Started Dec 24 01:42:41 PM PST 23
Finished Dec 24 01:42:53 PM PST 23
Peak memory 197024 kb
Host smart-fd627fd2-bf7b-4391-bad0-1e26112cd107
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3056887252 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 10.gpio_same_csr_outstanding.3056887252
Directory /workspace/10.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.gpio_tl_errors.2168655565
Short name T900
Test name
Test status
Simulation time 65689504 ps
CPU time 1.47 seconds
Started Dec 24 01:42:47 PM PST 23
Finished Dec 24 01:43:09 PM PST 23
Peak memory 198408 kb
Host smart-3891bef7-f4d7-4697-9829-681d121e361f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2168655565 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.gpio_tl_errors.2168655565
Directory /workspace/10.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.gpio_tl_intg_err.338106150
Short name T6
Test name
Test status
Simulation time 74731426 ps
CPU time 0.89 seconds
Started Dec 24 01:42:48 PM PST 23
Finished Dec 24 01:43:09 PM PST 23
Peak memory 198104 kb
Host smart-a87829dc-8c61-465b-9ae7-4086b3aa8bff
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=338106150 -assert nopostproc +UVM_TESTNAME=gpio_base_test +U
VM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam
e 10.gpio_tl_intg_err.338106150
Directory /workspace/10.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.gpio_csr_mem_rw_with_rand_reset.579711397
Short name T894
Test name
Test status
Simulation time 29323065 ps
CPU time 0.96 seconds
Started Dec 24 01:42:48 PM PST 23
Finished Dec 24 01:43:12 PM PST 23
Peak memory 198148 kb
Host smart-1c438d36-a0e4-46ed-b473-0cba0eeb3859
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=579711397 -asser
t nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage
/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.gpio_csr_mem_rw_with_rand_reset.579711397
Directory /workspace/11.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.gpio_csr_rw.3024981079
Short name T82
Test name
Test status
Simulation time 41043729 ps
CPU time 0.6 seconds
Started Dec 24 01:42:48 PM PST 23
Finished Dec 24 01:43:12 PM PST 23
Peak memory 195556 kb
Host smart-f6f60830-6c1d-4d61-b005-c136d64bc004
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3024981079 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.gpi
o_csr_rw.3024981079
Directory /workspace/11.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.gpio_intr_test.3805707456
Short name T905
Test name
Test status
Simulation time 32553989 ps
CPU time 0.58 seconds
Started Dec 24 01:42:52 PM PST 23
Finished Dec 24 01:43:15 PM PST 23
Peak memory 193936 kb
Host smart-7a981b55-d648-4347-886b-672ff8a73368
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3805707456 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.gpio_intr_test.3805707456
Directory /workspace/11.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.gpio_same_csr_outstanding.4167404791
Short name T100
Test name
Test status
Simulation time 15489691 ps
CPU time 0.72 seconds
Started Dec 24 01:42:47 PM PST 23
Finished Dec 24 01:43:06 PM PST 23
Peak memory 196320 kb
Host smart-217952be-b46e-4c51-a5aa-2977085d2a08
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4167404791 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 11.gpio_same_csr_outstanding.4167404791
Directory /workspace/11.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.gpio_tl_intg_err.2060534797
Short name T964
Test name
Test status
Simulation time 178902180 ps
CPU time 0.89 seconds
Started Dec 24 01:42:43 PM PST 23
Finished Dec 24 01:43:00 PM PST 23
Peak memory 197576 kb
Host smart-e7666989-6c4c-4235-b042-b46f01b71dc2
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2060534797 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 11.gpio_tl_intg_err.2060534797
Directory /workspace/11.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.gpio_csr_mem_rw_with_rand_reset.309769320
Short name T970
Test name
Test status
Simulation time 31384966 ps
CPU time 0.94 seconds
Started Dec 24 01:42:47 PM PST 23
Finished Dec 24 01:43:06 PM PST 23
Peak memory 198172 kb
Host smart-0fa8e4b0-49bd-47d3-8bc6-c8323c686413
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=309769320 -asser
t nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage
/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.gpio_csr_mem_rw_with_rand_reset.309769320
Directory /workspace/12.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.gpio_csr_rw.2020954184
Short name T86
Test name
Test status
Simulation time 166481461 ps
CPU time 0.6 seconds
Started Dec 24 01:42:48 PM PST 23
Finished Dec 24 01:43:09 PM PST 23
Peak memory 195760 kb
Host smart-62d14ec2-f9d9-43b5-b2e3-4ae3fd575fdd
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2020954184 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.gpi
o_csr_rw.2020954184
Directory /workspace/12.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.gpio_intr_test.1109594242
Short name T20
Test name
Test status
Simulation time 43002876 ps
CPU time 0.59 seconds
Started Dec 24 01:41:54 PM PST 23
Finished Dec 24 01:41:59 PM PST 23
Peak memory 194072 kb
Host smart-1bbdf821-41cc-4a2d-b98a-b2cf202b80dd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1109594242 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.gpio_intr_test.1109594242
Directory /workspace/12.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.gpio_same_csr_outstanding.2753165863
Short name T920
Test name
Test status
Simulation time 213672429 ps
CPU time 0.68 seconds
Started Dec 24 01:42:51 PM PST 23
Finished Dec 24 01:43:14 PM PST 23
Peak memory 194648 kb
Host smart-0ac2f217-7b45-4fdc-9ae0-e88565cb1996
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2753165863 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 12.gpio_same_csr_outstanding.2753165863
Directory /workspace/12.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.gpio_tl_errors.2074382334
Short name T30
Test name
Test status
Simulation time 37005551 ps
CPU time 2.06 seconds
Started Dec 24 01:42:47 PM PST 23
Finished Dec 24 01:43:09 PM PST 23
Peak memory 198416 kb
Host smart-96c4ba49-fccf-495c-98c3-eb329de83c31
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2074382334 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.gpio_tl_errors.2074382334
Directory /workspace/12.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.gpio_tl_intg_err.2055814289
Short name T940
Test name
Test status
Simulation time 167872276 ps
CPU time 0.9 seconds
Started Dec 24 01:41:54 PM PST 23
Finished Dec 24 01:42:00 PM PST 23
Peak memory 197164 kb
Host smart-10a9fd0c-b9bc-4f81-adab-0248a92a6e88
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2055814289 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 12.gpio_tl_intg_err.2055814289
Directory /workspace/12.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.gpio_csr_mem_rw_with_rand_reset.1435664943
Short name T72
Test name
Test status
Simulation time 360037722 ps
CPU time 1.33 seconds
Started Dec 24 01:41:52 PM PST 23
Finished Dec 24 01:41:57 PM PST 23
Peak memory 198468 kb
Host smart-a3c1704f-617f-44d4-b92f-8695bf7335ee
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1435664943 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.gpio_csr_mem_rw_with_rand_reset.1435664943
Directory /workspace/13.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.gpio_csr_rw.3978094873
Short name T891
Test name
Test status
Simulation time 37121296 ps
CPU time 0.63 seconds
Started Dec 24 01:41:51 PM PST 23
Finished Dec 24 01:41:53 PM PST 23
Peak memory 195092 kb
Host smart-d82dd80a-6764-4c76-bff0-325653402fc7
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3978094873 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.gpi
o_csr_rw.3978094873
Directory /workspace/13.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.gpio_intr_test.1668168483
Short name T889
Test name
Test status
Simulation time 12843065 ps
CPU time 0.6 seconds
Started Dec 24 01:41:53 PM PST 23
Finished Dec 24 01:41:59 PM PST 23
Peak memory 193976 kb
Host smart-66db3f7e-283a-4d69-9d30-cce3d8a69966
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1668168483 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.gpio_intr_test.1668168483
Directory /workspace/13.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.gpio_same_csr_outstanding.3744843609
Short name T107
Test name
Test status
Simulation time 18683699 ps
CPU time 0.71 seconds
Started Dec 24 01:41:51 PM PST 23
Finished Dec 24 01:41:55 PM PST 23
Peak memory 196440 kb
Host smart-e7c26c0d-c583-48cb-a6ee-308b0fcd6ce8
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3744843609 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 13.gpio_same_csr_outstanding.3744843609
Directory /workspace/13.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.gpio_tl_errors.3407945041
Short name T73
Test name
Test status
Simulation time 273163469 ps
CPU time 1.89 seconds
Started Dec 24 01:41:54 PM PST 23
Finished Dec 24 01:42:02 PM PST 23
Peak memory 198420 kb
Host smart-c513cb6c-33d2-42e0-b6c5-b25a9c0a885e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3407945041 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.gpio_tl_errors.3407945041
Directory /workspace/13.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.gpio_tl_intg_err.2901138131
Short name T38
Test name
Test status
Simulation time 358886589 ps
CPU time 1.41 seconds
Started Dec 24 01:41:50 PM PST 23
Finished Dec 24 01:41:52 PM PST 23
Peak memory 198384 kb
Host smart-502b82f4-81f9-4809-a818-8bc121308aad
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2901138131 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 13.gpio_tl_intg_err.2901138131
Directory /workspace/13.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.gpio_csr_mem_rw_with_rand_reset.1055519470
Short name T932
Test name
Test status
Simulation time 25106130 ps
CPU time 0.69 seconds
Started Dec 24 01:42:18 PM PST 23
Finished Dec 24 01:42:21 PM PST 23
Peak memory 197648 kb
Host smart-6b0d3b9f-4850-42b4-aacf-20c02d35e81b
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1055519470 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.gpio_csr_mem_rw_with_rand_reset.1055519470
Directory /workspace/14.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.gpio_same_csr_outstanding.3302238664
Short name T927
Test name
Test status
Simulation time 18222402 ps
CPU time 0.67 seconds
Started Dec 24 01:41:51 PM PST 23
Finished Dec 24 01:41:54 PM PST 23
Peak memory 195588 kb
Host smart-68f9cdda-e448-48ad-bc0b-d7f855425f81
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3302238664 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 14.gpio_same_csr_outstanding.3302238664
Directory /workspace/14.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.gpio_tl_errors.410759216
Short name T924
Test name
Test status
Simulation time 325466604 ps
CPU time 1.67 seconds
Started Dec 24 01:41:54 PM PST 23
Finished Dec 24 01:42:02 PM PST 23
Peak memory 198200 kb
Host smart-8b35f454-8dea-4419-bbfc-b6392a768241
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=410759216 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.gpio_tl_errors.410759216
Directory /workspace/14.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.gpio_tl_intg_err.1939214048
Short name T946
Test name
Test status
Simulation time 84962243 ps
CPU time 1.18 seconds
Started Dec 24 01:41:55 PM PST 23
Finished Dec 24 01:42:02 PM PST 23
Peak memory 198356 kb
Host smart-a6d7efb7-afa1-4427-8eb8-e57c0e101d9d
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1939214048 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 14.gpio_tl_intg_err.1939214048
Directory /workspace/14.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.gpio_csr_mem_rw_with_rand_reset.3430126701
Short name T92
Test name
Test status
Simulation time 75271543 ps
CPU time 0.92 seconds
Started Dec 24 01:42:37 PM PST 23
Finished Dec 24 01:42:44 PM PST 23
Peak memory 198240 kb
Host smart-fafdd928-659f-45ae-acc7-2e1eb07b18c0
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3430126701 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.gpio_csr_mem_rw_with_rand_reset.3430126701
Directory /workspace/15.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.gpio_csr_rw.1529807127
Short name T77
Test name
Test status
Simulation time 22251663 ps
CPU time 0.56 seconds
Started Dec 24 01:42:35 PM PST 23
Finished Dec 24 01:42:39 PM PST 23
Peak memory 194232 kb
Host smart-2bf53f90-4246-4ab9-90b3-6d2a01727347
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1529807127 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.gpi
o_csr_rw.1529807127
Directory /workspace/15.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.gpio_intr_test.3849045981
Short name T18
Test name
Test status
Simulation time 16240319 ps
CPU time 0.63 seconds
Started Dec 24 01:42:01 PM PST 23
Finished Dec 24 01:42:07 PM PST 23
Peak memory 194140 kb
Host smart-6ad9d680-05d7-4a5d-a8b1-192301d4c1fb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3849045981 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.gpio_intr_test.3849045981
Directory /workspace/15.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.gpio_same_csr_outstanding.2559170890
Short name T101
Test name
Test status
Simulation time 25730252 ps
CPU time 0.71 seconds
Started Dec 24 01:41:54 PM PST 23
Finished Dec 24 01:42:00 PM PST 23
Peak memory 196240 kb
Host smart-f7d2c57b-e6dd-4756-86a9-6ae60c27e88d
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2559170890 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 15.gpio_same_csr_outstanding.2559170890
Directory /workspace/15.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.gpio_tl_errors.3910700476
Short name T930
Test name
Test status
Simulation time 145942953 ps
CPU time 1.74 seconds
Started Dec 24 01:41:58 PM PST 23
Finished Dec 24 01:42:05 PM PST 23
Peak memory 198404 kb
Host smart-86a510e7-c311-4877-990d-5079d6f3d417
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3910700476 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.gpio_tl_errors.3910700476
Directory /workspace/15.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.gpio_csr_rw.2282989959
Short name T96
Test name
Test status
Simulation time 17983634 ps
CPU time 0.6 seconds
Started Dec 24 01:42:39 PM PST 23
Finished Dec 24 01:42:53 PM PST 23
Peak memory 194872 kb
Host smart-d24bf588-418b-4046-9d7d-46daa40cafa7
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2282989959 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.gpi
o_csr_rw.2282989959
Directory /workspace/16.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.gpio_intr_test.3379432236
Short name T22
Test name
Test status
Simulation time 14824885 ps
CPU time 0.6 seconds
Started Dec 24 01:42:43 PM PST 23
Finished Dec 24 01:43:00 PM PST 23
Peak memory 194620 kb
Host smart-b18070fe-694b-4c45-9a3d-1f9135fac520
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3379432236 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.gpio_intr_test.3379432236
Directory /workspace/16.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.gpio_same_csr_outstanding.2090469673
Short name T967
Test name
Test status
Simulation time 26445867 ps
CPU time 0.71 seconds
Started Dec 24 01:42:41 PM PST 23
Finished Dec 24 01:42:53 PM PST 23
Peak memory 196124 kb
Host smart-8461c33a-01a5-4806-a74c-e5d7092bfb4d
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2090469673 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 16.gpio_same_csr_outstanding.2090469673
Directory /workspace/16.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.gpio_tl_errors.973271980
Short name T893
Test name
Test status
Simulation time 63942799 ps
CPU time 1.65 seconds
Started Dec 24 01:41:53 PM PST 23
Finished Dec 24 01:42:00 PM PST 23
Peak memory 198432 kb
Host smart-52af5c95-9e5c-4534-8be0-1fd0c2eb32ee
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=973271980 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.gpio_tl_errors.973271980
Directory /workspace/16.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.gpio_csr_mem_rw_with_rand_reset.3164930946
Short name T921
Test name
Test status
Simulation time 29802861 ps
CPU time 0.69 seconds
Started Dec 24 01:42:43 PM PST 23
Finished Dec 24 01:43:01 PM PST 23
Peak memory 198036 kb
Host smart-c1e8f644-8802-4748-a4e0-b17593876034
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3164930946 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.gpio_csr_mem_rw_with_rand_reset.3164930946
Directory /workspace/17.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.gpio_csr_rw.199516682
Short name T85
Test name
Test status
Simulation time 17186068 ps
CPU time 0.63 seconds
Started Dec 24 01:42:44 PM PST 23
Finished Dec 24 01:43:04 PM PST 23
Peak memory 195132 kb
Host smart-3448b66a-e836-48d8-afaa-d9be7d6dc65d
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=199516682 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_S
EQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.gpio
_csr_rw.199516682
Directory /workspace/17.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.gpio_intr_test.131690913
Short name T899
Test name
Test status
Simulation time 111982312 ps
CPU time 0.66 seconds
Started Dec 24 01:41:55 PM PST 23
Finished Dec 24 01:42:02 PM PST 23
Peak memory 194076 kb
Host smart-e32c382c-c51c-4fcc-af77-737a0be55e62
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=131690913 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.gpio_intr_test.131690913
Directory /workspace/17.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.gpio_same_csr_outstanding.3481648858
Short name T901
Test name
Test status
Simulation time 46152376 ps
CPU time 0.74 seconds
Started Dec 24 01:42:40 PM PST 23
Finished Dec 24 01:42:53 PM PST 23
Peak memory 196212 kb
Host smart-f274f8ac-043d-499a-bc89-79307bd1d45b
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3481648858 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 17.gpio_same_csr_outstanding.3481648858
Directory /workspace/17.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.gpio_tl_errors.1719542990
Short name T13
Test name
Test status
Simulation time 538852373 ps
CPU time 2.82 seconds
Started Dec 24 01:42:43 PM PST 23
Finished Dec 24 01:43:02 PM PST 23
Peak memory 198416 kb
Host smart-12e5304e-68f3-423f-8508-98b0cefd9019
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1719542990 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.gpio_tl_errors.1719542990
Directory /workspace/17.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.gpio_csr_mem_rw_with_rand_reset.2531240121
Short name T910
Test name
Test status
Simulation time 17528351 ps
CPU time 0.96 seconds
Started Dec 24 01:41:52 PM PST 23
Finished Dec 24 01:41:57 PM PST 23
Peak memory 198020 kb
Host smart-e59250b3-4b2e-494d-ac7b-6443a99a521c
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2531240121 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.gpio_csr_mem_rw_with_rand_reset.2531240121
Directory /workspace/18.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.gpio_csr_rw.3193041085
Short name T937
Test name
Test status
Simulation time 38724222 ps
CPU time 0.6 seconds
Started Dec 24 01:42:13 PM PST 23
Finished Dec 24 01:42:15 PM PST 23
Peak memory 194948 kb
Host smart-4106ef04-d8a8-4caf-b6c7-b0b13ad94113
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3193041085 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.gpi
o_csr_rw.3193041085
Directory /workspace/18.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.gpio_intr_test.2282925140
Short name T918
Test name
Test status
Simulation time 25953942 ps
CPU time 0.62 seconds
Started Dec 24 01:41:52 PM PST 23
Finished Dec 24 01:41:56 PM PST 23
Peak memory 193232 kb
Host smart-b3d93c2a-aaa3-4616-b012-c250f44ac951
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2282925140 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.gpio_intr_test.2282925140
Directory /workspace/18.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.gpio_same_csr_outstanding.3733725688
Short name T89
Test name
Test status
Simulation time 42420261 ps
CPU time 0.7 seconds
Started Dec 24 01:41:57 PM PST 23
Finished Dec 24 01:42:04 PM PST 23
Peak memory 195224 kb
Host smart-a1ebec31-0acd-450a-b4a5-f87c399dcc6c
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3733725688 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 18.gpio_same_csr_outstanding.3733725688
Directory /workspace/18.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.gpio_tl_errors.3232576977
Short name T896
Test name
Test status
Simulation time 25150196 ps
CPU time 1.44 seconds
Started Dec 24 01:41:55 PM PST 23
Finished Dec 24 01:42:02 PM PST 23
Peak memory 198404 kb
Host smart-0514eeac-2cbe-4aeb-b1ed-58137f67233c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3232576977 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.gpio_tl_errors.3232576977
Directory /workspace/18.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.gpio_tl_intg_err.2945268579
Short name T109
Test name
Test status
Simulation time 52711785 ps
CPU time 0.89 seconds
Started Dec 24 01:41:51 PM PST 23
Finished Dec 24 01:41:55 PM PST 23
Peak memory 197556 kb
Host smart-03f584cd-5e07-4018-886d-a699c574ce50
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2945268579 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 18.gpio_tl_intg_err.2945268579
Directory /workspace/18.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.gpio_csr_mem_rw_with_rand_reset.1151473682
Short name T931
Test name
Test status
Simulation time 23881203 ps
CPU time 0.67 seconds
Started Dec 24 01:41:50 PM PST 23
Finished Dec 24 01:41:52 PM PST 23
Peak memory 197740 kb
Host smart-70429071-2688-45f1-b128-65ee89d9383b
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1151473682 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.gpio_csr_mem_rw_with_rand_reset.1151473682
Directory /workspace/19.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.gpio_csr_rw.2103434297
Short name T118
Test name
Test status
Simulation time 11812453 ps
CPU time 0.58 seconds
Started Dec 24 01:41:53 PM PST 23
Finished Dec 24 01:41:57 PM PST 23
Peak memory 194320 kb
Host smart-e66d2500-ad29-4b17-ac4a-ed1c963f897a
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2103434297 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.gpi
o_csr_rw.2103434297
Directory /workspace/19.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.gpio_intr_test.3413966138
Short name T955
Test name
Test status
Simulation time 32345541 ps
CPU time 0.59 seconds
Started Dec 24 01:41:54 PM PST 23
Finished Dec 24 01:42:00 PM PST 23
Peak memory 194036 kb
Host smart-bbae0fcb-c5a9-41d6-ab00-deb0a0c286b0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3413966138 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.gpio_intr_test.3413966138
Directory /workspace/19.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.gpio_tl_errors.1112458097
Short name T890
Test name
Test status
Simulation time 99431560 ps
CPU time 2.92 seconds
Started Dec 24 01:41:57 PM PST 23
Finished Dec 24 01:42:05 PM PST 23
Peak memory 198456 kb
Host smart-3226c53c-f8ca-4a91-990d-0a1bc7c2a9a4
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1112458097 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.gpio_tl_errors.1112458097
Directory /workspace/19.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.gpio_tl_intg_err.3501539341
Short name T23
Test name
Test status
Simulation time 691531361 ps
CPU time 1.63 seconds
Started Dec 24 01:41:54 PM PST 23
Finished Dec 24 01:42:00 PM PST 23
Peak memory 197924 kb
Host smart-d82c861a-a533-4897-890d-bf1520c30202
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3501539341 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 19.gpio_tl_intg_err.3501539341
Directory /workspace/19.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.gpio_csr_aliasing.1058617215
Short name T76
Test name
Test status
Simulation time 61643688 ps
CPU time 0.69 seconds
Started Dec 24 01:42:43 PM PST 23
Finished Dec 24 01:42:59 PM PST 23
Peak memory 195320 kb
Host smart-56f2ef61-95b3-4260-8e75-7d19450eaebe
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1058617215 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM
_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name
2.gpio_csr_aliasing.1058617215
Directory /workspace/2.gpio_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.gpio_csr_bit_bash.4029984844
Short name T122
Test name
Test status
Simulation time 36392361 ps
CPU time 1.37 seconds
Started Dec 24 01:42:30 PM PST 23
Finished Dec 24 01:42:33 PM PST 23
Peak memory 197236 kb
Host smart-7595d321-619f-47ab-beff-268fcfee8f5c
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4029984844 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.gpio_csr_bit_bash.4029984844
Directory /workspace/2.gpio_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.gpio_csr_hw_reset.355646184
Short name T31
Test name
Test status
Simulation time 17493457 ps
CPU time 0.67 seconds
Started Dec 24 01:42:29 PM PST 23
Finished Dec 24 01:42:31 PM PST 23
Peak memory 195736 kb
Host smart-33d6d50a-4452-44d1-b6e3-c23cfd2003e2
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=355646184 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.gpio_csr_hw_reset.355646184
Directory /workspace/2.gpio_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.gpio_csr_mem_rw_with_rand_reset.806327228
Short name T125
Test name
Test status
Simulation time 26978357 ps
CPU time 0.63 seconds
Started Dec 24 01:41:53 PM PST 23
Finished Dec 24 01:41:58 PM PST 23
Peak memory 197692 kb
Host smart-8938e9e5-a44f-49fe-be7a-271d3ef4f005
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=806327228 -asser
t nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage
/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.gpio_csr_mem_rw_with_rand_reset.806327228
Directory /workspace/2.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.gpio_csr_rw.168523961
Short name T950
Test name
Test status
Simulation time 64261912 ps
CPU time 0.61 seconds
Started Dec 24 01:42:39 PM PST 23
Finished Dec 24 01:42:53 PM PST 23
Peak memory 195004 kb
Host smart-592388e2-a624-4528-a22c-3ccbde2d1537
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=168523961 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_S
EQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.gpio_
csr_rw.168523961
Directory /workspace/2.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.gpio_same_csr_outstanding.2170352791
Short name T88
Test name
Test status
Simulation time 13972276 ps
CPU time 0.61 seconds
Started Dec 24 01:42:38 PM PST 23
Finished Dec 24 01:42:53 PM PST 23
Peak memory 195032 kb
Host smart-dbe1bbfe-611c-4f20-9e5e-3534f52c2e73
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2170352791 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 2.gpio_same_csr_outstanding.2170352791
Directory /workspace/2.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.gpio_tl_errors.3861962238
Short name T935
Test name
Test status
Simulation time 425403476 ps
CPU time 2.41 seconds
Started Dec 24 01:42:43 PM PST 23
Finished Dec 24 01:43:02 PM PST 23
Peak memory 198316 kb
Host smart-eccdb4ed-e7f3-40f9-bd4f-481fa474c7f8
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3861962238 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.gpio_tl_errors.3861962238
Directory /workspace/2.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.gpio_tl_intg_err.258142196
Short name T942
Test name
Test status
Simulation time 1298382280 ps
CPU time 0.93 seconds
Started Dec 24 01:42:44 PM PST 23
Finished Dec 24 01:43:04 PM PST 23
Peak memory 197564 kb
Host smart-e4b0c4eb-f0e3-435e-a8b8-ee8679e6e179
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=258142196 -assert nopostproc +UVM_TESTNAME=gpio_base_test +U
VM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam
e 2.gpio_tl_intg_err.258142196
Directory /workspace/2.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.gpio_intr_test.2847975687
Short name T958
Test name
Test status
Simulation time 43485935 ps
CPU time 0.57 seconds
Started Dec 24 01:41:53 PM PST 23
Finished Dec 24 01:41:59 PM PST 23
Peak memory 194028 kb
Host smart-6deca701-4da6-4000-9ae4-01e3f572d1b3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2847975687 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.gpio_intr_test.2847975687
Directory /workspace/20.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.gpio_intr_test.1006553168
Short name T962
Test name
Test status
Simulation time 35051140 ps
CPU time 0.58 seconds
Started Dec 24 01:42:35 PM PST 23
Finished Dec 24 01:42:39 PM PST 23
Peak memory 193888 kb
Host smart-8bb86ceb-9e17-40e8-833d-2ea0e58ff027
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1006553168 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.gpio_intr_test.1006553168
Directory /workspace/21.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.gpio_intr_test.934112271
Short name T952
Test name
Test status
Simulation time 20480516 ps
CPU time 0.61 seconds
Started Dec 24 01:41:53 PM PST 23
Finished Dec 24 01:41:59 PM PST 23
Peak memory 194140 kb
Host smart-393f8c93-5cb5-47f8-8c59-7e76d4b4360f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=934112271 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.gpio_intr_test.934112271
Directory /workspace/22.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.gpio_intr_test.1422261720
Short name T91
Test name
Test status
Simulation time 18336597 ps
CPU time 0.61 seconds
Started Dec 24 01:41:54 PM PST 23
Finished Dec 24 01:41:59 PM PST 23
Peak memory 194076 kb
Host smart-e69999a0-5046-4906-b07f-8a537db20955
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1422261720 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.gpio_intr_test.1422261720
Directory /workspace/23.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.gpio_intr_test.722905617
Short name T966
Test name
Test status
Simulation time 39809246 ps
CPU time 0.58 seconds
Started Dec 24 01:41:55 PM PST 23
Finished Dec 24 01:42:02 PM PST 23
Peak memory 194008 kb
Host smart-d7199b96-e05f-44af-a88e-0aaa5f3d8974
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=722905617 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.gpio_intr_test.722905617
Directory /workspace/24.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.gpio_intr_test.2762330839
Short name T919
Test name
Test status
Simulation time 13486810 ps
CPU time 0.57 seconds
Started Dec 24 01:41:53 PM PST 23
Finished Dec 24 01:41:59 PM PST 23
Peak memory 194024 kb
Host smart-99f78b42-d685-443a-b872-fa94c5271300
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2762330839 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.gpio_intr_test.2762330839
Directory /workspace/25.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.gpio_intr_test.1929061257
Short name T957
Test name
Test status
Simulation time 24905357 ps
CPU time 0.6 seconds
Started Dec 24 01:41:51 PM PST 23
Finished Dec 24 01:41:54 PM PST 23
Peak memory 194640 kb
Host smart-1b0deba6-d9fd-4a93-806b-2170c681344f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1929061257 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.gpio_intr_test.1929061257
Directory /workspace/26.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.gpio_intr_test.4123126502
Short name T117
Test name
Test status
Simulation time 75190215 ps
CPU time 0.62 seconds
Started Dec 24 01:41:52 PM PST 23
Finished Dec 24 01:41:56 PM PST 23
Peak memory 193192 kb
Host smart-32a138d5-7bca-4768-9666-705ab0ea6a1f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4123126502 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.gpio_intr_test.4123126502
Directory /workspace/27.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.gpio_intr_test.757081544
Short name T904
Test name
Test status
Simulation time 14699642 ps
CPU time 0.65 seconds
Started Dec 24 01:42:16 PM PST 23
Finished Dec 24 01:42:19 PM PST 23
Peak memory 194044 kb
Host smart-1ccde6d9-c0f1-4104-9306-234573854ce1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=757081544 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.gpio_intr_test.757081544
Directory /workspace/28.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.gpio_intr_test.3879797839
Short name T939
Test name
Test status
Simulation time 34365778 ps
CPU time 0.63 seconds
Started Dec 24 01:41:52 PM PST 23
Finished Dec 24 01:41:57 PM PST 23
Peak memory 194052 kb
Host smart-b8da67bd-55f2-4804-b522-f9db4d62fbb9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3879797839 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.gpio_intr_test.3879797839
Directory /workspace/29.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.gpio_csr_aliasing.2640458703
Short name T83
Test name
Test status
Simulation time 112630454 ps
CPU time 0.77 seconds
Started Dec 24 01:42:47 PM PST 23
Finished Dec 24 01:43:06 PM PST 23
Peak memory 196044 kb
Host smart-197404ce-46d8-46d1-bd3e-60f162729d86
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2640458703 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM
_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name
3.gpio_csr_aliasing.2640458703
Directory /workspace/3.gpio_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.gpio_csr_bit_bash.2303582622
Short name T903
Test name
Test status
Simulation time 537856030 ps
CPU time 1.53 seconds
Started Dec 24 01:42:48 PM PST 23
Finished Dec 24 01:43:12 PM PST 23
Peak memory 197252 kb
Host smart-08b4f62c-d1c4-48c5-b503-55b57b6b878d
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2303582622 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.gpio_csr_bit_bash.2303582622
Directory /workspace/3.gpio_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.gpio_csr_hw_reset.4064806428
Short name T892
Test name
Test status
Simulation time 39507386 ps
CPU time 0.59 seconds
Started Dec 24 01:42:39 PM PST 23
Finished Dec 24 01:42:53 PM PST 23
Peak memory 194920 kb
Host smart-6695e2fa-0522-4dd6-a19e-3fc898e9f8b8
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4064806428 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.gpio_csr_hw_reset.4064806428
Directory /workspace/3.gpio_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.gpio_csr_mem_rw_with_rand_reset.2474782911
Short name T123
Test name
Test status
Simulation time 19478698 ps
CPU time 0.71 seconds
Started Dec 24 01:42:45 PM PST 23
Finished Dec 24 01:43:05 PM PST 23
Peak memory 198116 kb
Host smart-f5eea971-c193-47b6-9c03-f72322d1a9a9
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2474782911 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.gpio_csr_mem_rw_with_rand_reset.2474782911
Directory /workspace/3.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.gpio_csr_rw.3718985963
Short name T969
Test name
Test status
Simulation time 16824803 ps
CPU time 0.63 seconds
Started Dec 24 01:42:37 PM PST 23
Finished Dec 24 01:42:43 PM PST 23
Peak memory 194728 kb
Host smart-5231615c-1272-4fa3-a3eb-8c6636ee529a
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3718985963 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.gpio
_csr_rw.3718985963
Directory /workspace/3.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.gpio_intr_test.1856042887
Short name T911
Test name
Test status
Simulation time 33493761 ps
CPU time 0.56 seconds
Started Dec 24 01:42:40 PM PST 23
Finished Dec 24 01:42:53 PM PST 23
Peak memory 193992 kb
Host smart-a8ade2c6-b426-4ee8-aa62-288adb263ede
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1856042887 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.gpio_intr_test.1856042887
Directory /workspace/3.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.gpio_same_csr_outstanding.2281196838
Short name T102
Test name
Test status
Simulation time 90867624 ps
CPU time 0.61 seconds
Started Dec 24 01:42:41 PM PST 23
Finished Dec 24 01:42:53 PM PST 23
Peak memory 195012 kb
Host smart-619145ab-8567-4f9d-90e8-8b54694081ac
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2281196838 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 3.gpio_same_csr_outstanding.2281196838
Directory /workspace/3.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.gpio_tl_errors.3338348562
Short name T959
Test name
Test status
Simulation time 54142453 ps
CPU time 2.45 seconds
Started Dec 24 01:42:38 PM PST 23
Finished Dec 24 01:42:54 PM PST 23
Peak memory 198396 kb
Host smart-876ca8de-ef9d-4c3c-805f-a721b2baa172
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3338348562 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.gpio_tl_errors.3338348562
Directory /workspace/3.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.gpio_tl_intg_err.2453797750
Short name T105
Test name
Test status
Simulation time 443834804 ps
CPU time 1.4 seconds
Started Dec 24 01:42:47 PM PST 23
Finished Dec 24 01:43:07 PM PST 23
Peak memory 198400 kb
Host smart-723ebd6d-1815-465a-aa13-f3466047fa6f
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2453797750 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 3.gpio_tl_intg_err.2453797750
Directory /workspace/3.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.gpio_intr_test.2649586647
Short name T963
Test name
Test status
Simulation time 12721498 ps
CPU time 0.59 seconds
Started Dec 24 01:42:17 PM PST 23
Finished Dec 24 01:42:20 PM PST 23
Peak memory 194504 kb
Host smart-c16625fb-9919-4be1-8475-d76abaad9761
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2649586647 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.gpio_intr_test.2649586647
Directory /workspace/30.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.gpio_intr_test.2433304448
Short name T121
Test name
Test status
Simulation time 34363778 ps
CPU time 0.57 seconds
Started Dec 24 01:41:51 PM PST 23
Finished Dec 24 01:41:54 PM PST 23
Peak memory 194688 kb
Host smart-6821be8b-83de-427b-9a3e-ed2e1278de0d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2433304448 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.gpio_intr_test.2433304448
Directory /workspace/31.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.gpio_intr_test.3830308888
Short name T909
Test name
Test status
Simulation time 18089481 ps
CPU time 0.62 seconds
Started Dec 24 01:41:53 PM PST 23
Finished Dec 24 01:41:59 PM PST 23
Peak memory 194072 kb
Host smart-cf113608-a42c-4400-9c40-a3e921a164c6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3830308888 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.gpio_intr_test.3830308888
Directory /workspace/32.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.gpio_intr_test.212760613
Short name T941
Test name
Test status
Simulation time 22290002 ps
CPU time 0.6 seconds
Started Dec 24 01:41:55 PM PST 23
Finished Dec 24 01:42:01 PM PST 23
Peak memory 194140 kb
Host smart-04ff3c2c-00d1-4697-9804-c1992bdbf0b7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=212760613 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.gpio_intr_test.212760613
Directory /workspace/33.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.gpio_intr_test.4266760379
Short name T936
Test name
Test status
Simulation time 30471165 ps
CPU time 0.6 seconds
Started Dec 24 01:41:50 PM PST 23
Finished Dec 24 01:41:52 PM PST 23
Peak memory 194064 kb
Host smart-3cdb3ccc-f063-4a76-8936-5cac604adaec
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4266760379 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.gpio_intr_test.4266760379
Directory /workspace/34.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.gpio_intr_test.3223088578
Short name T119
Test name
Test status
Simulation time 25810150 ps
CPU time 0.59 seconds
Started Dec 24 01:41:52 PM PST 23
Finished Dec 24 01:41:57 PM PST 23
Peak memory 194024 kb
Host smart-7bff55be-d9e1-4173-8540-06b77d95505c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3223088578 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.gpio_intr_test.3223088578
Directory /workspace/35.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.gpio_intr_test.398467423
Short name T90
Test name
Test status
Simulation time 133263186 ps
CPU time 0.6 seconds
Started Dec 24 01:41:50 PM PST 23
Finished Dec 24 01:41:52 PM PST 23
Peak memory 193980 kb
Host smart-4bd7d25b-0214-4582-a7ad-109b3bb731ef
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=398467423 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.gpio_intr_test.398467423
Directory /workspace/36.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.gpio_intr_test.3274159692
Short name T19
Test name
Test status
Simulation time 55056824 ps
CPU time 0.6 seconds
Started Dec 24 01:41:50 PM PST 23
Finished Dec 24 01:41:52 PM PST 23
Peak memory 194052 kb
Host smart-a5d8555a-563f-42e7-8843-37ffb5b0fd64
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3274159692 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.gpio_intr_test.3274159692
Directory /workspace/37.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.gpio_intr_test.4212706767
Short name T945
Test name
Test status
Simulation time 12466457 ps
CPU time 0.61 seconds
Started Dec 24 01:41:51 PM PST 23
Finished Dec 24 01:41:54 PM PST 23
Peak memory 194764 kb
Host smart-5cd51af3-03c4-469f-bb9b-847ffe031bed
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4212706767 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.gpio_intr_test.4212706767
Directory /workspace/38.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.gpio_intr_test.17380874
Short name T915
Test name
Test status
Simulation time 53482176 ps
CPU time 0.65 seconds
Started Dec 24 01:41:47 PM PST 23
Finished Dec 24 01:41:49 PM PST 23
Peak memory 194624 kb
Host smart-bd981681-1506-4faf-a284-778fbfc570f9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17380874 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.gpio_intr_test.17380874
Directory /workspace/39.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.gpio_csr_aliasing.3524216682
Short name T81
Test name
Test status
Simulation time 66717719 ps
CPU time 0.83 seconds
Started Dec 24 01:42:49 PM PST 23
Finished Dec 24 01:43:13 PM PST 23
Peak memory 196376 kb
Host smart-913e2ee1-e904-4814-8819-4bcc30616b67
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3524216682 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM
_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name
4.gpio_csr_aliasing.3524216682
Directory /workspace/4.gpio_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.gpio_csr_bit_bash.4169448835
Short name T914
Test name
Test status
Simulation time 1495214876 ps
CPU time 3.37 seconds
Started Dec 24 01:41:35 PM PST 23
Finished Dec 24 01:41:40 PM PST 23
Peak memory 197596 kb
Host smart-88dad3d5-ce21-4883-9e86-9407373a5a3e
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4169448835 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.gpio_csr_bit_bash.4169448835
Directory /workspace/4.gpio_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.gpio_csr_hw_reset.790968444
Short name T94
Test name
Test status
Simulation time 20415773 ps
CPU time 0.68 seconds
Started Dec 24 01:41:52 PM PST 23
Finished Dec 24 01:41:56 PM PST 23
Peak memory 195116 kb
Host smart-8204adde-58bd-4b91-bb52-f24c246eb749
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=790968444 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.gpio_csr_hw_reset.790968444
Directory /workspace/4.gpio_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.gpio_csr_mem_rw_with_rand_reset.1360191002
Short name T928
Test name
Test status
Simulation time 28938131 ps
CPU time 0.68 seconds
Started Dec 24 01:42:49 PM PST 23
Finished Dec 24 01:43:13 PM PST 23
Peak memory 197936 kb
Host smart-7258a120-2c5a-4f5b-8307-6df6557f8786
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1360191002 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.gpio_csr_mem_rw_with_rand_reset.1360191002
Directory /workspace/4.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.gpio_csr_rw.3106516517
Short name T15
Test name
Test status
Simulation time 31229480 ps
CPU time 0.57 seconds
Started Dec 24 01:42:41 PM PST 23
Finished Dec 24 01:42:53 PM PST 23
Peak memory 195028 kb
Host smart-403756cf-1ef9-4df5-892b-3f84405ea839
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3106516517 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.gpio
_csr_rw.3106516517
Directory /workspace/4.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.gpio_intr_test.3207227213
Short name T908
Test name
Test status
Simulation time 32052666 ps
CPU time 0.6 seconds
Started Dec 24 01:41:52 PM PST 23
Finished Dec 24 01:41:56 PM PST 23
Peak memory 194128 kb
Host smart-0972d838-c0d5-47dd-ac10-537d02bb0425
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3207227213 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.gpio_intr_test.3207227213
Directory /workspace/4.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.gpio_same_csr_outstanding.794833855
Short name T106
Test name
Test status
Simulation time 56053964 ps
CPU time 0.79 seconds
Started Dec 24 01:42:47 PM PST 23
Finished Dec 24 01:43:06 PM PST 23
Peak memory 197040 kb
Host smart-ae591af3-ba02-4204-9e9d-4e958b8b6f2b
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=794833855 -assert nopostproc +UVM_TESTNAME=gpio_bas
e_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul
l -cm_name 4.gpio_same_csr_outstanding.794833855
Directory /workspace/4.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.gpio_tl_errors.3590281541
Short name T74
Test name
Test status
Simulation time 556805522 ps
CPU time 2.28 seconds
Started Dec 24 01:41:53 PM PST 23
Finished Dec 24 01:42:01 PM PST 23
Peak memory 198368 kb
Host smart-6594cdaa-cccf-43e1-a438-869a2dfb2ad1
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3590281541 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.gpio_tl_errors.3590281541
Directory /workspace/4.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.gpio_tl_intg_err.1094334730
Short name T933
Test name
Test status
Simulation time 280383154 ps
CPU time 1.14 seconds
Started Dec 24 01:42:48 PM PST 23
Finished Dec 24 01:43:10 PM PST 23
Peak memory 197876 kb
Host smart-9d0dd649-bb73-4c6d-8456-0422c76f12b1
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1094334730 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 4.gpio_tl_intg_err.1094334730
Directory /workspace/4.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.gpio_intr_test.1545762849
Short name T16
Test name
Test status
Simulation time 86550659 ps
CPU time 0.62 seconds
Started Dec 24 01:42:37 PM PST 23
Finished Dec 24 01:42:43 PM PST 23
Peak memory 194660 kb
Host smart-b0730b46-665b-437d-b9b5-001c86810d2b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1545762849 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.gpio_intr_test.1545762849
Directory /workspace/40.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.gpio_intr_test.2958460775
Short name T960
Test name
Test status
Simulation time 43391216 ps
CPU time 0.62 seconds
Started Dec 24 01:41:55 PM PST 23
Finished Dec 24 01:42:02 PM PST 23
Peak memory 194004 kb
Host smart-f7d8afa5-e515-42df-ac7f-4b7210cee870
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2958460775 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.gpio_intr_test.2958460775
Directory /workspace/41.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.gpio_intr_test.3929912488
Short name T954
Test name
Test status
Simulation time 11685082 ps
CPU time 0.6 seconds
Started Dec 24 01:41:48 PM PST 23
Finished Dec 24 01:41:50 PM PST 23
Peak memory 194616 kb
Host smart-b670bb6d-4aa6-41ed-9cc1-16872b255831
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3929912488 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.gpio_intr_test.3929912488
Directory /workspace/42.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.gpio_intr_test.3688390090
Short name T929
Test name
Test status
Simulation time 19498604 ps
CPU time 0.62 seconds
Started Dec 24 01:41:52 PM PST 23
Finished Dec 24 01:41:57 PM PST 23
Peak memory 193992 kb
Host smart-d325638d-c0ac-4a49-a94c-59ff8b59e33e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3688390090 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.gpio_intr_test.3688390090
Directory /workspace/43.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.gpio_intr_test.1208865306
Short name T115
Test name
Test status
Simulation time 17059057 ps
CPU time 0.59 seconds
Started Dec 24 01:41:58 PM PST 23
Finished Dec 24 01:42:04 PM PST 23
Peak memory 194072 kb
Host smart-227ced41-f52a-477a-8367-dc2a90801aef
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1208865306 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.gpio_intr_test.1208865306
Directory /workspace/44.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.gpio_intr_test.276087019
Short name T913
Test name
Test status
Simulation time 18138004 ps
CPU time 0.64 seconds
Started Dec 24 01:41:54 PM PST 23
Finished Dec 24 01:42:01 PM PST 23
Peak memory 194724 kb
Host smart-34ea1e17-f5bf-4dcc-ba72-2bef3ff782f9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=276087019 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.gpio_intr_test.276087019
Directory /workspace/45.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.gpio_intr_test.1233269825
Short name T956
Test name
Test status
Simulation time 25285182 ps
CPU time 0.59 seconds
Started Dec 24 01:41:57 PM PST 23
Finished Dec 24 01:42:03 PM PST 23
Peak memory 193892 kb
Host smart-c5d36c4f-13b5-4524-be4d-9f84ae7cf8ee
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1233269825 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.gpio_intr_test.1233269825
Directory /workspace/46.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.gpio_intr_test.2394194309
Short name T114
Test name
Test status
Simulation time 17285818 ps
CPU time 0.6 seconds
Started Dec 24 01:41:54 PM PST 23
Finished Dec 24 01:41:59 PM PST 23
Peak memory 194140 kb
Host smart-e2fe04b8-e66c-4d1f-a952-da832ff00e89
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2394194309 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.gpio_intr_test.2394194309
Directory /workspace/47.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.gpio_intr_test.993125948
Short name T120
Test name
Test status
Simulation time 33686679 ps
CPU time 0.57 seconds
Started Dec 24 01:41:53 PM PST 23
Finished Dec 24 01:41:57 PM PST 23
Peak memory 194068 kb
Host smart-d39fb8d5-a308-4261-b3a1-2bc8adfda938
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=993125948 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.gpio_intr_test.993125948
Directory /workspace/48.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.gpio_intr_test.2243636168
Short name T907
Test name
Test status
Simulation time 16478856 ps
CPU time 0.63 seconds
Started Dec 24 01:41:55 PM PST 23
Finished Dec 24 01:42:02 PM PST 23
Peak memory 194204 kb
Host smart-7c5dccad-398b-4407-a75c-02f3008e26f8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2243636168 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.gpio_intr_test.2243636168
Directory /workspace/49.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.gpio_csr_mem_rw_with_rand_reset.1689060667
Short name T37
Test name
Test status
Simulation time 100088355 ps
CPU time 0.65 seconds
Started Dec 24 01:41:53 PM PST 23
Finished Dec 24 01:41:57 PM PST 23
Peak memory 196992 kb
Host smart-f0beda6d-ce77-424c-bf07-49d70bbf4f85
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1689060667 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.gpio_csr_mem_rw_with_rand_reset.1689060667
Directory /workspace/5.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.gpio_csr_rw.1529894614
Short name T17
Test name
Test status
Simulation time 29131436 ps
CPU time 0.57 seconds
Started Dec 24 01:41:52 PM PST 23
Finished Dec 24 01:41:55 PM PST 23
Peak memory 194852 kb
Host smart-b3ea5b7a-7333-4042-ad3c-6fc44071be03
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1529894614 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.gpio
_csr_rw.1529894614
Directory /workspace/5.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.gpio_intr_test.2453694289
Short name T926
Test name
Test status
Simulation time 14003648 ps
CPU time 0.61 seconds
Started Dec 24 01:41:50 PM PST 23
Finished Dec 24 01:41:52 PM PST 23
Peak memory 194080 kb
Host smart-c1e54e3d-bad8-4330-a49c-9e2571a422d2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2453694289 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.gpio_intr_test.2453694289
Directory /workspace/5.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.gpio_same_csr_outstanding.4207089793
Short name T78
Test name
Test status
Simulation time 128710642 ps
CPU time 0.66 seconds
Started Dec 24 01:42:16 PM PST 23
Finished Dec 24 01:42:18 PM PST 23
Peak memory 195116 kb
Host smart-2830d3a0-8cae-405c-a6d1-41d7e4040514
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4207089793 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 5.gpio_same_csr_outstanding.4207089793
Directory /workspace/5.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.gpio_tl_errors.247291532
Short name T906
Test name
Test status
Simulation time 183612596 ps
CPU time 2.62 seconds
Started Dec 24 01:42:37 PM PST 23
Finished Dec 24 01:42:45 PM PST 23
Peak memory 198244 kb
Host smart-ecf6e5f5-0294-496b-a5c7-9cb4b5fc0bed
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=247291532 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.gpio_tl_errors.247291532
Directory /workspace/5.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.gpio_tl_intg_err.456114980
Short name T902
Test name
Test status
Simulation time 184129024 ps
CPU time 0.87 seconds
Started Dec 24 01:42:36 PM PST 23
Finished Dec 24 01:42:43 PM PST 23
Peak memory 197592 kb
Host smart-a849d4e5-26a2-4ee4-afc1-8adec4007251
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=456114980 -assert nopostproc +UVM_TESTNAME=gpio_base_test +U
VM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam
e 5.gpio_tl_intg_err.456114980
Directory /workspace/5.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.gpio_csr_mem_rw_with_rand_reset.2449614469
Short name T888
Test name
Test status
Simulation time 26625509 ps
CPU time 0.88 seconds
Started Dec 24 01:42:19 PM PST 23
Finished Dec 24 01:42:22 PM PST 23
Peak memory 198108 kb
Host smart-ab70f212-356e-4e41-9ec6-025fc9f310b5
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2449614469 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.gpio_csr_mem_rw_with_rand_reset.2449614469
Directory /workspace/6.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.gpio_csr_rw.1251166810
Short name T84
Test name
Test status
Simulation time 28084924 ps
CPU time 0.67 seconds
Started Dec 24 01:41:52 PM PST 23
Finished Dec 24 01:41:56 PM PST 23
Peak memory 195108 kb
Host smart-5bc6aef3-f84f-41bf-bffa-b3c58c7984f1
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1251166810 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.gpio
_csr_rw.1251166810
Directory /workspace/6.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.gpio_intr_test.3702145594
Short name T922
Test name
Test status
Simulation time 98381482 ps
CPU time 0.61 seconds
Started Dec 24 01:42:38 PM PST 23
Finished Dec 24 01:42:53 PM PST 23
Peak memory 194136 kb
Host smart-007f427d-3ac4-4fe6-b1a1-c5a2dccb22dc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3702145594 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.gpio_intr_test.3702145594
Directory /workspace/6.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.gpio_same_csr_outstanding.2623591000
Short name T79
Test name
Test status
Simulation time 141560490 ps
CPU time 0.9 seconds
Started Dec 24 01:41:51 PM PST 23
Finished Dec 24 01:41:55 PM PST 23
Peak memory 196332 kb
Host smart-08d76f29-2273-44a8-8eb1-460573f83660
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2623591000 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 6.gpio_same_csr_outstanding.2623591000
Directory /workspace/6.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.gpio_tl_errors.2309683273
Short name T912
Test name
Test status
Simulation time 1116085231 ps
CPU time 2.58 seconds
Started Dec 24 01:42:16 PM PST 23
Finished Dec 24 01:42:21 PM PST 23
Peak memory 198364 kb
Host smart-590f5168-f988-42ae-973f-a6584139c75e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2309683273 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.gpio_tl_errors.2309683273
Directory /workspace/6.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.gpio_tl_intg_err.1608051529
Short name T35
Test name
Test status
Simulation time 71750561 ps
CPU time 1.19 seconds
Started Dec 24 01:41:55 PM PST 23
Finished Dec 24 01:42:02 PM PST 23
Peak memory 197964 kb
Host smart-3d1c725d-29fc-4b51-9170-fc5353f2c4e6
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1608051529 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 6.gpio_tl_intg_err.1608051529
Directory /workspace/6.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.gpio_csr_mem_rw_with_rand_reset.131361012
Short name T21
Test name
Test status
Simulation time 39051100 ps
CPU time 0.97 seconds
Started Dec 24 01:42:39 PM PST 23
Finished Dec 24 01:42:53 PM PST 23
Peak memory 198212 kb
Host smart-0b34d3d1-c622-4a6e-95e9-65a0273928b5
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=131361012 -asser
t nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage
/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.gpio_csr_mem_rw_with_rand_reset.131361012
Directory /workspace/7.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.gpio_csr_rw.2615892820
Short name T965
Test name
Test status
Simulation time 35002575 ps
CPU time 0.64 seconds
Started Dec 24 01:41:52 PM PST 23
Finished Dec 24 01:41:56 PM PST 23
Peak memory 194988 kb
Host smart-832bbc95-8dc7-475d-9c4b-300c1a918777
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2615892820 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.gpio
_csr_rw.2615892820
Directory /workspace/7.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.gpio_intr_test.2964190946
Short name T934
Test name
Test status
Simulation time 18288287 ps
CPU time 0.62 seconds
Started Dec 24 01:41:58 PM PST 23
Finished Dec 24 01:42:05 PM PST 23
Peak memory 194128 kb
Host smart-fb97f75a-4c95-4e22-a9d5-628d97494880
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2964190946 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.gpio_intr_test.2964190946
Directory /workspace/7.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.gpio_same_csr_outstanding.335068536
Short name T898
Test name
Test status
Simulation time 117027376 ps
CPU time 0.76 seconds
Started Dec 24 01:41:57 PM PST 23
Finished Dec 24 01:42:04 PM PST 23
Peak memory 196068 kb
Host smart-c69ace02-b49f-4f01-a145-1879dc383015
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=335068536 -assert nopostproc +UVM_TESTNAME=gpio_bas
e_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul
l -cm_name 7.gpio_same_csr_outstanding.335068536
Directory /workspace/7.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.gpio_tl_errors.2920611494
Short name T947
Test name
Test status
Simulation time 436337062 ps
CPU time 1.57 seconds
Started Dec 24 01:42:42 PM PST 23
Finished Dec 24 01:42:54 PM PST 23
Peak memory 198468 kb
Host smart-27f38dd7-42e8-49ed-b777-d88cc97cca4c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2920611494 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.gpio_tl_errors.2920611494
Directory /workspace/7.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.gpio_tl_intg_err.2307187912
Short name T938
Test name
Test status
Simulation time 181142085 ps
CPU time 0.92 seconds
Started Dec 24 01:41:57 PM PST 23
Finished Dec 24 01:42:04 PM PST 23
Peak memory 197352 kb
Host smart-2570e9e7-1587-41ab-91ae-67225f13d94f
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2307187912 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 7.gpio_tl_intg_err.2307187912
Directory /workspace/7.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.gpio_csr_mem_rw_with_rand_reset.669727322
Short name T917
Test name
Test status
Simulation time 85143979 ps
CPU time 0.77 seconds
Started Dec 24 01:42:41 PM PST 23
Finished Dec 24 01:42:53 PM PST 23
Peak memory 198220 kb
Host smart-f4bf9808-8a58-4f45-ab77-130f744dd363
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=669727322 -asser
t nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage
/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.gpio_csr_mem_rw_with_rand_reset.669727322
Directory /workspace/8.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.gpio_csr_rw.963750800
Short name T887
Test name
Test status
Simulation time 15178982 ps
CPU time 0.61 seconds
Started Dec 24 01:42:40 PM PST 23
Finished Dec 24 01:42:53 PM PST 23
Peak memory 195016 kb
Host smart-f6facaae-50b9-4b26-bda0-8e76b6e9e465
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=963750800 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_S
EQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.gpio_
csr_rw.963750800
Directory /workspace/8.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.gpio_intr_test.2785496381
Short name T949
Test name
Test status
Simulation time 15159524 ps
CPU time 0.58 seconds
Started Dec 24 01:42:44 PM PST 23
Finished Dec 24 01:43:05 PM PST 23
Peak memory 194016 kb
Host smart-f74a188a-9cd7-4828-9baf-9796e0288694
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2785496381 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.gpio_intr_test.2785496381
Directory /workspace/8.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.gpio_same_csr_outstanding.1988083691
Short name T953
Test name
Test status
Simulation time 65555551 ps
CPU time 0.84 seconds
Started Dec 24 01:42:02 PM PST 23
Finished Dec 24 01:42:07 PM PST 23
Peak memory 196396 kb
Host smart-db645a3c-2852-495e-b8f9-a7a74c3269d9
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1988083691 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 8.gpio_same_csr_outstanding.1988083691
Directory /workspace/8.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.gpio_tl_errors.1490418418
Short name T925
Test name
Test status
Simulation time 125430507 ps
CPU time 2.09 seconds
Started Dec 24 01:42:31 PM PST 23
Finished Dec 24 01:42:35 PM PST 23
Peak memory 198368 kb
Host smart-dc850dd8-f35b-4d96-a003-e1dc9e000db3
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1490418418 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.gpio_tl_errors.1490418418
Directory /workspace/8.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.gpio_tl_intg_err.3078333471
Short name T33
Test name
Test status
Simulation time 451944395 ps
CPU time 1.39 seconds
Started Dec 24 01:42:41 PM PST 23
Finished Dec 24 01:42:53 PM PST 23
Peak memory 198348 kb
Host smart-bf3cedc1-5f68-4898-8f0f-8e2304208948
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3078333471 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 8.gpio_tl_intg_err.3078333471
Directory /workspace/8.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.gpio_csr_mem_rw_with_rand_reset.2097344102
Short name T10
Test name
Test status
Simulation time 109944287 ps
CPU time 0.86 seconds
Started Dec 24 01:42:37 PM PST 23
Finished Dec 24 01:42:44 PM PST 23
Peak memory 198208 kb
Host smart-adfc6e05-acb2-4c27-8e3c-521fcadd8eb1
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2097344102 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.gpio_csr_mem_rw_with_rand_reset.2097344102
Directory /workspace/9.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.gpio_csr_rw.3430146197
Short name T4
Test name
Test status
Simulation time 19191179 ps
CPU time 0.56 seconds
Started Dec 24 01:42:32 PM PST 23
Finished Dec 24 01:42:34 PM PST 23
Peak memory 193572 kb
Host smart-4364fc03-5e25-41d7-8cd8-bb12ba7cf582
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3430146197 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.gpio
_csr_rw.3430146197
Directory /workspace/9.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.gpio_intr_test.3325834129
Short name T93
Test name
Test status
Simulation time 32818461 ps
CPU time 0.61 seconds
Started Dec 24 01:42:39 PM PST 23
Finished Dec 24 01:42:53 PM PST 23
Peak memory 193932 kb
Host smart-685c854e-418c-421b-9f57-5cc5c1c0e4ad
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3325834129 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.gpio_intr_test.3325834129
Directory /workspace/9.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.gpio_same_csr_outstanding.1521415099
Short name T1
Test name
Test status
Simulation time 159887244 ps
CPU time 0.86 seconds
Started Dec 24 01:42:40 PM PST 23
Finished Dec 24 01:42:53 PM PST 23
Peak memory 196704 kb
Host smart-f3c556b2-eb26-44fa-83cd-0641cb5dd042
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1521415099 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 9.gpio_same_csr_outstanding.1521415099
Directory /workspace/9.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.gpio_tl_errors.3909584256
Short name T28
Test name
Test status
Simulation time 108743458 ps
CPU time 1.5 seconds
Started Dec 24 01:42:45 PM PST 23
Finished Dec 24 01:43:06 PM PST 23
Peak memory 198432 kb
Host smart-be089569-0798-42fb-b7be-9907577abf6a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3909584256 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.gpio_tl_errors.3909584256
Directory /workspace/9.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.gpio_tl_intg_err.2957911212
Short name T12
Test name
Test status
Simulation time 46982738 ps
CPU time 0.94 seconds
Started Dec 24 01:42:46 PM PST 23
Finished Dec 24 01:43:05 PM PST 23
Peak memory 198000 kb
Host smart-87d0a3e0-bbbf-4a4b-89d0-9d64c611d537
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2957911212 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 9.gpio_tl_intg_err.2957911212
Directory /workspace/9.gpio_tl_intg_err/latest

Test location /workspace/coverage/default/0.gpio_alert_test.180670976
Short name T376
Test name
Test status
Simulation time 47867323 ps
CPU time 0.57 seconds
Started Dec 24 01:09:51 PM PST 23
Finished Dec 24 01:09:57 PM PST 23
Peak memory 194084 kb
Host smart-c4852e27-669a-4d44-aa20-b0fc474df5e4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=180670976 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_alert_test.180670976
Directory /workspace/0.gpio_alert_test/latest

Test location /workspace/coverage/default/0.gpio_dout_din_regs_random_rw.2355035050
Short name T537
Test name
Test status
Simulation time 17042531 ps
CPU time 0.63 seconds
Started Dec 24 01:09:54 PM PST 23
Finished Dec 24 01:09:59 PM PST 23
Peak memory 193964 kb
Host smart-91479631-8f6f-4817-b027-ceba3a7e035f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2355035050 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_dout_din_regs_random_rw.2355035050
Directory /workspace/0.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/0.gpio_filter_stress.2923211777
Short name T857
Test name
Test status
Simulation time 2934624063 ps
CPU time 23.28 seconds
Started Dec 24 01:10:06 PM PST 23
Finished Dec 24 01:10:35 PM PST 23
Peak memory 196688 kb
Host smart-2fad9677-32ec-4a96-8fcb-c408798f704b
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2923211777 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_filter_stres
s.2923211777
Directory /workspace/0.gpio_filter_stress/latest

Test location /workspace/coverage/default/0.gpio_full_random.2964046160
Short name T384
Test name
Test status
Simulation time 77209298 ps
CPU time 0.72 seconds
Started Dec 24 01:10:05 PM PST 23
Finished Dec 24 01:10:10 PM PST 23
Peak memory 194796 kb
Host smart-0acc8d74-bba2-472d-b7b1-b792ac1fae4e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2964046160 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_full_random.2964046160
Directory /workspace/0.gpio_full_random/latest

Test location /workspace/coverage/default/0.gpio_intr_rand_pgm.2860962112
Short name T658
Test name
Test status
Simulation time 174023105 ps
CPU time 1.37 seconds
Started Dec 24 01:10:00 PM PST 23
Finished Dec 24 01:10:05 PM PST 23
Peak memory 198172 kb
Host smart-44ab1531-dfe4-4bf3-bb98-7c34a408065f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2860962112 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_intr_rand_pgm.2860962112
Directory /workspace/0.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/0.gpio_intr_with_filter_rand_intr_event.3825634925
Short name T776
Test name
Test status
Simulation time 138202249 ps
CPU time 1.43 seconds
Started Dec 24 01:09:50 PM PST 23
Finished Dec 24 01:09:57 PM PST 23
Peak memory 197060 kb
Host smart-39692b2a-57e0-4e32-af82-7981d0397097
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3825634925 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 0.gpio_intr_with_filter_rand_intr_event.3825634925
Directory /workspace/0.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/0.gpio_rand_intr_trigger.4222363960
Short name T239
Test name
Test status
Simulation time 153297136 ps
CPU time 2.25 seconds
Started Dec 24 01:10:13 PM PST 23
Finished Dec 24 01:10:20 PM PST 23
Peak memory 197256 kb
Host smart-85d6d803-754f-4acd-9d35-d87cede46de9
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4222363960 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_rand_intr_trigger.
4222363960
Directory /workspace/0.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/0.gpio_random_dout_din.3399806386
Short name T373
Test name
Test status
Simulation time 25026066 ps
CPU time 0.96 seconds
Started Dec 24 01:10:04 PM PST 23
Finished Dec 24 01:10:09 PM PST 23
Peak memory 196648 kb
Host smart-e4a2dc99-ad72-4177-9480-abf9bfcb8b70
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3399806386 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_random_dout_din.3399806386
Directory /workspace/0.gpio_random_dout_din/latest

Test location /workspace/coverage/default/0.gpio_random_dout_din_no_pullup_pulldown.3810833064
Short name T361
Test name
Test status
Simulation time 22617183 ps
CPU time 0.89 seconds
Started Dec 24 01:10:16 PM PST 23
Finished Dec 24 01:10:21 PM PST 23
Peak memory 196780 kb
Host smart-845600af-0022-4af0-8a98-acc0fbb274d9
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3810833064 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_random_dout_din_no_pullup
_pulldown.3810833064
Directory /workspace/0.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/0.gpio_random_long_reg_writes_reg_reads.2940302796
Short name T707
Test name
Test status
Simulation time 3165821118 ps
CPU time 3.23 seconds
Started Dec 24 01:10:09 PM PST 23
Finished Dec 24 01:10:18 PM PST 23
Peak memory 198140 kb
Host smart-71f1bd77-9efc-46b3-970f-2e46797248aa
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2940302796 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_ran
dom_long_reg_writes_reg_reads.2940302796
Directory /workspace/0.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/0.gpio_sec_cm.2169764912
Short name T25
Test name
Test status
Simulation time 650250854 ps
CPU time 1.01 seconds
Started Dec 24 01:10:02 PM PST 23
Finished Dec 24 01:10:07 PM PST 23
Peak memory 214704 kb
Host smart-7a01b391-9fa3-4b5b-ab1f-c98c9236e728
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2169764912 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_sec_cm.2169764912
Directory /workspace/0.gpio_sec_cm/latest

Test location /workspace/coverage/default/0.gpio_smoke.2301933928
Short name T515
Test name
Test status
Simulation time 30482235 ps
CPU time 0.77 seconds
Started Dec 24 01:10:01 PM PST 23
Finished Dec 24 01:10:05 PM PST 23
Peak memory 195484 kb
Host smart-4b2513ca-44f9-4c70-8b48-bca8ebead21c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2301933928 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_smoke.2301933928
Directory /workspace/0.gpio_smoke/latest

Test location /workspace/coverage/default/0.gpio_smoke_no_pullup_pulldown.1131341044
Short name T749
Test name
Test status
Simulation time 113211061 ps
CPU time 1.16 seconds
Started Dec 24 01:09:50 PM PST 23
Finished Dec 24 01:09:57 PM PST 23
Peak memory 196972 kb
Host smart-c2899887-3c64-4584-8ee3-dd0a630aa69b
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1131341044 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_smoke_no_pullup_pulldown.1131341044
Directory /workspace/0.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/0.gpio_stress_all.1886518378
Short name T227
Test name
Test status
Simulation time 7264542208 ps
CPU time 194.44 seconds
Started Dec 24 01:10:02 PM PST 23
Finished Dec 24 01:13:20 PM PST 23
Peak memory 198260 kb
Host smart-1b053af5-2bec-4c22-bb48-cd2f65a64645
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1886518378 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.g
pio_stress_all.1886518378
Directory /workspace/0.gpio_stress_all/latest

Test location /workspace/coverage/default/0.gpio_stress_all_with_rand_reset.1236905419
Short name T843
Test name
Test status
Simulation time 262906845030 ps
CPU time 892.32 seconds
Started Dec 24 01:10:04 PM PST 23
Finished Dec 24 01:25:01 PM PST 23
Peak memory 198300 kb
Host smart-a73f30a5-79ac-4343-9bcf-180ab9dc4323
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=1236905419 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_stress_all_with_rand_reset.1236905419
Directory /workspace/0.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/1.gpio_alert_test.1037886799
Short name T455
Test name
Test status
Simulation time 12301094 ps
CPU time 0.58 seconds
Started Dec 24 01:09:51 PM PST 23
Finished Dec 24 01:09:57 PM PST 23
Peak memory 194968 kb
Host smart-234ce41d-c68d-4ec0-86be-6e4609aa43a9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1037886799 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_alert_test.1037886799
Directory /workspace/1.gpio_alert_test/latest

Test location /workspace/coverage/default/1.gpio_dout_din_regs_random_rw.219260458
Short name T657
Test name
Test status
Simulation time 40744440 ps
CPU time 0.94 seconds
Started Dec 24 01:10:03 PM PST 23
Finished Dec 24 01:10:14 PM PST 23
Peak memory 196800 kb
Host smart-cae5331f-cc90-4065-8472-bfbb44478fd0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=219260458 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_dout_din_regs_random_rw.219260458
Directory /workspace/1.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/1.gpio_filter_stress.3870826863
Short name T868
Test name
Test status
Simulation time 8210879518 ps
CPU time 23.26 seconds
Started Dec 24 01:10:00 PM PST 23
Finished Dec 24 01:10:26 PM PST 23
Peak memory 196840 kb
Host smart-bfb8e733-b416-4976-b9e5-57106f288ab5
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3870826863 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_filter_stres
s.3870826863
Directory /workspace/1.gpio_filter_stress/latest

Test location /workspace/coverage/default/1.gpio_full_random.2894814121
Short name T448
Test name
Test status
Simulation time 253907312 ps
CPU time 0.9 seconds
Started Dec 24 01:10:02 PM PST 23
Finished Dec 24 01:10:06 PM PST 23
Peak memory 197332 kb
Host smart-63889cb3-de32-47e7-9cf2-fb5713201895
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2894814121 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_full_random.2894814121
Directory /workspace/1.gpio_full_random/latest

Test location /workspace/coverage/default/1.gpio_intr_rand_pgm.4139036644
Short name T429
Test name
Test status
Simulation time 97115204 ps
CPU time 0.98 seconds
Started Dec 24 01:10:09 PM PST 23
Finished Dec 24 01:10:16 PM PST 23
Peak memory 196896 kb
Host smart-df170f5d-08be-43cf-ab07-0144d31eac14
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4139036644 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_intr_rand_pgm.4139036644
Directory /workspace/1.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/1.gpio_intr_with_filter_rand_intr_event.193418875
Short name T480
Test name
Test status
Simulation time 68685070 ps
CPU time 1.44 seconds
Started Dec 24 01:10:13 PM PST 23
Finished Dec 24 01:10:19 PM PST 23
Peak memory 196348 kb
Host smart-80b8a2b0-ff11-4264-bfa5-875f7240d225
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=193418875 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 1.gpio_intr_with_filter_rand_intr_event.193418875
Directory /workspace/1.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/1.gpio_rand_intr_trigger.1941885181
Short name T385
Test name
Test status
Simulation time 83489904 ps
CPU time 2.44 seconds
Started Dec 24 01:10:23 PM PST 23
Finished Dec 24 01:10:29 PM PST 23
Peak memory 198220 kb
Host smart-7496112b-8298-4ab5-be81-e7decf79accf
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1941885181 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_rand_intr_trigger.
1941885181
Directory /workspace/1.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/1.gpio_random_dout_din.2262399305
Short name T401
Test name
Test status
Simulation time 46295770 ps
CPU time 0.73 seconds
Started Dec 24 01:10:17 PM PST 23
Finished Dec 24 01:10:22 PM PST 23
Peak memory 196064 kb
Host smart-92e94a70-18ec-4d98-872b-d1be8617faae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2262399305 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_random_dout_din.2262399305
Directory /workspace/1.gpio_random_dout_din/latest

Test location /workspace/coverage/default/1.gpio_random_dout_din_no_pullup_pulldown.1469523749
Short name T494
Test name
Test status
Simulation time 95776055 ps
CPU time 0.68 seconds
Started Dec 24 01:10:04 PM PST 23
Finished Dec 24 01:10:09 PM PST 23
Peak memory 195468 kb
Host smart-ffcd3a07-ab8a-4616-9d1b-7c689d42d4f4
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1469523749 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_random_dout_din_no_pullup
_pulldown.1469523749
Directory /workspace/1.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/1.gpio_random_long_reg_writes_reg_reads.2290330084
Short name T627
Test name
Test status
Simulation time 109884427 ps
CPU time 4.75 seconds
Started Dec 24 01:10:01 PM PST 23
Finished Dec 24 01:10:09 PM PST 23
Peak memory 198088 kb
Host smart-678ec6ed-d352-47b3-977d-2a0e953057a2
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2290330084 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_ran
dom_long_reg_writes_reg_reads.2290330084
Directory /workspace/1.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/1.gpio_smoke.3967068971
Short name T645
Test name
Test status
Simulation time 28596608 ps
CPU time 0.88 seconds
Started Dec 24 01:10:09 PM PST 23
Finished Dec 24 01:10:16 PM PST 23
Peak memory 195428 kb
Host smart-b65f5503-e965-4935-a438-1b2d26a63fc1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3967068971 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_smoke.3967068971
Directory /workspace/1.gpio_smoke/latest

Test location /workspace/coverage/default/1.gpio_smoke_no_pullup_pulldown.1950881291
Short name T832
Test name
Test status
Simulation time 306627703 ps
CPU time 0.91 seconds
Started Dec 24 01:09:54 PM PST 23
Finished Dec 24 01:09:59 PM PST 23
Peak memory 196012 kb
Host smart-1ea7cc10-3b9c-46c9-9c47-2ea57e8f6503
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1950881291 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_smoke_no_pullup_pulldown.1950881291
Directory /workspace/1.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/1.gpio_stress_all.1007459045
Short name T240
Test name
Test status
Simulation time 29632960229 ps
CPU time 137.92 seconds
Started Dec 24 01:10:22 PM PST 23
Finished Dec 24 01:12:44 PM PST 23
Peak memory 198216 kb
Host smart-490cbd86-5305-47b7-ae82-cb5747663a2b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1007459045 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.g
pio_stress_all.1007459045
Directory /workspace/1.gpio_stress_all/latest

Test location /workspace/coverage/default/1.gpio_stress_all_with_rand_reset.1025967541
Short name T852
Test name
Test status
Simulation time 96454441211 ps
CPU time 1405.02 seconds
Started Dec 24 01:09:50 PM PST 23
Finished Dec 24 01:33:20 PM PST 23
Peak memory 198368 kb
Host smart-25681bf3-c471-4434-a70e-e6e84385aee3
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=1025967541 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_stress_all_with_rand_reset.1025967541
Directory /workspace/1.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/10.gpio_alert_test.2263703083
Short name T641
Test name
Test status
Simulation time 11087726 ps
CPU time 0.56 seconds
Started Dec 24 01:10:45 PM PST 23
Finished Dec 24 01:10:57 PM PST 23
Peak memory 194048 kb
Host smart-8aca4392-b2cd-4aee-96ee-7e0110ef8677
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2263703083 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_alert_test.2263703083
Directory /workspace/10.gpio_alert_test/latest

Test location /workspace/coverage/default/10.gpio_dout_din_regs_random_rw.2051669962
Short name T550
Test name
Test status
Simulation time 58106779 ps
CPU time 0.75 seconds
Started Dec 24 01:10:29 PM PST 23
Finished Dec 24 01:10:33 PM PST 23
Peak memory 195992 kb
Host smart-056a3564-0564-4224-96d9-776e0d969ec8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2051669962 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_dout_din_regs_random_rw.2051669962
Directory /workspace/10.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/10.gpio_filter_stress.535126924
Short name T774
Test name
Test status
Simulation time 785794955 ps
CPU time 24.83 seconds
Started Dec 24 01:10:26 PM PST 23
Finished Dec 24 01:11:04 PM PST 23
Peak memory 198120 kb
Host smart-174d51de-3cfd-4aa9-8076-4baeee38d5c7
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=535126924 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_filter_stres
s.535126924
Directory /workspace/10.gpio_filter_stress/latest

Test location /workspace/coverage/default/10.gpio_full_random.525942130
Short name T330
Test name
Test status
Simulation time 183310843 ps
CPU time 0.82 seconds
Started Dec 24 01:10:29 PM PST 23
Finished Dec 24 01:10:33 PM PST 23
Peak memory 196012 kb
Host smart-2b8c065c-4075-486d-9c03-9ad872096f73
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=525942130 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_full_random.525942130
Directory /workspace/10.gpio_full_random/latest

Test location /workspace/coverage/default/10.gpio_intr_rand_pgm.4182704954
Short name T732
Test name
Test status
Simulation time 139158817 ps
CPU time 0.94 seconds
Started Dec 24 01:10:40 PM PST 23
Finished Dec 24 01:10:49 PM PST 23
Peak memory 195848 kb
Host smart-18c33677-8ecd-445a-8847-7236395d1d67
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4182704954 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_intr_rand_pgm.4182704954
Directory /workspace/10.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/10.gpio_intr_with_filter_rand_intr_event.4072975982
Short name T700
Test name
Test status
Simulation time 42819619 ps
CPU time 1 seconds
Started Dec 24 01:10:17 PM PST 23
Finished Dec 24 01:10:22 PM PST 23
Peak memory 196404 kb
Host smart-5deecbd7-ee88-477c-b17e-fa064b7ad425
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4072975982 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 10.gpio_intr_with_filter_rand_intr_event.4072975982
Directory /workspace/10.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/10.gpio_rand_intr_trigger.2396060580
Short name T838
Test name
Test status
Simulation time 230360367 ps
CPU time 2.81 seconds
Started Dec 24 01:10:09 PM PST 23
Finished Dec 24 01:10:18 PM PST 23
Peak memory 196516 kb
Host smart-aaf84a1d-9978-4f7d-bf56-8777f173dd98
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2396060580 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_rand_intr_trigger
.2396060580
Directory /workspace/10.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/10.gpio_random_dout_din.3374975738
Short name T464
Test name
Test status
Simulation time 220594454 ps
CPU time 1 seconds
Started Dec 24 01:10:40 PM PST 23
Finished Dec 24 01:10:48 PM PST 23
Peak memory 196084 kb
Host smart-365600c8-85ef-4e3b-94cc-42c7030856d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3374975738 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_random_dout_din.3374975738
Directory /workspace/10.gpio_random_dout_din/latest

Test location /workspace/coverage/default/10.gpio_random_dout_din_no_pullup_pulldown.2203274042
Short name T321
Test name
Test status
Simulation time 62444322 ps
CPU time 0.79 seconds
Started Dec 24 01:10:26 PM PST 23
Finished Dec 24 01:10:29 PM PST 23
Peak memory 196692 kb
Host smart-d7907a06-be03-486d-8fbf-4770d47022dd
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2203274042 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_random_dout_din_no_pullu
p_pulldown.2203274042
Directory /workspace/10.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/10.gpio_random_long_reg_writes_reg_reads.1245720096
Short name T765
Test name
Test status
Simulation time 1120586738 ps
CPU time 3.7 seconds
Started Dec 24 01:10:18 PM PST 23
Finished Dec 24 01:10:25 PM PST 23
Peak memory 198068 kb
Host smart-b640824b-744f-4186-9871-77ef32ffc778
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1245720096 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_ra
ndom_long_reg_writes_reg_reads.1245720096
Directory /workspace/10.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/10.gpio_smoke.30645653
Short name T829
Test name
Test status
Simulation time 32019825 ps
CPU time 0.81 seconds
Started Dec 24 01:10:10 PM PST 23
Finished Dec 24 01:10:16 PM PST 23
Peak memory 195284 kb
Host smart-e305f848-f4a8-433d-b65a-d50fc2446462
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=30645653 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_smoke.30645653
Directory /workspace/10.gpio_smoke/latest

Test location /workspace/coverage/default/10.gpio_smoke_no_pullup_pulldown.1239201994
Short name T236
Test name
Test status
Simulation time 21800964 ps
CPU time 0.72 seconds
Started Dec 24 01:10:16 PM PST 23
Finished Dec 24 01:10:21 PM PST 23
Peak memory 194924 kb
Host smart-8922a220-3100-4a8a-a06d-5fbbe8c87439
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1239201994 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_smoke_no_pullup_pulldown.1239201994
Directory /workspace/10.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/10.gpio_stress_all.1250483223
Short name T792
Test name
Test status
Simulation time 1647022541 ps
CPU time 45.15 seconds
Started Dec 24 01:10:21 PM PST 23
Finished Dec 24 01:11:09 PM PST 23
Peak memory 198196 kb
Host smart-246ed2ea-194d-4ae7-84c1-b3db8867afc0
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1250483223 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.
gpio_stress_all.1250483223
Directory /workspace/10.gpio_stress_all/latest

Test location /workspace/coverage/default/10.gpio_stress_all_with_rand_reset.874438640
Short name T505
Test name
Test status
Simulation time 55980294423 ps
CPU time 577.43 seconds
Started Dec 24 01:10:20 PM PST 23
Finished Dec 24 01:20:01 PM PST 23
Peak memory 198280 kb
Host smart-3493c9e2-be62-4dd7-b6b0-93b186ac8d05
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=874438640 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_stress_all_with_rand_reset.874438640
Directory /workspace/10.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/11.gpio_dout_din_regs_random_rw.2397004522
Short name T433
Test name
Test status
Simulation time 19622731 ps
CPU time 0.67 seconds
Started Dec 24 01:10:39 PM PST 23
Finished Dec 24 01:10:46 PM PST 23
Peak memory 194080 kb
Host smart-274647ef-3f7e-4684-8b82-8480d18e954f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2397004522 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_dout_din_regs_random_rw.2397004522
Directory /workspace/11.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/11.gpio_filter_stress.783603398
Short name T471
Test name
Test status
Simulation time 2592005339 ps
CPU time 15.73 seconds
Started Dec 24 01:10:39 PM PST 23
Finished Dec 24 01:11:02 PM PST 23
Peak memory 198076 kb
Host smart-7d24b5f9-c66f-4b1a-813b-8fa07c5c0474
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=783603398 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_filter_stres
s.783603398
Directory /workspace/11.gpio_filter_stress/latest

Test location /workspace/coverage/default/11.gpio_full_random.262047272
Short name T686
Test name
Test status
Simulation time 685779815 ps
CPU time 0.94 seconds
Started Dec 24 01:10:43 PM PST 23
Finished Dec 24 01:10:53 PM PST 23
Peak memory 197924 kb
Host smart-5d0ac1c0-27b9-4c33-988f-9016f96d3eaf
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=262047272 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_full_random.262047272
Directory /workspace/11.gpio_full_random/latest

Test location /workspace/coverage/default/11.gpio_intr_rand_pgm.3568168092
Short name T293
Test name
Test status
Simulation time 42703659 ps
CPU time 0.86 seconds
Started Dec 24 01:10:32 PM PST 23
Finished Dec 24 01:10:36 PM PST 23
Peak memory 197092 kb
Host smart-e6bcd611-6b30-4a17-9798-2f4e628de1ae
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3568168092 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_intr_rand_pgm.3568168092
Directory /workspace/11.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/11.gpio_intr_with_filter_rand_intr_event.1775145434
Short name T796
Test name
Test status
Simulation time 207263592 ps
CPU time 2.23 seconds
Started Dec 24 01:10:17 PM PST 23
Finished Dec 24 01:10:24 PM PST 23
Peak memory 198284 kb
Host smart-8dea41af-1517-4cd4-9443-f44791a9bd3b
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1775145434 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 11.gpio_intr_with_filter_rand_intr_event.1775145434
Directory /workspace/11.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/11.gpio_rand_intr_trigger.3540442782
Short name T654
Test name
Test status
Simulation time 155810668 ps
CPU time 1.41 seconds
Started Dec 24 01:10:38 PM PST 23
Finished Dec 24 01:10:46 PM PST 23
Peak memory 196284 kb
Host smart-6f0a3ecc-9b94-4672-8dda-9d8ce9b72074
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3540442782 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_rand_intr_trigger
.3540442782
Directory /workspace/11.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/11.gpio_random_dout_din.1258008196
Short name T757
Test name
Test status
Simulation time 209462288 ps
CPU time 1.28 seconds
Started Dec 24 01:10:26 PM PST 23
Finished Dec 24 01:10:29 PM PST 23
Peak memory 197068 kb
Host smart-f401c9c1-c1e4-411c-9461-257c3177e22a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1258008196 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_random_dout_din.1258008196
Directory /workspace/11.gpio_random_dout_din/latest

Test location /workspace/coverage/default/11.gpio_random_dout_din_no_pullup_pulldown.3479037249
Short name T637
Test name
Test status
Simulation time 307342866 ps
CPU time 0.9 seconds
Started Dec 24 01:10:27 PM PST 23
Finished Dec 24 01:10:30 PM PST 23
Peak memory 196552 kb
Host smart-ba992ff0-9274-4df2-80b3-33e935629702
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3479037249 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_random_dout_din_no_pullu
p_pulldown.3479037249
Directory /workspace/11.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/11.gpio_random_long_reg_writes_reg_reads.859557657
Short name T289
Test name
Test status
Simulation time 559548717 ps
CPU time 6.03 seconds
Started Dec 24 01:10:38 PM PST 23
Finished Dec 24 01:10:50 PM PST 23
Peak memory 198100 kb
Host smart-4ecf5117-1258-4d78-90fa-bfb99d2cbaf3
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=859557657 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_ran
dom_long_reg_writes_reg_reads.859557657
Directory /workspace/11.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/11.gpio_smoke.1079311988
Short name T258
Test name
Test status
Simulation time 137068102 ps
CPU time 1.15 seconds
Started Dec 24 01:10:15 PM PST 23
Finished Dec 24 01:10:21 PM PST 23
Peak memory 196600 kb
Host smart-98be08f3-2e62-4f00-98ec-bfbe03fae3fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1079311988 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_smoke.1079311988
Directory /workspace/11.gpio_smoke/latest

Test location /workspace/coverage/default/11.gpio_smoke_no_pullup_pulldown.2722625793
Short name T337
Test name
Test status
Simulation time 58157486 ps
CPU time 0.88 seconds
Started Dec 24 01:10:20 PM PST 23
Finished Dec 24 01:10:24 PM PST 23
Peak memory 195444 kb
Host smart-abcf250b-a4dc-4e15-a705-d3f1ec6686b6
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2722625793 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_smoke_no_pullup_pulldown.2722625793
Directory /workspace/11.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/11.gpio_stress_all.4151781200
Short name T831
Test name
Test status
Simulation time 36494756105 ps
CPU time 86.28 seconds
Started Dec 24 01:10:41 PM PST 23
Finished Dec 24 01:12:15 PM PST 23
Peak memory 198256 kb
Host smart-d4946e0c-4c47-4e33-b7b6-d4510de0f4d8
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4151781200 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.
gpio_stress_all.4151781200
Directory /workspace/11.gpio_stress_all/latest

Test location /workspace/coverage/default/11.gpio_stress_all_with_rand_reset.815361556
Short name T87
Test name
Test status
Simulation time 87140798621 ps
CPU time 292.25 seconds
Started Dec 24 01:10:37 PM PST 23
Finished Dec 24 01:15:35 PM PST 23
Peak memory 206596 kb
Host smart-e1f8a007-c2b1-4a1b-b83b-8a0feb45f799
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=815361556 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_stress_all_with_rand_reset.815361556
Directory /workspace/11.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/12.gpio_alert_test.1043591336
Short name T758
Test name
Test status
Simulation time 156179400 ps
CPU time 0.56 seconds
Started Dec 24 01:10:16 PM PST 23
Finished Dec 24 01:10:21 PM PST 23
Peak memory 193944 kb
Host smart-19c0a4b9-2cfc-46d0-ad98-eabad878179f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1043591336 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_alert_test.1043591336
Directory /workspace/12.gpio_alert_test/latest

Test location /workspace/coverage/default/12.gpio_dout_din_regs_random_rw.2721800517
Short name T415
Test name
Test status
Simulation time 173815634 ps
CPU time 0.79 seconds
Started Dec 24 01:10:29 PM PST 23
Finished Dec 24 01:10:32 PM PST 23
Peak memory 195340 kb
Host smart-478dadd5-01df-4a1d-a41a-b09306aaf4a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2721800517 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_dout_din_regs_random_rw.2721800517
Directory /workspace/12.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/12.gpio_filter_stress.2984784781
Short name T608
Test name
Test status
Simulation time 994001657 ps
CPU time 12.69 seconds
Started Dec 24 01:10:28 PM PST 23
Finished Dec 24 01:10:44 PM PST 23
Peak memory 196520 kb
Host smart-26380b19-1f57-452b-ae0f-37b83c30f003
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2984784781 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_filter_stre
ss.2984784781
Directory /workspace/12.gpio_filter_stress/latest

Test location /workspace/coverage/default/12.gpio_full_random.2971542566
Short name T800
Test name
Test status
Simulation time 63772794 ps
CPU time 0.72 seconds
Started Dec 24 01:10:30 PM PST 23
Finished Dec 24 01:10:40 PM PST 23
Peak memory 194864 kb
Host smart-8070ce89-9307-4955-b4aa-b83262a89ab1
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2971542566 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_full_random.2971542566
Directory /workspace/12.gpio_full_random/latest

Test location /workspace/coverage/default/12.gpio_intr_rand_pgm.151027685
Short name T777
Test name
Test status
Simulation time 75119425 ps
CPU time 0.73 seconds
Started Dec 24 01:10:41 PM PST 23
Finished Dec 24 01:10:49 PM PST 23
Peak memory 194484 kb
Host smart-11c50834-505b-4aa5-9aec-b48e4007ed04
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=151027685 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_intr_rand_pgm.151027685
Directory /workspace/12.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/12.gpio_rand_intr_trigger.1470822617
Short name T771
Test name
Test status
Simulation time 68309182 ps
CPU time 2.18 seconds
Started Dec 24 01:10:43 PM PST 23
Finished Dec 24 01:10:54 PM PST 23
Peak memory 198144 kb
Host smart-f057ca79-2cf4-4402-90f9-d379766a93a8
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1470822617 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_rand_intr_trigger
.1470822617
Directory /workspace/12.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/12.gpio_random_dout_din.2600984703
Short name T588
Test name
Test status
Simulation time 17994851 ps
CPU time 0.72 seconds
Started Dec 24 01:10:36 PM PST 23
Finished Dec 24 01:10:42 PM PST 23
Peak memory 195320 kb
Host smart-bb86be39-d0a0-41de-8351-a6ba70fd3c3a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2600984703 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_random_dout_din.2600984703
Directory /workspace/12.gpio_random_dout_din/latest

Test location /workspace/coverage/default/12.gpio_random_dout_din_no_pullup_pulldown.413104533
Short name T526
Test name
Test status
Simulation time 62164962 ps
CPU time 0.78 seconds
Started Dec 24 01:10:34 PM PST 23
Finished Dec 24 01:10:55 PM PST 23
Peak memory 196256 kb
Host smart-ec474ce7-6eae-4afd-a11e-0266f10459e6
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=413104533 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_random_dout_din_no_pullup
_pulldown.413104533
Directory /workspace/12.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/12.gpio_random_long_reg_writes_reg_reads.1137437598
Short name T551
Test name
Test status
Simulation time 354442867 ps
CPU time 2.31 seconds
Started Dec 24 01:10:25 PM PST 23
Finished Dec 24 01:10:30 PM PST 23
Peak memory 198116 kb
Host smart-d860ca4b-7305-4640-9ecb-2d5cbe33265b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1137437598 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_ra
ndom_long_reg_writes_reg_reads.1137437598
Directory /workspace/12.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/12.gpio_smoke.1315755217
Short name T685
Test name
Test status
Simulation time 216893453 ps
CPU time 0.88 seconds
Started Dec 24 01:10:31 PM PST 23
Finished Dec 24 01:10:34 PM PST 23
Peak memory 196040 kb
Host smart-9d0bcacc-8886-4efc-bd88-1024d05d38f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1315755217 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_smoke.1315755217
Directory /workspace/12.gpio_smoke/latest

Test location /workspace/coverage/default/12.gpio_smoke_no_pullup_pulldown.3112668996
Short name T708
Test name
Test status
Simulation time 251718071 ps
CPU time 1.2 seconds
Started Dec 24 01:10:30 PM PST 23
Finished Dec 24 01:10:34 PM PST 23
Peak memory 195532 kb
Host smart-b7b643d7-8849-4a77-aeed-3ee37d8de030
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3112668996 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_smoke_no_pullup_pulldown.3112668996
Directory /workspace/12.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/12.gpio_stress_all.1292339335
Short name T49
Test name
Test status
Simulation time 32553152604 ps
CPU time 192.88 seconds
Started Dec 24 01:10:29 PM PST 23
Finished Dec 24 01:13:45 PM PST 23
Peak memory 198276 kb
Host smart-013e308f-86ea-42d7-8d45-7743fec4b5a7
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1292339335 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.
gpio_stress_all.1292339335
Directory /workspace/12.gpio_stress_all/latest

Test location /workspace/coverage/default/13.gpio_alert_test.1579495069
Short name T723
Test name
Test status
Simulation time 36529125 ps
CPU time 0.56 seconds
Started Dec 24 01:10:47 PM PST 23
Finished Dec 24 01:10:59 PM PST 23
Peak memory 194060 kb
Host smart-d3ae613a-5256-4816-a001-6d7fca17b3d3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1579495069 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_alert_test.1579495069
Directory /workspace/13.gpio_alert_test/latest

Test location /workspace/coverage/default/13.gpio_dout_din_regs_random_rw.549060702
Short name T789
Test name
Test status
Simulation time 47162577 ps
CPU time 0.63 seconds
Started Dec 24 01:10:31 PM PST 23
Finished Dec 24 01:10:34 PM PST 23
Peak memory 194736 kb
Host smart-b0d90616-dce4-42f6-b277-4b74fef70cf9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=549060702 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_dout_din_regs_random_rw.549060702
Directory /workspace/13.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/13.gpio_filter_stress.4216510625
Short name T374
Test name
Test status
Simulation time 2236555592 ps
CPU time 12.58 seconds
Started Dec 24 01:10:36 PM PST 23
Finished Dec 24 01:10:53 PM PST 23
Peak memory 196672 kb
Host smart-d2e64d3a-8b43-4c48-bcf7-e1798d0b6899
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4216510625 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_filter_stre
ss.4216510625
Directory /workspace/13.gpio_filter_stress/latest

Test location /workspace/coverage/default/13.gpio_full_random.1117493312
Short name T261
Test name
Test status
Simulation time 57284318 ps
CPU time 0.86 seconds
Started Dec 24 01:10:22 PM PST 23
Finished Dec 24 01:10:27 PM PST 23
Peak memory 196104 kb
Host smart-0df41d20-baed-48f8-b850-7f05e0c4a6df
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1117493312 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_full_random.1117493312
Directory /workspace/13.gpio_full_random/latest

Test location /workspace/coverage/default/13.gpio_intr_rand_pgm.2345044992
Short name T567
Test name
Test status
Simulation time 105317087 ps
CPU time 0.87 seconds
Started Dec 24 01:10:19 PM PST 23
Finished Dec 24 01:10:23 PM PST 23
Peak memory 196328 kb
Host smart-17a06244-65fe-4b32-bcf3-ef4666a3f200
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2345044992 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_intr_rand_pgm.2345044992
Directory /workspace/13.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/13.gpio_intr_with_filter_rand_intr_event.3270137304
Short name T669
Test name
Test status
Simulation time 73097446 ps
CPU time 1.62 seconds
Started Dec 24 01:10:14 PM PST 23
Finished Dec 24 01:10:20 PM PST 23
Peak memory 198268 kb
Host smart-57b5602c-53eb-46e0-aecb-f56c602da817
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3270137304 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 13.gpio_intr_with_filter_rand_intr_event.3270137304
Directory /workspace/13.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/13.gpio_rand_intr_trigger.3981602226
Short name T814
Test name
Test status
Simulation time 551545319 ps
CPU time 2.9 seconds
Started Dec 24 01:10:31 PM PST 23
Finished Dec 24 01:10:37 PM PST 23
Peak memory 196856 kb
Host smart-c9fefeca-4968-44e4-9863-c20bf8aa43ba
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3981602226 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_rand_intr_trigger
.3981602226
Directory /workspace/13.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/13.gpio_random_dout_din.1268798062
Short name T421
Test name
Test status
Simulation time 32094294 ps
CPU time 1.14 seconds
Started Dec 24 01:10:21 PM PST 23
Finished Dec 24 01:10:25 PM PST 23
Peak memory 196104 kb
Host smart-76762c69-812c-465d-82cc-0c86ecb5241e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1268798062 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_random_dout_din.1268798062
Directory /workspace/13.gpio_random_dout_din/latest

Test location /workspace/coverage/default/13.gpio_random_dout_din_no_pullup_pulldown.631930050
Short name T648
Test name
Test status
Simulation time 26609574 ps
CPU time 0.73 seconds
Started Dec 24 01:10:13 PM PST 23
Finished Dec 24 01:10:18 PM PST 23
Peak memory 195404 kb
Host smart-3afeb02e-d218-4b9a-966f-c02c4aa6dc4f
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=631930050 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_random_dout_din_no_pullup
_pulldown.631930050
Directory /workspace/13.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/13.gpio_random_long_reg_writes_reg_reads.4140812305
Short name T764
Test name
Test status
Simulation time 7872687055 ps
CPU time 6.53 seconds
Started Dec 24 01:10:30 PM PST 23
Finished Dec 24 01:10:40 PM PST 23
Peak memory 198184 kb
Host smart-5e4a52a6-e874-4286-bff8-db27f9de248f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4140812305 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_ra
ndom_long_reg_writes_reg_reads.4140812305
Directory /workspace/13.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/13.gpio_smoke.2296464073
Short name T299
Test name
Test status
Simulation time 43564622 ps
CPU time 0.99 seconds
Started Dec 24 01:10:36 PM PST 23
Finished Dec 24 01:10:43 PM PST 23
Peak memory 196252 kb
Host smart-088a00a3-ba1f-4c11-b6f9-9d90ca820b0b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2296464073 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_smoke.2296464073
Directory /workspace/13.gpio_smoke/latest

Test location /workspace/coverage/default/13.gpio_smoke_no_pullup_pulldown.3736708898
Short name T524
Test name
Test status
Simulation time 197685411 ps
CPU time 0.97 seconds
Started Dec 24 01:10:26 PM PST 23
Finished Dec 24 01:10:29 PM PST 23
Peak memory 195436 kb
Host smart-a16d5a38-2504-47ce-a2b3-baf70d01f920
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3736708898 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_smoke_no_pullup_pulldown.3736708898
Directory /workspace/13.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/13.gpio_stress_all.150286470
Short name T382
Test name
Test status
Simulation time 28034961180 ps
CPU time 205.15 seconds
Started Dec 24 01:10:26 PM PST 23
Finished Dec 24 01:13:54 PM PST 23
Peak memory 198176 kb
Host smart-cb4920c4-4267-44cc-b208-08d404ea90ea
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=150286470 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.g
pio_stress_all.150286470
Directory /workspace/13.gpio_stress_all/latest

Test location /workspace/coverage/default/13.gpio_stress_all_with_rand_reset.3240849988
Short name T402
Test name
Test status
Simulation time 100193447660 ps
CPU time 2497.21 seconds
Started Dec 24 01:10:26 PM PST 23
Finished Dec 24 01:52:05 PM PST 23
Peak memory 198340 kb
Host smart-cbfbc880-7e9b-44cb-883f-fb6ad73f62dd
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=3240849988 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_stress_all_with_rand_reset.3240849988
Directory /workspace/13.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/14.gpio_alert_test.4231949007
Short name T416
Test name
Test status
Simulation time 20639476 ps
CPU time 0.57 seconds
Started Dec 24 01:10:23 PM PST 23
Finished Dec 24 01:10:27 PM PST 23
Peak memory 194088 kb
Host smart-a3a0ea71-b403-4d1c-8ff7-d8801b426550
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4231949007 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_alert_test.4231949007
Directory /workspace/14.gpio_alert_test/latest

Test location /workspace/coverage/default/14.gpio_dout_din_regs_random_rw.3964334843
Short name T499
Test name
Test status
Simulation time 62652872 ps
CPU time 0.73 seconds
Started Dec 24 01:10:19 PM PST 23
Finished Dec 24 01:10:23 PM PST 23
Peak memory 196092 kb
Host smart-22eb80c4-c7f9-42ac-ae84-d34efa631116
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3964334843 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_dout_din_regs_random_rw.3964334843
Directory /workspace/14.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/14.gpio_filter_stress.4141289559
Short name T530
Test name
Test status
Simulation time 866448922 ps
CPU time 6.83 seconds
Started Dec 24 01:10:21 PM PST 23
Finished Dec 24 01:10:31 PM PST 23
Peak memory 195656 kb
Host smart-f8b3a3dc-df82-4db0-bac4-862664d4cffe
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4141289559 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_filter_stre
ss.4141289559
Directory /workspace/14.gpio_filter_stress/latest

Test location /workspace/coverage/default/14.gpio_full_random.391168108
Short name T769
Test name
Test status
Simulation time 316878119 ps
CPU time 1.06 seconds
Started Dec 24 01:10:15 PM PST 23
Finished Dec 24 01:10:21 PM PST 23
Peak memory 196600 kb
Host smart-40afdb60-e128-49fc-9daf-1b266a8ac8e0
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=391168108 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_full_random.391168108
Directory /workspace/14.gpio_full_random/latest

Test location /workspace/coverage/default/14.gpio_intr_rand_pgm.3036242770
Short name T712
Test name
Test status
Simulation time 61319011 ps
CPU time 1.15 seconds
Started Dec 24 01:10:20 PM PST 23
Finished Dec 24 01:10:25 PM PST 23
Peak memory 196196 kb
Host smart-becde620-2945-46d2-98a5-e23c6cd1b8b8
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3036242770 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_intr_rand_pgm.3036242770
Directory /workspace/14.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/14.gpio_intr_with_filter_rand_intr_event.3434851027
Short name T439
Test name
Test status
Simulation time 179602912 ps
CPU time 1.91 seconds
Started Dec 24 01:10:20 PM PST 23
Finished Dec 24 01:10:25 PM PST 23
Peak memory 196604 kb
Host smart-1746ec93-c5bf-4b22-a9da-cb5cdbe1468a
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3434851027 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 14.gpio_intr_with_filter_rand_intr_event.3434851027
Directory /workspace/14.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/14.gpio_rand_intr_trigger.1682209383
Short name T630
Test name
Test status
Simulation time 208967749 ps
CPU time 2.12 seconds
Started Dec 24 01:10:20 PM PST 23
Finished Dec 24 01:10:25 PM PST 23
Peak memory 196364 kb
Host smart-663c237b-33d1-4769-b5b2-8caa706973df
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1682209383 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_rand_intr_trigger
.1682209383
Directory /workspace/14.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/14.gpio_random_dout_din.2553677038
Short name T636
Test name
Test status
Simulation time 35539316 ps
CPU time 0.9 seconds
Started Dec 24 01:10:39 PM PST 23
Finished Dec 24 01:10:46 PM PST 23
Peak memory 196792 kb
Host smart-565e54ee-0db4-4278-945a-82c25cd87afd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2553677038 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_random_dout_din.2553677038
Directory /workspace/14.gpio_random_dout_din/latest

Test location /workspace/coverage/default/14.gpio_random_dout_din_no_pullup_pulldown.222191987
Short name T311
Test name
Test status
Simulation time 21735579 ps
CPU time 0.77 seconds
Started Dec 24 01:10:17 PM PST 23
Finished Dec 24 01:10:22 PM PST 23
Peak memory 195344 kb
Host smart-27e2f027-96af-4a05-870a-31b340257408
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=222191987 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_random_dout_din_no_pullup
_pulldown.222191987
Directory /workspace/14.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/14.gpio_random_long_reg_writes_reg_reads.845244472
Short name T538
Test name
Test status
Simulation time 217476391 ps
CPU time 5.07 seconds
Started Dec 24 01:10:21 PM PST 23
Finished Dec 24 01:10:29 PM PST 23
Peak memory 198076 kb
Host smart-383f275c-e926-43e0-903d-239f32cbb62e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=845244472 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_ran
dom_long_reg_writes_reg_reads.845244472
Directory /workspace/14.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/14.gpio_smoke.965566692
Short name T571
Test name
Test status
Simulation time 90989703 ps
CPU time 0.94 seconds
Started Dec 24 01:10:16 PM PST 23
Finished Dec 24 01:10:22 PM PST 23
Peak memory 197308 kb
Host smart-92100620-14d2-498a-9ea0-310cc903da81
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=965566692 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_smoke.965566692
Directory /workspace/14.gpio_smoke/latest

Test location /workspace/coverage/default/14.gpio_smoke_no_pullup_pulldown.1622137901
Short name T675
Test name
Test status
Simulation time 94543942 ps
CPU time 0.99 seconds
Started Dec 24 01:10:41 PM PST 23
Finished Dec 24 01:10:50 PM PST 23
Peak memory 196444 kb
Host smart-841f23a8-e870-47ac-9ccd-dbd45f8cc8f1
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1622137901 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_smoke_no_pullup_pulldown.1622137901
Directory /workspace/14.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/14.gpio_stress_all.1044715246
Short name T670
Test name
Test status
Simulation time 13486774349 ps
CPU time 85.42 seconds
Started Dec 24 01:10:30 PM PST 23
Finished Dec 24 01:11:58 PM PST 23
Peak memory 198192 kb
Host smart-9fc5419a-32a8-4fe2-aa9f-4c430a5b89ad
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1044715246 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.
gpio_stress_all.1044715246
Directory /workspace/14.gpio_stress_all/latest

Test location /workspace/coverage/default/14.gpio_stress_all_with_rand_reset.1822229873
Short name T740
Test name
Test status
Simulation time 279360411334 ps
CPU time 818.83 seconds
Started Dec 24 01:10:26 PM PST 23
Finished Dec 24 01:24:07 PM PST 23
Peak memory 198400 kb
Host smart-bd35cfcc-15d2-4529-8948-017d5a6b0518
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=1822229873 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_stress_all_with_rand_reset.1822229873
Directory /workspace/14.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/15.gpio_alert_test.4181796118
Short name T507
Test name
Test status
Simulation time 40650642 ps
CPU time 0.55 seconds
Started Dec 24 01:10:12 PM PST 23
Finished Dec 24 01:10:17 PM PST 23
Peak memory 193488 kb
Host smart-2f9ed91f-8bb8-4efd-a952-880ed4321791
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4181796118 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_alert_test.4181796118
Directory /workspace/15.gpio_alert_test/latest

Test location /workspace/coverage/default/15.gpio_dout_din_regs_random_rw.2883031557
Short name T389
Test name
Test status
Simulation time 95593472 ps
CPU time 0.77 seconds
Started Dec 24 01:10:14 PM PST 23
Finished Dec 24 01:10:19 PM PST 23
Peak memory 195396 kb
Host smart-c8cee87f-1e8b-41bf-90fd-175e0118713c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2883031557 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_dout_din_regs_random_rw.2883031557
Directory /workspace/15.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/15.gpio_filter_stress.2115405272
Short name T695
Test name
Test status
Simulation time 691883365 ps
CPU time 18.06 seconds
Started Dec 24 01:10:38 PM PST 23
Finished Dec 24 01:11:03 PM PST 23
Peak memory 196820 kb
Host smart-257802a3-8ffa-48ba-b5ec-0ff5be36d325
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2115405272 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_filter_stre
ss.2115405272
Directory /workspace/15.gpio_filter_stress/latest

Test location /workspace/coverage/default/15.gpio_full_random.2458528811
Short name T663
Test name
Test status
Simulation time 414865229 ps
CPU time 0.88 seconds
Started Dec 24 01:10:23 PM PST 23
Finished Dec 24 01:10:28 PM PST 23
Peak memory 197112 kb
Host smart-e2c9ec50-26a5-47cc-93e1-4d80482dc691
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2458528811 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_full_random.2458528811
Directory /workspace/15.gpio_full_random/latest

Test location /workspace/coverage/default/15.gpio_intr_rand_pgm.3424151346
Short name T622
Test name
Test status
Simulation time 358981172 ps
CPU time 0.73 seconds
Started Dec 24 01:10:21 PM PST 23
Finished Dec 24 01:10:25 PM PST 23
Peak memory 195288 kb
Host smart-76475af1-8907-4194-8a2d-1db80a9827ca
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3424151346 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_intr_rand_pgm.3424151346
Directory /workspace/15.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/15.gpio_intr_with_filter_rand_intr_event.1863512737
Short name T366
Test name
Test status
Simulation time 311729633 ps
CPU time 2.88 seconds
Started Dec 24 01:10:15 PM PST 23
Finished Dec 24 01:10:22 PM PST 23
Peak memory 198128 kb
Host smart-e868b760-bbec-4445-903f-5a162654a4ca
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1863512737 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 15.gpio_intr_with_filter_rand_intr_event.1863512737
Directory /workspace/15.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/15.gpio_rand_intr_trigger.1686643884
Short name T368
Test name
Test status
Simulation time 114868521 ps
CPU time 3.14 seconds
Started Dec 24 01:10:27 PM PST 23
Finished Dec 24 01:10:33 PM PST 23
Peak memory 195888 kb
Host smart-ee2e5839-d3c9-4b8b-a7c8-2b16196c408a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1686643884 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_rand_intr_trigger
.1686643884
Directory /workspace/15.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/15.gpio_random_dout_din.4131945945
Short name T242
Test name
Test status
Simulation time 53622315 ps
CPU time 1.19 seconds
Started Dec 24 01:10:36 PM PST 23
Finished Dec 24 01:10:43 PM PST 23
Peak memory 197228 kb
Host smart-f7e2a1ff-bcf4-4c41-8f13-cc09dc25e1f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4131945945 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_random_dout_din.4131945945
Directory /workspace/15.gpio_random_dout_din/latest

Test location /workspace/coverage/default/15.gpio_random_dout_din_no_pullup_pulldown.202449866
Short name T532
Test name
Test status
Simulation time 29473763 ps
CPU time 1.08 seconds
Started Dec 24 01:10:34 PM PST 23
Finished Dec 24 01:10:39 PM PST 23
Peak memory 196192 kb
Host smart-83e10c49-726b-4914-b95f-1458f5a424ff
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=202449866 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_random_dout_din_no_pullup
_pulldown.202449866
Directory /workspace/15.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/15.gpio_random_long_reg_writes_reg_reads.123142727
Short name T824
Test name
Test status
Simulation time 832730272 ps
CPU time 5.47 seconds
Started Dec 24 01:10:23 PM PST 23
Finished Dec 24 01:10:32 PM PST 23
Peak memory 198016 kb
Host smart-8a8fdf99-26d4-4146-ab4e-3848dd844948
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=123142727 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_ran
dom_long_reg_writes_reg_reads.123142727
Directory /workspace/15.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/15.gpio_smoke.501579016
Short name T349
Test name
Test status
Simulation time 52210070 ps
CPU time 0.88 seconds
Started Dec 24 01:10:24 PM PST 23
Finished Dec 24 01:10:28 PM PST 23
Peak memory 195360 kb
Host smart-c24ed2c6-2668-4d81-8ae7-5d2cb2011ad7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=501579016 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_smoke.501579016
Directory /workspace/15.gpio_smoke/latest

Test location /workspace/coverage/default/15.gpio_smoke_no_pullup_pulldown.435458204
Short name T414
Test name
Test status
Simulation time 200814279 ps
CPU time 1.35 seconds
Started Dec 24 01:10:22 PM PST 23
Finished Dec 24 01:10:27 PM PST 23
Peak memory 196880 kb
Host smart-bb2af68f-1826-40d6-9b05-030471b831f2
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=435458204 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_smoke_no_pullup_pulldown.435458204
Directory /workspace/15.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/15.gpio_stress_all.3268245465
Short name T579
Test name
Test status
Simulation time 1385058079 ps
CPU time 29.67 seconds
Started Dec 24 01:10:32 PM PST 23
Finished Dec 24 01:11:06 PM PST 23
Peak memory 197860 kb
Host smart-c76b783a-5979-4d39-a243-dd7336c87fcf
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3268245465 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.
gpio_stress_all.3268245465
Directory /workspace/15.gpio_stress_all/latest

Test location /workspace/coverage/default/15.gpio_stress_all_with_rand_reset.511018278
Short name T436
Test name
Test status
Simulation time 193628167280 ps
CPU time 1638.38 seconds
Started Dec 24 01:10:35 PM PST 23
Finished Dec 24 01:37:58 PM PST 23
Peak memory 198280 kb
Host smart-9d854a03-a73d-4ec2-a280-ef2b93babd92
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=511018278 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_stress_all_with_rand_reset.511018278
Directory /workspace/15.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/16.gpio_alert_test.3776205848
Short name T849
Test name
Test status
Simulation time 11447387 ps
CPU time 0.57 seconds
Started Dec 24 01:10:41 PM PST 23
Finished Dec 24 01:10:49 PM PST 23
Peak memory 193968 kb
Host smart-8d96fee5-70c9-474d-bc3f-46c0271b6966
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3776205848 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_alert_test.3776205848
Directory /workspace/16.gpio_alert_test/latest

Test location /workspace/coverage/default/16.gpio_dout_din_regs_random_rw.2554583421
Short name T497
Test name
Test status
Simulation time 20403207 ps
CPU time 0.66 seconds
Started Dec 24 01:10:23 PM PST 23
Finished Dec 24 01:10:27 PM PST 23
Peak memory 194112 kb
Host smart-d92d0257-1cee-4580-b21b-87189045be5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2554583421 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_dout_din_regs_random_rw.2554583421
Directory /workspace/16.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/16.gpio_filter_stress.4193716020
Short name T528
Test name
Test status
Simulation time 1124926983 ps
CPU time 13.98 seconds
Started Dec 24 01:10:34 PM PST 23
Finished Dec 24 01:10:52 PM PST 23
Peak memory 196952 kb
Host smart-28e5c0ac-f403-4af9-96f1-ca27e9b11448
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4193716020 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_filter_stre
ss.4193716020
Directory /workspace/16.gpio_filter_stress/latest

Test location /workspace/coverage/default/16.gpio_full_random.2584405255
Short name T713
Test name
Test status
Simulation time 78084172 ps
CPU time 0.61 seconds
Started Dec 24 01:10:29 PM PST 23
Finished Dec 24 01:10:32 PM PST 23
Peak memory 194652 kb
Host smart-7f23a477-4741-4328-b337-fb5f5049c8da
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2584405255 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_full_random.2584405255
Directory /workspace/16.gpio_full_random/latest

Test location /workspace/coverage/default/16.gpio_intr_rand_pgm.310643747
Short name T701
Test name
Test status
Simulation time 41517569 ps
CPU time 1.21 seconds
Started Dec 24 01:10:23 PM PST 23
Finished Dec 24 01:10:28 PM PST 23
Peak memory 196216 kb
Host smart-0e3dce1e-2427-46a5-861f-76f12601c0da
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=310643747 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_intr_rand_pgm.310643747
Directory /workspace/16.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/16.gpio_intr_with_filter_rand_intr_event.2417316983
Short name T626
Test name
Test status
Simulation time 656459060 ps
CPU time 1.79 seconds
Started Dec 24 01:10:41 PM PST 23
Finished Dec 24 01:10:51 PM PST 23
Peak memory 198196 kb
Host smart-ced51032-ed00-4060-8116-d2513a07b4ba
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2417316983 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 16.gpio_intr_with_filter_rand_intr_event.2417316983
Directory /workspace/16.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/16.gpio_rand_intr_trigger.2534352764
Short name T453
Test name
Test status
Simulation time 72008424 ps
CPU time 2.04 seconds
Started Dec 24 01:10:37 PM PST 23
Finished Dec 24 01:10:45 PM PST 23
Peak memory 197292 kb
Host smart-62b2ee46-571c-4ae9-a2b9-eb2e588258cb
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2534352764 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_rand_intr_trigger
.2534352764
Directory /workspace/16.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/16.gpio_random_dout_din.1059475485
Short name T62
Test name
Test status
Simulation time 95304029 ps
CPU time 0.73 seconds
Started Dec 24 01:10:38 PM PST 23
Finished Dec 24 01:10:46 PM PST 23
Peak memory 195568 kb
Host smart-c2f9dd85-6d96-45d6-910e-41b3038cc9c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1059475485 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_random_dout_din.1059475485
Directory /workspace/16.gpio_random_dout_din/latest

Test location /workspace/coverage/default/16.gpio_random_dout_din_no_pullup_pulldown.2215882679
Short name T787
Test name
Test status
Simulation time 104917102 ps
CPU time 1.2 seconds
Started Dec 24 01:10:41 PM PST 23
Finished Dec 24 01:10:50 PM PST 23
Peak memory 197132 kb
Host smart-8f239271-f395-4c2e-8841-8ae146b6ad83
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2215882679 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_random_dout_din_no_pullu
p_pulldown.2215882679
Directory /workspace/16.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/16.gpio_random_long_reg_writes_reg_reads.3551770716
Short name T564
Test name
Test status
Simulation time 574436221 ps
CPU time 4.82 seconds
Started Dec 24 01:10:37 PM PST 23
Finished Dec 24 01:10:48 PM PST 23
Peak memory 198024 kb
Host smart-eb474350-3012-4a38-b5c9-51f997581250
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3551770716 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_ra
ndom_long_reg_writes_reg_reads.3551770716
Directory /workspace/16.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/16.gpio_smoke.2879736095
Short name T290
Test name
Test status
Simulation time 53946467 ps
CPU time 1.13 seconds
Started Dec 24 01:10:23 PM PST 23
Finished Dec 24 01:10:27 PM PST 23
Peak memory 196456 kb
Host smart-7ea2c923-542e-4f2a-ac6d-7566439c1ffd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2879736095 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_smoke.2879736095
Directory /workspace/16.gpio_smoke/latest

Test location /workspace/coverage/default/16.gpio_smoke_no_pullup_pulldown.761187590
Short name T722
Test name
Test status
Simulation time 173710430 ps
CPU time 1.09 seconds
Started Dec 24 01:10:27 PM PST 23
Finished Dec 24 01:10:31 PM PST 23
Peak memory 195676 kb
Host smart-c55a05da-c8d9-43ff-bc94-c38085ce6890
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=761187590 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_smoke_no_pullup_pulldown.761187590
Directory /workspace/16.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/16.gpio_stress_all.4237343955
Short name T466
Test name
Test status
Simulation time 10868865854 ps
CPU time 120.72 seconds
Started Dec 24 01:10:34 PM PST 23
Finished Dec 24 01:12:39 PM PST 23
Peak memory 198272 kb
Host smart-078a400e-c209-476e-ba5d-81eaf82b760a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4237343955 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.
gpio_stress_all.4237343955
Directory /workspace/16.gpio_stress_all/latest

Test location /workspace/coverage/default/16.gpio_stress_all_with_rand_reset.1325991021
Short name T326
Test name
Test status
Simulation time 83542312528 ps
CPU time 327.4 seconds
Started Dec 24 01:10:34 PM PST 23
Finished Dec 24 01:16:05 PM PST 23
Peak memory 206580 kb
Host smart-9f6ff265-f347-4339-8afd-f295f1defd6a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=1325991021 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_stress_all_with_rand_reset.1325991021
Directory /workspace/16.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/17.gpio_alert_test.1107368568
Short name T750
Test name
Test status
Simulation time 11071720 ps
CPU time 0.57 seconds
Started Dec 24 01:10:31 PM PST 23
Finished Dec 24 01:10:34 PM PST 23
Peak memory 193996 kb
Host smart-56ab8815-956c-43ef-9b66-7945e478d1d6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1107368568 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_alert_test.1107368568
Directory /workspace/17.gpio_alert_test/latest

Test location /workspace/coverage/default/17.gpio_dout_din_regs_random_rw.926905202
Short name T523
Test name
Test status
Simulation time 43358198 ps
CPU time 0.82 seconds
Started Dec 24 01:10:35 PM PST 23
Finished Dec 24 01:10:40 PM PST 23
Peak memory 195572 kb
Host smart-44b492b8-0d52-4362-95a6-cb4e7e4c06a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=926905202 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_dout_din_regs_random_rw.926905202
Directory /workspace/17.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/17.gpio_filter_stress.252883560
Short name T638
Test name
Test status
Simulation time 345056311 ps
CPU time 18.5 seconds
Started Dec 24 01:10:52 PM PST 23
Finished Dec 24 01:11:21 PM PST 23
Peak memory 197216 kb
Host smart-ae6fc51a-667b-40b0-9a43-ae5ffdb45a29
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=252883560 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_filter_stres
s.252883560
Directory /workspace/17.gpio_filter_stress/latest

Test location /workspace/coverage/default/17.gpio_full_random.1257947303
Short name T246
Test name
Test status
Simulation time 290256799 ps
CPU time 0.95 seconds
Started Dec 24 01:10:40 PM PST 23
Finished Dec 24 01:10:48 PM PST 23
Peak memory 196656 kb
Host smart-299987f1-b0a4-4930-9e7f-2f8de4d2700b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1257947303 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_full_random.1257947303
Directory /workspace/17.gpio_full_random/latest

Test location /workspace/coverage/default/17.gpio_intr_rand_pgm.912179983
Short name T624
Test name
Test status
Simulation time 128541889 ps
CPU time 1.01 seconds
Started Dec 24 01:10:45 PM PST 23
Finished Dec 24 01:11:01 PM PST 23
Peak memory 196140 kb
Host smart-166ba7a1-4799-45d5-b01a-84bf484adff2
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=912179983 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_intr_rand_pgm.912179983
Directory /workspace/17.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/17.gpio_intr_with_filter_rand_intr_event.2409464811
Short name T651
Test name
Test status
Simulation time 31274570 ps
CPU time 1.29 seconds
Started Dec 24 01:10:39 PM PST 23
Finished Dec 24 01:10:46 PM PST 23
Peak memory 196904 kb
Host smart-8f437ee2-627d-424b-a661-5499111b85ba
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2409464811 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 17.gpio_intr_with_filter_rand_intr_event.2409464811
Directory /workspace/17.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/17.gpio_rand_intr_trigger.473091542
Short name T539
Test name
Test status
Simulation time 260573896 ps
CPU time 1.36 seconds
Started Dec 24 01:10:40 PM PST 23
Finished Dec 24 01:10:48 PM PST 23
Peak memory 196616 kb
Host smart-e4280134-5dcf-43c7-86ee-82f25283dc0d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=473091542 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_rand_intr_trigger.
473091542
Directory /workspace/17.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/17.gpio_random_dout_din.1098683361
Short name T693
Test name
Test status
Simulation time 113231976 ps
CPU time 1.16 seconds
Started Dec 24 01:10:50 PM PST 23
Finished Dec 24 01:11:02 PM PST 23
Peak memory 197088 kb
Host smart-9812e922-3cbf-4cd0-a6a8-be437b7b7ef1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1098683361 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_random_dout_din.1098683361
Directory /workspace/17.gpio_random_dout_din/latest

Test location /workspace/coverage/default/17.gpio_random_dout_din_no_pullup_pulldown.1902993039
Short name T730
Test name
Test status
Simulation time 62643724 ps
CPU time 1.09 seconds
Started Dec 24 01:10:30 PM PST 23
Finished Dec 24 01:10:34 PM PST 23
Peak memory 196832 kb
Host smart-7aaf5cb0-2ec0-43a7-9052-23025b060a00
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1902993039 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_random_dout_din_no_pullu
p_pulldown.1902993039
Directory /workspace/17.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/17.gpio_random_long_reg_writes_reg_reads.2924149229
Short name T220
Test name
Test status
Simulation time 219946469 ps
CPU time 2.82 seconds
Started Dec 24 01:10:49 PM PST 23
Finished Dec 24 01:11:02 PM PST 23
Peak memory 198036 kb
Host smart-3779c980-9ef8-48ad-9ec2-f4c1620b1102
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2924149229 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_ra
ndom_long_reg_writes_reg_reads.2924149229
Directory /workspace/17.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/17.gpio_smoke.3973533265
Short name T819
Test name
Test status
Simulation time 59129122 ps
CPU time 1.02 seconds
Started Dec 24 01:10:37 PM PST 23
Finished Dec 24 01:10:43 PM PST 23
Peak memory 195692 kb
Host smart-1bdaef19-e3a9-4da9-a140-9f608f3a75fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3973533265 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_smoke.3973533265
Directory /workspace/17.gpio_smoke/latest

Test location /workspace/coverage/default/17.gpio_smoke_no_pullup_pulldown.1506433470
Short name T516
Test name
Test status
Simulation time 36527540 ps
CPU time 1.1 seconds
Started Dec 24 01:10:42 PM PST 23
Finished Dec 24 01:10:52 PM PST 23
Peak memory 196584 kb
Host smart-02c0b2aa-d048-4a0f-9465-cb475603999f
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1506433470 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_smoke_no_pullup_pulldown.1506433470
Directory /workspace/17.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/17.gpio_stress_all.394691641
Short name T644
Test name
Test status
Simulation time 39815914761 ps
CPU time 146.7 seconds
Started Dec 24 01:10:42 PM PST 23
Finished Dec 24 01:13:17 PM PST 23
Peak memory 198232 kb
Host smart-c31be798-fb42-4a78-b81b-d56681c85549
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=394691641 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.g
pio_stress_all.394691641
Directory /workspace/17.gpio_stress_all/latest

Test location /workspace/coverage/default/17.gpio_stress_all_with_rand_reset.1479677512
Short name T633
Test name
Test status
Simulation time 466205078201 ps
CPU time 1224.79 seconds
Started Dec 24 01:10:30 PM PST 23
Finished Dec 24 01:30:58 PM PST 23
Peak memory 206632 kb
Host smart-7bba55d6-d17a-4fba-9806-42b7bddf6256
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=1479677512 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_stress_all_with_rand_reset.1479677512
Directory /workspace/17.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/18.gpio_alert_test.3091561871
Short name T690
Test name
Test status
Simulation time 27731160 ps
CPU time 0.55 seconds
Started Dec 24 01:10:39 PM PST 23
Finished Dec 24 01:10:46 PM PST 23
Peak memory 193900 kb
Host smart-a3165dc6-3f86-4394-9401-f4b683e9c6b7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3091561871 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_alert_test.3091561871
Directory /workspace/18.gpio_alert_test/latest

Test location /workspace/coverage/default/18.gpio_dout_din_regs_random_rw.2680659836
Short name T391
Test name
Test status
Simulation time 71598836 ps
CPU time 0.76 seconds
Started Dec 24 01:10:40 PM PST 23
Finished Dec 24 01:10:48 PM PST 23
Peak memory 195280 kb
Host smart-4d1cddb1-e057-48a2-bfe6-066c00db09e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2680659836 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_dout_din_regs_random_rw.2680659836
Directory /workspace/18.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/18.gpio_filter_stress.790373857
Short name T363
Test name
Test status
Simulation time 1313265998 ps
CPU time 24.34 seconds
Started Dec 24 01:10:29 PM PST 23
Finished Dec 24 01:10:56 PM PST 23
Peak memory 196952 kb
Host smart-00a8648a-2a50-40f9-add7-accc480b0971
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=790373857 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_filter_stres
s.790373857
Directory /workspace/18.gpio_filter_stress/latest

Test location /workspace/coverage/default/18.gpio_full_random.3471588346
Short name T520
Test name
Test status
Simulation time 353860392 ps
CPU time 1.08 seconds
Started Dec 24 01:10:38 PM PST 23
Finished Dec 24 01:10:45 PM PST 23
Peak memory 196780 kb
Host smart-b9607e2a-e25d-4325-9350-3f07432affa7
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3471588346 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_full_random.3471588346
Directory /workspace/18.gpio_full_random/latest

Test location /workspace/coverage/default/18.gpio_intr_rand_pgm.4126913210
Short name T420
Test name
Test status
Simulation time 54505540 ps
CPU time 1.36 seconds
Started Dec 24 01:10:40 PM PST 23
Finished Dec 24 01:10:49 PM PST 23
Peak memory 198196 kb
Host smart-51795e6f-a267-41dd-8b38-c7f05072ad53
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4126913210 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_intr_rand_pgm.4126913210
Directory /workspace/18.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/18.gpio_intr_with_filter_rand_intr_event.1780703511
Short name T594
Test name
Test status
Simulation time 36797491 ps
CPU time 1.49 seconds
Started Dec 24 01:10:39 PM PST 23
Finished Dec 24 01:10:47 PM PST 23
Peak memory 196576 kb
Host smart-2183c571-ade5-4419-9d89-b8d91d5a169b
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1780703511 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 18.gpio_intr_with_filter_rand_intr_event.1780703511
Directory /workspace/18.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/18.gpio_rand_intr_trigger.1376154479
Short name T273
Test name
Test status
Simulation time 94890870 ps
CPU time 2.8 seconds
Started Dec 24 01:10:47 PM PST 23
Finished Dec 24 01:11:01 PM PST 23
Peak memory 197172 kb
Host smart-e6c714ec-e767-42e2-9347-9985e3c5940c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1376154479 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_rand_intr_trigger
.1376154479
Directory /workspace/18.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/18.gpio_random_dout_din.2740161491
Short name T860
Test name
Test status
Simulation time 51579479 ps
CPU time 1.08 seconds
Started Dec 24 01:10:43 PM PST 23
Finished Dec 24 01:10:53 PM PST 23
Peak memory 196636 kb
Host smart-d0619545-d15d-41ca-b8e7-9285255cede8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2740161491 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_random_dout_din.2740161491
Directory /workspace/18.gpio_random_dout_din/latest

Test location /workspace/coverage/default/18.gpio_random_dout_din_no_pullup_pulldown.586530557
Short name T419
Test name
Test status
Simulation time 282567748 ps
CPU time 1.31 seconds
Started Dec 24 01:10:43 PM PST 23
Finished Dec 24 01:10:54 PM PST 23
Peak memory 196928 kb
Host smart-106a6c39-de23-40b6-a493-4f5550b9a1f4
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=586530557 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_random_dout_din_no_pullup
_pulldown.586530557
Directory /workspace/18.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/18.gpio_random_long_reg_writes_reg_reads.416756482
Short name T262
Test name
Test status
Simulation time 33571637 ps
CPU time 1.49 seconds
Started Dec 24 01:10:34 PM PST 23
Finished Dec 24 01:10:39 PM PST 23
Peak memory 198028 kb
Host smart-0f010172-4074-4f2e-9c5c-d6a7c35ef4d0
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=416756482 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_ran
dom_long_reg_writes_reg_reads.416756482
Directory /workspace/18.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/18.gpio_smoke.1792507901
Short name T500
Test name
Test status
Simulation time 581474724 ps
CPU time 1.04 seconds
Started Dec 24 01:10:35 PM PST 23
Finished Dec 24 01:10:40 PM PST 23
Peak memory 195852 kb
Host smart-a343d1c0-7f2f-4002-a98b-21222d15a4b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1792507901 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_smoke.1792507901
Directory /workspace/18.gpio_smoke/latest

Test location /workspace/coverage/default/18.gpio_smoke_no_pullup_pulldown.3675506438
Short name T563
Test name
Test status
Simulation time 399773143 ps
CPU time 1 seconds
Started Dec 24 01:10:41 PM PST 23
Finished Dec 24 01:10:49 PM PST 23
Peak memory 195820 kb
Host smart-cf61197f-7f36-493d-91ba-8342b54fc19f
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3675506438 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_smoke_no_pullup_pulldown.3675506438
Directory /workspace/18.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/18.gpio_stress_all.1856000765
Short name T463
Test name
Test status
Simulation time 33947387670 ps
CPU time 89.12 seconds
Started Dec 24 01:10:32 PM PST 23
Finished Dec 24 01:12:05 PM PST 23
Peak memory 198228 kb
Host smart-2f11fae5-d4ce-4736-85ae-147542124d03
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1856000765 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.
gpio_stress_all.1856000765
Directory /workspace/18.gpio_stress_all/latest

Test location /workspace/coverage/default/18.gpio_stress_all_with_rand_reset.798474648
Short name T615
Test name
Test status
Simulation time 378592967222 ps
CPU time 1436.18 seconds
Started Dec 24 01:10:55 PM PST 23
Finished Dec 24 01:35:03 PM PST 23
Peak memory 198320 kb
Host smart-0f13cfc2-f4f7-4f9a-969d-9d6fda2a5df5
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=798474648 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_stress_all_with_rand_reset.798474648
Directory /workspace/18.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/19.gpio_alert_test.2062971232
Short name T399
Test name
Test status
Simulation time 15113323 ps
CPU time 0.55 seconds
Started Dec 24 01:10:28 PM PST 23
Finished Dec 24 01:10:37 PM PST 23
Peak memory 193968 kb
Host smart-31ca44e3-84e9-4495-ba75-640656ca11d1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2062971232 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_alert_test.2062971232
Directory /workspace/19.gpio_alert_test/latest

Test location /workspace/coverage/default/19.gpio_dout_din_regs_random_rw.1417593287
Short name T259
Test name
Test status
Simulation time 116599975 ps
CPU time 0.88 seconds
Started Dec 24 01:10:43 PM PST 23
Finished Dec 24 01:10:53 PM PST 23
Peak memory 196480 kb
Host smart-78ada51e-12c4-471e-9044-8c5ed3010fff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1417593287 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_dout_din_regs_random_rw.1417593287
Directory /workspace/19.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/19.gpio_filter_stress.422035121
Short name T294
Test name
Test status
Simulation time 100998671 ps
CPU time 5.23 seconds
Started Dec 24 01:10:40 PM PST 23
Finished Dec 24 01:10:52 PM PST 23
Peak memory 196900 kb
Host smart-dca81771-05be-4828-bbb1-8338d12414b0
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=422035121 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_filter_stres
s.422035121
Directory /workspace/19.gpio_filter_stress/latest

Test location /workspace/coverage/default/19.gpio_full_random.3302036507
Short name T279
Test name
Test status
Simulation time 76781845 ps
CPU time 1 seconds
Started Dec 24 01:10:36 PM PST 23
Finished Dec 24 01:10:42 PM PST 23
Peak memory 196740 kb
Host smart-bed88ef5-89b0-4136-9d00-a6933885d2a5
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3302036507 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_full_random.3302036507
Directory /workspace/19.gpio_full_random/latest

Test location /workspace/coverage/default/19.gpio_intr_rand_pgm.1325535190
Short name T718
Test name
Test status
Simulation time 137704721 ps
CPU time 1.09 seconds
Started Dec 24 01:10:40 PM PST 23
Finished Dec 24 01:10:48 PM PST 23
Peak memory 196024 kb
Host smart-40892c9a-7d8f-4f05-bedb-dd1b6c23bad5
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1325535190 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_intr_rand_pgm.1325535190
Directory /workspace/19.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/19.gpio_intr_with_filter_rand_intr_event.2492993171
Short name T801
Test name
Test status
Simulation time 52228238 ps
CPU time 2.29 seconds
Started Dec 24 01:10:51 PM PST 23
Finished Dec 24 01:11:03 PM PST 23
Peak memory 198288 kb
Host smart-66403bfb-102c-4cb2-bef5-29ead9062eb4
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2492993171 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 19.gpio_intr_with_filter_rand_intr_event.2492993171
Directory /workspace/19.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/19.gpio_rand_intr_trigger.4039567313
Short name T474
Test name
Test status
Simulation time 296055555 ps
CPU time 2.26 seconds
Started Dec 24 01:10:44 PM PST 23
Finished Dec 24 01:10:55 PM PST 23
Peak memory 197308 kb
Host smart-68430aac-bde2-407b-a89b-3b3b753350cb
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4039567313 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_rand_intr_trigger
.4039567313
Directory /workspace/19.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/19.gpio_random_dout_din.1158648786
Short name T113
Test name
Test status
Simulation time 124130418 ps
CPU time 1.03 seconds
Started Dec 24 01:10:28 PM PST 23
Finished Dec 24 01:10:32 PM PST 23
Peak memory 196076 kb
Host smart-b544ca50-c9eb-4d36-8df5-737bf87639a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1158648786 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_random_dout_din.1158648786
Directory /workspace/19.gpio_random_dout_din/latest

Test location /workspace/coverage/default/19.gpio_random_dout_din_no_pullup_pulldown.2420597772
Short name T351
Test name
Test status
Simulation time 22379756 ps
CPU time 0.83 seconds
Started Dec 24 01:10:35 PM PST 23
Finished Dec 24 01:10:40 PM PST 23
Peak memory 196568 kb
Host smart-f03625c2-5196-4589-868d-2ceadea9a8f3
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2420597772 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_random_dout_din_no_pullu
p_pulldown.2420597772
Directory /workspace/19.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/19.gpio_random_long_reg_writes_reg_reads.2810304993
Short name T365
Test name
Test status
Simulation time 323095696 ps
CPU time 1.42 seconds
Started Dec 24 01:10:45 PM PST 23
Finished Dec 24 01:10:57 PM PST 23
Peak memory 198148 kb
Host smart-0b4e2980-4ad8-4584-9387-60562ba3a371
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2810304993 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_ra
ndom_long_reg_writes_reg_reads.2810304993
Directory /workspace/19.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/19.gpio_smoke.754265350
Short name T395
Test name
Test status
Simulation time 261835417 ps
CPU time 1.03 seconds
Started Dec 24 01:10:37 PM PST 23
Finished Dec 24 01:10:44 PM PST 23
Peak memory 195672 kb
Host smart-e5dd3c67-1d71-4f68-8030-b6aee995c688
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=754265350 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_smoke.754265350
Directory /workspace/19.gpio_smoke/latest

Test location /workspace/coverage/default/19.gpio_smoke_no_pullup_pulldown.1475485984
Short name T689
Test name
Test status
Simulation time 85497403 ps
CPU time 1.02 seconds
Started Dec 24 01:10:42 PM PST 23
Finished Dec 24 01:10:52 PM PST 23
Peak memory 195592 kb
Host smart-4521fa7c-81e7-4c8c-ab05-df70097b9b75
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1475485984 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_smoke_no_pullup_pulldown.1475485984
Directory /workspace/19.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/19.gpio_stress_all.3738532243
Short name T692
Test name
Test status
Simulation time 6430715893 ps
CPU time 171.15 seconds
Started Dec 24 01:10:38 PM PST 23
Finished Dec 24 01:13:36 PM PST 23
Peak memory 198268 kb
Host smart-3304df15-1abd-4f8c-b9d7-0c6caac09ed4
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3738532243 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.
gpio_stress_all.3738532243
Directory /workspace/19.gpio_stress_all/latest

Test location /workspace/coverage/default/19.gpio_stress_all_with_rand_reset.2555557608
Short name T763
Test name
Test status
Simulation time 91799984823 ps
CPU time 705.1 seconds
Started Dec 24 01:10:51 PM PST 23
Finished Dec 24 01:22:46 PM PST 23
Peak memory 198216 kb
Host smart-acbf4746-e491-448a-95cc-ba87ea50e838
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=2555557608 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_stress_all_with_rand_reset.2555557608
Directory /workspace/19.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/2.gpio_alert_test.951628291
Short name T45
Test name
Test status
Simulation time 19558566 ps
CPU time 0.56 seconds
Started Dec 24 01:10:10 PM PST 23
Finished Dec 24 01:10:16 PM PST 23
Peak memory 194056 kb
Host smart-6596a7dc-0e19-4828-ab6a-7a52dfd1f469
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=951628291 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_alert_test.951628291
Directory /workspace/2.gpio_alert_test/latest

Test location /workspace/coverage/default/2.gpio_dout_din_regs_random_rw.915220934
Short name T864
Test name
Test status
Simulation time 97551099 ps
CPU time 0.76 seconds
Started Dec 24 01:10:03 PM PST 23
Finished Dec 24 01:10:08 PM PST 23
Peak memory 195212 kb
Host smart-5951480e-44c2-49d9-bf87-e2dcdaf3885b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=915220934 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_dout_din_regs_random_rw.915220934
Directory /workspace/2.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/2.gpio_filter_stress.3835445426
Short name T661
Test name
Test status
Simulation time 1137192117 ps
CPU time 19.18 seconds
Started Dec 24 01:10:07 PM PST 23
Finished Dec 24 01:10:33 PM PST 23
Peak memory 198124 kb
Host smart-f951f283-d218-4ef7-a4d4-9859c2e7a4f0
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3835445426 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_filter_stres
s.3835445426
Directory /workspace/2.gpio_filter_stress/latest

Test location /workspace/coverage/default/2.gpio_full_random.1328756073
Short name T865
Test name
Test status
Simulation time 195946222 ps
CPU time 0.91 seconds
Started Dec 24 01:10:02 PM PST 23
Finished Dec 24 01:10:06 PM PST 23
Peak memory 197240 kb
Host smart-a0c33286-192c-4992-a09c-f089b679ac65
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1328756073 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_full_random.1328756073
Directory /workspace/2.gpio_full_random/latest

Test location /workspace/coverage/default/2.gpio_intr_rand_pgm.1442946647
Short name T859
Test name
Test status
Simulation time 112760786 ps
CPU time 0.78 seconds
Started Dec 24 01:10:20 PM PST 23
Finished Dec 24 01:10:24 PM PST 23
Peak memory 195568 kb
Host smart-78311e0f-f10b-47df-bffd-15444f25bd8e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1442946647 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_intr_rand_pgm.1442946647
Directory /workspace/2.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/2.gpio_intr_with_filter_rand_intr_event.1136781309
Short name T543
Test name
Test status
Simulation time 57137258 ps
CPU time 2.26 seconds
Started Dec 24 01:10:38 PM PST 23
Finished Dec 24 01:10:47 PM PST 23
Peak memory 198008 kb
Host smart-1e271d3b-da53-40b6-a6b2-b88d6158bbc5
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1136781309 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 2.gpio_intr_with_filter_rand_intr_event.1136781309
Directory /workspace/2.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/2.gpio_rand_intr_trigger.3080618991
Short name T656
Test name
Test status
Simulation time 144014429 ps
CPU time 1.6 seconds
Started Dec 24 01:10:14 PM PST 23
Finished Dec 24 01:10:20 PM PST 23
Peak memory 196072 kb
Host smart-304d34f5-944d-4fbe-a06e-829d3f72d452
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3080618991 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_rand_intr_trigger.
3080618991
Directory /workspace/2.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/2.gpio_random_dout_din.3633672837
Short name T822
Test name
Test status
Simulation time 90496776 ps
CPU time 0.65 seconds
Started Dec 24 01:10:03 PM PST 23
Finished Dec 24 01:10:07 PM PST 23
Peak memory 194456 kb
Host smart-3c429477-16ba-4d88-9ea0-4354b287fda0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3633672837 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_random_dout_din.3633672837
Directory /workspace/2.gpio_random_dout_din/latest

Test location /workspace/coverage/default/2.gpio_random_dout_din_no_pullup_pulldown.4248612946
Short name T427
Test name
Test status
Simulation time 304040702 ps
CPU time 1.32 seconds
Started Dec 24 01:10:03 PM PST 23
Finished Dec 24 01:10:08 PM PST 23
Peak memory 197108 kb
Host smart-5039a228-e617-4217-862b-917066283813
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4248612946 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_random_dout_din_no_pullup
_pulldown.4248612946
Directory /workspace/2.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/2.gpio_random_long_reg_writes_reg_reads.2598402618
Short name T802
Test name
Test status
Simulation time 118995182 ps
CPU time 2.01 seconds
Started Dec 24 01:10:33 PM PST 23
Finished Dec 24 01:10:39 PM PST 23
Peak memory 198132 kb
Host smart-47415282-4b09-4f83-8745-6187c442debb
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2598402618 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_ran
dom_long_reg_writes_reg_reads.2598402618
Directory /workspace/2.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/2.gpio_sec_cm.2212810407
Short name T26
Test name
Test status
Simulation time 229456257 ps
CPU time 0.86 seconds
Started Dec 24 01:10:20 PM PST 23
Finished Dec 24 01:10:24 PM PST 23
Peak memory 213560 kb
Host smart-0f8c461c-ef4e-4969-8b11-e64d0d65901e
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2212810407 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_sec_cm.2212810407
Directory /workspace/2.gpio_sec_cm/latest

Test location /workspace/coverage/default/2.gpio_smoke.2845686761
Short name T609
Test name
Test status
Simulation time 34014266 ps
CPU time 0.72 seconds
Started Dec 24 01:09:58 PM PST 23
Finished Dec 24 01:10:03 PM PST 23
Peak memory 195216 kb
Host smart-66b76426-fb35-41d8-8644-cb7a3bb5caee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2845686761 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_smoke.2845686761
Directory /workspace/2.gpio_smoke/latest

Test location /workspace/coverage/default/2.gpio_smoke_no_pullup_pulldown.3719052537
Short name T845
Test name
Test status
Simulation time 333064805 ps
CPU time 0.98 seconds
Started Dec 24 01:10:07 PM PST 23
Finished Dec 24 01:10:14 PM PST 23
Peak memory 195680 kb
Host smart-3f542e7c-b85b-41b1-9f83-9be194848fbc
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3719052537 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_smoke_no_pullup_pulldown.3719052537
Directory /workspace/2.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/2.gpio_stress_all.235078642
Short name T568
Test name
Test status
Simulation time 2804259500 ps
CPU time 69.28 seconds
Started Dec 24 01:10:05 PM PST 23
Finished Dec 24 01:11:21 PM PST 23
Peak memory 198288 kb
Host smart-05818970-d701-4680-9027-fb8bace6ca0e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=235078642 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gp
io_stress_all.235078642
Directory /workspace/2.gpio_stress_all/latest

Test location /workspace/coverage/default/2.gpio_stress_all_with_rand_reset.497900912
Short name T725
Test name
Test status
Simulation time 108993771452 ps
CPU time 2515.11 seconds
Started Dec 24 01:10:09 PM PST 23
Finished Dec 24 01:52:10 PM PST 23
Peak memory 198404 kb
Host smart-bacc025d-b075-4c97-86ba-74f3c740a63e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=497900912 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_stress_all_with_rand_reset.497900912
Directory /workspace/2.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/20.gpio_alert_test.2903104864
Short name T406
Test name
Test status
Simulation time 33133023 ps
CPU time 0.58 seconds
Started Dec 24 01:10:45 PM PST 23
Finished Dec 24 01:10:56 PM PST 23
Peak memory 194196 kb
Host smart-0fefd298-cb36-45f4-b096-c4047dac10d1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2903104864 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_alert_test.2903104864
Directory /workspace/20.gpio_alert_test/latest

Test location /workspace/coverage/default/20.gpio_dout_din_regs_random_rw.982007363
Short name T744
Test name
Test status
Simulation time 75106671 ps
CPU time 0.69 seconds
Started Dec 24 01:10:30 PM PST 23
Finished Dec 24 01:10:34 PM PST 23
Peak memory 195356 kb
Host smart-cee9b0e7-3b49-4fbb-99de-60ba796afabd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=982007363 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_dout_din_regs_random_rw.982007363
Directory /workspace/20.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/20.gpio_filter_stress.963915231
Short name T812
Test name
Test status
Simulation time 163564513 ps
CPU time 7.17 seconds
Started Dec 24 01:10:37 PM PST 23
Finished Dec 24 01:10:50 PM PST 23
Peak memory 196936 kb
Host smart-10d90e23-95d0-43a7-bdb6-82f4a6c0104c
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=963915231 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_filter_stres
s.963915231
Directory /workspace/20.gpio_filter_stress/latest

Test location /workspace/coverage/default/20.gpio_full_random.1017409831
Short name T407
Test name
Test status
Simulation time 263579052 ps
CPU time 0.85 seconds
Started Dec 24 01:10:40 PM PST 23
Finished Dec 24 01:10:49 PM PST 23
Peak memory 196928 kb
Host smart-1fc37f30-4320-4505-aa29-7698b7d97c3d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1017409831 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_full_random.1017409831
Directory /workspace/20.gpio_full_random/latest

Test location /workspace/coverage/default/20.gpio_intr_rand_pgm.111910186
Short name T746
Test name
Test status
Simulation time 26905530 ps
CPU time 0.82 seconds
Started Dec 24 01:10:35 PM PST 23
Finished Dec 24 01:10:40 PM PST 23
Peak memory 195632 kb
Host smart-0df40c51-4730-40db-8b32-02943af6e4cf
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=111910186 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_intr_rand_pgm.111910186
Directory /workspace/20.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/20.gpio_intr_with_filter_rand_intr_event.3310869870
Short name T882
Test name
Test status
Simulation time 67899718 ps
CPU time 2.63 seconds
Started Dec 24 01:10:27 PM PST 23
Finished Dec 24 01:10:32 PM PST 23
Peak memory 198140 kb
Host smart-74722551-8327-4ba0-9ba6-8a325e8ff0a3
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3310869870 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 20.gpio_intr_with_filter_rand_intr_event.3310869870
Directory /workspace/20.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/20.gpio_rand_intr_trigger.1943203750
Short name T766
Test name
Test status
Simulation time 953223586 ps
CPU time 1.74 seconds
Started Dec 24 01:10:43 PM PST 23
Finished Dec 24 01:10:54 PM PST 23
Peak memory 196752 kb
Host smart-c395e684-5b89-4a8d-a4d2-287ef982e4f5
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1943203750 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_rand_intr_trigger
.1943203750
Directory /workspace/20.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/20.gpio_random_dout_din.2400708264
Short name T479
Test name
Test status
Simulation time 92490325 ps
CPU time 0.97 seconds
Started Dec 24 01:10:36 PM PST 23
Finished Dec 24 01:10:43 PM PST 23
Peak memory 196100 kb
Host smart-9e340b0e-deda-4d60-b62f-f371de681cb3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2400708264 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_random_dout_din.2400708264
Directory /workspace/20.gpio_random_dout_din/latest

Test location /workspace/coverage/default/20.gpio_random_dout_din_no_pullup_pulldown.685371985
Short name T357
Test name
Test status
Simulation time 26194583 ps
CPU time 0.68 seconds
Started Dec 24 01:10:52 PM PST 23
Finished Dec 24 01:11:02 PM PST 23
Peak memory 195036 kb
Host smart-8cce913d-64e1-4bed-ba70-20ce3a554b2d
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=685371985 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_random_dout_din_no_pullup
_pulldown.685371985
Directory /workspace/20.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/20.gpio_random_long_reg_writes_reg_reads.2909179362
Short name T770
Test name
Test status
Simulation time 366143684 ps
CPU time 4.49 seconds
Started Dec 24 01:10:32 PM PST 23
Finished Dec 24 01:10:40 PM PST 23
Peak memory 198048 kb
Host smart-41abf775-e5b2-4398-9b35-4b7eb7c0d0cd
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2909179362 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_ra
ndom_long_reg_writes_reg_reads.2909179362
Directory /workspace/20.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/20.gpio_smoke.4090824752
Short name T613
Test name
Test status
Simulation time 46733824 ps
CPU time 1.3 seconds
Started Dec 24 01:10:52 PM PST 23
Finished Dec 24 01:11:04 PM PST 23
Peak memory 198036 kb
Host smart-24a704b4-5f3c-4e59-adb6-055b0ccceef6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4090824752 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_smoke.4090824752
Directory /workspace/20.gpio_smoke/latest

Test location /workspace/coverage/default/20.gpio_smoke_no_pullup_pulldown.1900905863
Short name T61
Test name
Test status
Simulation time 44582788 ps
CPU time 1.23 seconds
Started Dec 24 01:10:36 PM PST 23
Finished Dec 24 01:10:43 PM PST 23
Peak memory 196764 kb
Host smart-cb693093-8348-469c-b8c3-26e366173909
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1900905863 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_smoke_no_pullup_pulldown.1900905863
Directory /workspace/20.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/20.gpio_stress_all.1612197560
Short name T224
Test name
Test status
Simulation time 6262092521 ps
CPU time 47.13 seconds
Started Dec 24 01:10:37 PM PST 23
Finished Dec 24 01:11:30 PM PST 23
Peak memory 197924 kb
Host smart-ff747c0c-10f1-44d0-8a38-bb56d0dcaf1c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1612197560 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.
gpio_stress_all.1612197560
Directory /workspace/20.gpio_stress_all/latest

Test location /workspace/coverage/default/20.gpio_stress_all_with_rand_reset.3827341713
Short name T790
Test name
Test status
Simulation time 89902595631 ps
CPU time 2470.77 seconds
Started Dec 24 01:10:33 PM PST 23
Finished Dec 24 01:51:47 PM PST 23
Peak memory 197612 kb
Host smart-e7cc8358-97a1-470b-9980-c5c1fb889e34
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=3827341713 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_stress_all_with_rand_reset.3827341713
Directory /workspace/20.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/21.gpio_alert_test.1339674607
Short name T605
Test name
Test status
Simulation time 56819591 ps
CPU time 0.56 seconds
Started Dec 24 01:10:52 PM PST 23
Finished Dec 24 01:11:03 PM PST 23
Peak memory 194764 kb
Host smart-09cef855-aedf-4a55-a51c-2879aa016113
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1339674607 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_alert_test.1339674607
Directory /workspace/21.gpio_alert_test/latest

Test location /workspace/coverage/default/21.gpio_dout_din_regs_random_rw.2862368718
Short name T873
Test name
Test status
Simulation time 162838554 ps
CPU time 0.88 seconds
Started Dec 24 01:10:53 PM PST 23
Finished Dec 24 01:11:04 PM PST 23
Peak memory 197292 kb
Host smart-10775808-cd1f-4ccf-bd4f-bcbcee17c8cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2862368718 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_dout_din_regs_random_rw.2862368718
Directory /workspace/21.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/21.gpio_filter_stress.2520188350
Short name T619
Test name
Test status
Simulation time 1713453162 ps
CPU time 22.75 seconds
Started Dec 24 01:10:46 PM PST 23
Finished Dec 24 01:11:20 PM PST 23
Peak memory 196920 kb
Host smart-057e919e-bda2-4a4a-afc0-f8c84f9c8560
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2520188350 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_filter_stre
ss.2520188350
Directory /workspace/21.gpio_filter_stress/latest

Test location /workspace/coverage/default/21.gpio_full_random.2988022010
Short name T355
Test name
Test status
Simulation time 71167885 ps
CPU time 0.97 seconds
Started Dec 24 01:10:42 PM PST 23
Finished Dec 24 01:10:51 PM PST 23
Peak memory 196776 kb
Host smart-a4f2816a-2011-48b1-99bf-3a0e772c4174
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2988022010 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_full_random.2988022010
Directory /workspace/21.gpio_full_random/latest

Test location /workspace/coverage/default/21.gpio_intr_rand_pgm.1783796593
Short name T760
Test name
Test status
Simulation time 176170242 ps
CPU time 0.87 seconds
Started Dec 24 01:10:35 PM PST 23
Finished Dec 24 01:10:40 PM PST 23
Peak memory 195768 kb
Host smart-6ca7b563-9bde-48f2-a62c-a0848689dacc
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1783796593 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_intr_rand_pgm.1783796593
Directory /workspace/21.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/21.gpio_intr_with_filter_rand_intr_event.3784302981
Short name T425
Test name
Test status
Simulation time 380771816 ps
CPU time 3.11 seconds
Started Dec 24 01:10:41 PM PST 23
Finished Dec 24 01:10:51 PM PST 23
Peak memory 198064 kb
Host smart-d1f84e57-d9a8-4b2a-a0a3-96580d50ea2f
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3784302981 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 21.gpio_intr_with_filter_rand_intr_event.3784302981
Directory /workspace/21.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/21.gpio_rand_intr_trigger.2182907008
Short name T403
Test name
Test status
Simulation time 468190413 ps
CPU time 2.64 seconds
Started Dec 24 01:10:38 PM PST 23
Finished Dec 24 01:10:47 PM PST 23
Peak memory 197200 kb
Host smart-701d3d9a-dafc-4f56-bdf8-cce5e2b45a2c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2182907008 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_rand_intr_trigger
.2182907008
Directory /workspace/21.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/21.gpio_random_dout_din.2574454933
Short name T397
Test name
Test status
Simulation time 61322754 ps
CPU time 0.75 seconds
Started Dec 24 01:10:41 PM PST 23
Finished Dec 24 01:10:50 PM PST 23
Peak memory 196044 kb
Host smart-6427bcf9-bcb7-434e-8555-5759204affd7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2574454933 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_random_dout_din.2574454933
Directory /workspace/21.gpio_random_dout_din/latest

Test location /workspace/coverage/default/21.gpio_random_dout_din_no_pullup_pulldown.3368417976
Short name T518
Test name
Test status
Simulation time 54070095 ps
CPU time 1.08 seconds
Started Dec 24 01:10:40 PM PST 23
Finished Dec 24 01:10:49 PM PST 23
Peak memory 195976 kb
Host smart-6450774d-b91e-4cf5-922a-4ce5a27c5f4c
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3368417976 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_random_dout_din_no_pullu
p_pulldown.3368417976
Directory /workspace/21.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/21.gpio_random_long_reg_writes_reg_reads.465081038
Short name T703
Test name
Test status
Simulation time 394989044 ps
CPU time 5.09 seconds
Started Dec 24 01:10:46 PM PST 23
Finished Dec 24 01:11:02 PM PST 23
Peak memory 197996 kb
Host smart-a39ba393-12d4-455a-9946-5b593ddb59ef
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=465081038 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_ran
dom_long_reg_writes_reg_reads.465081038
Directory /workspace/21.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/21.gpio_smoke.1556474978
Short name T655
Test name
Test status
Simulation time 102264396 ps
CPU time 1.36 seconds
Started Dec 24 01:10:43 PM PST 23
Finished Dec 24 01:10:54 PM PST 23
Peak memory 196840 kb
Host smart-b3c5f569-adb4-4090-8579-3c82ed493c3e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1556474978 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_smoke.1556474978
Directory /workspace/21.gpio_smoke/latest

Test location /workspace/coverage/default/21.gpio_smoke_no_pullup_pulldown.1700492440
Short name T778
Test name
Test status
Simulation time 235404534 ps
CPU time 1.18 seconds
Started Dec 24 01:10:36 PM PST 23
Finished Dec 24 01:10:43 PM PST 23
Peak memory 196792 kb
Host smart-162d8f09-cda7-47c7-b9e1-fd3743432896
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1700492440 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_smoke_no_pullup_pulldown.1700492440
Directory /workspace/21.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/21.gpio_stress_all.2770993589
Short name T855
Test name
Test status
Simulation time 13932049646 ps
CPU time 146.64 seconds
Started Dec 24 01:10:39 PM PST 23
Finished Dec 24 01:13:12 PM PST 23
Peak memory 198244 kb
Host smart-26152bfa-d20d-4c18-aa40-72a637049b6f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2770993589 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.
gpio_stress_all.2770993589
Directory /workspace/21.gpio_stress_all/latest

Test location /workspace/coverage/default/21.gpio_stress_all_with_rand_reset.1209217622
Short name T435
Test name
Test status
Simulation time 223057447886 ps
CPU time 1813.34 seconds
Started Dec 24 01:10:53 PM PST 23
Finished Dec 24 01:41:17 PM PST 23
Peak memory 198288 kb
Host smart-431f1b56-c7ce-4775-b6f6-47154c65c5fb
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=1209217622 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_stress_all_with_rand_reset.1209217622
Directory /workspace/21.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/22.gpio_alert_test.869423522
Short name T696
Test name
Test status
Simulation time 75752862 ps
CPU time 0.59 seconds
Started Dec 24 01:10:42 PM PST 23
Finished Dec 24 01:10:52 PM PST 23
Peak memory 193992 kb
Host smart-0720444e-5b9d-4909-88a0-f244bfe69fa8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=869423522 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_alert_test.869423522
Directory /workspace/22.gpio_alert_test/latest

Test location /workspace/coverage/default/22.gpio_dout_din_regs_random_rw.837837138
Short name T255
Test name
Test status
Simulation time 198499838 ps
CPU time 0.91 seconds
Started Dec 24 01:10:39 PM PST 23
Finished Dec 24 01:10:46 PM PST 23
Peak memory 195728 kb
Host smart-b976f14c-ba42-4b0e-92a2-c1f1677974db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=837837138 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_dout_din_regs_random_rw.837837138
Directory /workspace/22.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/22.gpio_filter_stress.1553209952
Short name T370
Test name
Test status
Simulation time 5274879606 ps
CPU time 23.39 seconds
Started Dec 24 01:10:35 PM PST 23
Finished Dec 24 01:11:03 PM PST 23
Peak memory 197640 kb
Host smart-54304179-af4f-4c41-bf4a-5665bb94f594
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1553209952 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_filter_stre
ss.1553209952
Directory /workspace/22.gpio_filter_stress/latest

Test location /workspace/coverage/default/22.gpio_full_random.1021102871
Short name T348
Test name
Test status
Simulation time 283746201 ps
CPU time 0.94 seconds
Started Dec 24 01:11:02 PM PST 23
Finished Dec 24 01:11:15 PM PST 23
Peak memory 197176 kb
Host smart-feaef809-fa6f-4cc5-b851-9886267c1064
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1021102871 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_full_random.1021102871
Directory /workspace/22.gpio_full_random/latest

Test location /workspace/coverage/default/22.gpio_intr_rand_pgm.2267925081
Short name T485
Test name
Test status
Simulation time 21643873 ps
CPU time 0.75 seconds
Started Dec 24 01:10:43 PM PST 23
Finished Dec 24 01:10:54 PM PST 23
Peak memory 195476 kb
Host smart-66f29705-3f98-49fc-8494-2dd927a0f78f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2267925081 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_intr_rand_pgm.2267925081
Directory /workspace/22.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/22.gpio_intr_with_filter_rand_intr_event.3533062877
Short name T268
Test name
Test status
Simulation time 59319586 ps
CPU time 2.35 seconds
Started Dec 24 01:10:53 PM PST 23
Finished Dec 24 01:11:07 PM PST 23
Peak memory 198064 kb
Host smart-9a1da3fa-51b8-4257-aa0f-79dc987f3a96
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3533062877 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 22.gpio_intr_with_filter_rand_intr_event.3533062877
Directory /workspace/22.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/22.gpio_rand_intr_trigger.2284074652
Short name T842
Test name
Test status
Simulation time 212997493 ps
CPU time 1.68 seconds
Started Dec 24 01:10:37 PM PST 23
Finished Dec 24 01:10:45 PM PST 23
Peak memory 195816 kb
Host smart-f4ffe7ac-2d51-4bb7-b4a9-6de647ca4a8c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2284074652 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_rand_intr_trigger
.2284074652
Directory /workspace/22.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/22.gpio_random_dout_din.21322566
Short name T509
Test name
Test status
Simulation time 38371958 ps
CPU time 0.72 seconds
Started Dec 24 01:10:45 PM PST 23
Finished Dec 24 01:10:56 PM PST 23
Peak memory 195328 kb
Host smart-9cf98010-25b7-4a9c-8717-506a688dccbf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=21322566 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_random_dout_din.21322566
Directory /workspace/22.gpio_random_dout_din/latest

Test location /workspace/coverage/default/22.gpio_random_dout_din_no_pullup_pulldown.1356008991
Short name T682
Test name
Test status
Simulation time 100109272 ps
CPU time 1.09 seconds
Started Dec 24 01:10:32 PM PST 23
Finished Dec 24 01:10:37 PM PST 23
Peak memory 196608 kb
Host smart-89caa2ac-fb6f-4775-98ca-2582186a6395
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1356008991 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_random_dout_din_no_pullu
p_pulldown.1356008991
Directory /workspace/22.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/22.gpio_random_long_reg_writes_reg_reads.2983801442
Short name T886
Test name
Test status
Simulation time 56872292 ps
CPU time 1.29 seconds
Started Dec 24 01:10:28 PM PST 23
Finished Dec 24 01:10:32 PM PST 23
Peak memory 197980 kb
Host smart-e4bdbe24-7a95-430f-a87e-170b144dbd00
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2983801442 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_ra
ndom_long_reg_writes_reg_reads.2983801442
Directory /workspace/22.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/22.gpio_smoke.3413652486
Short name T417
Test name
Test status
Simulation time 32910518 ps
CPU time 0.92 seconds
Started Dec 24 01:10:40 PM PST 23
Finished Dec 24 01:10:48 PM PST 23
Peak memory 195508 kb
Host smart-b3806e70-8707-4830-b8fb-bcf2f45d2ac4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3413652486 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_smoke.3413652486
Directory /workspace/22.gpio_smoke/latest

Test location /workspace/coverage/default/22.gpio_smoke_no_pullup_pulldown.1654415624
Short name T99
Test name
Test status
Simulation time 46077197 ps
CPU time 0.84 seconds
Started Dec 24 01:10:40 PM PST 23
Finished Dec 24 01:10:49 PM PST 23
Peak memory 195348 kb
Host smart-85b5cc7a-264e-43ea-b301-daceeea1eded
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1654415624 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_smoke_no_pullup_pulldown.1654415624
Directory /workspace/22.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/22.gpio_stress_all.1691497414
Short name T699
Test name
Test status
Simulation time 27897095752 ps
CPU time 102.47 seconds
Started Dec 24 01:10:35 PM PST 23
Finished Dec 24 01:12:22 PM PST 23
Peak memory 198252 kb
Host smart-aa5a19d5-4e4a-4643-9657-7354fd0df788
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1691497414 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.
gpio_stress_all.1691497414
Directory /workspace/22.gpio_stress_all/latest

Test location /workspace/coverage/default/22.gpio_stress_all_with_rand_reset.3773054093
Short name T412
Test name
Test status
Simulation time 120429518805 ps
CPU time 1593.54 seconds
Started Dec 24 01:10:46 PM PST 23
Finished Dec 24 01:37:31 PM PST 23
Peak memory 198224 kb
Host smart-9cb1d09c-d4b4-4212-a4fa-cb69f8086848
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=3773054093 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_stress_all_with_rand_reset.3773054093
Directory /workspace/22.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/23.gpio_alert_test.2756414268
Short name T642
Test name
Test status
Simulation time 40061651 ps
CPU time 0.57 seconds
Started Dec 24 01:10:30 PM PST 23
Finished Dec 24 01:10:40 PM PST 23
Peak memory 194296 kb
Host smart-14aca2b6-8ace-422e-96f4-1830d1beec85
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2756414268 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_alert_test.2756414268
Directory /workspace/23.gpio_alert_test/latest

Test location /workspace/coverage/default/23.gpio_dout_din_regs_random_rw.3470833626
Short name T743
Test name
Test status
Simulation time 32323895 ps
CPU time 0.76 seconds
Started Dec 24 01:10:41 PM PST 23
Finished Dec 24 01:10:50 PM PST 23
Peak memory 195276 kb
Host smart-842985d7-8ee5-453f-90a1-796faaebd484
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3470833626 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_dout_din_regs_random_rw.3470833626
Directory /workspace/23.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/23.gpio_filter_stress.854253092
Short name T879
Test name
Test status
Simulation time 1401112271 ps
CPU time 11.69 seconds
Started Dec 24 01:10:37 PM PST 23
Finished Dec 24 01:10:55 PM PST 23
Peak memory 196720 kb
Host smart-9b71bacc-e74d-4eeb-b14c-cb490dd729e2
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=854253092 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_filter_stres
s.854253092
Directory /workspace/23.gpio_filter_stress/latest

Test location /workspace/coverage/default/23.gpio_full_random.496040016
Short name T437
Test name
Test status
Simulation time 42766666 ps
CPU time 0.79 seconds
Started Dec 24 01:10:43 PM PST 23
Finished Dec 24 01:10:53 PM PST 23
Peak memory 196540 kb
Host smart-b395b99b-c11d-4c9e-8fad-15f324010bfe
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=496040016 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_full_random.496040016
Directory /workspace/23.gpio_full_random/latest

Test location /workspace/coverage/default/23.gpio_intr_rand_pgm.624655939
Short name T572
Test name
Test status
Simulation time 104564283 ps
CPU time 1.35 seconds
Started Dec 24 01:10:44 PM PST 23
Finished Dec 24 01:10:55 PM PST 23
Peak memory 197128 kb
Host smart-d64afbce-f6cd-4419-a817-3368010b28c0
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=624655939 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_intr_rand_pgm.624655939
Directory /workspace/23.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/23.gpio_intr_with_filter_rand_intr_event.57676013
Short name T691
Test name
Test status
Simulation time 528434619 ps
CPU time 3.56 seconds
Started Dec 24 01:10:36 PM PST 23
Finished Dec 24 01:10:44 PM PST 23
Peak memory 198296 kb
Host smart-843ed15c-6dd5-4785-8378-d38d75fbf515
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=57676013 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_S
EQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 23.gpio_intr_with_filter_rand_intr_event.57676013
Directory /workspace/23.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/23.gpio_rand_intr_trigger.1580666505
Short name T379
Test name
Test status
Simulation time 588948317 ps
CPU time 3.06 seconds
Started Dec 24 01:10:43 PM PST 23
Finished Dec 24 01:11:02 PM PST 23
Peak memory 197516 kb
Host smart-fc856a6e-1b5c-4bd4-ace4-21eff084b78d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1580666505 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_rand_intr_trigger
.1580666505
Directory /workspace/23.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/23.gpio_random_dout_din.3645805707
Short name T362
Test name
Test status
Simulation time 126309785 ps
CPU time 0.89 seconds
Started Dec 24 01:10:47 PM PST 23
Finished Dec 24 01:10:59 PM PST 23
Peak memory 196092 kb
Host smart-af00d549-fe33-4832-9cff-da55f9ec5e6a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3645805707 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_random_dout_din.3645805707
Directory /workspace/23.gpio_random_dout_din/latest

Test location /workspace/coverage/default/23.gpio_random_dout_din_no_pullup_pulldown.617089053
Short name T493
Test name
Test status
Simulation time 90969653 ps
CPU time 1.03 seconds
Started Dec 24 01:10:39 PM PST 23
Finished Dec 24 01:10:48 PM PST 23
Peak memory 196004 kb
Host smart-65390ee3-24b0-4b9d-8467-ce12caed9d30
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=617089053 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_random_dout_din_no_pullup
_pulldown.617089053
Directory /workspace/23.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/23.gpio_random_long_reg_writes_reg_reads.473799367
Short name T254
Test name
Test status
Simulation time 270815613 ps
CPU time 3.37 seconds
Started Dec 24 01:11:07 PM PST 23
Finished Dec 24 01:11:20 PM PST 23
Peak memory 198124 kb
Host smart-356c5c56-f2aa-4115-85e9-4510aa2f6804
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=473799367 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_ran
dom_long_reg_writes_reg_reads.473799367
Directory /workspace/23.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/23.gpio_smoke.2386834633
Short name T340
Test name
Test status
Simulation time 277094017 ps
CPU time 1.32 seconds
Started Dec 24 01:10:45 PM PST 23
Finished Dec 24 01:11:01 PM PST 23
Peak memory 198140 kb
Host smart-f672082f-af10-42f8-95b6-0391b04dc165
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2386834633 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_smoke.2386834633
Directory /workspace/23.gpio_smoke/latest

Test location /workspace/coverage/default/23.gpio_smoke_no_pullup_pulldown.2809315193
Short name T280
Test name
Test status
Simulation time 106341185 ps
CPU time 0.93 seconds
Started Dec 24 01:10:32 PM PST 23
Finished Dec 24 01:10:36 PM PST 23
Peak memory 195832 kb
Host smart-b2d519aa-bf83-4b8a-844b-b5921ecce79f
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2809315193 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_smoke_no_pullup_pulldown.2809315193
Directory /workspace/23.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/23.gpio_stress_all.1226294119
Short name T542
Test name
Test status
Simulation time 101920154785 ps
CPU time 141.95 seconds
Started Dec 24 01:10:37 PM PST 23
Finished Dec 24 01:13:05 PM PST 23
Peak memory 198164 kb
Host smart-2d10f8cf-7fff-4615-8b8c-8f7274979125
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1226294119 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.
gpio_stress_all.1226294119
Directory /workspace/23.gpio_stress_all/latest

Test location /workspace/coverage/default/23.gpio_stress_all_with_rand_reset.3119517371
Short name T665
Test name
Test status
Simulation time 139753813389 ps
CPU time 925.25 seconds
Started Dec 24 01:10:37 PM PST 23
Finished Dec 24 01:26:08 PM PST 23
Peak memory 198324 kb
Host smart-db8a0d22-3fe7-48d4-a339-14b55b29aeaa
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=3119517371 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_stress_all_with_rand_reset.3119517371
Directory /workspace/23.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/24.gpio_alert_test.3197049208
Short name T612
Test name
Test status
Simulation time 12466670 ps
CPU time 0.56 seconds
Started Dec 24 01:10:37 PM PST 23
Finished Dec 24 01:10:43 PM PST 23
Peak memory 194044 kb
Host smart-867bd05c-1b0d-40b7-93e7-fa4af6c56336
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3197049208 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_alert_test.3197049208
Directory /workspace/24.gpio_alert_test/latest

Test location /workspace/coverage/default/24.gpio_dout_din_regs_random_rw.2547628137
Short name T423
Test name
Test status
Simulation time 34789815 ps
CPU time 0.89 seconds
Started Dec 24 01:10:40 PM PST 23
Finished Dec 24 01:10:48 PM PST 23
Peak memory 195788 kb
Host smart-3f13b9ad-777a-4e1d-9c05-a8109f8740da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2547628137 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_dout_din_regs_random_rw.2547628137
Directory /workspace/24.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/24.gpio_filter_stress.2719414704
Short name T451
Test name
Test status
Simulation time 528679078 ps
CPU time 27.4 seconds
Started Dec 24 01:10:50 PM PST 23
Finished Dec 24 01:11:27 PM PST 23
Peak memory 197100 kb
Host smart-8d43275a-ac10-4744-a6ca-99503935fd2e
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2719414704 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_filter_stre
ss.2719414704
Directory /workspace/24.gpio_filter_stress/latest

Test location /workspace/coverage/default/24.gpio_full_random.1634972780
Short name T816
Test name
Test status
Simulation time 70309467 ps
CPU time 0.7 seconds
Started Dec 24 01:10:33 PM PST 23
Finished Dec 24 01:10:37 PM PST 23
Peak memory 193884 kb
Host smart-dde05ddb-930b-4e09-9465-f9039896b335
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1634972780 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_full_random.1634972780
Directory /workspace/24.gpio_full_random/latest

Test location /workspace/coverage/default/24.gpio_intr_rand_pgm.1590148835
Short name T229
Test name
Test status
Simulation time 34907499 ps
CPU time 1.03 seconds
Started Dec 24 01:10:25 PM PST 23
Finished Dec 24 01:10:29 PM PST 23
Peak memory 196608 kb
Host smart-86930bd0-8a33-47f4-a8b0-d91086e4d17a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1590148835 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_intr_rand_pgm.1590148835
Directory /workspace/24.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/24.gpio_intr_with_filter_rand_intr_event.538994293
Short name T735
Test name
Test status
Simulation time 65646740 ps
CPU time 2.52 seconds
Started Dec 24 01:10:30 PM PST 23
Finished Dec 24 01:10:36 PM PST 23
Peak memory 198100 kb
Host smart-ef15e53f-0a13-4ed1-a755-709ee45284bc
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=538994293 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 24.gpio_intr_with_filter_rand_intr_event.538994293
Directory /workspace/24.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/24.gpio_rand_intr_trigger.1395954545
Short name T745
Test name
Test status
Simulation time 417382925 ps
CPU time 2.86 seconds
Started Dec 24 01:10:33 PM PST 23
Finished Dec 24 01:10:40 PM PST 23
Peak memory 198164 kb
Host smart-47040c76-34de-42e2-baae-b48c2425573a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1395954545 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_rand_intr_trigger
.1395954545
Directory /workspace/24.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/24.gpio_random_dout_din.4197385434
Short name T828
Test name
Test status
Simulation time 100365689 ps
CPU time 0.8 seconds
Started Dec 24 01:10:55 PM PST 23
Finished Dec 24 01:11:07 PM PST 23
Peak memory 196628 kb
Host smart-507ce321-722a-483d-b110-b51d426a2829
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4197385434 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_random_dout_din.4197385434
Directory /workspace/24.gpio_random_dout_din/latest

Test location /workspace/coverage/default/24.gpio_random_dout_din_no_pullup_pulldown.2978854551
Short name T797
Test name
Test status
Simulation time 55113188 ps
CPU time 1.14 seconds
Started Dec 24 01:10:34 PM PST 23
Finished Dec 24 01:10:39 PM PST 23
Peak memory 196768 kb
Host smart-4816ad78-d129-465c-85e1-098f3cee5c75
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2978854551 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_random_dout_din_no_pullu
p_pulldown.2978854551
Directory /workspace/24.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/24.gpio_random_long_reg_writes_reg_reads.3707683762
Short name T475
Test name
Test status
Simulation time 231838759 ps
CPU time 1.97 seconds
Started Dec 24 01:10:26 PM PST 23
Finished Dec 24 01:10:30 PM PST 23
Peak memory 198088 kb
Host smart-6a5daadd-d8c2-41d0-bc07-a98c370bcb42
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3707683762 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_ra
ndom_long_reg_writes_reg_reads.3707683762
Directory /workspace/24.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/24.gpio_smoke.2615094307
Short name T710
Test name
Test status
Simulation time 121549109 ps
CPU time 1.22 seconds
Started Dec 24 01:10:37 PM PST 23
Finished Dec 24 01:10:44 PM PST 23
Peak memory 195820 kb
Host smart-14a9e158-0a78-450c-884f-d67bb2706b2a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2615094307 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_smoke.2615094307
Directory /workspace/24.gpio_smoke/latest

Test location /workspace/coverage/default/24.gpio_smoke_no_pullup_pulldown.232295463
Short name T428
Test name
Test status
Simulation time 209942292 ps
CPU time 1.34 seconds
Started Dec 24 01:10:41 PM PST 23
Finished Dec 24 01:10:50 PM PST 23
Peak memory 195664 kb
Host smart-4cb239b3-c21c-4c06-9c1e-a38c9fc9146a
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=232295463 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_smoke_no_pullup_pulldown.232295463
Directory /workspace/24.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/24.gpio_stress_all.637572594
Short name T298
Test name
Test status
Simulation time 9809940128 ps
CPU time 135.66 seconds
Started Dec 24 01:10:37 PM PST 23
Finished Dec 24 01:12:58 PM PST 23
Peak memory 198220 kb
Host smart-292379c9-c9a5-4cb1-a2e1-b750035546f8
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=637572594 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.g
pio_stress_all.637572594
Directory /workspace/24.gpio_stress_all/latest

Test location /workspace/coverage/default/24.gpio_stress_all_with_rand_reset.3842164603
Short name T704
Test name
Test status
Simulation time 60898670808 ps
CPU time 689.23 seconds
Started Dec 24 01:10:37 PM PST 23
Finished Dec 24 01:22:12 PM PST 23
Peak memory 198288 kb
Host smart-d706d06f-7549-4b0f-9394-50a674a98039
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=3842164603 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_stress_all_with_rand_reset.3842164603
Directory /workspace/24.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/25.gpio_alert_test.2590773261
Short name T339
Test name
Test status
Simulation time 16745154 ps
CPU time 0.58 seconds
Started Dec 24 01:10:42 PM PST 23
Finished Dec 24 01:10:51 PM PST 23
Peak memory 194672 kb
Host smart-a9a0cb77-585c-48bb-a104-bd2f9a729e93
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2590773261 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_alert_test.2590773261
Directory /workspace/25.gpio_alert_test/latest

Test location /workspace/coverage/default/25.gpio_dout_din_regs_random_rw.1741764160
Short name T680
Test name
Test status
Simulation time 41696537 ps
CPU time 0.67 seconds
Started Dec 24 01:10:33 PM PST 23
Finished Dec 24 01:10:37 PM PST 23
Peak memory 194240 kb
Host smart-12471d36-b241-4d90-a27f-a8d9adf86bd1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1741764160 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_dout_din_regs_random_rw.1741764160
Directory /workspace/25.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/25.gpio_filter_stress.1466513391
Short name T660
Test name
Test status
Simulation time 174715830 ps
CPU time 8.74 seconds
Started Dec 24 01:10:30 PM PST 23
Finished Dec 24 01:10:42 PM PST 23
Peak memory 196876 kb
Host smart-68b982cb-4eae-4aae-b0b9-9848c3bf32af
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1466513391 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_filter_stre
ss.1466513391
Directory /workspace/25.gpio_filter_stress/latest

Test location /workspace/coverage/default/25.gpio_full_random.3595761548
Short name T590
Test name
Test status
Simulation time 138025057 ps
CPU time 1.01 seconds
Started Dec 24 01:10:52 PM PST 23
Finished Dec 24 01:11:03 PM PST 23
Peak memory 198056 kb
Host smart-140f33cd-2a5d-459e-8b2a-76849a88ed2c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3595761548 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_full_random.3595761548
Directory /workspace/25.gpio_full_random/latest

Test location /workspace/coverage/default/25.gpio_intr_rand_pgm.1400433324
Short name T335
Test name
Test status
Simulation time 605431588 ps
CPU time 1.18 seconds
Started Dec 24 01:10:37 PM PST 23
Finished Dec 24 01:10:45 PM PST 23
Peak memory 196168 kb
Host smart-eb7ecbdb-273e-4833-8388-72998cee525d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1400433324 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_intr_rand_pgm.1400433324
Directory /workspace/25.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/25.gpio_intr_with_filter_rand_intr_event.2988183671
Short name T877
Test name
Test status
Simulation time 64584901 ps
CPU time 2.58 seconds
Started Dec 24 01:10:35 PM PST 23
Finished Dec 24 01:10:42 PM PST 23
Peak memory 198164 kb
Host smart-6ef52224-c78e-4dcf-aa12-4be33ffad65a
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2988183671 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 25.gpio_intr_with_filter_rand_intr_event.2988183671
Directory /workspace/25.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/25.gpio_rand_intr_trigger.1107344475
Short name T469
Test name
Test status
Simulation time 46662243 ps
CPU time 1.18 seconds
Started Dec 24 01:10:39 PM PST 23
Finished Dec 24 01:10:47 PM PST 23
Peak memory 196428 kb
Host smart-0c7577b2-2e21-44a8-9712-f4506d5c2146
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1107344475 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_rand_intr_trigger
.1107344475
Directory /workspace/25.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/25.gpio_random_dout_din.3683980220
Short name T806
Test name
Test status
Simulation time 161285082 ps
CPU time 0.97 seconds
Started Dec 24 01:10:33 PM PST 23
Finished Dec 24 01:10:38 PM PST 23
Peak memory 195900 kb
Host smart-b3fbb0fc-6b7c-4bdd-a318-e348839c1141
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3683980220 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_random_dout_din.3683980220
Directory /workspace/25.gpio_random_dout_din/latest

Test location /workspace/coverage/default/25.gpio_random_dout_din_no_pullup_pulldown.439259348
Short name T536
Test name
Test status
Simulation time 29806416 ps
CPU time 0.88 seconds
Started Dec 24 01:10:32 PM PST 23
Finished Dec 24 01:10:36 PM PST 23
Peak memory 196704 kb
Host smart-8dad9f6a-8d6a-4604-a980-f2c22df7ae46
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=439259348 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_random_dout_din_no_pullup
_pulldown.439259348
Directory /workspace/25.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/25.gpio_random_long_reg_writes_reg_reads.2041320863
Short name T548
Test name
Test status
Simulation time 419068825 ps
CPU time 1.63 seconds
Started Dec 24 01:10:39 PM PST 23
Finished Dec 24 01:10:47 PM PST 23
Peak memory 198036 kb
Host smart-181e502d-4d71-4a12-8213-79d1f4c3e124
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2041320863 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_ra
ndom_long_reg_writes_reg_reads.2041320863
Directory /workspace/25.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/25.gpio_smoke.347430950
Short name T217
Test name
Test status
Simulation time 329891126 ps
CPU time 1.36 seconds
Started Dec 24 01:10:39 PM PST 23
Finished Dec 24 01:10:47 PM PST 23
Peak memory 196884 kb
Host smart-25e5c700-34b4-45a5-9a6d-5abdf56cdf8b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=347430950 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_smoke.347430950
Directory /workspace/25.gpio_smoke/latest

Test location /workspace/coverage/default/25.gpio_smoke_no_pullup_pulldown.1109190551
Short name T811
Test name
Test status
Simulation time 112097656 ps
CPU time 0.86 seconds
Started Dec 24 01:10:43 PM PST 23
Finished Dec 24 01:10:53 PM PST 23
Peak memory 195288 kb
Host smart-3d01a11d-80cd-4996-bd90-7a2d15fb189a
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1109190551 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_smoke_no_pullup_pulldown.1109190551
Directory /workspace/25.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/25.gpio_stress_all.2895019469
Short name T327
Test name
Test status
Simulation time 12435634441 ps
CPU time 180.82 seconds
Started Dec 24 01:10:58 PM PST 23
Finished Dec 24 01:14:11 PM PST 23
Peak memory 198152 kb
Host smart-9d6e0abd-4b40-4b3e-b3ed-0682f079bc28
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2895019469 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.
gpio_stress_all.2895019469
Directory /workspace/25.gpio_stress_all/latest

Test location /workspace/coverage/default/25.gpio_stress_all_with_rand_reset.1397124138
Short name T834
Test name
Test status
Simulation time 301287018271 ps
CPU time 829.18 seconds
Started Dec 24 01:10:42 PM PST 23
Finished Dec 24 01:24:40 PM PST 23
Peak memory 198408 kb
Host smart-62d35bf3-2248-4127-b025-3a9bf2927c10
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=1397124138 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_stress_all_with_rand_reset.1397124138
Directory /workspace/25.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/26.gpio_alert_test.2965111911
Short name T681
Test name
Test status
Simulation time 19846623 ps
CPU time 0.55 seconds
Started Dec 24 01:10:55 PM PST 23
Finished Dec 24 01:11:07 PM PST 23
Peak memory 194080 kb
Host smart-c5a25d14-1768-4971-9a28-f5bdff44568b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2965111911 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_alert_test.2965111911
Directory /workspace/26.gpio_alert_test/latest

Test location /workspace/coverage/default/26.gpio_dout_din_regs_random_rw.3037424109
Short name T885
Test name
Test status
Simulation time 172741872 ps
CPU time 0.72 seconds
Started Dec 24 01:10:59 PM PST 23
Finished Dec 24 01:11:13 PM PST 23
Peak memory 196084 kb
Host smart-770d568a-a3e2-4dc9-9764-9f4e846e1fc5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3037424109 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_dout_din_regs_random_rw.3037424109
Directory /workspace/26.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/26.gpio_filter_stress.1500962540
Short name T697
Test name
Test status
Simulation time 1832624106 ps
CPU time 22.4 seconds
Started Dec 24 01:10:34 PM PST 23
Finished Dec 24 01:11:01 PM PST 23
Peak memory 198144 kb
Host smart-d9145925-3f6c-4c58-81de-f3247897590d
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1500962540 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_filter_stre
ss.1500962540
Directory /workspace/26.gpio_filter_stress/latest

Test location /workspace/coverage/default/26.gpio_intr_rand_pgm.2175773643
Short name T450
Test name
Test status
Simulation time 21261439 ps
CPU time 0.72 seconds
Started Dec 24 01:10:37 PM PST 23
Finished Dec 24 01:10:43 PM PST 23
Peak memory 195400 kb
Host smart-b559c0ea-cc91-4613-9433-f5fb9c0c49e3
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2175773643 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_intr_rand_pgm.2175773643
Directory /workspace/26.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/26.gpio_intr_with_filter_rand_intr_event.46953784
Short name T826
Test name
Test status
Simulation time 93608355 ps
CPU time 3.66 seconds
Started Dec 24 01:10:40 PM PST 23
Finished Dec 24 01:10:51 PM PST 23
Peak memory 198212 kb
Host smart-6f9570d6-11e3-4131-a3aa-70cfe958507c
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=46953784 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_S
EQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 26.gpio_intr_with_filter_rand_intr_event.46953784
Directory /workspace/26.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/26.gpio_rand_intr_trigger.304715741
Short name T431
Test name
Test status
Simulation time 297941200 ps
CPU time 2.84 seconds
Started Dec 24 01:10:53 PM PST 23
Finished Dec 24 01:11:07 PM PST 23
Peak memory 197372 kb
Host smart-cc939d8f-5871-4fcd-918e-62dd5e7d3df8
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=304715741 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_rand_intr_trigger.
304715741
Directory /workspace/26.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/26.gpio_random_dout_din.3428473135
Short name T233
Test name
Test status
Simulation time 37442249 ps
CPU time 0.76 seconds
Started Dec 24 01:10:48 PM PST 23
Finished Dec 24 01:10:59 PM PST 23
Peak memory 196256 kb
Host smart-0eff7c46-e9bc-4911-a84c-e56d96879695
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3428473135 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_random_dout_din.3428473135
Directory /workspace/26.gpio_random_dout_din/latest

Test location /workspace/coverage/default/26.gpio_random_dout_din_no_pullup_pulldown.3468988220
Short name T628
Test name
Test status
Simulation time 17223499 ps
CPU time 0.68 seconds
Started Dec 24 01:10:40 PM PST 23
Finished Dec 24 01:10:47 PM PST 23
Peak memory 195388 kb
Host smart-38ae7953-299c-4d11-ad8f-42c86e84fa60
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3468988220 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_random_dout_din_no_pullu
p_pulldown.3468988220
Directory /workspace/26.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/26.gpio_random_long_reg_writes_reg_reads.422075019
Short name T235
Test name
Test status
Simulation time 90745053 ps
CPU time 1.69 seconds
Started Dec 24 01:10:40 PM PST 23
Finished Dec 24 01:10:49 PM PST 23
Peak memory 198096 kb
Host smart-49a81ee3-1032-445a-a278-cb79ef36d915
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=422075019 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_ran
dom_long_reg_writes_reg_reads.422075019
Directory /workspace/26.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/26.gpio_smoke.2170837963
Short name T65
Test name
Test status
Simulation time 168739331 ps
CPU time 1.42 seconds
Started Dec 24 01:10:32 PM PST 23
Finished Dec 24 01:10:36 PM PST 23
Peak memory 196540 kb
Host smart-ad87dc63-7f92-4953-b7e7-a8a0209f108b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2170837963 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_smoke.2170837963
Directory /workspace/26.gpio_smoke/latest

Test location /workspace/coverage/default/26.gpio_smoke_no_pullup_pulldown.1838793546
Short name T63
Test name
Test status
Simulation time 50927201 ps
CPU time 1.37 seconds
Started Dec 24 01:10:50 PM PST 23
Finished Dec 24 01:11:02 PM PST 23
Peak memory 195636 kb
Host smart-8d51cd69-365c-4f87-8e58-aa1888b94d0a
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1838793546 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_smoke_no_pullup_pulldown.1838793546
Directory /workspace/26.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/26.gpio_stress_all.3858106733
Short name T269
Test name
Test status
Simulation time 1874428494 ps
CPU time 51.45 seconds
Started Dec 24 01:10:43 PM PST 23
Finished Dec 24 01:11:44 PM PST 23
Peak memory 198108 kb
Host smart-e87c6072-aae5-4a18-8890-21175d44e258
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3858106733 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.
gpio_stress_all.3858106733
Directory /workspace/26.gpio_stress_all/latest

Test location /workspace/coverage/default/26.gpio_stress_all_with_rand_reset.3530296813
Short name T698
Test name
Test status
Simulation time 244965032501 ps
CPU time 1613.67 seconds
Started Dec 24 01:10:31 PM PST 23
Finished Dec 24 01:37:28 PM PST 23
Peak memory 198384 kb
Host smart-17369f7f-50db-4a06-8ef1-4b7e875fe32e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=3530296813 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_stress_all_with_rand_reset.3530296813
Directory /workspace/26.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/27.gpio_alert_test.802779114
Short name T432
Test name
Test status
Simulation time 14151963 ps
CPU time 0.6 seconds
Started Dec 24 01:10:39 PM PST 23
Finished Dec 24 01:10:46 PM PST 23
Peak memory 194068 kb
Host smart-6487ccf0-d65a-4d22-a0e8-797dcf27dd0a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=802779114 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_alert_test.802779114
Directory /workspace/27.gpio_alert_test/latest

Test location /workspace/coverage/default/27.gpio_dout_din_regs_random_rw.1162075201
Short name T872
Test name
Test status
Simulation time 70798877 ps
CPU time 0.82 seconds
Started Dec 24 01:10:43 PM PST 23
Finished Dec 24 01:10:54 PM PST 23
Peak memory 195424 kb
Host smart-96664725-f046-427e-9c98-8af5eca90640
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1162075201 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_dout_din_regs_random_rw.1162075201
Directory /workspace/27.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/27.gpio_filter_stress.4235044971
Short name T306
Test name
Test status
Simulation time 689031269 ps
CPU time 20.85 seconds
Started Dec 24 01:10:40 PM PST 23
Finished Dec 24 01:11:16 PM PST 23
Peak memory 197336 kb
Host smart-c1c6279a-2325-468f-bb0f-b6be430ab270
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4235044971 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_filter_stre
ss.4235044971
Directory /workspace/27.gpio_filter_stress/latest

Test location /workspace/coverage/default/27.gpio_full_random.3270907637
Short name T601
Test name
Test status
Simulation time 344743674 ps
CPU time 0.94 seconds
Started Dec 24 01:10:45 PM PST 23
Finished Dec 24 01:10:57 PM PST 23
Peak memory 197984 kb
Host smart-78985c8e-4cc6-4af2-8ec3-27ed4635d9ca
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3270907637 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_full_random.3270907637
Directory /workspace/27.gpio_full_random/latest

Test location /workspace/coverage/default/27.gpio_intr_rand_pgm.3873536197
Short name T410
Test name
Test status
Simulation time 196977155 ps
CPU time 1.41 seconds
Started Dec 24 01:10:38 PM PST 23
Finished Dec 24 01:10:45 PM PST 23
Peak memory 197052 kb
Host smart-f2ec834e-5a72-4a3c-b8a4-6cccec8aa679
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3873536197 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_intr_rand_pgm.3873536197
Directory /workspace/27.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/27.gpio_intr_with_filter_rand_intr_event.1031114122
Short name T791
Test name
Test status
Simulation time 107804285 ps
CPU time 2.31 seconds
Started Dec 24 01:10:55 PM PST 23
Finished Dec 24 01:11:08 PM PST 23
Peak memory 198124 kb
Host smart-544911c1-9021-41bf-9b2e-fe17d3775372
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1031114122 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 27.gpio_intr_with_filter_rand_intr_event.1031114122
Directory /workspace/27.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/27.gpio_rand_intr_trigger.1653798941
Short name T473
Test name
Test status
Simulation time 86060728 ps
CPU time 1.74 seconds
Started Dec 24 01:11:05 PM PST 23
Finished Dec 24 01:11:17 PM PST 23
Peak memory 196752 kb
Host smart-828491da-3d29-4131-95e4-0c4c57ed186e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1653798941 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_rand_intr_trigger
.1653798941
Directory /workspace/27.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/27.gpio_random_dout_din.2487108914
Short name T501
Test name
Test status
Simulation time 35884530 ps
CPU time 1.26 seconds
Started Dec 24 01:10:44 PM PST 23
Finished Dec 24 01:10:54 PM PST 23
Peak memory 197256 kb
Host smart-e9891508-3308-484d-9588-c090e914a9ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2487108914 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_random_dout_din.2487108914
Directory /workspace/27.gpio_random_dout_din/latest

Test location /workspace/coverage/default/27.gpio_random_dout_din_no_pullup_pulldown.2041472342
Short name T547
Test name
Test status
Simulation time 90615497 ps
CPU time 0.87 seconds
Started Dec 24 01:10:36 PM PST 23
Finished Dec 24 01:10:43 PM PST 23
Peak memory 196976 kb
Host smart-d6601abc-e2cd-40c0-8a89-8a6c0f346e85
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2041472342 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_random_dout_din_no_pullu
p_pulldown.2041472342
Directory /workspace/27.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/27.gpio_random_long_reg_writes_reg_reads.2843769098
Short name T734
Test name
Test status
Simulation time 117107354 ps
CPU time 1.57 seconds
Started Dec 24 01:10:41 PM PST 23
Finished Dec 24 01:10:50 PM PST 23
Peak memory 197992 kb
Host smart-8a73e414-fe36-4ccc-afd0-486dc749686a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2843769098 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_ra
ndom_long_reg_writes_reg_reads.2843769098
Directory /workspace/27.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/27.gpio_smoke.2041679435
Short name T241
Test name
Test status
Simulation time 38598485 ps
CPU time 1.09 seconds
Started Dec 24 01:10:56 PM PST 23
Finished Dec 24 01:11:09 PM PST 23
Peak memory 195836 kb
Host smart-cdb3ca58-9319-416c-a90f-66a1f1f1d239
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2041679435 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_smoke.2041679435
Directory /workspace/27.gpio_smoke/latest

Test location /workspace/coverage/default/27.gpio_smoke_no_pullup_pulldown.883257879
Short name T276
Test name
Test status
Simulation time 339541610 ps
CPU time 1.34 seconds
Started Dec 24 01:10:42 PM PST 23
Finished Dec 24 01:10:51 PM PST 23
Peak memory 195768 kb
Host smart-abffd342-14f9-483e-8f94-21cb0913be27
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=883257879 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_smoke_no_pullup_pulldown.883257879
Directory /workspace/27.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/27.gpio_stress_all.1446316862
Short name T867
Test name
Test status
Simulation time 57768163055 ps
CPU time 144.34 seconds
Started Dec 24 01:11:03 PM PST 23
Finished Dec 24 01:13:39 PM PST 23
Peak memory 198144 kb
Host smart-c28ff707-5ca2-4790-9ee0-431ed621b62e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1446316862 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.
gpio_stress_all.1446316862
Directory /workspace/27.gpio_stress_all/latest

Test location /workspace/coverage/default/27.gpio_stress_all_with_rand_reset.1996727951
Short name T70
Test name
Test status
Simulation time 81364843195 ps
CPU time 1940.96 seconds
Started Dec 24 01:10:34 PM PST 23
Finished Dec 24 01:42:59 PM PST 23
Peak memory 198304 kb
Host smart-5e3e83d2-b25b-4200-a1ba-7ce23b2c33f0
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=1996727951 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_stress_all_with_rand_reset.1996727951
Directory /workspace/27.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/28.gpio_alert_test.768002398
Short name T553
Test name
Test status
Simulation time 14207838 ps
CPU time 0.55 seconds
Started Dec 24 01:10:45 PM PST 23
Finished Dec 24 01:10:56 PM PST 23
Peak memory 194056 kb
Host smart-eb812e19-6fc2-479d-ac30-258963e6c453
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=768002398 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_alert_test.768002398
Directory /workspace/28.gpio_alert_test/latest

Test location /workspace/coverage/default/28.gpio_dout_din_regs_random_rw.487076350
Short name T325
Test name
Test status
Simulation time 117202768 ps
CPU time 0.74 seconds
Started Dec 24 01:10:42 PM PST 23
Finished Dec 24 01:10:52 PM PST 23
Peak memory 195260 kb
Host smart-b1c4a7da-559a-40b0-9226-eab35de59af1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=487076350 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_dout_din_regs_random_rw.487076350
Directory /workspace/28.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/28.gpio_filter_stress.57469357
Short name T512
Test name
Test status
Simulation time 489408348 ps
CPU time 17.02 seconds
Started Dec 24 01:10:44 PM PST 23
Finished Dec 24 01:11:11 PM PST 23
Peak memory 197124 kb
Host smart-91c5cdda-d5e9-484f-9f6f-0639d6aa9df2
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=57469357 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter_
stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_filter_stress
.57469357
Directory /workspace/28.gpio_filter_stress/latest

Test location /workspace/coverage/default/28.gpio_full_random.2892426995
Short name T540
Test name
Test status
Simulation time 70366259 ps
CPU time 0.86 seconds
Started Dec 24 01:10:43 PM PST 23
Finished Dec 24 01:10:53 PM PST 23
Peak memory 196224 kb
Host smart-72753445-36e6-4ad7-8ad6-99b3afc94117
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2892426995 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_full_random.2892426995
Directory /workspace/28.gpio_full_random/latest

Test location /workspace/coverage/default/28.gpio_intr_rand_pgm.3123906437
Short name T738
Test name
Test status
Simulation time 49745926 ps
CPU time 0.98 seconds
Started Dec 24 01:10:35 PM PST 23
Finished Dec 24 01:10:40 PM PST 23
Peak memory 195976 kb
Host smart-3230ca75-db50-4272-b40f-92190f61ed89
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3123906437 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_intr_rand_pgm.3123906437
Directory /workspace/28.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/28.gpio_intr_with_filter_rand_intr_event.310171848
Short name T110
Test name
Test status
Simulation time 319770286 ps
CPU time 3.85 seconds
Started Dec 24 01:11:02 PM PST 23
Finished Dec 24 01:11:17 PM PST 23
Peak memory 198244 kb
Host smart-1a6edce4-d4c7-4549-981a-642d53c2f687
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=310171848 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 28.gpio_intr_with_filter_rand_intr_event.310171848
Directory /workspace/28.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/28.gpio_rand_intr_trigger.1954337484
Short name T621
Test name
Test status
Simulation time 269759052 ps
CPU time 1.58 seconds
Started Dec 24 01:10:40 PM PST 23
Finished Dec 24 01:10:49 PM PST 23
Peak memory 196972 kb
Host smart-5cf8553e-91a6-4286-8493-384f96ed37e7
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1954337484 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_rand_intr_trigger
.1954337484
Directory /workspace/28.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/28.gpio_random_dout_din.3355621024
Short name T586
Test name
Test status
Simulation time 104120231 ps
CPU time 1.07 seconds
Started Dec 24 01:10:32 PM PST 23
Finished Dec 24 01:10:36 PM PST 23
Peak memory 196872 kb
Host smart-097bc9a6-c56d-4f33-acc2-b11f33179a70
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3355621024 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_random_dout_din.3355621024
Directory /workspace/28.gpio_random_dout_din/latest

Test location /workspace/coverage/default/28.gpio_random_dout_din_no_pullup_pulldown.1999004445
Short name T418
Test name
Test status
Simulation time 29724630 ps
CPU time 0.66 seconds
Started Dec 24 01:10:53 PM PST 23
Finished Dec 24 01:11:06 PM PST 23
Peak memory 194924 kb
Host smart-53df49fe-1a5c-435c-9796-883329d93c75
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1999004445 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_random_dout_din_no_pullu
p_pulldown.1999004445
Directory /workspace/28.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/28.gpio_random_long_reg_writes_reg_reads.1568371981
Short name T252
Test name
Test status
Simulation time 701352413 ps
CPU time 5.09 seconds
Started Dec 24 01:10:47 PM PST 23
Finished Dec 24 01:11:05 PM PST 23
Peak memory 198136 kb
Host smart-9a1f89ab-bf1b-4dde-b377-ab6982add861
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1568371981 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_ra
ndom_long_reg_writes_reg_reads.1568371981
Directory /workspace/28.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/28.gpio_smoke.328528709
Short name T799
Test name
Test status
Simulation time 188523100 ps
CPU time 1.34 seconds
Started Dec 24 01:10:45 PM PST 23
Finished Dec 24 01:10:57 PM PST 23
Peak memory 196944 kb
Host smart-3e562fee-7415-4c4c-be93-3c4d39f39b1c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=328528709 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_smoke.328528709
Directory /workspace/28.gpio_smoke/latest

Test location /workspace/coverage/default/28.gpio_smoke_no_pullup_pulldown.184596592
Short name T226
Test name
Test status
Simulation time 142135918 ps
CPU time 1.14 seconds
Started Dec 24 01:10:40 PM PST 23
Finished Dec 24 01:10:49 PM PST 23
Peak memory 196456 kb
Host smart-f49754af-46e7-4f61-8f8d-d86e6d8aa65f
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=184596592 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_smoke_no_pullup_pulldown.184596592
Directory /workspace/28.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/28.gpio_stress_all.2227814252
Short name T343
Test name
Test status
Simulation time 31688077154 ps
CPU time 190.83 seconds
Started Dec 24 01:10:39 PM PST 23
Finished Dec 24 01:13:56 PM PST 23
Peak memory 198268 kb
Host smart-851dd085-c0f8-4a0c-b2b4-510dba9dc10d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2227814252 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.
gpio_stress_all.2227814252
Directory /workspace/28.gpio_stress_all/latest

Test location /workspace/coverage/default/28.gpio_stress_all_with_rand_reset.3870677542
Short name T876
Test name
Test status
Simulation time 28648940909 ps
CPU time 469.69 seconds
Started Dec 24 01:10:41 PM PST 23
Finished Dec 24 01:18:38 PM PST 23
Peak memory 198356 kb
Host smart-4092f86e-01d9-4b16-9e45-10b4ca7a0b5e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=3870677542 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_stress_all_with_rand_reset.3870677542
Directory /workspace/28.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/29.gpio_alert_test.2094414517
Short name T411
Test name
Test status
Simulation time 13651382 ps
CPU time 0.6 seconds
Started Dec 24 01:10:43 PM PST 23
Finished Dec 24 01:10:53 PM PST 23
Peak memory 194028 kb
Host smart-dcb665aa-dcd9-4151-b030-affde6674b53
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2094414517 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_alert_test.2094414517
Directory /workspace/29.gpio_alert_test/latest

Test location /workspace/coverage/default/29.gpio_dout_din_regs_random_rw.3302634531
Short name T618
Test name
Test status
Simulation time 93438830 ps
CPU time 0.83 seconds
Started Dec 24 01:10:35 PM PST 23
Finished Dec 24 01:10:40 PM PST 23
Peak memory 196588 kb
Host smart-85587dac-5a0a-4768-81cb-af91c1792957
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3302634531 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_dout_din_regs_random_rw.3302634531
Directory /workspace/29.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/29.gpio_filter_stress.909677817
Short name T607
Test name
Test status
Simulation time 1334110735 ps
CPU time 27.02 seconds
Started Dec 24 01:10:42 PM PST 23
Finished Dec 24 01:11:18 PM PST 23
Peak memory 198080 kb
Host smart-55ae1f12-4d1f-4c3d-9d91-79a32235abf8
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=909677817 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_filter_stres
s.909677817
Directory /workspace/29.gpio_filter_stress/latest

Test location /workspace/coverage/default/29.gpio_full_random.1150028177
Short name T314
Test name
Test status
Simulation time 77329749 ps
CPU time 0.68 seconds
Started Dec 24 01:10:41 PM PST 23
Finished Dec 24 01:10:49 PM PST 23
Peak memory 194816 kb
Host smart-9f6c30d2-3618-4cd4-a10f-1bca15aac6c6
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1150028177 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_full_random.1150028177
Directory /workspace/29.gpio_full_random/latest

Test location /workspace/coverage/default/29.gpio_intr_rand_pgm.2165853306
Short name T866
Test name
Test status
Simulation time 59189078 ps
CPU time 0.96 seconds
Started Dec 24 01:11:03 PM PST 23
Finished Dec 24 01:11:16 PM PST 23
Peak memory 196896 kb
Host smart-4c9da9da-132f-4456-aa3b-c982b382b3ed
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2165853306 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_intr_rand_pgm.2165853306
Directory /workspace/29.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/29.gpio_intr_with_filter_rand_intr_event.1896012724
Short name T492
Test name
Test status
Simulation time 137441762 ps
CPU time 1.56 seconds
Started Dec 24 01:10:30 PM PST 23
Finished Dec 24 01:10:34 PM PST 23
Peak memory 196428 kb
Host smart-01c1c2c5-c4f5-47c6-977a-46faf5fb81c4
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1896012724 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 29.gpio_intr_with_filter_rand_intr_event.1896012724
Directory /workspace/29.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/29.gpio_rand_intr_trigger.4063293656
Short name T861
Test name
Test status
Simulation time 104477950 ps
CPU time 2.03 seconds
Started Dec 24 01:10:42 PM PST 23
Finished Dec 24 01:10:53 PM PST 23
Peak memory 196328 kb
Host smart-a9e46ae4-8e8b-4eb2-81e4-7c974fe856f7
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4063293656 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_rand_intr_trigger
.4063293656
Directory /workspace/29.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/29.gpio_random_dout_din.1315326753
Short name T443
Test name
Test status
Simulation time 60446152 ps
CPU time 1.2 seconds
Started Dec 24 01:10:51 PM PST 23
Finished Dec 24 01:11:02 PM PST 23
Peak memory 196976 kb
Host smart-c5742e53-fa95-4b4a-a4d6-0c02d6e78231
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1315326753 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_random_dout_din.1315326753
Directory /workspace/29.gpio_random_dout_din/latest

Test location /workspace/coverage/default/29.gpio_random_dout_din_no_pullup_pulldown.2503195621
Short name T508
Test name
Test status
Simulation time 28600323 ps
CPU time 1.09 seconds
Started Dec 24 01:10:54 PM PST 23
Finished Dec 24 01:11:06 PM PST 23
Peak memory 196512 kb
Host smart-9c0fc4a0-12c1-4007-af75-77ae4ada6aa7
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2503195621 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_random_dout_din_no_pullu
p_pulldown.2503195621
Directory /workspace/29.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/29.gpio_random_long_reg_writes_reg_reads.2528333668
Short name T232
Test name
Test status
Simulation time 1122452770 ps
CPU time 3.67 seconds
Started Dec 24 01:10:31 PM PST 23
Finished Dec 24 01:10:37 PM PST 23
Peak memory 197996 kb
Host smart-2ec99266-00f7-4539-8c03-719f4311cbde
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2528333668 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_ra
ndom_long_reg_writes_reg_reads.2528333668
Directory /workspace/29.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/29.gpio_smoke.3814080010
Short name T230
Test name
Test status
Simulation time 40966962 ps
CPU time 0.66 seconds
Started Dec 24 01:10:33 PM PST 23
Finished Dec 24 01:10:37 PM PST 23
Peak memory 194112 kb
Host smart-b3ddbc7e-af00-484c-b59d-48bc8f03419d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3814080010 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_smoke.3814080010
Directory /workspace/29.gpio_smoke/latest

Test location /workspace/coverage/default/29.gpio_smoke_no_pullup_pulldown.1100443772
Short name T522
Test name
Test status
Simulation time 254045121 ps
CPU time 1.24 seconds
Started Dec 24 01:11:03 PM PST 23
Finished Dec 24 01:11:16 PM PST 23
Peak memory 196880 kb
Host smart-2bd86abe-354b-404f-aae0-5197835b85e5
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1100443772 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_smoke_no_pullup_pulldown.1100443772
Directory /workspace/29.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/29.gpio_stress_all.1925168179
Short name T870
Test name
Test status
Simulation time 24108292610 ps
CPU time 28.72 seconds
Started Dec 24 01:10:39 PM PST 23
Finished Dec 24 01:11:15 PM PST 23
Peak memory 198220 kb
Host smart-74b8ae14-5db3-4fb5-a12e-efd2dd02a9f4
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1925168179 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.
gpio_stress_all.1925168179
Directory /workspace/29.gpio_stress_all/latest

Test location /workspace/coverage/default/29.gpio_stress_all_with_rand_reset.1009920022
Short name T772
Test name
Test status
Simulation time 362204650669 ps
CPU time 1158.55 seconds
Started Dec 24 01:10:45 PM PST 23
Finished Dec 24 01:30:15 PM PST 23
Peak memory 198420 kb
Host smart-bfd6be16-7ad6-4b3c-9c05-fad4e1e85582
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=1009920022 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_stress_all_with_rand_reset.1009920022
Directory /workspace/29.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/3.gpio_alert_test.2828862996
Short name T481
Test name
Test status
Simulation time 11036975 ps
CPU time 0.61 seconds
Started Dec 24 01:10:44 PM PST 23
Finished Dec 24 01:10:54 PM PST 23
Peak memory 194048 kb
Host smart-8927fcb1-bf7f-4dd8-90c2-a5147dd6efbc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2828862996 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_alert_test.2828862996
Directory /workspace/3.gpio_alert_test/latest

Test location /workspace/coverage/default/3.gpio_dout_din_regs_random_rw.3653743233
Short name T408
Test name
Test status
Simulation time 72348720 ps
CPU time 0.9 seconds
Started Dec 24 01:10:29 PM PST 23
Finished Dec 24 01:10:33 PM PST 23
Peak memory 196604 kb
Host smart-7587cbb4-eef4-4336-9186-f07676c3c6c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3653743233 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_dout_din_regs_random_rw.3653743233
Directory /workspace/3.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/3.gpio_filter_stress.3397521566
Short name T676
Test name
Test status
Simulation time 459439175 ps
CPU time 15.53 seconds
Started Dec 24 01:10:20 PM PST 23
Finished Dec 24 01:10:39 PM PST 23
Peak memory 197120 kb
Host smart-7602d80e-2e52-4dd6-8c2f-514f8e654068
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3397521566 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_filter_stres
s.3397521566
Directory /workspace/3.gpio_filter_stress/latest

Test location /workspace/coverage/default/3.gpio_full_random.3997271816
Short name T249
Test name
Test status
Simulation time 160977267 ps
CPU time 0.75 seconds
Started Dec 24 01:10:18 PM PST 23
Finished Dec 24 01:10:23 PM PST 23
Peak memory 194632 kb
Host smart-8f4007c7-e664-4725-8465-6ff337801a46
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3997271816 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_full_random.3997271816
Directory /workspace/3.gpio_full_random/latest

Test location /workspace/coverage/default/3.gpio_intr_rand_pgm.2763940155
Short name T629
Test name
Test status
Simulation time 224418928 ps
CPU time 1.02 seconds
Started Dec 24 01:10:36 PM PST 23
Finished Dec 24 01:10:43 PM PST 23
Peak memory 196824 kb
Host smart-b74f1e04-da7d-4f2c-ba4c-502bf982a9d9
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2763940155 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_intr_rand_pgm.2763940155
Directory /workspace/3.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/3.gpio_intr_with_filter_rand_intr_event.3422918683
Short name T323
Test name
Test status
Simulation time 134012655 ps
CPU time 1.53 seconds
Started Dec 24 01:10:16 PM PST 23
Finished Dec 24 01:10:22 PM PST 23
Peak memory 196912 kb
Host smart-a1ec0fc8-d776-4629-af82-f99b0fffc391
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3422918683 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 3.gpio_intr_with_filter_rand_intr_event.3422918683
Directory /workspace/3.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/3.gpio_rand_intr_trigger.1119612956
Short name T504
Test name
Test status
Simulation time 339716548 ps
CPU time 2.79 seconds
Started Dec 24 01:10:18 PM PST 23
Finished Dec 24 01:10:25 PM PST 23
Peak memory 198072 kb
Host smart-d0adab41-cb04-4ca1-b35c-7cdf98e72003
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1119612956 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_rand_intr_trigger.
1119612956
Directory /workspace/3.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/3.gpio_random_dout_din.2745883879
Short name T554
Test name
Test status
Simulation time 29269247 ps
CPU time 1.01 seconds
Started Dec 24 01:10:17 PM PST 23
Finished Dec 24 01:10:22 PM PST 23
Peak memory 195960 kb
Host smart-bf324298-8254-4a43-b88d-ab149e4b7ba9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2745883879 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_random_dout_din.2745883879
Directory /workspace/3.gpio_random_dout_din/latest

Test location /workspace/coverage/default/3.gpio_random_dout_din_no_pullup_pulldown.1201529072
Short name T546
Test name
Test status
Simulation time 165096611 ps
CPU time 1.06 seconds
Started Dec 24 01:10:05 PM PST 23
Finished Dec 24 01:10:12 PM PST 23
Peak memory 196776 kb
Host smart-10cce868-516d-4f7c-971b-a0520bc53433
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1201529072 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_random_dout_din_no_pullup
_pulldown.1201529072
Directory /workspace/3.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/3.gpio_random_long_reg_writes_reg_reads.3215576841
Short name T496
Test name
Test status
Simulation time 352664994 ps
CPU time 5.7 seconds
Started Dec 24 01:10:25 PM PST 23
Finished Dec 24 01:10:33 PM PST 23
Peak memory 198040 kb
Host smart-0cbcc70f-029a-4411-8f63-222da281e0fb
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3215576841 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_ran
dom_long_reg_writes_reg_reads.3215576841
Directory /workspace/3.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/3.gpio_sec_cm.491693675
Short name T58
Test name
Test status
Simulation time 407328446 ps
CPU time 0.93 seconds
Started Dec 24 01:10:22 PM PST 23
Finished Dec 24 01:10:27 PM PST 23
Peak memory 214676 kb
Host smart-3ae50578-23ca-4859-bddc-1a6962ea6f72
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=491693675 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_sec_cm.491693675
Directory /workspace/3.gpio_sec_cm/latest

Test location /workspace/coverage/default/3.gpio_smoke.3677927529
Short name T756
Test name
Test status
Simulation time 74215204 ps
CPU time 1.34 seconds
Started Dec 24 01:10:27 PM PST 23
Finished Dec 24 01:10:31 PM PST 23
Peak memory 196864 kb
Host smart-31c81ad0-19d0-4b4c-903b-df23f8c52559
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3677927529 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_smoke.3677927529
Directory /workspace/3.gpio_smoke/latest

Test location /workspace/coverage/default/3.gpio_smoke_no_pullup_pulldown.2391693777
Short name T257
Test name
Test status
Simulation time 58402237 ps
CPU time 1.15 seconds
Started Dec 24 01:10:20 PM PST 23
Finished Dec 24 01:10:24 PM PST 23
Peak memory 195636 kb
Host smart-e0af9fed-ab7e-4482-b446-04bcc0558945
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2391693777 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_smoke_no_pullup_pulldown.2391693777
Directory /workspace/3.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/3.gpio_stress_all.2444363894
Short name T322
Test name
Test status
Simulation time 6035966870 ps
CPU time 65.64 seconds
Started Dec 24 01:10:15 PM PST 23
Finished Dec 24 01:11:25 PM PST 23
Peak memory 198176 kb
Host smart-7422ec05-bfa9-4ad0-ad4b-637aff90c045
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2444363894 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.g
pio_stress_all.2444363894
Directory /workspace/3.gpio_stress_all/latest

Test location /workspace/coverage/default/3.gpio_stress_all_with_rand_reset.4184096277
Short name T69
Test name
Test status
Simulation time 341057743832 ps
CPU time 1098.15 seconds
Started Dec 24 01:10:25 PM PST 23
Finished Dec 24 01:28:46 PM PST 23
Peak memory 198392 kb
Host smart-dea284e3-cbd7-4527-81e6-b70ede7a4875
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=4184096277 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_stress_all_with_rand_reset.4184096277
Directory /workspace/3.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/30.gpio_alert_test.2333217249
Short name T388
Test name
Test status
Simulation time 38171922 ps
CPU time 0.64 seconds
Started Dec 24 01:10:34 PM PST 23
Finished Dec 24 01:10:39 PM PST 23
Peak memory 194152 kb
Host smart-4c62a453-66ba-4f8e-9d65-49a66ab8ab6b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2333217249 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_alert_test.2333217249
Directory /workspace/30.gpio_alert_test/latest

Test location /workspace/coverage/default/30.gpio_dout_din_regs_random_rw.1009115227
Short name T748
Test name
Test status
Simulation time 172579379 ps
CPU time 0.87 seconds
Started Dec 24 01:10:46 PM PST 23
Finished Dec 24 01:10:58 PM PST 23
Peak memory 195864 kb
Host smart-340d361e-a7c3-4867-a8a7-b444c3642a73
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1009115227 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_dout_din_regs_random_rw.1009115227
Directory /workspace/30.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/30.gpio_filter_stress.3408216029
Short name T646
Test name
Test status
Simulation time 706694770 ps
CPU time 17.96 seconds
Started Dec 24 01:10:43 PM PST 23
Finished Dec 24 01:11:10 PM PST 23
Peak memory 197096 kb
Host smart-e0df5067-35dd-4c88-a4fc-12c303963ade
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3408216029 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_filter_stre
ss.3408216029
Directory /workspace/30.gpio_filter_stress/latest

Test location /workspace/coverage/default/30.gpio_full_random.3928100780
Short name T809
Test name
Test status
Simulation time 53892505 ps
CPU time 0.89 seconds
Started Dec 24 01:10:43 PM PST 23
Finished Dec 24 01:10:53 PM PST 23
Peak memory 197244 kb
Host smart-cfe2cfa4-a626-4f97-9ceb-3ceda448d5f3
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3928100780 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_full_random.3928100780
Directory /workspace/30.gpio_full_random/latest

Test location /workspace/coverage/default/30.gpio_intr_rand_pgm.183346749
Short name T256
Test name
Test status
Simulation time 248143688 ps
CPU time 1.47 seconds
Started Dec 24 01:10:42 PM PST 23
Finished Dec 24 01:10:59 PM PST 23
Peak memory 198188 kb
Host smart-1658e095-1108-4c92-b946-a35cc8b69ab7
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=183346749 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_intr_rand_pgm.183346749
Directory /workspace/30.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/30.gpio_intr_with_filter_rand_intr_event.3619460491
Short name T358
Test name
Test status
Simulation time 123988986 ps
CPU time 1.33 seconds
Started Dec 24 01:10:40 PM PST 23
Finished Dec 24 01:10:49 PM PST 23
Peak memory 196628 kb
Host smart-1e1c99d7-77e5-4724-8cff-ede40834e46f
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3619460491 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 30.gpio_intr_with_filter_rand_intr_event.3619460491
Directory /workspace/30.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/30.gpio_rand_intr_trigger.2444215961
Short name T840
Test name
Test status
Simulation time 101150198 ps
CPU time 2.99 seconds
Started Dec 24 01:10:42 PM PST 23
Finished Dec 24 01:10:53 PM PST 23
Peak memory 197012 kb
Host smart-75d866a5-b283-4290-8e30-62021f7b50c8
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2444215961 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_rand_intr_trigger
.2444215961
Directory /workspace/30.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/30.gpio_random_dout_din.3778484824
Short name T238
Test name
Test status
Simulation time 32044299 ps
CPU time 0.82 seconds
Started Dec 24 01:10:40 PM PST 23
Finished Dec 24 01:10:47 PM PST 23
Peak memory 196432 kb
Host smart-368e0169-39c0-4ada-bb8c-c5cbaa0e6cea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3778484824 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_random_dout_din.3778484824
Directory /workspace/30.gpio_random_dout_din/latest

Test location /workspace/coverage/default/30.gpio_random_dout_din_no_pullup_pulldown.3448699145
Short name T659
Test name
Test status
Simulation time 70298987 ps
CPU time 0.95 seconds
Started Dec 24 01:10:39 PM PST 23
Finished Dec 24 01:10:47 PM PST 23
Peak memory 195900 kb
Host smart-8db08f2c-830f-427e-869b-311022eadfba
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3448699145 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_random_dout_din_no_pullu
p_pulldown.3448699145
Directory /workspace/30.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/30.gpio_random_long_reg_writes_reg_reads.3909929578
Short name T329
Test name
Test status
Simulation time 285044217 ps
CPU time 4.79 seconds
Started Dec 24 01:10:44 PM PST 23
Finished Dec 24 01:11:03 PM PST 23
Peak memory 198096 kb
Host smart-467e2aab-bfbc-4fed-a6bc-b703e58774e7
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3909929578 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_ra
ndom_long_reg_writes_reg_reads.3909929578
Directory /workspace/30.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/30.gpio_smoke.686859216
Short name T875
Test name
Test status
Simulation time 34080092 ps
CPU time 0.86 seconds
Started Dec 24 01:10:43 PM PST 23
Finished Dec 24 01:10:53 PM PST 23
Peak memory 195400 kb
Host smart-1f3facc1-815a-4fa7-abe9-0e8d37011e26
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=686859216 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_smoke.686859216
Directory /workspace/30.gpio_smoke/latest

Test location /workspace/coverage/default/30.gpio_smoke_no_pullup_pulldown.2120553010
Short name T643
Test name
Test status
Simulation time 404568305 ps
CPU time 1.28 seconds
Started Dec 24 01:10:43 PM PST 23
Finished Dec 24 01:10:53 PM PST 23
Peak memory 196964 kb
Host smart-a2f26af1-d72d-4fa8-89e6-5b1ba2b3d2af
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2120553010 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_smoke_no_pullup_pulldown.2120553010
Directory /workspace/30.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/30.gpio_stress_all.3244260695
Short name T781
Test name
Test status
Simulation time 25944815574 ps
CPU time 161.07 seconds
Started Dec 24 01:10:52 PM PST 23
Finished Dec 24 01:13:44 PM PST 23
Peak memory 198176 kb
Host smart-9fb1dbfd-5d05-4378-9bac-5871a9cd41d3
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3244260695 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.
gpio_stress_all.3244260695
Directory /workspace/30.gpio_stress_all/latest

Test location /workspace/coverage/default/30.gpio_stress_all_with_rand_reset.1776431832
Short name T668
Test name
Test status
Simulation time 195759755159 ps
CPU time 783.99 seconds
Started Dec 24 01:10:42 PM PST 23
Finished Dec 24 01:23:55 PM PST 23
Peak memory 198412 kb
Host smart-6c4b4775-fdc2-46ef-b957-dc3572be73d2
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=1776431832 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_stress_all_with_rand_reset.1776431832
Directory /workspace/30.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/31.gpio_alert_test.2840668469
Short name T555
Test name
Test status
Simulation time 15248415 ps
CPU time 0.57 seconds
Started Dec 24 01:10:55 PM PST 23
Finished Dec 24 01:11:08 PM PST 23
Peak memory 194080 kb
Host smart-4141ce76-6525-4572-89ce-9c1fca91715b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2840668469 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_alert_test.2840668469
Directory /workspace/31.gpio_alert_test/latest

Test location /workspace/coverage/default/31.gpio_dout_din_regs_random_rw.797650984
Short name T316
Test name
Test status
Simulation time 199693165 ps
CPU time 0.93 seconds
Started Dec 24 01:10:48 PM PST 23
Finished Dec 24 01:10:59 PM PST 23
Peak memory 195976 kb
Host smart-84786099-0e10-48d4-a8f5-07b8c5b23081
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=797650984 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_dout_din_regs_random_rw.797650984
Directory /workspace/31.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/31.gpio_filter_stress.2735459077
Short name T837
Test name
Test status
Simulation time 159103248 ps
CPU time 8.19 seconds
Started Dec 24 01:10:51 PM PST 23
Finished Dec 24 01:11:09 PM PST 23
Peak memory 196304 kb
Host smart-1d0ec44f-b806-43cd-912e-ba5e9612c229
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2735459077 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_filter_stre
ss.2735459077
Directory /workspace/31.gpio_filter_stress/latest

Test location /workspace/coverage/default/31.gpio_full_random.1392030161
Short name T440
Test name
Test status
Simulation time 234538331 ps
CPU time 0.85 seconds
Started Dec 24 01:10:52 PM PST 23
Finished Dec 24 01:11:03 PM PST 23
Peak memory 196532 kb
Host smart-0d217770-06cc-4a64-a203-0372efa59c9b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1392030161 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_full_random.1392030161
Directory /workspace/31.gpio_full_random/latest

Test location /workspace/coverage/default/31.gpio_intr_rand_pgm.4262363868
Short name T334
Test name
Test status
Simulation time 24167885 ps
CPU time 0.78 seconds
Started Dec 24 01:10:53 PM PST 23
Finished Dec 24 01:11:06 PM PST 23
Peak memory 195452 kb
Host smart-fac81a88-1d43-44f8-a54c-f75329156258
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4262363868 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_intr_rand_pgm.4262363868
Directory /workspace/31.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/31.gpio_intr_with_filter_rand_intr_event.1946533899
Short name T570
Test name
Test status
Simulation time 291256269 ps
CPU time 3.12 seconds
Started Dec 24 01:10:31 PM PST 23
Finished Dec 24 01:10:37 PM PST 23
Peak memory 198156 kb
Host smart-fed1811d-1a33-4255-8d68-01dd7a64b755
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1946533899 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 31.gpio_intr_with_filter_rand_intr_event.1946533899
Directory /workspace/31.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/31.gpio_rand_intr_trigger.987454732
Short name T465
Test name
Test status
Simulation time 204568415 ps
CPU time 2.08 seconds
Started Dec 24 01:10:45 PM PST 23
Finished Dec 24 01:10:58 PM PST 23
Peak memory 198216 kb
Host smart-9ff6579c-8c50-4ef0-af9c-4da977e4e30e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=987454732 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_rand_intr_trigger.
987454732
Directory /workspace/31.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/31.gpio_random_dout_din.3055288323
Short name T477
Test name
Test status
Simulation time 75025503 ps
CPU time 0.89 seconds
Started Dec 24 01:10:45 PM PST 23
Finished Dec 24 01:10:56 PM PST 23
Peak memory 196088 kb
Host smart-f683fbd1-fef2-447d-8247-f2322ec1223b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3055288323 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_random_dout_din.3055288323
Directory /workspace/31.gpio_random_dout_din/latest

Test location /workspace/coverage/default/31.gpio_random_dout_din_no_pullup_pulldown.2988157060
Short name T347
Test name
Test status
Simulation time 358586135 ps
CPU time 0.79 seconds
Started Dec 24 01:10:34 PM PST 23
Finished Dec 24 01:10:39 PM PST 23
Peak memory 195296 kb
Host smart-4911a280-9b42-4a40-9433-c6df5b5b8952
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2988157060 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_random_dout_din_no_pullu
p_pulldown.2988157060
Directory /workspace/31.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/31.gpio_random_long_reg_writes_reg_reads.2161527947
Short name T851
Test name
Test status
Simulation time 265851781 ps
CPU time 4.42 seconds
Started Dec 24 01:10:43 PM PST 23
Finished Dec 24 01:10:56 PM PST 23
Peak memory 198076 kb
Host smart-dd44ddc9-848f-4cff-b48a-426f31185957
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2161527947 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_ra
ndom_long_reg_writes_reg_reads.2161527947
Directory /workspace/31.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/31.gpio_smoke.3807749838
Short name T711
Test name
Test status
Simulation time 100688230 ps
CPU time 1.06 seconds
Started Dec 24 01:10:53 PM PST 23
Finished Dec 24 01:11:06 PM PST 23
Peak memory 195676 kb
Host smart-3a30aa9f-f3c8-4bb6-88df-44776b272021
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3807749838 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_smoke.3807749838
Directory /workspace/31.gpio_smoke/latest

Test location /workspace/coverage/default/31.gpio_smoke_no_pullup_pulldown.2288952902
Short name T705
Test name
Test status
Simulation time 33515832 ps
CPU time 0.68 seconds
Started Dec 24 01:10:54 PM PST 23
Finished Dec 24 01:11:06 PM PST 23
Peak memory 194044 kb
Host smart-c5898e6b-7844-43eb-9535-9c9ca2840a1e
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2288952902 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_smoke_no_pullup_pulldown.2288952902
Directory /workspace/31.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/31.gpio_stress_all.921243616
Short name T490
Test name
Test status
Simulation time 21175919835 ps
CPU time 148.77 seconds
Started Dec 24 01:10:49 PM PST 23
Finished Dec 24 01:13:28 PM PST 23
Peak memory 198264 kb
Host smart-8f450bfc-1341-4179-89cd-bdad7b2fac65
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=921243616 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.g
pio_stress_all.921243616
Directory /workspace/31.gpio_stress_all/latest

Test location /workspace/coverage/default/31.gpio_stress_all_with_rand_reset.318528991
Short name T650
Test name
Test status
Simulation time 75035269433 ps
CPU time 1019.95 seconds
Started Dec 24 01:10:56 PM PST 23
Finished Dec 24 01:28:08 PM PST 23
Peak memory 198428 kb
Host smart-e91a607f-7faf-472c-b85d-b1d0c0c4e1ea
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=318528991 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_stress_all_with_rand_reset.318528991
Directory /workspace/31.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/32.gpio_alert_test.2146518516
Short name T350
Test name
Test status
Simulation time 39030502 ps
CPU time 0.56 seconds
Started Dec 24 01:10:32 PM PST 23
Finished Dec 24 01:10:37 PM PST 23
Peak memory 194328 kb
Host smart-159ec711-ccfe-4d87-9de6-96eed10d2a6f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2146518516 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_alert_test.2146518516
Directory /workspace/32.gpio_alert_test/latest

Test location /workspace/coverage/default/32.gpio_dout_din_regs_random_rw.4285131631
Short name T264
Test name
Test status
Simulation time 110869985 ps
CPU time 0.73 seconds
Started Dec 24 01:10:34 PM PST 23
Finished Dec 24 01:10:39 PM PST 23
Peak memory 195272 kb
Host smart-16266399-e3df-440b-9927-61c492cf83e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4285131631 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_dout_din_regs_random_rw.4285131631
Directory /workspace/32.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/32.gpio_filter_stress.1434065169
Short name T514
Test name
Test status
Simulation time 1699015922 ps
CPU time 25.9 seconds
Started Dec 24 01:10:52 PM PST 23
Finished Dec 24 01:11:27 PM PST 23
Peak memory 198068 kb
Host smart-9adc2de3-6fe7-4189-82d3-7fd118884a1e
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1434065169 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_filter_stre
ss.1434065169
Directory /workspace/32.gpio_filter_stress/latest

Test location /workspace/coverage/default/32.gpio_full_random.331559568
Short name T815
Test name
Test status
Simulation time 311765135 ps
CPU time 0.88 seconds
Started Dec 24 01:10:49 PM PST 23
Finished Dec 24 01:11:00 PM PST 23
Peak memory 197048 kb
Host smart-e28f3712-dd6c-4a0d-875e-94f98c970581
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=331559568 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_full_random.331559568
Directory /workspace/32.gpio_full_random/latest

Test location /workspace/coverage/default/32.gpio_intr_rand_pgm.3126057389
Short name T793
Test name
Test status
Simulation time 103458640 ps
CPU time 0.98 seconds
Started Dec 24 01:10:48 PM PST 23
Finished Dec 24 01:10:59 PM PST 23
Peak memory 196952 kb
Host smart-dfc8fec5-9062-455e-856d-9f9c146bcaf4
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3126057389 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_intr_rand_pgm.3126057389
Directory /workspace/32.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/32.gpio_intr_with_filter_rand_intr_event.425010505
Short name T853
Test name
Test status
Simulation time 96640688 ps
CPU time 1.24 seconds
Started Dec 24 01:10:39 PM PST 23
Finished Dec 24 01:10:48 PM PST 23
Peak memory 198248 kb
Host smart-1de343c5-2f8e-4fa1-89bf-3d26e3a9ae20
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=425010505 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 32.gpio_intr_with_filter_rand_intr_event.425010505
Directory /workspace/32.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/32.gpio_rand_intr_trigger.2710235541
Short name T250
Test name
Test status
Simulation time 632363933 ps
CPU time 2.1 seconds
Started Dec 24 01:10:40 PM PST 23
Finished Dec 24 01:10:49 PM PST 23
Peak memory 197164 kb
Host smart-38ed24eb-a242-4d07-a621-cd99798f8cda
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2710235541 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_rand_intr_trigger
.2710235541
Directory /workspace/32.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/32.gpio_random_dout_din.165354320
Short name T225
Test name
Test status
Simulation time 99551403 ps
CPU time 0.84 seconds
Started Dec 24 01:10:35 PM PST 23
Finished Dec 24 01:10:40 PM PST 23
Peak memory 196628 kb
Host smart-7b6725f1-aaf4-434a-a13c-ef45dbdeb73e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=165354320 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_random_dout_din.165354320
Directory /workspace/32.gpio_random_dout_din/latest

Test location /workspace/coverage/default/32.gpio_random_dout_din_no_pullup_pulldown.3082653641
Short name T441
Test name
Test status
Simulation time 72491807 ps
CPU time 0.74 seconds
Started Dec 24 01:10:54 PM PST 23
Finished Dec 24 01:11:06 PM PST 23
Peak memory 196004 kb
Host smart-b8c0a546-cd89-46fa-ae4e-51bb1572750a
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3082653641 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_random_dout_din_no_pullu
p_pulldown.3082653641
Directory /workspace/32.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/32.gpio_random_long_reg_writes_reg_reads.498786995
Short name T747
Test name
Test status
Simulation time 1195230497 ps
CPU time 4.8 seconds
Started Dec 24 01:10:34 PM PST 23
Finished Dec 24 01:10:43 PM PST 23
Peak memory 198120 kb
Host smart-fdab0f87-3793-4b79-b61f-77054e79b977
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=498786995 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_ran
dom_long_reg_writes_reg_reads.498786995
Directory /workspace/32.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/32.gpio_smoke.558660894
Short name T317
Test name
Test status
Simulation time 34995707 ps
CPU time 0.83 seconds
Started Dec 24 01:10:48 PM PST 23
Finished Dec 24 01:10:59 PM PST 23
Peak memory 196152 kb
Host smart-4ae322a0-e9e4-4c2b-9b32-610cd9cf2089
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=558660894 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_smoke.558660894
Directory /workspace/32.gpio_smoke/latest

Test location /workspace/coverage/default/32.gpio_smoke_no_pullup_pulldown.1906926732
Short name T684
Test name
Test status
Simulation time 81689567 ps
CPU time 1.07 seconds
Started Dec 24 01:10:34 PM PST 23
Finished Dec 24 01:10:40 PM PST 23
Peak memory 195672 kb
Host smart-2c986169-ad87-4cbc-b89c-2a632a053aed
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1906926732 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_smoke_no_pullup_pulldown.1906926732
Directory /workspace/32.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/32.gpio_stress_all.4069210528
Short name T773
Test name
Test status
Simulation time 26414899115 ps
CPU time 154.09 seconds
Started Dec 24 01:10:54 PM PST 23
Finished Dec 24 01:13:39 PM PST 23
Peak memory 198140 kb
Host smart-6ca40c04-e59f-4c38-bde0-ab2848b268cd
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4069210528 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.
gpio_stress_all.4069210528
Directory /workspace/32.gpio_stress_all/latest

Test location /workspace/coverage/default/32.gpio_stress_all_with_rand_reset.3854118569
Short name T484
Test name
Test status
Simulation time 25065103694 ps
CPU time 423.52 seconds
Started Dec 24 01:10:53 PM PST 23
Finished Dec 24 01:18:08 PM PST 23
Peak memory 197932 kb
Host smart-00727ef1-2baf-4ff2-a086-3a07bcf2860f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=3854118569 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_stress_all_with_rand_reset.3854118569
Directory /workspace/32.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/33.gpio_alert_test.442703958
Short name T457
Test name
Test status
Simulation time 11635320 ps
CPU time 0.57 seconds
Started Dec 24 01:10:45 PM PST 23
Finished Dec 24 01:10:55 PM PST 23
Peak memory 194776 kb
Host smart-bb94126e-2bc1-4be2-ae91-6f21325f033f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=442703958 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_alert_test.442703958
Directory /workspace/33.gpio_alert_test/latest

Test location /workspace/coverage/default/33.gpio_dout_din_regs_random_rw.1521780863
Short name T285
Test name
Test status
Simulation time 93708741 ps
CPU time 0.81 seconds
Started Dec 24 01:10:48 PM PST 23
Finished Dec 24 01:10:59 PM PST 23
Peak memory 196084 kb
Host smart-0fc16932-2a6b-4aa9-9de6-b5080c04ce3a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1521780863 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_dout_din_regs_random_rw.1521780863
Directory /workspace/33.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/33.gpio_filter_stress.750063198
Short name T287
Test name
Test status
Simulation time 232445198 ps
CPU time 6.9 seconds
Started Dec 24 01:10:44 PM PST 23
Finished Dec 24 01:11:00 PM PST 23
Peak memory 195660 kb
Host smart-b394da97-bae5-4258-9b97-241cc5eb2da1
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=750063198 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_filter_stres
s.750063198
Directory /workspace/33.gpio_filter_stress/latest

Test location /workspace/coverage/default/33.gpio_full_random.1604872897
Short name T620
Test name
Test status
Simulation time 295429221 ps
CPU time 0.97 seconds
Started Dec 24 01:10:46 PM PST 23
Finished Dec 24 01:10:58 PM PST 23
Peak memory 196464 kb
Host smart-c33bb792-586c-4d68-8e6e-b24f57098d84
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1604872897 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_full_random.1604872897
Directory /workspace/33.gpio_full_random/latest

Test location /workspace/coverage/default/33.gpio_intr_rand_pgm.490123187
Short name T820
Test name
Test status
Simulation time 251956140 ps
CPU time 1.06 seconds
Started Dec 24 01:10:53 PM PST 23
Finished Dec 24 01:11:05 PM PST 23
Peak memory 196204 kb
Host smart-05beb8bb-2ea8-4d5c-b782-dfaeed4f001f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=490123187 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_intr_rand_pgm.490123187
Directory /workspace/33.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/33.gpio_intr_with_filter_rand_intr_event.3358632619
Short name T111
Test name
Test status
Simulation time 350351516 ps
CPU time 2.94 seconds
Started Dec 24 01:11:00 PM PST 23
Finished Dec 24 01:11:16 PM PST 23
Peak memory 198228 kb
Host smart-d0e9dbff-9185-4ef9-a7c8-b98914ae42a0
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3358632619 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 33.gpio_intr_with_filter_rand_intr_event.3358632619
Directory /workspace/33.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/33.gpio_rand_intr_trigger.868049240
Short name T353
Test name
Test status
Simulation time 123110335 ps
CPU time 3.42 seconds
Started Dec 24 01:10:53 PM PST 23
Finished Dec 24 01:11:08 PM PST 23
Peak memory 195952 kb
Host smart-a4c33edc-1bb3-4677-84aa-d144f9c8be4a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=868049240 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_rand_intr_trigger.
868049240
Directory /workspace/33.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/33.gpio_random_dout_din.3763177386
Short name T307
Test name
Test status
Simulation time 25096442 ps
CPU time 0.69 seconds
Started Dec 24 01:10:48 PM PST 23
Finished Dec 24 01:10:59 PM PST 23
Peak memory 195516 kb
Host smart-bece6d25-5ecd-454a-9abb-48f6f3bc2877
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3763177386 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_random_dout_din.3763177386
Directory /workspace/33.gpio_random_dout_din/latest

Test location /workspace/coverage/default/33.gpio_random_dout_din_no_pullup_pulldown.3546991399
Short name T491
Test name
Test status
Simulation time 314575086 ps
CPU time 1.03 seconds
Started Dec 24 01:10:44 PM PST 23
Finished Dec 24 01:10:55 PM PST 23
Peak memory 195968 kb
Host smart-a53e36a3-cb98-4d87-b6b4-ecc8fc07a2e9
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3546991399 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_random_dout_din_no_pullu
p_pulldown.3546991399
Directory /workspace/33.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/33.gpio_random_long_reg_writes_reg_reads.2226084621
Short name T576
Test name
Test status
Simulation time 288928767 ps
CPU time 4.8 seconds
Started Dec 24 01:10:50 PM PST 23
Finished Dec 24 01:11:05 PM PST 23
Peak memory 198108 kb
Host smart-6a1b38ed-3038-45fb-8fb0-039be112e984
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2226084621 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_ra
ndom_long_reg_writes_reg_reads.2226084621
Directory /workspace/33.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/33.gpio_smoke.3026014839
Short name T687
Test name
Test status
Simulation time 138394643 ps
CPU time 0.88 seconds
Started Dec 24 01:10:53 PM PST 23
Finished Dec 24 01:11:06 PM PST 23
Peak memory 195912 kb
Host smart-6c936740-4637-4be9-8e9c-9a9a03b0efd3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3026014839 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_smoke.3026014839
Directory /workspace/33.gpio_smoke/latest

Test location /workspace/coverage/default/33.gpio_smoke_no_pullup_pulldown.1040155019
Short name T557
Test name
Test status
Simulation time 218498646 ps
CPU time 1.18 seconds
Started Dec 24 01:10:53 PM PST 23
Finished Dec 24 01:11:05 PM PST 23
Peak memory 196816 kb
Host smart-d89a0439-73ec-47a8-afe2-3c4c418f789e
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1040155019 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_smoke_no_pullup_pulldown.1040155019
Directory /workspace/33.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/33.gpio_stress_all.44504979
Short name T345
Test name
Test status
Simulation time 148350157843 ps
CPU time 154.12 seconds
Started Dec 24 01:11:03 PM PST 23
Finished Dec 24 01:13:48 PM PST 23
Peak memory 198236 kb
Host smart-4477f4a8-fb27-494a-8c0f-7313451f8501
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=44504979 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TE
ST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gp
io_stress_all.44504979
Directory /workspace/33.gpio_stress_all/latest

Test location /workspace/coverage/default/33.gpio_stress_all_with_rand_reset.4055652457
Short name T775
Test name
Test status
Simulation time 62695462691 ps
CPU time 248.43 seconds
Started Dec 24 01:10:46 PM PST 23
Finished Dec 24 01:15:05 PM PST 23
Peak memory 198344 kb
Host smart-94687554-ade7-4e74-aaef-9e51c7c5bf37
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=4055652457 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_stress_all_with_rand_reset.4055652457
Directory /workspace/33.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/34.gpio_alert_test.3206221613
Short name T844
Test name
Test status
Simulation time 94013358 ps
CPU time 0.59 seconds
Started Dec 24 01:10:39 PM PST 23
Finished Dec 24 01:10:47 PM PST 23
Peak memory 194244 kb
Host smart-f79c862b-b0b1-4b67-8ac6-6f393da7a970
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3206221613 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_alert_test.3206221613
Directory /workspace/34.gpio_alert_test/latest

Test location /workspace/coverage/default/34.gpio_dout_din_regs_random_rw.164150003
Short name T313
Test name
Test status
Simulation time 48847794 ps
CPU time 0.95 seconds
Started Dec 24 01:10:53 PM PST 23
Finished Dec 24 01:11:04 PM PST 23
Peak memory 196568 kb
Host smart-1632fd97-bbc3-4faf-b78b-eb35f3731d2b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=164150003 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_dout_din_regs_random_rw.164150003
Directory /workspace/34.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/34.gpio_filter_stress.3052678565
Short name T266
Test name
Test status
Simulation time 162175904 ps
CPU time 8.73 seconds
Started Dec 24 01:10:54 PM PST 23
Finished Dec 24 01:11:14 PM PST 23
Peak memory 196400 kb
Host smart-a4d9e759-2336-404d-a01b-82ca92fc635f
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3052678565 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_filter_stre
ss.3052678565
Directory /workspace/34.gpio_filter_stress/latest

Test location /workspace/coverage/default/34.gpio_full_random.3522562957
Short name T754
Test name
Test status
Simulation time 76259901 ps
CPU time 0.96 seconds
Started Dec 24 01:11:06 PM PST 23
Finished Dec 24 01:11:17 PM PST 23
Peak memory 197152 kb
Host smart-641de140-3227-42a9-a84f-994dbb6e0838
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3522562957 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_full_random.3522562957
Directory /workspace/34.gpio_full_random/latest

Test location /workspace/coverage/default/34.gpio_intr_rand_pgm.520958399
Short name T883
Test name
Test status
Simulation time 36308767 ps
CPU time 0.67 seconds
Started Dec 24 01:10:53 PM PST 23
Finished Dec 24 01:11:05 PM PST 23
Peak memory 194572 kb
Host smart-dff56ca6-63ab-459d-b0d2-d28fd2822019
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=520958399 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_intr_rand_pgm.520958399
Directory /workspace/34.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/34.gpio_intr_with_filter_rand_intr_event.591540279
Short name T653
Test name
Test status
Simulation time 226296573 ps
CPU time 2.22 seconds
Started Dec 24 01:10:46 PM PST 23
Finished Dec 24 01:10:59 PM PST 23
Peak memory 198196 kb
Host smart-7d75270f-c873-4a7f-8f9d-06deb4eadf9d
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=591540279 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 34.gpio_intr_with_filter_rand_intr_event.591540279
Directory /workspace/34.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/34.gpio_rand_intr_trigger.1541244620
Short name T753
Test name
Test status
Simulation time 594344507 ps
CPU time 3.18 seconds
Started Dec 24 01:10:59 PM PST 23
Finished Dec 24 01:11:15 PM PST 23
Peak memory 197308 kb
Host smart-f6e6e516-0f23-457b-86aa-8e1c44460933
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1541244620 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_rand_intr_trigger
.1541244620
Directory /workspace/34.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/34.gpio_random_dout_din.3247962025
Short name T874
Test name
Test status
Simulation time 338984842 ps
CPU time 1.28 seconds
Started Dec 24 01:10:47 PM PST 23
Finished Dec 24 01:10:59 PM PST 23
Peak memory 195948 kb
Host smart-36c6f582-958a-42f1-81b5-ebf41cee5fea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3247962025 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_random_dout_din.3247962025
Directory /workspace/34.gpio_random_dout_din/latest

Test location /workspace/coverage/default/34.gpio_random_dout_din_no_pullup_pulldown.1223517409
Short name T578
Test name
Test status
Simulation time 40535740 ps
CPU time 0.85 seconds
Started Dec 24 01:10:44 PM PST 23
Finished Dec 24 01:10:55 PM PST 23
Peak memory 196104 kb
Host smart-1999d6b9-6509-4257-9d95-d5d125ddb265
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1223517409 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_random_dout_din_no_pullu
p_pulldown.1223517409
Directory /workspace/34.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/34.gpio_random_long_reg_writes_reg_reads.2906177217
Short name T728
Test name
Test status
Simulation time 323821021 ps
CPU time 5.38 seconds
Started Dec 24 01:10:53 PM PST 23
Finished Dec 24 01:11:08 PM PST 23
Peak memory 198084 kb
Host smart-06be0657-6ae2-4c49-bd7d-5e42109168db
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2906177217 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_ra
ndom_long_reg_writes_reg_reads.2906177217
Directory /workspace/34.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/34.gpio_smoke.3462779854
Short name T430
Test name
Test status
Simulation time 68498425 ps
CPU time 0.99 seconds
Started Dec 24 01:10:43 PM PST 23
Finished Dec 24 01:10:53 PM PST 23
Peak memory 196612 kb
Host smart-b0118f82-f749-4e53-b58b-efb7398de3f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3462779854 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_smoke.3462779854
Directory /workspace/34.gpio_smoke/latest

Test location /workspace/coverage/default/34.gpio_smoke_no_pullup_pulldown.1902411900
Short name T569
Test name
Test status
Simulation time 100992398 ps
CPU time 1.38 seconds
Started Dec 24 01:10:46 PM PST 23
Finished Dec 24 01:10:59 PM PST 23
Peak memory 198092 kb
Host smart-71fd479e-9730-4320-8e40-c4223679659f
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1902411900 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_smoke_no_pullup_pulldown.1902411900
Directory /workspace/34.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/34.gpio_stress_all.2512974831
Short name T488
Test name
Test status
Simulation time 29049878280 ps
CPU time 178.78 seconds
Started Dec 24 01:10:44 PM PST 23
Finished Dec 24 01:13:52 PM PST 23
Peak memory 198236 kb
Host smart-e8511fed-0a05-4b44-aab9-c75358143bf5
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2512974831 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.
gpio_stress_all.2512974831
Directory /workspace/34.gpio_stress_all/latest

Test location /workspace/coverage/default/34.gpio_stress_all_with_rand_reset.1627918286
Short name T535
Test name
Test status
Simulation time 561248357280 ps
CPU time 1904.36 seconds
Started Dec 24 01:11:10 PM PST 23
Finished Dec 24 01:43:03 PM PST 23
Peak memory 206596 kb
Host smart-380f0d8b-a7c0-4481-8a75-97c09dfa621d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=1627918286 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_stress_all_with_rand_reset.1627918286
Directory /workspace/34.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/35.gpio_alert_test.2869798623
Short name T664
Test name
Test status
Simulation time 42822921 ps
CPU time 0.58 seconds
Started Dec 24 01:11:00 PM PST 23
Finished Dec 24 01:11:13 PM PST 23
Peak memory 193988 kb
Host smart-88d4036f-8c01-4e77-970b-c2b7cb87dd45
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2869798623 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_alert_test.2869798623
Directory /workspace/35.gpio_alert_test/latest

Test location /workspace/coverage/default/35.gpio_dout_din_regs_random_rw.2039261983
Short name T808
Test name
Test status
Simulation time 36317345 ps
CPU time 0.73 seconds
Started Dec 24 01:10:54 PM PST 23
Finished Dec 24 01:11:06 PM PST 23
Peak memory 195232 kb
Host smart-839aad14-c6e6-4a9a-97de-2835f765cf12
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2039261983 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_dout_din_regs_random_rw.2039261983
Directory /workspace/35.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/35.gpio_filter_stress.1171211387
Short name T786
Test name
Test status
Simulation time 894552153 ps
CPU time 15.21 seconds
Started Dec 24 01:11:18 PM PST 23
Finished Dec 24 01:11:42 PM PST 23
Peak memory 196916 kb
Host smart-180e6826-3118-4a34-a779-3e7d5367ab1a
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1171211387 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_filter_stre
ss.1171211387
Directory /workspace/35.gpio_filter_stress/latest

Test location /workspace/coverage/default/35.gpio_full_random.3359713648
Short name T587
Test name
Test status
Simulation time 305963093 ps
CPU time 1.07 seconds
Started Dec 24 01:10:33 PM PST 23
Finished Dec 24 01:10:38 PM PST 23
Peak memory 197876 kb
Host smart-218aad74-4eaf-45e1-98d3-2f0e35c7561b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3359713648 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_full_random.3359713648
Directory /workspace/35.gpio_full_random/latest

Test location /workspace/coverage/default/35.gpio_intr_rand_pgm.3101129188
Short name T462
Test name
Test status
Simulation time 46873834 ps
CPU time 1.26 seconds
Started Dec 24 01:10:47 PM PST 23
Finished Dec 24 01:10:59 PM PST 23
Peak memory 198020 kb
Host smart-cfb89623-7817-45e6-82d5-036ef2bc8e86
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3101129188 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_intr_rand_pgm.3101129188
Directory /workspace/35.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/35.gpio_intr_with_filter_rand_intr_event.3041016099
Short name T810
Test name
Test status
Simulation time 339996531 ps
CPU time 3.32 seconds
Started Dec 24 01:10:53 PM PST 23
Finished Dec 24 01:11:08 PM PST 23
Peak memory 198272 kb
Host smart-d850483b-2b6e-40d4-9a39-82a9ce83f992
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3041016099 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 35.gpio_intr_with_filter_rand_intr_event.3041016099
Directory /workspace/35.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/35.gpio_rand_intr_trigger.3222403952
Short name T332
Test name
Test status
Simulation time 243345689 ps
CPU time 1.21 seconds
Started Dec 24 01:10:41 PM PST 23
Finished Dec 24 01:10:51 PM PST 23
Peak memory 195732 kb
Host smart-ff2cd874-a65a-4279-993f-37d2aadc21a4
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3222403952 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_rand_intr_trigger
.3222403952
Directory /workspace/35.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/35.gpio_random_dout_din.2620496187
Short name T574
Test name
Test status
Simulation time 37116139 ps
CPU time 0.75 seconds
Started Dec 24 01:10:52 PM PST 23
Finished Dec 24 01:11:03 PM PST 23
Peak memory 195584 kb
Host smart-28b3938f-8e6d-4198-b80b-b6d8c277debf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2620496187 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_random_dout_din.2620496187
Directory /workspace/35.gpio_random_dout_din/latest

Test location /workspace/coverage/default/35.gpio_random_dout_din_no_pullup_pulldown.1785636760
Short name T818
Test name
Test status
Simulation time 182434329 ps
CPU time 0.99 seconds
Started Dec 24 01:10:56 PM PST 23
Finished Dec 24 01:11:08 PM PST 23
Peak memory 196832 kb
Host smart-298d1b3c-a687-478a-9643-8c9de2ff9e10
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1785636760 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_random_dout_din_no_pullu
p_pulldown.1785636760
Directory /workspace/35.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/35.gpio_random_long_reg_writes_reg_reads.3484528094
Short name T549
Test name
Test status
Simulation time 666825585 ps
CPU time 3.92 seconds
Started Dec 24 01:10:46 PM PST 23
Finished Dec 24 01:11:01 PM PST 23
Peak memory 197956 kb
Host smart-1f14ac0c-d016-4bbf-96a1-b270868129a0
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3484528094 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_ra
ndom_long_reg_writes_reg_reads.3484528094
Directory /workspace/35.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/35.gpio_smoke.1968793807
Short name T359
Test name
Test status
Simulation time 76534874 ps
CPU time 0.96 seconds
Started Dec 24 01:10:59 PM PST 23
Finished Dec 24 01:11:13 PM PST 23
Peak memory 196488 kb
Host smart-bf8a7da3-7a78-4712-8903-715f8494507f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1968793807 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_smoke.1968793807
Directory /workspace/35.gpio_smoke/latest

Test location /workspace/coverage/default/35.gpio_smoke_no_pullup_pulldown.1805358032
Short name T486
Test name
Test status
Simulation time 297008121 ps
CPU time 1.25 seconds
Started Dec 24 01:10:58 PM PST 23
Finished Dec 24 01:11:12 PM PST 23
Peak memory 196392 kb
Host smart-179ce691-33f2-4369-a905-8073e3c73ab2
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1805358032 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_smoke_no_pullup_pulldown.1805358032
Directory /workspace/35.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/35.gpio_stress_all.436985347
Short name T521
Test name
Test status
Simulation time 25231283397 ps
CPU time 172.18 seconds
Started Dec 24 01:10:46 PM PST 23
Finished Dec 24 01:13:49 PM PST 23
Peak memory 198068 kb
Host smart-d053bb08-10ef-4000-a8db-f0424e49b62e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=436985347 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.g
pio_stress_all.436985347
Directory /workspace/35.gpio_stress_all/latest

Test location /workspace/coverage/default/35.gpio_stress_all_with_rand_reset.1857073410
Short name T673
Test name
Test status
Simulation time 90744906154 ps
CPU time 527.98 seconds
Started Dec 24 01:10:47 PM PST 23
Finished Dec 24 01:19:46 PM PST 23
Peak memory 198412 kb
Host smart-b0575c6d-c5db-4640-bfdd-adbe40284a4d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=1857073410 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_stress_all_with_rand_reset.1857073410
Directory /workspace/35.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/36.gpio_alert_test.3889164880
Short name T367
Test name
Test status
Simulation time 19782941 ps
CPU time 0.55 seconds
Started Dec 24 01:10:44 PM PST 23
Finished Dec 24 01:10:55 PM PST 23
Peak memory 194056 kb
Host smart-5d8ea733-aa7e-404f-9db0-963fa284ca60
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3889164880 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_alert_test.3889164880
Directory /workspace/36.gpio_alert_test/latest

Test location /workspace/coverage/default/36.gpio_dout_din_regs_random_rw.1104584472
Short name T729
Test name
Test status
Simulation time 34478786 ps
CPU time 0.85 seconds
Started Dec 24 01:10:40 PM PST 23
Finished Dec 24 01:10:48 PM PST 23
Peak memory 195436 kb
Host smart-c0058c69-fe55-4477-86a1-dfb717ecd015
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1104584472 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_dout_din_regs_random_rw.1104584472
Directory /workspace/36.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/36.gpio_filter_stress.762633869
Short name T60
Test name
Test status
Simulation time 272675608 ps
CPU time 13.57 seconds
Started Dec 24 01:10:41 PM PST 23
Finished Dec 24 01:11:02 PM PST 23
Peak memory 195672 kb
Host smart-7a887737-7e0c-4e4b-8add-b4f4ee876f2f
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=762633869 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_filter_stres
s.762633869
Directory /workspace/36.gpio_filter_stress/latest

Test location /workspace/coverage/default/36.gpio_full_random.2961499744
Short name T573
Test name
Test status
Simulation time 76786440 ps
CPU time 0.76 seconds
Started Dec 24 01:10:51 PM PST 23
Finished Dec 24 01:11:02 PM PST 23
Peak memory 195744 kb
Host smart-088b9e44-99db-4314-919e-23d47578f231
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2961499744 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_full_random.2961499744
Directory /workspace/36.gpio_full_random/latest

Test location /workspace/coverage/default/36.gpio_intr_rand_pgm.2568042083
Short name T716
Test name
Test status
Simulation time 1334343057 ps
CPU time 1.27 seconds
Started Dec 24 01:10:45 PM PST 23
Finished Dec 24 01:10:57 PM PST 23
Peak memory 197464 kb
Host smart-fe8be215-f5fe-4e79-afad-25a8bc89af41
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2568042083 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_intr_rand_pgm.2568042083
Directory /workspace/36.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/36.gpio_intr_with_filter_rand_intr_event.2557006447
Short name T527
Test name
Test status
Simulation time 49764887 ps
CPU time 1.45 seconds
Started Dec 24 01:10:42 PM PST 23
Finished Dec 24 01:10:51 PM PST 23
Peak memory 196456 kb
Host smart-174e6615-0677-443a-ba3a-ab3fc6e2025d
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2557006447 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 36.gpio_intr_with_filter_rand_intr_event.2557006447
Directory /workspace/36.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/36.gpio_rand_intr_trigger.2920402393
Short name T677
Test name
Test status
Simulation time 122463293 ps
CPU time 3.84 seconds
Started Dec 24 01:10:38 PM PST 23
Finished Dec 24 01:10:48 PM PST 23
Peak memory 197000 kb
Host smart-6f15fe34-2f65-4464-b074-c8caa1a5affa
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2920402393 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_rand_intr_trigger
.2920402393
Directory /workspace/36.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/36.gpio_random_dout_din.3713974269
Short name T788
Test name
Test status
Simulation time 75081265 ps
CPU time 0.68 seconds
Started Dec 24 01:10:58 PM PST 23
Finished Dec 24 01:11:10 PM PST 23
Peak memory 195144 kb
Host smart-3ae8caa6-8d89-41f6-bca2-859c21055908
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3713974269 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_random_dout_din.3713974269
Directory /workspace/36.gpio_random_dout_din/latest

Test location /workspace/coverage/default/36.gpio_random_dout_din_no_pullup_pulldown.3871641166
Short name T244
Test name
Test status
Simulation time 62936857 ps
CPU time 0.69 seconds
Started Dec 24 01:10:57 PM PST 23
Finished Dec 24 01:11:09 PM PST 23
Peak memory 195472 kb
Host smart-7f9fc2a8-c01d-435a-882c-06b13689a03e
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3871641166 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_random_dout_din_no_pullu
p_pulldown.3871641166
Directory /workspace/36.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/36.gpio_random_long_reg_writes_reg_reads.2678559813
Short name T823
Test name
Test status
Simulation time 108534622 ps
CPU time 4.91 seconds
Started Dec 24 01:10:47 PM PST 23
Finished Dec 24 01:11:03 PM PST 23
Peak memory 198152 kb
Host smart-fdcbf931-2b58-4178-bc13-1d9ab7d3d83d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2678559813 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_ra
ndom_long_reg_writes_reg_reads.2678559813
Directory /workspace/36.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/36.gpio_smoke.1948986241
Short name T498
Test name
Test status
Simulation time 39743966 ps
CPU time 1.07 seconds
Started Dec 24 01:11:03 PM PST 23
Finished Dec 24 01:11:15 PM PST 23
Peak memory 195544 kb
Host smart-1e495372-8213-4f06-90c2-3e546f3a2018
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1948986241 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_smoke.1948986241
Directory /workspace/36.gpio_smoke/latest

Test location /workspace/coverage/default/36.gpio_smoke_no_pullup_pulldown.946172089
Short name T667
Test name
Test status
Simulation time 209996746 ps
CPU time 0.85 seconds
Started Dec 24 01:10:52 PM PST 23
Finished Dec 24 01:11:03 PM PST 23
Peak memory 195176 kb
Host smart-60d06fc8-5391-41ed-8b98-819bf3ad747c
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=946172089 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_smoke_no_pullup_pulldown.946172089
Directory /workspace/36.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/36.gpio_stress_all.1612213465
Short name T219
Test name
Test status
Simulation time 16191457019 ps
CPU time 117.01 seconds
Started Dec 24 01:10:55 PM PST 23
Finished Dec 24 01:13:03 PM PST 23
Peak memory 198240 kb
Host smart-69024afd-d9bb-433e-b924-a0c920130ddd
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1612213465 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.
gpio_stress_all.1612213465
Directory /workspace/36.gpio_stress_all/latest

Test location /workspace/coverage/default/36.gpio_stress_all_with_rand_reset.2635803888
Short name T736
Test name
Test status
Simulation time 102460534307 ps
CPU time 1364.98 seconds
Started Dec 24 01:10:57 PM PST 23
Finished Dec 24 01:33:53 PM PST 23
Peak memory 198456 kb
Host smart-9b11542d-97df-4253-bcf3-3e8e13ceb9a1
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=2635803888 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_stress_all_with_rand_reset.2635803888
Directory /workspace/36.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/37.gpio_alert_test.3392600881
Short name T304
Test name
Test status
Simulation time 52323608 ps
CPU time 0.54 seconds
Started Dec 24 01:11:04 PM PST 23
Finished Dec 24 01:11:16 PM PST 23
Peak memory 194056 kb
Host smart-3cb1ecd1-da65-4bbd-8a61-795e4430431b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3392600881 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_alert_test.3392600881
Directory /workspace/37.gpio_alert_test/latest

Test location /workspace/coverage/default/37.gpio_dout_din_regs_random_rw.577210054
Short name T383
Test name
Test status
Simulation time 45510120 ps
CPU time 0.71 seconds
Started Dec 24 01:10:41 PM PST 23
Finished Dec 24 01:10:50 PM PST 23
Peak memory 194816 kb
Host smart-3b1da629-7b1f-4c19-b1a2-054da0596d02
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=577210054 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_dout_din_regs_random_rw.577210054
Directory /workspace/37.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/37.gpio_filter_stress.2305985806
Short name T768
Test name
Test status
Simulation time 343754167 ps
CPU time 11.75 seconds
Started Dec 24 01:11:07 PM PST 23
Finished Dec 24 01:11:28 PM PST 23
Peak memory 198156 kb
Host smart-6dca5edd-faec-4a7b-a42a-5f2597ae47cb
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2305985806 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_filter_stre
ss.2305985806
Directory /workspace/37.gpio_filter_stress/latest

Test location /workspace/coverage/default/37.gpio_full_random.298504975
Short name T341
Test name
Test status
Simulation time 252770034 ps
CPU time 0.92 seconds
Started Dec 24 01:10:56 PM PST 23
Finished Dec 24 01:11:08 PM PST 23
Peak memory 197844 kb
Host smart-520dbe33-32f9-4bdf-9827-f60243bec860
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=298504975 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_full_random.298504975
Directory /workspace/37.gpio_full_random/latest

Test location /workspace/coverage/default/37.gpio_intr_rand_pgm.4079678835
Short name T533
Test name
Test status
Simulation time 31311635 ps
CPU time 0.97 seconds
Started Dec 24 01:10:59 PM PST 23
Finished Dec 24 01:11:13 PM PST 23
Peak memory 195772 kb
Host smart-11ac25b0-9b3d-4027-8092-3cfb1ec5427a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4079678835 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_intr_rand_pgm.4079678835
Directory /workspace/37.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/37.gpio_intr_with_filter_rand_intr_event.672901830
Short name T884
Test name
Test status
Simulation time 92639015 ps
CPU time 3.72 seconds
Started Dec 24 01:10:49 PM PST 23
Finished Dec 24 01:11:03 PM PST 23
Peak memory 198284 kb
Host smart-7c507f4a-9046-48be-bd74-37bf9273e864
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=672901830 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 37.gpio_intr_with_filter_rand_intr_event.672901830
Directory /workspace/37.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/37.gpio_rand_intr_trigger.3118815671
Short name T805
Test name
Test status
Simulation time 67984696 ps
CPU time 1.95 seconds
Started Dec 24 01:10:43 PM PST 23
Finished Dec 24 01:10:54 PM PST 23
Peak memory 195904 kb
Host smart-fb2fa916-e927-4c3d-847a-14374e56dfed
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3118815671 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_rand_intr_trigger
.3118815671
Directory /workspace/37.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/37.gpio_random_dout_din.1002173007
Short name T377
Test name
Test status
Simulation time 22537033 ps
CPU time 0.7 seconds
Started Dec 24 01:10:50 PM PST 23
Finished Dec 24 01:11:01 PM PST 23
Peak memory 195964 kb
Host smart-affbf6c9-2dc4-4a1e-8677-5865e33d581d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1002173007 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_random_dout_din.1002173007
Directory /workspace/37.gpio_random_dout_din/latest

Test location /workspace/coverage/default/37.gpio_random_dout_din_no_pullup_pulldown.1017913513
Short name T562
Test name
Test status
Simulation time 88543436 ps
CPU time 1 seconds
Started Dec 24 01:10:49 PM PST 23
Finished Dec 24 01:11:00 PM PST 23
Peak memory 196788 kb
Host smart-93acce73-14c1-4e1e-9231-518d1f940bcf
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1017913513 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_random_dout_din_no_pullu
p_pulldown.1017913513
Directory /workspace/37.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/37.gpio_random_long_reg_writes_reg_reads.1272475253
Short name T821
Test name
Test status
Simulation time 70993033 ps
CPU time 3.56 seconds
Started Dec 24 01:10:59 PM PST 23
Finished Dec 24 01:11:15 PM PST 23
Peak memory 197980 kb
Host smart-50d9a31c-8007-4679-a2c0-10233e2d3513
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1272475253 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_ra
ndom_long_reg_writes_reg_reads.1272475253
Directory /workspace/37.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/37.gpio_smoke.2429846297
Short name T360
Test name
Test status
Simulation time 103725606 ps
CPU time 0.94 seconds
Started Dec 24 01:10:52 PM PST 23
Finished Dec 24 01:11:02 PM PST 23
Peak memory 196300 kb
Host smart-9c944e02-890b-4675-b619-19cf941c023d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2429846297 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_smoke.2429846297
Directory /workspace/37.gpio_smoke/latest

Test location /workspace/coverage/default/37.gpio_smoke_no_pullup_pulldown.3288182792
Short name T253
Test name
Test status
Simulation time 70899665 ps
CPU time 0.73 seconds
Started Dec 24 01:10:46 PM PST 23
Finished Dec 24 01:10:58 PM PST 23
Peak memory 195556 kb
Host smart-4ebf8033-64dd-4477-b7f9-0bed0fd6d0e0
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3288182792 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_smoke_no_pullup_pulldown.3288182792
Directory /workspace/37.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/37.gpio_stress_all.630073040
Short name T342
Test name
Test status
Simulation time 25756716230 ps
CPU time 155.65 seconds
Started Dec 24 01:10:46 PM PST 23
Finished Dec 24 01:13:33 PM PST 23
Peak memory 197904 kb
Host smart-a9614a9c-75cc-4643-aef3-76b9e0e90efe
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=630073040 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.g
pio_stress_all.630073040
Directory /workspace/37.gpio_stress_all/latest

Test location /workspace/coverage/default/37.gpio_stress_all_with_rand_reset.1362716392
Short name T565
Test name
Test status
Simulation time 77985481262 ps
CPU time 978.59 seconds
Started Dec 24 01:11:00 PM PST 23
Finished Dec 24 01:27:31 PM PST 23
Peak memory 198364 kb
Host smart-684a8c7d-a950-4f57-adbd-682b59dd3e56
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=1362716392 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_stress_all_with_rand_reset.1362716392
Directory /workspace/37.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/38.gpio_alert_test.1202010671
Short name T545
Test name
Test status
Simulation time 14537243 ps
CPU time 0.56 seconds
Started Dec 24 01:10:59 PM PST 23
Finished Dec 24 01:11:12 PM PST 23
Peak memory 194260 kb
Host smart-e898c61b-3acc-4715-b25a-098c8e8fc874
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1202010671 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_alert_test.1202010671
Directory /workspace/38.gpio_alert_test/latest

Test location /workspace/coverage/default/38.gpio_dout_din_regs_random_rw.2369027537
Short name T369
Test name
Test status
Simulation time 50721319 ps
CPU time 0.7 seconds
Started Dec 24 01:10:49 PM PST 23
Finished Dec 24 01:10:59 PM PST 23
Peak memory 195176 kb
Host smart-14b47646-f481-4508-9e8f-948edd5af04a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2369027537 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_dout_din_regs_random_rw.2369027537
Directory /workspace/38.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/38.gpio_filter_stress.1152984891
Short name T248
Test name
Test status
Simulation time 624219392 ps
CPU time 9.14 seconds
Started Dec 24 01:10:59 PM PST 23
Finished Dec 24 01:11:21 PM PST 23
Peak memory 196388 kb
Host smart-a79c6c96-e0b0-484f-ae3c-e89d6f710c47
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1152984891 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_filter_stre
ss.1152984891
Directory /workspace/38.gpio_filter_stress/latest

Test location /workspace/coverage/default/38.gpio_full_random.2924815802
Short name T286
Test name
Test status
Simulation time 67655762 ps
CPU time 0.96 seconds
Started Dec 24 01:10:50 PM PST 23
Finished Dec 24 01:11:00 PM PST 23
Peak memory 196636 kb
Host smart-7f40ff7e-02a2-4ffc-87a7-6b7ae35b7015
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2924815802 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_full_random.2924815802
Directory /workspace/38.gpio_full_random/latest

Test location /workspace/coverage/default/38.gpio_intr_rand_pgm.2734626243
Short name T671
Test name
Test status
Simulation time 38500610 ps
CPU time 0.98 seconds
Started Dec 24 01:10:55 PM PST 23
Finished Dec 24 01:11:08 PM PST 23
Peak memory 196628 kb
Host smart-df8284a7-61a2-4765-a7a2-3f34b662cbcf
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2734626243 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_intr_rand_pgm.2734626243
Directory /workspace/38.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/38.gpio_intr_with_filter_rand_intr_event.3267305325
Short name T566
Test name
Test status
Simulation time 209113183 ps
CPU time 1.78 seconds
Started Dec 24 01:10:46 PM PST 23
Finished Dec 24 01:10:59 PM PST 23
Peak memory 197940 kb
Host smart-09f386ec-facc-447a-bd4d-17b773a34492
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3267305325 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 38.gpio_intr_with_filter_rand_intr_event.3267305325
Directory /workspace/38.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/38.gpio_rand_intr_trigger.2581926814
Short name T731
Test name
Test status
Simulation time 52262158 ps
CPU time 1.1 seconds
Started Dec 24 01:10:48 PM PST 23
Finished Dec 24 01:10:59 PM PST 23
Peak memory 195788 kb
Host smart-c8615070-5b7d-4e61-9465-4912cf36707c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2581926814 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_rand_intr_trigger
.2581926814
Directory /workspace/38.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/38.gpio_random_dout_din.2726244811
Short name T598
Test name
Test status
Simulation time 13287937 ps
CPU time 0.63 seconds
Started Dec 24 01:10:56 PM PST 23
Finished Dec 24 01:11:08 PM PST 23
Peak memory 194160 kb
Host smart-b2c13279-33f9-4073-8b63-1978bc63a2bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2726244811 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_random_dout_din.2726244811
Directory /workspace/38.gpio_random_dout_din/latest

Test location /workspace/coverage/default/38.gpio_random_dout_din_no_pullup_pulldown.3559013995
Short name T694
Test name
Test status
Simulation time 27582885 ps
CPU time 1.08 seconds
Started Dec 24 01:10:50 PM PST 23
Finished Dec 24 01:11:01 PM PST 23
Peak memory 196664 kb
Host smart-cc01533b-cd4f-44df-ba58-feaf6d0da5b3
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3559013995 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_random_dout_din_no_pullu
p_pulldown.3559013995
Directory /workspace/38.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/38.gpio_random_long_reg_writes_reg_reads.2341820090
Short name T517
Test name
Test status
Simulation time 87161765 ps
CPU time 3.9 seconds
Started Dec 24 01:10:57 PM PST 23
Finished Dec 24 01:11:12 PM PST 23
Peak memory 198028 kb
Host smart-bb573562-2b06-413d-a656-fe7f26bdbfa2
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2341820090 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_ra
ndom_long_reg_writes_reg_reads.2341820090
Directory /workspace/38.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/38.gpio_smoke.237194054
Short name T371
Test name
Test status
Simulation time 267131026 ps
CPU time 1.26 seconds
Started Dec 24 01:10:44 PM PST 23
Finished Dec 24 01:10:56 PM PST 23
Peak memory 198004 kb
Host smart-8e584cb8-b440-4989-a239-026af5bd226f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=237194054 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_smoke.237194054
Directory /workspace/38.gpio_smoke/latest

Test location /workspace/coverage/default/38.gpio_smoke_no_pullup_pulldown.455884424
Short name T305
Test name
Test status
Simulation time 65925470 ps
CPU time 1.15 seconds
Started Dec 24 01:10:48 PM PST 23
Finished Dec 24 01:10:59 PM PST 23
Peak memory 195584 kb
Host smart-4e410657-2b19-4df4-bbec-c7d3d4e2ad78
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=455884424 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_smoke_no_pullup_pulldown.455884424
Directory /workspace/38.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/38.gpio_stress_all.914810062
Short name T292
Test name
Test status
Simulation time 11402804839 ps
CPU time 72.83 seconds
Started Dec 24 01:10:59 PM PST 23
Finished Dec 24 01:12:25 PM PST 23
Peak memory 198236 kb
Host smart-5b96702f-4501-4384-ba42-a097fb42e88b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=914810062 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.g
pio_stress_all.914810062
Directory /workspace/38.gpio_stress_all/latest

Test location /workspace/coverage/default/38.gpio_stress_all_with_rand_reset.3864886178
Short name T424
Test name
Test status
Simulation time 94247298767 ps
CPU time 1895.92 seconds
Started Dec 24 01:11:00 PM PST 23
Finished Dec 24 01:42:49 PM PST 23
Peak memory 198376 kb
Host smart-41f4da38-2834-409d-813b-da3a821827f0
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=3864886178 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_stress_all_with_rand_reset.3864886178
Directory /workspace/38.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/39.gpio_alert_test.1158457677
Short name T47
Test name
Test status
Simulation time 14145197 ps
CPU time 0.6 seconds
Started Dec 24 01:11:08 PM PST 23
Finished Dec 24 01:11:18 PM PST 23
Peak memory 194068 kb
Host smart-4d69f50d-bfa8-480c-a2bd-720fc66060f7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1158457677 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_alert_test.1158457677
Directory /workspace/39.gpio_alert_test/latest

Test location /workspace/coverage/default/39.gpio_dout_din_regs_random_rw.245689865
Short name T577
Test name
Test status
Simulation time 20449740 ps
CPU time 0.68 seconds
Started Dec 24 01:10:55 PM PST 23
Finished Dec 24 01:11:07 PM PST 23
Peak memory 194128 kb
Host smart-c540eb9f-e43e-4933-a9a8-7fd51494adc9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=245689865 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_dout_din_regs_random_rw.245689865
Directory /workspace/39.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/39.gpio_filter_stress.475089804
Short name T625
Test name
Test status
Simulation time 1232328611 ps
CPU time 8.26 seconds
Started Dec 24 01:11:11 PM PST 23
Finished Dec 24 01:11:28 PM PST 23
Peak memory 195664 kb
Host smart-09840531-c401-4c67-aad5-70ee7e278b9f
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=475089804 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_filter_stres
s.475089804
Directory /workspace/39.gpio_filter_stress/latest

Test location /workspace/coverage/default/39.gpio_full_random.1617073945
Short name T631
Test name
Test status
Simulation time 84263200 ps
CPU time 0.63 seconds
Started Dec 24 01:11:01 PM PST 23
Finished Dec 24 01:11:14 PM PST 23
Peak memory 194520 kb
Host smart-4200a61d-edd3-4721-b44e-7725aa48d54d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1617073945 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_full_random.1617073945
Directory /workspace/39.gpio_full_random/latest

Test location /workspace/coverage/default/39.gpio_intr_rand_pgm.777013185
Short name T854
Test name
Test status
Simulation time 23600221 ps
CPU time 0.8 seconds
Started Dec 24 01:10:58 PM PST 23
Finished Dec 24 01:11:12 PM PST 23
Peak memory 195672 kb
Host smart-87f058ac-b317-48ad-ae99-2dee2b45d767
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=777013185 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_intr_rand_pgm.777013185
Directory /workspace/39.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/39.gpio_intr_with_filter_rand_intr_event.2435649893
Short name T759
Test name
Test status
Simulation time 284489513 ps
CPU time 2.42 seconds
Started Dec 24 01:11:02 PM PST 23
Finished Dec 24 01:11:16 PM PST 23
Peak memory 198216 kb
Host smart-2879213d-41f0-4a08-b1a9-bd03db93104d
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2435649893 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 39.gpio_intr_with_filter_rand_intr_event.2435649893
Directory /workspace/39.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/39.gpio_rand_intr_trigger.2501360804
Short name T104
Test name
Test status
Simulation time 215809358 ps
CPU time 2.15 seconds
Started Dec 24 01:11:13 PM PST 23
Finished Dec 24 01:11:24 PM PST 23
Peak memory 198184 kb
Host smart-2fa90ff2-46ac-4d45-8985-9233e517845f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2501360804 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_rand_intr_trigger
.2501360804
Directory /workspace/39.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/39.gpio_random_dout_din.926155531
Short name T717
Test name
Test status
Simulation time 415837043 ps
CPU time 0.73 seconds
Started Dec 24 01:10:55 PM PST 23
Finished Dec 24 01:11:08 PM PST 23
Peak memory 196232 kb
Host smart-2af4b0d5-17c8-4948-9cdc-bf1f3b9e9485
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=926155531 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_random_dout_din.926155531
Directory /workspace/39.gpio_random_dout_din/latest

Test location /workspace/coverage/default/39.gpio_random_dout_din_no_pullup_pulldown.2581898364
Short name T263
Test name
Test status
Simulation time 53777658 ps
CPU time 1.05 seconds
Started Dec 24 01:11:00 PM PST 23
Finished Dec 24 01:11:14 PM PST 23
Peak memory 196088 kb
Host smart-7a75812f-6803-496f-88a6-68baff559278
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2581898364 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_random_dout_din_no_pullu
p_pulldown.2581898364
Directory /workspace/39.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/39.gpio_random_long_reg_writes_reg_reads.2181009256
Short name T780
Test name
Test status
Simulation time 201343760 ps
CPU time 1.55 seconds
Started Dec 24 01:11:09 PM PST 23
Finished Dec 24 01:11:19 PM PST 23
Peak memory 198068 kb
Host smart-9e86aa3c-feb5-4f0b-aa6c-2c0772c5c8d9
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2181009256 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_ra
ndom_long_reg_writes_reg_reads.2181009256
Directory /workspace/39.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/39.gpio_smoke.4227438305
Short name T400
Test name
Test status
Simulation time 58841627 ps
CPU time 1.13 seconds
Started Dec 24 01:11:04 PM PST 23
Finished Dec 24 01:11:16 PM PST 23
Peak memory 195952 kb
Host smart-ad027dc8-f2c9-4e7f-9728-374aa18a0527
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4227438305 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_smoke.4227438305
Directory /workspace/39.gpio_smoke/latest

Test location /workspace/coverage/default/39.gpio_smoke_no_pullup_pulldown.971542752
Short name T552
Test name
Test status
Simulation time 81187287 ps
CPU time 0.89 seconds
Started Dec 24 01:11:04 PM PST 23
Finished Dec 24 01:11:16 PM PST 23
Peak memory 196220 kb
Host smart-e4261a80-f1a6-4f9a-b0d9-3e8322417131
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=971542752 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_smoke_no_pullup_pulldown.971542752
Directory /workspace/39.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/39.gpio_stress_all.1001836623
Short name T541
Test name
Test status
Simulation time 57215869927 ps
CPU time 134.55 seconds
Started Dec 24 01:10:52 PM PST 23
Finished Dec 24 01:13:18 PM PST 23
Peak memory 198260 kb
Host smart-4bfbb4ae-3275-4896-a621-7579045e0068
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1001836623 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.
gpio_stress_all.1001836623
Directory /workspace/39.gpio_stress_all/latest

Test location /workspace/coverage/default/39.gpio_stress_all_with_rand_reset.691541636
Short name T66
Test name
Test status
Simulation time 29329865404 ps
CPU time 248.75 seconds
Started Dec 24 01:11:16 PM PST 23
Finished Dec 24 01:15:33 PM PST 23
Peak memory 198396 kb
Host smart-cafd9641-5544-4972-8ae4-32baf1960bd1
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=691541636 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_stress_all_with_rand_reset.691541636
Directory /workspace/39.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/4.gpio_alert_test.3776824612
Short name T356
Test name
Test status
Simulation time 14622850 ps
CPU time 0.58 seconds
Started Dec 24 01:10:04 PM PST 23
Finished Dec 24 01:10:09 PM PST 23
Peak memory 194136 kb
Host smart-ee3aa9d5-9743-4371-9d8d-b44219a0abda
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3776824612 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_alert_test.3776824612
Directory /workspace/4.gpio_alert_test/latest

Test location /workspace/coverage/default/4.gpio_dout_din_regs_random_rw.1514205708
Short name T245
Test name
Test status
Simulation time 28987485 ps
CPU time 0.89 seconds
Started Dec 24 01:10:24 PM PST 23
Finished Dec 24 01:10:28 PM PST 23
Peak memory 197424 kb
Host smart-c81df999-c85c-45f6-bc14-3c324cae57df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1514205708 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_dout_din_regs_random_rw.1514205708
Directory /workspace/4.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/4.gpio_filter_stress.12275950
Short name T741
Test name
Test status
Simulation time 480572144 ps
CPU time 5.8 seconds
Started Dec 24 01:10:31 PM PST 23
Finished Dec 24 01:10:40 PM PST 23
Peak memory 198112 kb
Host smart-03e58e1c-3258-4ff0-b614-ae6b219b725f
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12275950 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter_
stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_filter_stress.12275950
Directory /workspace/4.gpio_filter_stress/latest

Test location /workspace/coverage/default/4.gpio_full_random.2243210350
Short name T596
Test name
Test status
Simulation time 28405483 ps
CPU time 0.65 seconds
Started Dec 24 01:10:09 PM PST 23
Finished Dec 24 01:10:15 PM PST 23
Peak memory 194676 kb
Host smart-3c53e4a3-4b92-43d0-97fd-8b2cd5d60d36
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2243210350 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_full_random.2243210350
Directory /workspace/4.gpio_full_random/latest

Test location /workspace/coverage/default/4.gpio_intr_rand_pgm.3361497617
Short name T813
Test name
Test status
Simulation time 283545912 ps
CPU time 1.3 seconds
Started Dec 24 01:10:39 PM PST 23
Finished Dec 24 01:10:47 PM PST 23
Peak memory 197112 kb
Host smart-787200e3-ffd8-4b14-9345-e3046ff0c786
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3361497617 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_intr_rand_pgm.3361497617
Directory /workspace/4.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/4.gpio_intr_with_filter_rand_intr_event.2156202948
Short name T589
Test name
Test status
Simulation time 89796731 ps
CPU time 3.39 seconds
Started Dec 24 01:10:04 PM PST 23
Finished Dec 24 01:10:11 PM PST 23
Peak memory 198140 kb
Host smart-b4605e41-244a-4f6f-8860-26be9392ae4d
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2156202948 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 4.gpio_intr_with_filter_rand_intr_event.2156202948
Directory /workspace/4.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/4.gpio_rand_intr_trigger.3250621925
Short name T795
Test name
Test status
Simulation time 144713119 ps
CPU time 1.52 seconds
Started Dec 24 01:10:19 PM PST 23
Finished Dec 24 01:10:24 PM PST 23
Peak memory 196220 kb
Host smart-cc8cf368-6e7a-4309-b5d0-536db42f8d79
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3250621925 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_rand_intr_trigger.
3250621925
Directory /workspace/4.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/4.gpio_random_dout_din.3812787937
Short name T784
Test name
Test status
Simulation time 22311184 ps
CPU time 0.87 seconds
Started Dec 24 01:10:35 PM PST 23
Finished Dec 24 01:10:40 PM PST 23
Peak memory 196128 kb
Host smart-00600f98-415e-4f7a-baed-f179c8ba7f00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3812787937 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_random_dout_din.3812787937
Directory /workspace/4.gpio_random_dout_din/latest

Test location /workspace/coverage/default/4.gpio_random_dout_din_no_pullup_pulldown.456697662
Short name T739
Test name
Test status
Simulation time 44661314 ps
CPU time 1.24 seconds
Started Dec 24 01:10:39 PM PST 23
Finished Dec 24 01:10:48 PM PST 23
Peak memory 196592 kb
Host smart-48df3698-6277-4328-94a9-7bf9fd35c6e3
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=456697662 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_random_dout_din_no_pullup_
pulldown.456697662
Directory /workspace/4.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/4.gpio_random_long_reg_writes_reg_reads.2781419524
Short name T270
Test name
Test status
Simulation time 219316747 ps
CPU time 2.82 seconds
Started Dec 24 01:10:36 PM PST 23
Finished Dec 24 01:10:44 PM PST 23
Peak memory 198040 kb
Host smart-387a0671-ed5b-4ddb-9f84-608be0ee8316
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2781419524 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_ran
dom_long_reg_writes_reg_reads.2781419524
Directory /workspace/4.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/4.gpio_sec_cm.370270894
Short name T57
Test name
Test status
Simulation time 49736344 ps
CPU time 0.84 seconds
Started Dec 24 01:10:05 PM PST 23
Finished Dec 24 01:10:10 PM PST 23
Peak memory 213548 kb
Host smart-6aae749a-6e14-43a4-9a01-f236dce03e62
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=370270894 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_sec_cm.370270894
Directory /workspace/4.gpio_sec_cm/latest

Test location /workspace/coverage/default/4.gpio_smoke.4019085120
Short name T438
Test name
Test status
Simulation time 135267127 ps
CPU time 1.08 seconds
Started Dec 24 01:10:24 PM PST 23
Finished Dec 24 01:10:28 PM PST 23
Peak memory 195912 kb
Host smart-46c3380e-3f29-47c2-a519-8686c45d5553
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4019085120 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_smoke.4019085120
Directory /workspace/4.gpio_smoke/latest

Test location /workspace/coverage/default/4.gpio_smoke_no_pullup_pulldown.3716016274
Short name T380
Test name
Test status
Simulation time 25239342 ps
CPU time 0.78 seconds
Started Dec 24 01:10:31 PM PST 23
Finished Dec 24 01:10:35 PM PST 23
Peak memory 195220 kb
Host smart-b6a60f07-156b-4aa3-b547-12e1373b99da
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3716016274 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_smoke_no_pullup_pulldown.3716016274
Directory /workspace/4.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/4.gpio_stress_all.1954229008
Short name T381
Test name
Test status
Simulation time 11408214240 ps
CPU time 125.32 seconds
Started Dec 24 01:09:51 PM PST 23
Finished Dec 24 01:12:02 PM PST 23
Peak memory 198220 kb
Host smart-2a81789f-6c40-48e3-917b-a6a8ddf24e8e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1954229008 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.g
pio_stress_all.1954229008
Directory /workspace/4.gpio_stress_all/latest

Test location /workspace/coverage/default/4.gpio_stress_all_with_rand_reset.1689875162
Short name T715
Test name
Test status
Simulation time 48614471373 ps
CPU time 848.1 seconds
Started Dec 24 01:10:03 PM PST 23
Finished Dec 24 01:24:16 PM PST 23
Peak memory 198408 kb
Host smart-c6ca410f-7364-47e0-89d4-639477695e9c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=1689875162 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_stress_all_with_rand_reset.1689875162
Directory /workspace/4.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/40.gpio_alert_test.3848536651
Short name T719
Test name
Test status
Simulation time 14510578 ps
CPU time 0.57 seconds
Started Dec 24 01:11:00 PM PST 23
Finished Dec 24 01:11:13 PM PST 23
Peak memory 194076 kb
Host smart-97534c12-be20-4a49-bbb6-8738dabdf9d0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3848536651 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_alert_test.3848536651
Directory /workspace/40.gpio_alert_test/latest

Test location /workspace/coverage/default/40.gpio_dout_din_regs_random_rw.3601859496
Short name T247
Test name
Test status
Simulation time 85015263 ps
CPU time 0.69 seconds
Started Dec 24 01:11:17 PM PST 23
Finished Dec 24 01:11:26 PM PST 23
Peak memory 196008 kb
Host smart-7be6a807-0a8d-4a98-89a3-f6b965ee0f34
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3601859496 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_dout_din_regs_random_rw.3601859496
Directory /workspace/40.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/40.gpio_filter_stress.654197857
Short name T338
Test name
Test status
Simulation time 1978060787 ps
CPU time 24.81 seconds
Started Dec 24 01:10:55 PM PST 23
Finished Dec 24 01:11:32 PM PST 23
Peak memory 196720 kb
Host smart-5c4c4598-a721-45d2-841d-301097ce2f04
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=654197857 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_filter_stres
s.654197857
Directory /workspace/40.gpio_filter_stress/latest

Test location /workspace/coverage/default/40.gpio_full_random.109814028
Short name T409
Test name
Test status
Simulation time 101915931 ps
CPU time 1.07 seconds
Started Dec 24 01:10:58 PM PST 23
Finished Dec 24 01:11:12 PM PST 23
Peak memory 198176 kb
Host smart-ffa09b07-1e54-41ae-9b50-249a8fa50e70
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=109814028 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_full_random.109814028
Directory /workspace/40.gpio_full_random/latest

Test location /workspace/coverage/default/40.gpio_intr_rand_pgm.647643650
Short name T461
Test name
Test status
Simulation time 57799220 ps
CPU time 0.76 seconds
Started Dec 24 01:11:27 PM PST 23
Finished Dec 24 01:11:34 PM PST 23
Peak memory 196320 kb
Host smart-f923a556-e9ec-4b86-93c8-9c6ce0a19eff
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=647643650 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_intr_rand_pgm.647643650
Directory /workspace/40.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/40.gpio_intr_with_filter_rand_intr_event.66443767
Short name T534
Test name
Test status
Simulation time 73653591 ps
CPU time 2.7 seconds
Started Dec 24 01:11:19 PM PST 23
Finished Dec 24 01:11:30 PM PST 23
Peak memory 198260 kb
Host smart-1e177680-bb6e-421d-8ef0-5f11286b24fb
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=66443767 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_S
EQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 40.gpio_intr_with_filter_rand_intr_event.66443767
Directory /workspace/40.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/40.gpio_rand_intr_trigger.2336749236
Short name T303
Test name
Test status
Simulation time 108889550 ps
CPU time 1.76 seconds
Started Dec 24 01:11:15 PM PST 23
Finished Dec 24 01:11:25 PM PST 23
Peak memory 196864 kb
Host smart-af11dbc4-3d4c-481e-ad7e-7064b88f5e20
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2336749236 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_rand_intr_trigger
.2336749236
Directory /workspace/40.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/40.gpio_random_dout_din.3593978083
Short name T375
Test name
Test status
Simulation time 101194385 ps
CPU time 1.03 seconds
Started Dec 24 01:11:15 PM PST 23
Finished Dec 24 01:11:24 PM PST 23
Peak memory 195848 kb
Host smart-6ac906d4-5aaf-4b4e-b973-66407eb82f51
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3593978083 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_random_dout_din.3593978083
Directory /workspace/40.gpio_random_dout_din/latest

Test location /workspace/coverage/default/40.gpio_random_dout_din_no_pullup_pulldown.2010184238
Short name T724
Test name
Test status
Simulation time 100828606 ps
CPU time 1.34 seconds
Started Dec 24 01:11:07 PM PST 23
Finished Dec 24 01:11:18 PM PST 23
Peak memory 198172 kb
Host smart-a3423a4d-4c0e-4bbe-966d-657dbe772d28
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2010184238 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_random_dout_din_no_pullu
p_pulldown.2010184238
Directory /workspace/40.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/40.gpio_random_long_reg_writes_reg_reads.1851610233
Short name T386
Test name
Test status
Simulation time 722645352 ps
CPU time 4.9 seconds
Started Dec 24 01:11:12 PM PST 23
Finished Dec 24 01:11:25 PM PST 23
Peak memory 198092 kb
Host smart-9bca2f12-1687-4924-b183-b577e72dced3
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1851610233 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_ra
ndom_long_reg_writes_reg_reads.1851610233
Directory /workspace/40.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/40.gpio_smoke.1440242154
Short name T215
Test name
Test status
Simulation time 262125940 ps
CPU time 0.99 seconds
Started Dec 24 01:11:14 PM PST 23
Finished Dec 24 01:11:23 PM PST 23
Peak memory 195928 kb
Host smart-b7fb59ff-2515-4a96-ae65-9c332fac51f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1440242154 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_smoke.1440242154
Directory /workspace/40.gpio_smoke/latest

Test location /workspace/coverage/default/40.gpio_smoke_no_pullup_pulldown.3565723484
Short name T302
Test name
Test status
Simulation time 184305223 ps
CPU time 1.44 seconds
Started Dec 24 01:11:03 PM PST 23
Finished Dec 24 01:11:16 PM PST 23
Peak memory 195680 kb
Host smart-af75573d-13de-4f1f-81b3-8a777c2f7313
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3565723484 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_smoke_no_pullup_pulldown.3565723484
Directory /workspace/40.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/40.gpio_stress_all.2722215492
Short name T489
Test name
Test status
Simulation time 4821204382 ps
CPU time 54.61 seconds
Started Dec 24 01:11:01 PM PST 23
Finished Dec 24 01:12:08 PM PST 23
Peak memory 198168 kb
Host smart-348df428-3f7a-441c-ab4b-0146ce01b45a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2722215492 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.
gpio_stress_all.2722215492
Directory /workspace/40.gpio_stress_all/latest

Test location /workspace/coverage/default/40.gpio_stress_all_with_rand_reset.3913700183
Short name T794
Test name
Test status
Simulation time 380559715401 ps
CPU time 1572.58 seconds
Started Dec 24 01:11:13 PM PST 23
Finished Dec 24 01:37:34 PM PST 23
Peak memory 198232 kb
Host smart-b123df36-e697-4595-803b-ed6397e33834
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=3913700183 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_stress_all_with_rand_reset.3913700183
Directory /workspace/40.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/41.gpio_alert_test.3597617828
Short name T666
Test name
Test status
Simulation time 29024285 ps
CPU time 0.54 seconds
Started Dec 24 01:11:07 PM PST 23
Finished Dec 24 01:11:17 PM PST 23
Peak memory 192796 kb
Host smart-2784ed77-78fb-4175-927b-cba64c7baabb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3597617828 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_alert_test.3597617828
Directory /workspace/41.gpio_alert_test/latest

Test location /workspace/coverage/default/41.gpio_dout_din_regs_random_rw.2250859021
Short name T404
Test name
Test status
Simulation time 27210964 ps
CPU time 0.66 seconds
Started Dec 24 01:11:13 PM PST 23
Finished Dec 24 01:11:21 PM PST 23
Peak memory 194080 kb
Host smart-9aa47833-2771-4841-8941-6384ba964f2a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2250859021 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_dout_din_regs_random_rw.2250859021
Directory /workspace/41.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/41.gpio_filter_stress.1692336931
Short name T721
Test name
Test status
Simulation time 372277325 ps
CPU time 14.04 seconds
Started Dec 24 01:11:06 PM PST 23
Finished Dec 24 01:11:30 PM PST 23
Peak memory 197228 kb
Host smart-8a8a5e34-05ec-4094-a113-88e29766743c
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1692336931 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_filter_stre
ss.1692336931
Directory /workspace/41.gpio_filter_stress/latest

Test location /workspace/coverage/default/41.gpio_full_random.2228832626
Short name T597
Test name
Test status
Simulation time 137273306 ps
CPU time 1.06 seconds
Started Dec 24 01:11:03 PM PST 23
Finished Dec 24 01:11:15 PM PST 23
Peak memory 196976 kb
Host smart-a6603733-f503-4aa6-8b03-372d5308b0b6
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2228832626 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_full_random.2228832626
Directory /workspace/41.gpio_full_random/latest

Test location /workspace/coverage/default/41.gpio_intr_rand_pgm.777711804
Short name T519
Test name
Test status
Simulation time 22768531 ps
CPU time 0.67 seconds
Started Dec 24 01:11:26 PM PST 23
Finished Dec 24 01:11:34 PM PST 23
Peak memory 194996 kb
Host smart-8111b0c8-ffb9-4426-b39b-75612cbf9d1b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=777711804 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_intr_rand_pgm.777711804
Directory /workspace/41.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/41.gpio_intr_with_filter_rand_intr_event.1685220103
Short name T881
Test name
Test status
Simulation time 69538745 ps
CPU time 1.55 seconds
Started Dec 24 01:11:15 PM PST 23
Finished Dec 24 01:11:25 PM PST 23
Peak memory 198148 kb
Host smart-bdb66b6d-b5a9-4cc5-87e3-9567a525503d
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1685220103 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 41.gpio_intr_with_filter_rand_intr_event.1685220103
Directory /workspace/41.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/41.gpio_rand_intr_trigger.1672257784
Short name T862
Test name
Test status
Simulation time 195909007 ps
CPU time 1.56 seconds
Started Dec 24 01:11:04 PM PST 23
Finished Dec 24 01:11:16 PM PST 23
Peak memory 196112 kb
Host smart-ea955a9c-664b-4281-90bb-0ebf220a8a5f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1672257784 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_rand_intr_trigger
.1672257784
Directory /workspace/41.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/41.gpio_random_dout_din.1715818439
Short name T223
Test name
Test status
Simulation time 231025916 ps
CPU time 1.26 seconds
Started Dec 24 01:11:12 PM PST 23
Finished Dec 24 01:11:21 PM PST 23
Peak memory 197204 kb
Host smart-e48eefab-844a-4686-a8fa-e7a7f08f9ec1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1715818439 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_random_dout_din.1715818439
Directory /workspace/41.gpio_random_dout_din/latest

Test location /workspace/coverage/default/41.gpio_random_dout_din_no_pullup_pulldown.2982260253
Short name T222
Test name
Test status
Simulation time 67965193 ps
CPU time 1.18 seconds
Started Dec 24 01:10:59 PM PST 23
Finished Dec 24 01:11:13 PM PST 23
Peak memory 196948 kb
Host smart-c6329b47-fccf-47a4-815d-9a3489fb75f4
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2982260253 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_random_dout_din_no_pullu
p_pulldown.2982260253
Directory /workspace/41.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/41.gpio_random_long_reg_writes_reg_reads.3097072122
Short name T863
Test name
Test status
Simulation time 906432203 ps
CPU time 3.83 seconds
Started Dec 24 01:11:00 PM PST 23
Finished Dec 24 01:11:16 PM PST 23
Peak memory 197188 kb
Host smart-add8eaf7-f370-4bdb-b49a-8dd0607d71f8
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3097072122 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_ra
ndom_long_reg_writes_reg_reads.3097072122
Directory /workspace/41.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/41.gpio_smoke.199129341
Short name T265
Test name
Test status
Simulation time 61535967 ps
CPU time 1.06 seconds
Started Dec 24 01:11:28 PM PST 23
Finished Dec 24 01:11:36 PM PST 23
Peak memory 195768 kb
Host smart-93783c56-7d0a-45c5-ab9c-4a43ef0703cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=199129341 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_smoke.199129341
Directory /workspace/41.gpio_smoke/latest

Test location /workspace/coverage/default/41.gpio_smoke_no_pullup_pulldown.3979251000
Short name T742
Test name
Test status
Simulation time 124667238 ps
CPU time 0.84 seconds
Started Dec 24 01:11:11 PM PST 23
Finished Dec 24 01:11:20 PM PST 23
Peak memory 196296 kb
Host smart-adce4fc1-713a-4821-9e96-8987f084125e
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3979251000 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_smoke_no_pullup_pulldown.3979251000
Directory /workspace/41.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/41.gpio_stress_all.1787455930
Short name T394
Test name
Test status
Simulation time 34201976827 ps
CPU time 58.84 seconds
Started Dec 24 01:11:00 PM PST 23
Finished Dec 24 01:12:11 PM PST 23
Peak memory 198264 kb
Host smart-73594475-b2f6-4399-92d1-5beda4745e12
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1787455930 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.
gpio_stress_all.1787455930
Directory /workspace/41.gpio_stress_all/latest

Test location /workspace/coverage/default/41.gpio_stress_all_with_rand_reset.2139300184
Short name T315
Test name
Test status
Simulation time 913945158192 ps
CPU time 1782.88 seconds
Started Dec 24 01:11:26 PM PST 23
Finished Dec 24 01:41:16 PM PST 23
Peak memory 198360 kb
Host smart-ff277877-a9f5-4686-a216-4344c38e0030
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=2139300184 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_stress_all_with_rand_reset.2139300184
Directory /workspace/41.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/42.gpio_alert_test.3142935208
Short name T752
Test name
Test status
Simulation time 13042288 ps
CPU time 0.56 seconds
Started Dec 24 01:10:56 PM PST 23
Finished Dec 24 01:11:08 PM PST 23
Peak memory 194052 kb
Host smart-a9cdf573-586f-47c5-8eac-29ec5dc7a263
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3142935208 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_alert_test.3142935208
Directory /workspace/42.gpio_alert_test/latest

Test location /workspace/coverage/default/42.gpio_dout_din_regs_random_rw.2918192610
Short name T880
Test name
Test status
Simulation time 30219550 ps
CPU time 0.71 seconds
Started Dec 24 01:11:02 PM PST 23
Finished Dec 24 01:11:14 PM PST 23
Peak memory 195328 kb
Host smart-aedd5af1-0627-406f-ad5f-5f18528fe873
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2918192610 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_dout_din_regs_random_rw.2918192610
Directory /workspace/42.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/42.gpio_filter_stress.2286794616
Short name T720
Test name
Test status
Simulation time 292599541 ps
CPU time 8.76 seconds
Started Dec 24 01:11:00 PM PST 23
Finished Dec 24 01:11:21 PM PST 23
Peak memory 195572 kb
Host smart-6d591db8-7de4-41f0-a8f5-2815190cc738
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2286794616 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_filter_stre
ss.2286794616
Directory /workspace/42.gpio_filter_stress/latest

Test location /workspace/coverage/default/42.gpio_full_random.3203205028
Short name T43
Test name
Test status
Simulation time 64473697 ps
CPU time 0.89 seconds
Started Dec 24 01:11:26 PM PST 23
Finished Dec 24 01:11:34 PM PST 23
Peak memory 196096 kb
Host smart-137b6867-71d2-4448-b0a5-2ae950287d0a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3203205028 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_full_random.3203205028
Directory /workspace/42.gpio_full_random/latest

Test location /workspace/coverage/default/42.gpio_intr_rand_pgm.2518545318
Short name T460
Test name
Test status
Simulation time 277638372 ps
CPU time 1.09 seconds
Started Dec 24 01:10:51 PM PST 23
Finished Dec 24 01:11:02 PM PST 23
Peak memory 196016 kb
Host smart-5999bc43-78a5-433b-b937-ade97bb86acf
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2518545318 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_intr_rand_pgm.2518545318
Directory /workspace/42.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/42.gpio_intr_with_filter_rand_intr_event.3823668082
Short name T727
Test name
Test status
Simulation time 173144196 ps
CPU time 1.12 seconds
Started Dec 24 01:11:14 PM PST 23
Finished Dec 24 01:11:24 PM PST 23
Peak memory 197324 kb
Host smart-81e8995a-bbdb-4442-a94b-b940168332ff
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3823668082 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 42.gpio_intr_with_filter_rand_intr_event.3823668082
Directory /workspace/42.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/42.gpio_rand_intr_trigger.106811114
Short name T839
Test name
Test status
Simulation time 1001474230 ps
CPU time 2.06 seconds
Started Dec 24 01:10:56 PM PST 23
Finished Dec 24 01:11:10 PM PST 23
Peak memory 196260 kb
Host smart-5ea1a63d-de40-4631-bbe0-866995a938c1
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=106811114 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_rand_intr_trigger.
106811114
Directory /workspace/42.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/42.gpio_random_dout_din.3627450551
Short name T782
Test name
Test status
Simulation time 678285874 ps
CPU time 1.31 seconds
Started Dec 24 01:11:12 PM PST 23
Finished Dec 24 01:11:21 PM PST 23
Peak memory 198156 kb
Host smart-44ae5a16-1886-42f1-b670-26a6c8780ff6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3627450551 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_random_dout_din.3627450551
Directory /workspace/42.gpio_random_dout_din/latest

Test location /workspace/coverage/default/42.gpio_random_dout_din_no_pullup_pulldown.3248980436
Short name T762
Test name
Test status
Simulation time 193857488 ps
CPU time 1.19 seconds
Started Dec 24 01:10:56 PM PST 23
Finished Dec 24 01:11:09 PM PST 23
Peak memory 196080 kb
Host smart-47b6d658-c49e-4976-ba4f-3c6e52f52843
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3248980436 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_random_dout_din_no_pullu
p_pulldown.3248980436
Directory /workspace/42.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/42.gpio_random_long_reg_writes_reg_reads.2567782691
Short name T683
Test name
Test status
Simulation time 150947327 ps
CPU time 2.05 seconds
Started Dec 24 01:11:26 PM PST 23
Finished Dec 24 01:11:35 PM PST 23
Peak memory 198072 kb
Host smart-a4320347-dfd2-4c13-bd6a-99a905f8000d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2567782691 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_ra
ndom_long_reg_writes_reg_reads.2567782691
Directory /workspace/42.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/42.gpio_smoke.2468670148
Short name T649
Test name
Test status
Simulation time 250106618 ps
CPU time 1.13 seconds
Started Dec 24 01:10:56 PM PST 23
Finished Dec 24 01:11:09 PM PST 23
Peak memory 195620 kb
Host smart-67181fd0-41d7-44a5-b65b-fd5ab1294125
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2468670148 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_smoke.2468670148
Directory /workspace/42.gpio_smoke/latest

Test location /workspace/coverage/default/42.gpio_smoke_no_pullup_pulldown.3138781746
Short name T333
Test name
Test status
Simulation time 23455257 ps
CPU time 0.74 seconds
Started Dec 24 01:11:10 PM PST 23
Finished Dec 24 01:11:20 PM PST 23
Peak memory 194176 kb
Host smart-acd5dd25-54aa-4fce-a466-53c40bc82083
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3138781746 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_smoke_no_pullup_pulldown.3138781746
Directory /workspace/42.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/42.gpio_stress_all.3805552218
Short name T422
Test name
Test status
Simulation time 6496512321 ps
CPU time 68.28 seconds
Started Dec 24 01:11:03 PM PST 23
Finished Dec 24 01:12:23 PM PST 23
Peak memory 198252 kb
Host smart-17ecc541-d1f3-49f8-915c-18e1d85b4d5f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3805552218 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.
gpio_stress_all.3805552218
Directory /workspace/42.gpio_stress_all/latest

Test location /workspace/coverage/default/42.gpio_stress_all_with_rand_reset.368893502
Short name T841
Test name
Test status
Simulation time 52816345640 ps
CPU time 348.02 seconds
Started Dec 24 01:10:59 PM PST 23
Finished Dec 24 01:17:00 PM PST 23
Peak memory 198404 kb
Host smart-9e9b1489-968a-4605-8a85-94e0232f1a15
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=368893502 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_stress_all_with_rand_reset.368893502
Directory /workspace/42.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/43.gpio_alert_test.3242310290
Short name T761
Test name
Test status
Simulation time 12495185 ps
CPU time 0.59 seconds
Started Dec 24 01:11:12 PM PST 23
Finished Dec 24 01:11:20 PM PST 23
Peak memory 194312 kb
Host smart-843e1b5c-1f46-4e86-8c4f-9d56f03631fe
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3242310290 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_alert_test.3242310290
Directory /workspace/43.gpio_alert_test/latest

Test location /workspace/coverage/default/43.gpio_dout_din_regs_random_rw.3445139998
Short name T478
Test name
Test status
Simulation time 142260320 ps
CPU time 0.77 seconds
Started Dec 24 01:10:58 PM PST 23
Finished Dec 24 01:11:10 PM PST 23
Peak memory 195316 kb
Host smart-6f16a469-f627-4ee9-8567-bd7d987772fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3445139998 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_dout_din_regs_random_rw.3445139998
Directory /workspace/43.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/43.gpio_filter_stress.1981479998
Short name T364
Test name
Test status
Simulation time 436101645 ps
CPU time 14.63 seconds
Started Dec 24 01:11:19 PM PST 23
Finished Dec 24 01:11:42 PM PST 23
Peak memory 197028 kb
Host smart-82e9dbd4-0cd4-4f73-831a-6cc74279befa
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1981479998 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_filter_stre
ss.1981479998
Directory /workspace/43.gpio_filter_stress/latest

Test location /workspace/coverage/default/43.gpio_full_random.1244114670
Short name T595
Test name
Test status
Simulation time 25704184 ps
CPU time 0.63 seconds
Started Dec 24 01:11:31 PM PST 23
Finished Dec 24 01:11:39 PM PST 23
Peak memory 194496 kb
Host smart-76fdf629-b27c-4495-8f6e-7c84808104bc
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1244114670 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_full_random.1244114670
Directory /workspace/43.gpio_full_random/latest

Test location /workspace/coverage/default/43.gpio_intr_rand_pgm.1486627876
Short name T413
Test name
Test status
Simulation time 24417007 ps
CPU time 0.7 seconds
Started Dec 24 01:11:15 PM PST 23
Finished Dec 24 01:11:24 PM PST 23
Peak memory 195192 kb
Host smart-e5566c96-f3ea-4fcd-bdc8-d2d3d58830b3
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1486627876 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_intr_rand_pgm.1486627876
Directory /workspace/43.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/43.gpio_intr_with_filter_rand_intr_event.3757757261
Short name T803
Test name
Test status
Simulation time 313006133 ps
CPU time 0.98 seconds
Started Dec 24 01:11:27 PM PST 23
Finished Dec 24 01:11:35 PM PST 23
Peak memory 196460 kb
Host smart-cfb172f8-fa8c-4ba9-905f-ea0da957f512
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3757757261 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 43.gpio_intr_with_filter_rand_intr_event.3757757261
Directory /workspace/43.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/43.gpio_rand_intr_trigger.2016663943
Short name T836
Test name
Test status
Simulation time 103300479 ps
CPU time 1.89 seconds
Started Dec 24 01:11:05 PM PST 23
Finished Dec 24 01:11:17 PM PST 23
Peak memory 195892 kb
Host smart-619b7642-821c-4dbf-8515-61771687ab2a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2016663943 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_rand_intr_trigger
.2016663943
Directory /workspace/43.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/43.gpio_random_dout_din.3533571067
Short name T591
Test name
Test status
Simulation time 53780004 ps
CPU time 0.66 seconds
Started Dec 24 01:11:14 PM PST 23
Finished Dec 24 01:11:24 PM PST 23
Peak memory 194420 kb
Host smart-3960e822-d2ad-4a34-9bc5-c5e124ddf77b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3533571067 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_random_dout_din.3533571067
Directory /workspace/43.gpio_random_dout_din/latest

Test location /workspace/coverage/default/43.gpio_random_dout_din_no_pullup_pulldown.85762930
Short name T459
Test name
Test status
Simulation time 84137826 ps
CPU time 0.88 seconds
Started Dec 24 01:11:09 PM PST 23
Finished Dec 24 01:11:19 PM PST 23
Peak memory 195924 kb
Host smart-93a8f546-bcb5-44c7-a9a3-5b7a34007a5a
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=85762930 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_random_dout_din_no_pullup_
pulldown.85762930
Directory /workspace/43.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/43.gpio_random_long_reg_writes_reg_reads.495137615
Short name T458
Test name
Test status
Simulation time 5124138499 ps
CPU time 6.61 seconds
Started Dec 24 01:11:16 PM PST 23
Finished Dec 24 01:11:31 PM PST 23
Peak memory 198196 kb
Host smart-941d327b-0e4e-4fb1-b7d6-4e0f490c7f9a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=495137615 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_ran
dom_long_reg_writes_reg_reads.495137615
Directory /workspace/43.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/43.gpio_smoke.420269344
Short name T446
Test name
Test status
Simulation time 94144645 ps
CPU time 0.91 seconds
Started Dec 24 01:11:28 PM PST 23
Finished Dec 24 01:11:36 PM PST 23
Peak memory 195792 kb
Host smart-04146169-1b0e-49a3-8f4c-0d406692c6e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=420269344 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_smoke.420269344
Directory /workspace/43.gpio_smoke/latest

Test location /workspace/coverage/default/43.gpio_smoke_no_pullup_pulldown.396053506
Short name T714
Test name
Test status
Simulation time 169609134 ps
CPU time 1.3 seconds
Started Dec 24 01:10:58 PM PST 23
Finished Dec 24 01:11:11 PM PST 23
Peak memory 196844 kb
Host smart-ca8f9e9d-ce85-48a0-9c5b-3f5f5d2e3e57
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=396053506 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_smoke_no_pullup_pulldown.396053506
Directory /workspace/43.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/43.gpio_stress_all.1966030519
Short name T228
Test name
Test status
Simulation time 6488896137 ps
CPU time 174.31 seconds
Started Dec 24 01:11:12 PM PST 23
Finished Dec 24 01:14:14 PM PST 23
Peak memory 198172 kb
Host smart-16492e00-a2a9-4c25-be26-670ce9032052
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1966030519 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.
gpio_stress_all.1966030519
Directory /workspace/43.gpio_stress_all/latest

Test location /workspace/coverage/default/43.gpio_stress_all_with_rand_reset.3773566516
Short name T556
Test name
Test status
Simulation time 83927951081 ps
CPU time 1131.51 seconds
Started Dec 24 01:11:12 PM PST 23
Finished Dec 24 01:30:11 PM PST 23
Peak memory 198336 kb
Host smart-ca9525bc-0459-444b-8bda-56b1493a7c18
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=3773566516 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_stress_all_with_rand_reset.3773566516
Directory /workspace/43.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/44.gpio_alert_test.3250590290
Short name T525
Test name
Test status
Simulation time 21101333 ps
CPU time 0.57 seconds
Started Dec 24 01:11:17 PM PST 23
Finished Dec 24 01:11:26 PM PST 23
Peak memory 194036 kb
Host smart-5468051d-3c2f-40df-9558-58dd7188f9d9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3250590290 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_alert_test.3250590290
Directory /workspace/44.gpio_alert_test/latest

Test location /workspace/coverage/default/44.gpio_dout_din_regs_random_rw.1963883233
Short name T510
Test name
Test status
Simulation time 31778977 ps
CPU time 0.73 seconds
Started Dec 24 01:11:31 PM PST 23
Finished Dec 24 01:11:40 PM PST 23
Peak memory 194340 kb
Host smart-77edfc96-372d-4bf7-b6c3-d9a4512c3f41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1963883233 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_dout_din_regs_random_rw.1963883233
Directory /workspace/44.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/44.gpio_filter_stress.1409941150
Short name T604
Test name
Test status
Simulation time 2414382469 ps
CPU time 20.23 seconds
Started Dec 24 01:11:18 PM PST 23
Finished Dec 24 01:11:47 PM PST 23
Peak memory 197116 kb
Host smart-b46cf97b-7f8b-46d4-b0df-e912ef1db3a9
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1409941150 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_filter_stre
ss.1409941150
Directory /workspace/44.gpio_filter_stress/latest

Test location /workspace/coverage/default/44.gpio_full_random.1589380566
Short name T611
Test name
Test status
Simulation time 320590865 ps
CPU time 0.84 seconds
Started Dec 24 01:11:15 PM PST 23
Finished Dec 24 01:11:24 PM PST 23
Peak memory 196004 kb
Host smart-a773b2af-622c-4fa6-b64e-4ea65299060c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1589380566 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_full_random.1589380566
Directory /workspace/44.gpio_full_random/latest

Test location /workspace/coverage/default/44.gpio_intr_rand_pgm.2067639287
Short name T678
Test name
Test status
Simulation time 22625771 ps
CPU time 0.74 seconds
Started Dec 24 01:11:18 PM PST 23
Finished Dec 24 01:11:27 PM PST 23
Peak memory 195472 kb
Host smart-b0efdcfc-de81-4fe4-81d2-29e5652c807e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2067639287 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_intr_rand_pgm.2067639287
Directory /workspace/44.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/44.gpio_intr_with_filter_rand_intr_event.809033228
Short name T300
Test name
Test status
Simulation time 72562748 ps
CPU time 2.6 seconds
Started Dec 24 01:11:23 PM PST 23
Finished Dec 24 01:11:33 PM PST 23
Peak memory 196568 kb
Host smart-04f2ec41-62fd-4373-b46c-fedda07bc52a
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=809033228 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 44.gpio_intr_with_filter_rand_intr_event.809033228
Directory /workspace/44.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/44.gpio_rand_intr_trigger.1531691060
Short name T283
Test name
Test status
Simulation time 175932646 ps
CPU time 1.47 seconds
Started Dec 24 01:11:17 PM PST 23
Finished Dec 24 01:11:27 PM PST 23
Peak memory 196836 kb
Host smart-dbbee501-c09a-4ca1-b0d1-6315c5219ada
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1531691060 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_rand_intr_trigger
.1531691060
Directory /workspace/44.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/44.gpio_random_dout_din.3783359905
Short name T602
Test name
Test status
Simulation time 53219554 ps
CPU time 0.98 seconds
Started Dec 24 01:11:06 PM PST 23
Finished Dec 24 01:11:17 PM PST 23
Peak memory 196852 kb
Host smart-724a6d22-599c-4e54-843d-4179c43a5490
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3783359905 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_random_dout_din.3783359905
Directory /workspace/44.gpio_random_dout_din/latest

Test location /workspace/coverage/default/44.gpio_random_dout_din_no_pullup_pulldown.4144873357
Short name T32
Test name
Test status
Simulation time 27135400 ps
CPU time 0.77 seconds
Started Dec 24 01:11:11 PM PST 23
Finished Dec 24 01:11:20 PM PST 23
Peak memory 196096 kb
Host smart-1e6af16b-a3ab-466a-8d2c-9b5823358912
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4144873357 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_random_dout_din_no_pullu
p_pulldown.4144873357
Directory /workspace/44.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/44.gpio_random_long_reg_writes_reg_reads.1768642476
Short name T603
Test name
Test status
Simulation time 223447797 ps
CPU time 1.86 seconds
Started Dec 24 01:11:08 PM PST 23
Finished Dec 24 01:11:19 PM PST 23
Peak memory 197980 kb
Host smart-59acc9f3-6554-414f-8d2b-9d8cfcc3ac2c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1768642476 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_ra
ndom_long_reg_writes_reg_reads.1768642476
Directory /workspace/44.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/44.gpio_smoke.3104468340
Short name T559
Test name
Test status
Simulation time 58600131 ps
CPU time 0.97 seconds
Started Dec 24 01:11:09 PM PST 23
Finished Dec 24 01:11:19 PM PST 23
Peak memory 196508 kb
Host smart-2a958f30-6458-4212-941f-bf0e4afb8ca1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3104468340 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_smoke.3104468340
Directory /workspace/44.gpio_smoke/latest

Test location /workspace/coverage/default/44.gpio_smoke_no_pullup_pulldown.3512759226
Short name T336
Test name
Test status
Simulation time 154433432 ps
CPU time 1.08 seconds
Started Dec 24 01:11:20 PM PST 23
Finished Dec 24 01:11:29 PM PST 23
Peak memory 195920 kb
Host smart-88803c12-552f-4940-b697-17422f0efaca
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3512759226 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_smoke_no_pullup_pulldown.3512759226
Directory /workspace/44.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/44.gpio_stress_all.3404931918
Short name T617
Test name
Test status
Simulation time 46696558845 ps
CPU time 171.94 seconds
Started Dec 24 01:11:19 PM PST 23
Finished Dec 24 01:14:20 PM PST 23
Peak memory 198260 kb
Host smart-69a1fc8b-5c07-44fc-82d3-39e9f271931a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3404931918 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.
gpio_stress_all.3404931918
Directory /workspace/44.gpio_stress_all/latest

Test location /workspace/coverage/default/44.gpio_stress_all_with_rand_reset.2769963020
Short name T426
Test name
Test status
Simulation time 35026494074 ps
CPU time 935.77 seconds
Started Dec 24 01:11:16 PM PST 23
Finished Dec 24 01:27:01 PM PST 23
Peak memory 198412 kb
Host smart-04996d7d-d8a0-43da-9202-49ce260a8fde
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=2769963020 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_stress_all_with_rand_reset.2769963020
Directory /workspace/44.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/45.gpio_alert_test.3705995696
Short name T310
Test name
Test status
Simulation time 15052961 ps
CPU time 0.59 seconds
Started Dec 24 01:11:40 PM PST 23
Finished Dec 24 01:11:53 PM PST 23
Peak memory 193964 kb
Host smart-5410d7ae-546b-4c9a-8f02-bbad1be8f92e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3705995696 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_alert_test.3705995696
Directory /workspace/45.gpio_alert_test/latest

Test location /workspace/coverage/default/45.gpio_dout_din_regs_random_rw.347363213
Short name T284
Test name
Test status
Simulation time 22250819 ps
CPU time 0.74 seconds
Started Dec 24 01:11:31 PM PST 23
Finished Dec 24 01:11:39 PM PST 23
Peak memory 195412 kb
Host smart-58d50e27-255c-4ae0-9fab-74fff87d6789
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=347363213 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_dout_din_regs_random_rw.347363213
Directory /workspace/45.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/45.gpio_filter_stress.1092184818
Short name T272
Test name
Test status
Simulation time 70817792 ps
CPU time 3.83 seconds
Started Dec 24 01:11:38 PM PST 23
Finished Dec 24 01:11:55 PM PST 23
Peak memory 195764 kb
Host smart-6d5eae4a-34ca-48f2-ad70-be7636bded1e
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1092184818 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_filter_stre
ss.1092184818
Directory /workspace/45.gpio_filter_stress/latest

Test location /workspace/coverage/default/45.gpio_full_random.2999306129
Short name T593
Test name
Test status
Simulation time 69653463 ps
CPU time 0.78 seconds
Started Dec 24 01:11:36 PM PST 23
Finished Dec 24 01:11:49 PM PST 23
Peak memory 196056 kb
Host smart-c400303f-090e-48ff-b9ff-bad1a8d780c5
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2999306129 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_full_random.2999306129
Directory /workspace/45.gpio_full_random/latest

Test location /workspace/coverage/default/45.gpio_intr_rand_pgm.27439137
Short name T352
Test name
Test status
Simulation time 36808469 ps
CPU time 0.84 seconds
Started Dec 24 01:11:29 PM PST 23
Finished Dec 24 01:11:37 PM PST 23
Peak memory 195772 kb
Host smart-f0378472-b18c-429d-9556-59157f3ea3d4
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27439137 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_intr_rand_pgm.27439137
Directory /workspace/45.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/45.gpio_intr_with_filter_rand_intr_event.623975280
Short name T387
Test name
Test status
Simulation time 275836396 ps
CPU time 2.6 seconds
Started Dec 24 01:11:18 PM PST 23
Finished Dec 24 01:11:29 PM PST 23
Peak memory 198172 kb
Host smart-9476f3ef-f2ec-41fc-a360-c151c1329bc2
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=623975280 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 45.gpio_intr_with_filter_rand_intr_event.623975280
Directory /workspace/45.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/45.gpio_rand_intr_trigger.1321533786
Short name T583
Test name
Test status
Simulation time 75187541 ps
CPU time 1.47 seconds
Started Dec 24 01:11:15 PM PST 23
Finished Dec 24 01:11:25 PM PST 23
Peak memory 195912 kb
Host smart-c687b4f9-f493-43ff-bcfb-cbabedbb0323
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1321533786 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_rand_intr_trigger
.1321533786
Directory /workspace/45.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/45.gpio_random_dout_din.3515618378
Short name T878
Test name
Test status
Simulation time 44520171 ps
CPU time 0.97 seconds
Started Dec 24 01:11:19 PM PST 23
Finished Dec 24 01:11:28 PM PST 23
Peak memory 196164 kb
Host smart-90c60bba-fef6-4b88-8dd7-30e30065c208
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3515618378 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_random_dout_din.3515618378
Directory /workspace/45.gpio_random_dout_din/latest

Test location /workspace/coverage/default/45.gpio_random_dout_din_no_pullup_pulldown.1130796892
Short name T444
Test name
Test status
Simulation time 238008662 ps
CPU time 1.32 seconds
Started Dec 24 01:11:16 PM PST 23
Finished Dec 24 01:11:26 PM PST 23
Peak memory 196964 kb
Host smart-a98a307d-3002-4eec-80f5-c5e8a0589c48
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1130796892 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_random_dout_din_no_pullu
p_pulldown.1130796892
Directory /workspace/45.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/45.gpio_random_long_reg_writes_reg_reads.1520178743
Short name T277
Test name
Test status
Simulation time 119797840 ps
CPU time 5.35 seconds
Started Dec 24 01:11:25 PM PST 23
Finished Dec 24 01:11:38 PM PST 23
Peak memory 198100 kb
Host smart-59cf80b1-9f95-4e1d-84d5-547f0d64cef4
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1520178743 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_ra
ndom_long_reg_writes_reg_reads.1520178743
Directory /workspace/45.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/45.gpio_smoke.2482301911
Short name T434
Test name
Test status
Simulation time 74150462 ps
CPU time 1.17 seconds
Started Dec 24 01:11:14 PM PST 23
Finished Dec 24 01:11:23 PM PST 23
Peak memory 195968 kb
Host smart-bf1824d5-3f8d-4824-b7d3-1830ebc27ae5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2482301911 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_smoke.2482301911
Directory /workspace/45.gpio_smoke/latest

Test location /workspace/coverage/default/45.gpio_smoke_no_pullup_pulldown.2163679127
Short name T560
Test name
Test status
Simulation time 209802093 ps
CPU time 1.12 seconds
Started Dec 24 01:11:13 PM PST 23
Finished Dec 24 01:11:22 PM PST 23
Peak memory 195940 kb
Host smart-d41fe752-a748-4a00-ab4b-cbe7a8a3944b
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2163679127 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_smoke_no_pullup_pulldown.2163679127
Directory /workspace/45.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/45.gpio_stress_all.3121131304
Short name T830
Test name
Test status
Simulation time 17161442736 ps
CPU time 126.57 seconds
Started Dec 24 01:11:32 PM PST 23
Finished Dec 24 01:13:47 PM PST 23
Peak memory 198108 kb
Host smart-282052ce-0b88-4b22-8a27-da2970840f7c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3121131304 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.
gpio_stress_all.3121131304
Directory /workspace/45.gpio_stress_all/latest

Test location /workspace/coverage/default/45.gpio_stress_all_with_rand_reset.2240224424
Short name T662
Test name
Test status
Simulation time 218264382112 ps
CPU time 653.38 seconds
Started Dec 24 01:11:35 PM PST 23
Finished Dec 24 01:22:39 PM PST 23
Peak memory 206580 kb
Host smart-4ea42978-3746-4cdc-80d7-010a40a68f34
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=2240224424 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_stress_all_with_rand_reset.2240224424
Directory /workspace/45.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/46.gpio_alert_test.1065799336
Short name T476
Test name
Test status
Simulation time 25052301 ps
CPU time 0.56 seconds
Started Dec 24 01:11:34 PM PST 23
Finished Dec 24 01:11:45 PM PST 23
Peak memory 194184 kb
Host smart-8c2b54fc-8bbc-45f8-9477-578a493232a5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1065799336 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_alert_test.1065799336
Directory /workspace/46.gpio_alert_test/latest

Test location /workspace/coverage/default/46.gpio_dout_din_regs_random_rw.3897000436
Short name T274
Test name
Test status
Simulation time 27916104 ps
CPU time 0.91 seconds
Started Dec 24 01:11:34 PM PST 23
Finished Dec 24 01:11:44 PM PST 23
Peak memory 196592 kb
Host smart-1e6ce9a3-9e77-4179-aa8d-40443b604c95
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3897000436 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_dout_din_regs_random_rw.3897000436
Directory /workspace/46.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/46.gpio_filter_stress.2754518507
Short name T278
Test name
Test status
Simulation time 676622570 ps
CPU time 21.65 seconds
Started Dec 24 01:11:33 PM PST 23
Finished Dec 24 01:12:04 PM PST 23
Peak memory 198064 kb
Host smart-018e2fd0-c470-4b3e-a527-de89a85f4355
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2754518507 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_filter_stre
ss.2754518507
Directory /workspace/46.gpio_filter_stress/latest

Test location /workspace/coverage/default/46.gpio_full_random.1981336350
Short name T260
Test name
Test status
Simulation time 269139733 ps
CPU time 0.86 seconds
Started Dec 24 01:11:33 PM PST 23
Finished Dec 24 01:11:43 PM PST 23
Peak memory 196236 kb
Host smart-ceb9a6af-9359-483b-909b-49bd2526cd6b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1981336350 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_full_random.1981336350
Directory /workspace/46.gpio_full_random/latest

Test location /workspace/coverage/default/46.gpio_intr_rand_pgm.2856812865
Short name T308
Test name
Test status
Simulation time 201717992 ps
CPU time 1.18 seconds
Started Dec 24 01:11:23 PM PST 23
Finished Dec 24 01:11:31 PM PST 23
Peak memory 196144 kb
Host smart-291ed7af-23ac-4888-a6f2-22a2c8832d9b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2856812865 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_intr_rand_pgm.2856812865
Directory /workspace/46.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/46.gpio_intr_with_filter_rand_intr_event.3852459944
Short name T405
Test name
Test status
Simulation time 146064315 ps
CPU time 2.91 seconds
Started Dec 24 01:11:34 PM PST 23
Finished Dec 24 01:11:46 PM PST 23
Peak memory 198184 kb
Host smart-be04f5ae-46e0-4507-8e43-0595dc923939
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3852459944 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 46.gpio_intr_with_filter_rand_intr_event.3852459944
Directory /workspace/46.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/46.gpio_rand_intr_trigger.1348261860
Short name T221
Test name
Test status
Simulation time 39159848 ps
CPU time 1.05 seconds
Started Dec 24 01:11:26 PM PST 23
Finished Dec 24 01:11:34 PM PST 23
Peak memory 196140 kb
Host smart-8f9b5e63-d014-410f-b75c-808c1153d586
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1348261860 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_rand_intr_trigger
.1348261860
Directory /workspace/46.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/46.gpio_random_dout_din.3780356366
Short name T243
Test name
Test status
Simulation time 31707315 ps
CPU time 0.8 seconds
Started Dec 24 01:11:34 PM PST 23
Finished Dec 24 01:11:46 PM PST 23
Peak memory 195480 kb
Host smart-7ad4b12b-5a49-4ef0-a24f-d643c68141e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3780356366 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_random_dout_din.3780356366
Directory /workspace/46.gpio_random_dout_din/latest

Test location /workspace/coverage/default/46.gpio_random_dout_din_no_pullup_pulldown.627908876
Short name T858
Test name
Test status
Simulation time 67766691 ps
CPU time 1.2 seconds
Started Dec 24 01:11:35 PM PST 23
Finished Dec 24 01:11:47 PM PST 23
Peak memory 195876 kb
Host smart-a6481cd7-9d18-415f-92e9-79ce331debeb
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=627908876 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_random_dout_din_no_pullup
_pulldown.627908876
Directory /workspace/46.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/46.gpio_random_long_reg_writes_reg_reads.3217996026
Short name T59
Test name
Test status
Simulation time 1328636404 ps
CPU time 2 seconds
Started Dec 24 01:11:32 PM PST 23
Finished Dec 24 01:11:43 PM PST 23
Peak memory 198108 kb
Host smart-ce3c8ab6-b39e-4363-9f90-31b30017f3bc
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3217996026 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_ra
ndom_long_reg_writes_reg_reads.3217996026
Directory /workspace/46.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/46.gpio_smoke.1933142132
Short name T495
Test name
Test status
Simulation time 32969249 ps
CPU time 0.98 seconds
Started Dec 24 01:11:48 PM PST 23
Finished Dec 24 01:11:59 PM PST 23
Peak memory 195732 kb
Host smart-cf95c14c-a66e-4f1c-b148-52342614fcd8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1933142132 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_smoke.1933142132
Directory /workspace/46.gpio_smoke/latest

Test location /workspace/coverage/default/46.gpio_smoke_no_pullup_pulldown.1492793115
Short name T584
Test name
Test status
Simulation time 183384699 ps
CPU time 1.03 seconds
Started Dec 24 01:11:40 PM PST 23
Finished Dec 24 01:11:53 PM PST 23
Peak memory 195528 kb
Host smart-cb8b6fc0-a820-4932-aae3-ff90699ceabd
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1492793115 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_smoke_no_pullup_pulldown.1492793115
Directory /workspace/46.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/46.gpio_stress_all_with_rand_reset.3075439977
Short name T513
Test name
Test status
Simulation time 162330131945 ps
CPU time 1170.07 seconds
Started Dec 24 01:11:17 PM PST 23
Finished Dec 24 01:30:56 PM PST 23
Peak memory 198364 kb
Host smart-98dd1289-230b-441c-b273-4a5c9681d020
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=3075439977 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_stress_all_with_rand_reset.3075439977
Directory /workspace/46.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/47.gpio_alert_test.3374368542
Short name T482
Test name
Test status
Simulation time 28635929 ps
CPU time 0.54 seconds
Started Dec 24 01:11:36 PM PST 23
Finished Dec 24 01:11:49 PM PST 23
Peak memory 192812 kb
Host smart-89b227d5-37ea-4f1c-91a8-d80a1234f3d3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3374368542 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_alert_test.3374368542
Directory /workspace/47.gpio_alert_test/latest

Test location /workspace/coverage/default/47.gpio_dout_din_regs_random_rw.1188464405
Short name T291
Test name
Test status
Simulation time 36636790 ps
CPU time 0.7 seconds
Started Dec 24 01:11:34 PM PST 23
Finished Dec 24 01:11:46 PM PST 23
Peak memory 194892 kb
Host smart-5b57d50d-ecf1-44c3-afd3-204ba88255ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1188464405 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_dout_din_regs_random_rw.1188464405
Directory /workspace/47.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/47.gpio_filter_stress.176005925
Short name T817
Test name
Test status
Simulation time 657968002 ps
CPU time 5.19 seconds
Started Dec 24 01:11:34 PM PST 23
Finished Dec 24 01:11:49 PM PST 23
Peak memory 195644 kb
Host smart-f2e8b78a-1958-41a2-9fad-59a4a53a6ec4
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=176005925 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_filter_stres
s.176005925
Directory /workspace/47.gpio_filter_stress/latest

Test location /workspace/coverage/default/47.gpio_full_random.2586804001
Short name T581
Test name
Test status
Simulation time 620629814 ps
CPU time 0.74 seconds
Started Dec 24 01:11:30 PM PST 23
Finished Dec 24 01:11:38 PM PST 23
Peak memory 196476 kb
Host smart-ad02891a-6bcb-4db5-81ba-4501dd47ac68
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2586804001 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_full_random.2586804001
Directory /workspace/47.gpio_full_random/latest

Test location /workspace/coverage/default/47.gpio_intr_rand_pgm.4136247931
Short name T271
Test name
Test status
Simulation time 47570308 ps
CPU time 0.84 seconds
Started Dec 24 01:11:38 PM PST 23
Finished Dec 24 01:11:51 PM PST 23
Peak memory 195632 kb
Host smart-70ffaa83-0482-43a4-9641-74c1e2ed3f20
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4136247931 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_intr_rand_pgm.4136247931
Directory /workspace/47.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/47.gpio_intr_with_filter_rand_intr_event.2154842350
Short name T112
Test name
Test status
Simulation time 136032087 ps
CPU time 2.06 seconds
Started Dec 24 01:11:40 PM PST 23
Finished Dec 24 01:11:54 PM PST 23
Peak memory 198144 kb
Host smart-fe135f97-026b-4bf8-b287-9a7da0ec457e
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2154842350 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 47.gpio_intr_with_filter_rand_intr_event.2154842350
Directory /workspace/47.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/47.gpio_rand_intr_trigger.3901014773
Short name T218
Test name
Test status
Simulation time 240934356 ps
CPU time 1.23 seconds
Started Dec 24 01:11:25 PM PST 23
Finished Dec 24 01:11:33 PM PST 23
Peak memory 195804 kb
Host smart-70ffd4e9-553d-4358-b4e3-b07dafc516fb
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3901014773 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_rand_intr_trigger
.3901014773
Directory /workspace/47.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/47.gpio_random_dout_din.727444219
Short name T452
Test name
Test status
Simulation time 20926420 ps
CPU time 0.77 seconds
Started Dec 24 01:11:22 PM PST 23
Finished Dec 24 01:11:29 PM PST 23
Peak memory 196216 kb
Host smart-148053bf-319e-4e89-843c-9e1b403d8897
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=727444219 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_random_dout_din.727444219
Directory /workspace/47.gpio_random_dout_din/latest

Test location /workspace/coverage/default/47.gpio_random_dout_din_no_pullup_pulldown.1625045218
Short name T445
Test name
Test status
Simulation time 22179474 ps
CPU time 0.67 seconds
Started Dec 24 01:11:32 PM PST 23
Finished Dec 24 01:11:41 PM PST 23
Peak memory 194412 kb
Host smart-181a2651-eaf5-4fff-b7c5-6605b16e8f29
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1625045218 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_random_dout_din_no_pullu
p_pulldown.1625045218
Directory /workspace/47.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/47.gpio_random_long_reg_writes_reg_reads.4181948640
Short name T846
Test name
Test status
Simulation time 1032170234 ps
CPU time 4.46 seconds
Started Dec 24 01:11:38 PM PST 23
Finished Dec 24 01:11:56 PM PST 23
Peak memory 197976 kb
Host smart-16209c9b-a115-45f3-9736-e54aacea7b2d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4181948640 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_ra
ndom_long_reg_writes_reg_reads.4181948640
Directory /workspace/47.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/47.gpio_smoke.3239439625
Short name T319
Test name
Test status
Simulation time 320390811 ps
CPU time 1.39 seconds
Started Dec 24 01:11:19 PM PST 23
Finished Dec 24 01:11:29 PM PST 23
Peak memory 196364 kb
Host smart-6acb7738-94ab-4af1-bfce-2d658bd15190
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3239439625 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_smoke.3239439625
Directory /workspace/47.gpio_smoke/latest

Test location /workspace/coverage/default/47.gpio_smoke_no_pullup_pulldown.1076389377
Short name T544
Test name
Test status
Simulation time 53014449 ps
CPU time 0.99 seconds
Started Dec 24 01:11:27 PM PST 23
Finished Dec 24 01:11:35 PM PST 23
Peak memory 196528 kb
Host smart-7e6b4e35-5220-4dde-b9f4-7ef88a746c7f
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1076389377 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_smoke_no_pullup_pulldown.1076389377
Directory /workspace/47.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/47.gpio_stress_all.445466199
Short name T706
Test name
Test status
Simulation time 13903001123 ps
CPU time 96.21 seconds
Started Dec 24 01:11:36 PM PST 23
Finished Dec 24 01:13:24 PM PST 23
Peak memory 198164 kb
Host smart-5bf3ae45-e41c-4b04-b847-84e5bcf76620
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=445466199 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.g
pio_stress_all.445466199
Directory /workspace/47.gpio_stress_all/latest

Test location /workspace/coverage/default/47.gpio_stress_all_with_rand_reset.2660071618
Short name T472
Test name
Test status
Simulation time 52308237060 ps
CPU time 646.67 seconds
Started Dec 24 01:12:10 PM PST 23
Finished Dec 24 01:23:08 PM PST 23
Peak memory 198412 kb
Host smart-555b1df4-8667-4ad7-a3e0-f6d8425093cf
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=2660071618 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_stress_all_with_rand_reset.2660071618
Directory /workspace/47.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/48.gpio_alert_test.2362065699
Short name T807
Test name
Test status
Simulation time 12376106 ps
CPU time 0.56 seconds
Started Dec 24 01:11:30 PM PST 23
Finished Dec 24 01:11:38 PM PST 23
Peak memory 194056 kb
Host smart-a1456717-8ba7-4784-b424-6c92dcf58535
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2362065699 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_alert_test.2362065699
Directory /workspace/48.gpio_alert_test/latest

Test location /workspace/coverage/default/48.gpio_dout_din_regs_random_rw.1670251408
Short name T616
Test name
Test status
Simulation time 47736230 ps
CPU time 0.75 seconds
Started Dec 24 01:12:12 PM PST 23
Finished Dec 24 01:12:24 PM PST 23
Peak memory 195924 kb
Host smart-87d47ca0-1920-4f3b-9b42-6a0e3378a37b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1670251408 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_dout_din_regs_random_rw.1670251408
Directory /workspace/48.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/48.gpio_filter_stress.3111340657
Short name T275
Test name
Test status
Simulation time 404812967 ps
CPU time 20.98 seconds
Started Dec 24 01:11:31 PM PST 23
Finished Dec 24 01:11:59 PM PST 23
Peak memory 196804 kb
Host smart-2c13d79d-256d-4d07-bfc8-5aac00eded96
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3111340657 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_filter_stre
ss.3111340657
Directory /workspace/48.gpio_filter_stress/latest

Test location /workspace/coverage/default/48.gpio_full_random.2848374823
Short name T558
Test name
Test status
Simulation time 24249590 ps
CPU time 0.67 seconds
Started Dec 24 01:11:24 PM PST 23
Finished Dec 24 01:11:32 PM PST 23
Peak memory 194528 kb
Host smart-2f61451e-4c3e-45e6-bb03-a43a986729d9
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2848374823 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_full_random.2848374823
Directory /workspace/48.gpio_full_random/latest

Test location /workspace/coverage/default/48.gpio_intr_rand_pgm.729188082
Short name T296
Test name
Test status
Simulation time 34704529 ps
CPU time 0.77 seconds
Started Dec 24 01:11:53 PM PST 23
Finished Dec 24 01:12:02 PM PST 23
Peak memory 195432 kb
Host smart-25cd318f-18e1-4938-ab4a-b555ac113438
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=729188082 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_intr_rand_pgm.729188082
Directory /workspace/48.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/48.gpio_intr_with_filter_rand_intr_event.1604167826
Short name T702
Test name
Test status
Simulation time 74570827 ps
CPU time 2.85 seconds
Started Dec 24 01:11:23 PM PST 23
Finished Dec 24 01:11:32 PM PST 23
Peak memory 197820 kb
Host smart-7a50a3d9-519d-4b33-a17f-986fed63b28f
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1604167826 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 48.gpio_intr_with_filter_rand_intr_event.1604167826
Directory /workspace/48.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/48.gpio_rand_intr_trigger.2442614006
Short name T301
Test name
Test status
Simulation time 58525631 ps
CPU time 1.8 seconds
Started Dec 24 01:12:18 PM PST 23
Finished Dec 24 01:12:32 PM PST 23
Peak memory 196268 kb
Host smart-bf363854-b97c-4ad9-8851-afc5c19a4ae5
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2442614006 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_rand_intr_trigger
.2442614006
Directory /workspace/48.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/48.gpio_random_dout_din.1271994258
Short name T825
Test name
Test status
Simulation time 25634396 ps
CPU time 0.98 seconds
Started Dec 24 01:11:53 PM PST 23
Finished Dec 24 01:12:02 PM PST 23
Peak memory 196108 kb
Host smart-6199f3cd-3ea4-4512-9791-12174967879e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1271994258 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_random_dout_din.1271994258
Directory /workspace/48.gpio_random_dout_din/latest

Test location /workspace/coverage/default/48.gpio_random_dout_din_no_pullup_pulldown.1418061809
Short name T487
Test name
Test status
Simulation time 79250324 ps
CPU time 1.25 seconds
Started Dec 24 01:12:07 PM PST 23
Finished Dec 24 01:12:16 PM PST 23
Peak memory 196912 kb
Host smart-ba0e0eaf-ff6c-43ce-9142-45349d6168d3
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1418061809 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_random_dout_din_no_pullu
p_pulldown.1418061809
Directory /workspace/48.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/48.gpio_random_long_reg_writes_reg_reads.1719096492
Short name T447
Test name
Test status
Simulation time 552529475 ps
CPU time 4.71 seconds
Started Dec 24 01:11:49 PM PST 23
Finished Dec 24 01:12:04 PM PST 23
Peak memory 198132 kb
Host smart-145a0351-5263-4797-adbe-7bbb70cbd369
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1719096492 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_ra
ndom_long_reg_writes_reg_reads.1719096492
Directory /workspace/48.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/48.gpio_smoke.2478154966
Short name T231
Test name
Test status
Simulation time 66409468 ps
CPU time 1.21 seconds
Started Dec 24 01:11:53 PM PST 23
Finished Dec 24 01:12:02 PM PST 23
Peak memory 195860 kb
Host smart-948f74fd-7c29-4cae-8c5d-e5b5c89ce3be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2478154966 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_smoke.2478154966
Directory /workspace/48.gpio_smoke/latest

Test location /workspace/coverage/default/48.gpio_smoke_no_pullup_pulldown.1152445760
Short name T679
Test name
Test status
Simulation time 334251101 ps
CPU time 1.35 seconds
Started Dec 24 01:12:28 PM PST 23
Finished Dec 24 01:12:42 PM PST 23
Peak memory 196820 kb
Host smart-35ea3826-bd80-4bfc-bc92-78489004cce6
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1152445760 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_smoke_no_pullup_pulldown.1152445760
Directory /workspace/48.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/48.gpio_stress_all.1793910451
Short name T396
Test name
Test status
Simulation time 25781100207 ps
CPU time 70.2 seconds
Started Dec 24 01:11:23 PM PST 23
Finished Dec 24 01:12:40 PM PST 23
Peak memory 197680 kb
Host smart-8122ced6-ed93-46fd-b78a-c3d99e0ead16
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1793910451 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.
gpio_stress_all.1793910451
Directory /workspace/48.gpio_stress_all/latest

Test location /workspace/coverage/default/48.gpio_stress_all_with_rand_reset.667258298
Short name T68
Test name
Test status
Simulation time 40213669606 ps
CPU time 634.3 seconds
Started Dec 24 01:11:54 PM PST 23
Finished Dec 24 01:22:36 PM PST 23
Peak memory 198392 kb
Host smart-75cdd35f-b37c-48fb-a50f-ed9b8c490a4f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=667258298 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_stress_all_with_rand_reset.667258298
Directory /workspace/48.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/49.gpio_alert_test.1069550637
Short name T328
Test name
Test status
Simulation time 54340308 ps
CPU time 0.57 seconds
Started Dec 24 01:11:29 PM PST 23
Finished Dec 24 01:11:36 PM PST 23
Peak memory 193984 kb
Host smart-08c18255-a6be-43d4-a631-b3e8cb6047ad
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1069550637 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_alert_test.1069550637
Directory /workspace/49.gpio_alert_test/latest

Test location /workspace/coverage/default/49.gpio_dout_din_regs_random_rw.1808432723
Short name T454
Test name
Test status
Simulation time 18239051 ps
CPU time 0.62 seconds
Started Dec 24 01:11:36 PM PST 23
Finished Dec 24 01:11:49 PM PST 23
Peak memory 194784 kb
Host smart-93beb019-d571-44cb-9181-5c76d101ffd9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1808432723 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_dout_din_regs_random_rw.1808432723
Directory /workspace/49.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/49.gpio_filter_stress.102714061
Short name T674
Test name
Test status
Simulation time 412283319 ps
CPU time 12.61 seconds
Started Dec 24 01:11:31 PM PST 23
Finished Dec 24 01:12:03 PM PST 23
Peak memory 198176 kb
Host smart-a2f70ffb-c8da-4c78-9f9c-6bd2dd0f84a5
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=102714061 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_filter_stres
s.102714061
Directory /workspace/49.gpio_filter_stress/latest

Test location /workspace/coverage/default/49.gpio_full_random.2200517705
Short name T354
Test name
Test status
Simulation time 204814345 ps
CPU time 0.89 seconds
Started Dec 24 01:11:33 PM PST 23
Finished Dec 24 01:11:43 PM PST 23
Peak memory 196944 kb
Host smart-00d48053-25b9-4261-bd19-7cdeb9d2df1d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2200517705 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_full_random.2200517705
Directory /workspace/49.gpio_full_random/latest

Test location /workspace/coverage/default/49.gpio_intr_rand_pgm.700663952
Short name T511
Test name
Test status
Simulation time 111812682 ps
CPU time 0.92 seconds
Started Dec 24 01:11:35 PM PST 23
Finished Dec 24 01:11:48 PM PST 23
Peak memory 196196 kb
Host smart-a6f56bb6-289e-4572-947d-c16835553545
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=700663952 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_intr_rand_pgm.700663952
Directory /workspace/49.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/49.gpio_intr_with_filter_rand_intr_event.3765539844
Short name T398
Test name
Test status
Simulation time 151715833 ps
CPU time 2.78 seconds
Started Dec 24 01:11:30 PM PST 23
Finished Dec 24 01:11:40 PM PST 23
Peak memory 198216 kb
Host smart-e357de2a-7e89-4c9a-b513-596817841869
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3765539844 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 49.gpio_intr_with_filter_rand_intr_event.3765539844
Directory /workspace/49.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/49.gpio_rand_intr_trigger.1186326216
Short name T237
Test name
Test status
Simulation time 108648080 ps
CPU time 3.08 seconds
Started Dec 24 01:11:34 PM PST 23
Finished Dec 24 01:11:48 PM PST 23
Peak memory 197136 kb
Host smart-bda1163f-c5f0-4882-9417-18b1c7bac732
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1186326216 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_rand_intr_trigger
.1186326216
Directory /workspace/49.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/49.gpio_random_dout_din.237461480
Short name T502
Test name
Test status
Simulation time 79256499 ps
CPU time 0.76 seconds
Started Dec 24 01:11:31 PM PST 23
Finished Dec 24 01:11:39 PM PST 23
Peak memory 195496 kb
Host smart-29368ae5-5116-479a-93f7-a2fb47b7077c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=237461480 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_random_dout_din.237461480
Directory /workspace/49.gpio_random_dout_din/latest

Test location /workspace/coverage/default/49.gpio_random_dout_din_no_pullup_pulldown.630667590
Short name T449
Test name
Test status
Simulation time 49229545 ps
CPU time 0.96 seconds
Started Dec 24 01:11:30 PM PST 23
Finished Dec 24 01:11:37 PM PST 23
Peak memory 195860 kb
Host smart-bedd2c95-88ae-473f-a6cc-85b753d7cece
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=630667590 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_random_dout_din_no_pullup
_pulldown.630667590
Directory /workspace/49.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/49.gpio_random_long_reg_writes_reg_reads.3496809559
Short name T281
Test name
Test status
Simulation time 101254340 ps
CPU time 1.21 seconds
Started Dec 24 01:11:31 PM PST 23
Finished Dec 24 01:11:40 PM PST 23
Peak memory 198088 kb
Host smart-7ec6c312-c470-44a9-804d-8c360fa9ae49
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3496809559 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_ra
ndom_long_reg_writes_reg_reads.3496809559
Directory /workspace/49.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/49.gpio_smoke.242445999
Short name T726
Test name
Test status
Simulation time 100733412 ps
CPU time 1.31 seconds
Started Dec 24 01:11:30 PM PST 23
Finished Dec 24 01:11:38 PM PST 23
Peak memory 197048 kb
Host smart-4b79a77d-6d9f-4ea1-aca7-e08b170e28da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=242445999 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_smoke.242445999
Directory /workspace/49.gpio_smoke/latest

Test location /workspace/coverage/default/49.gpio_smoke_no_pullup_pulldown.2202565961
Short name T216
Test name
Test status
Simulation time 168914422 ps
CPU time 1.35 seconds
Started Dec 24 01:11:25 PM PST 23
Finished Dec 24 01:11:33 PM PST 23
Peak memory 198052 kb
Host smart-e04ac23b-9acb-41ad-941d-9524e3fa4b0b
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2202565961 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_smoke_no_pullup_pulldown.2202565961
Directory /workspace/49.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/49.gpio_stress_all.2831897089
Short name T67
Test name
Test status
Simulation time 2131662622 ps
CPU time 49.57 seconds
Started Dec 24 01:11:33 PM PST 23
Finished Dec 24 01:12:31 PM PST 23
Peak memory 198116 kb
Host smart-9037391f-ee04-41ce-8d30-7af2d4444f2d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2831897089 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.
gpio_stress_all.2831897089
Directory /workspace/49.gpio_stress_all/latest

Test location /workspace/coverage/default/49.gpio_stress_all_with_rand_reset.1149965374
Short name T585
Test name
Test status
Simulation time 281588992506 ps
CPU time 727.83 seconds
Started Dec 24 01:11:24 PM PST 23
Finished Dec 24 01:23:39 PM PST 23
Peak memory 198388 kb
Host smart-723152fb-b4a4-46a9-b7b1-a65c31e1eb34
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=1149965374 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_stress_all_with_rand_reset.1149965374
Directory /workspace/49.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/5.gpio_alert_test.1683725558
Short name T783
Test name
Test status
Simulation time 14541130 ps
CPU time 0.59 seconds
Started Dec 24 01:10:03 PM PST 23
Finished Dec 24 01:10:08 PM PST 23
Peak memory 194784 kb
Host smart-ec874339-ae52-49cf-8e43-868623629659
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1683725558 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_alert_test.1683725558
Directory /workspace/5.gpio_alert_test/latest

Test location /workspace/coverage/default/5.gpio_dout_din_regs_random_rw.2417518951
Short name T639
Test name
Test status
Simulation time 47473274 ps
CPU time 0.66 seconds
Started Dec 24 01:09:50 PM PST 23
Finished Dec 24 01:09:57 PM PST 23
Peak memory 194892 kb
Host smart-8f6b1e82-6064-4b9b-a56a-bece313e30a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2417518951 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_dout_din_regs_random_rw.2417518951
Directory /workspace/5.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/5.gpio_filter_stress.2234201395
Short name T44
Test name
Test status
Simulation time 2395835471 ps
CPU time 22.14 seconds
Started Dec 24 01:10:12 PM PST 23
Finished Dec 24 01:10:39 PM PST 23
Peak memory 196900 kb
Host smart-a9352775-0d1d-4cac-ba2d-2245f2bebb35
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2234201395 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_filter_stres
s.2234201395
Directory /workspace/5.gpio_filter_stress/latest

Test location /workspace/coverage/default/5.gpio_full_random.1590035636
Short name T467
Test name
Test status
Simulation time 43587824 ps
CPU time 0.74 seconds
Started Dec 24 01:10:03 PM PST 23
Finished Dec 24 01:10:08 PM PST 23
Peak memory 195940 kb
Host smart-938abe77-8075-4f2a-a051-a8d6d1a93b7d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1590035636 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_full_random.1590035636
Directory /workspace/5.gpio_full_random/latest

Test location /workspace/coverage/default/5.gpio_intr_rand_pgm.1336325866
Short name T606
Test name
Test status
Simulation time 46751167 ps
CPU time 0.65 seconds
Started Dec 24 01:10:05 PM PST 23
Finished Dec 24 01:10:11 PM PST 23
Peak memory 194324 kb
Host smart-3ec3cc34-2112-499a-9785-d90c5290244e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1336325866 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_intr_rand_pgm.1336325866
Directory /workspace/5.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/5.gpio_intr_with_filter_rand_intr_event.3272323892
Short name T392
Test name
Test status
Simulation time 82134161 ps
CPU time 3.11 seconds
Started Dec 24 01:10:00 PM PST 23
Finished Dec 24 01:10:06 PM PST 23
Peak memory 198096 kb
Host smart-ae82a1dc-f681-43df-9a05-f9f6d5701336
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3272323892 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 5.gpio_intr_with_filter_rand_intr_event.3272323892
Directory /workspace/5.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/5.gpio_rand_intr_trigger.2539002734
Short name T378
Test name
Test status
Simulation time 542802102 ps
CPU time 3.17 seconds
Started Dec 24 01:10:10 PM PST 23
Finished Dec 24 01:10:18 PM PST 23
Peak memory 196872 kb
Host smart-16a354dd-524f-4455-8cae-147ec9d6a9ef
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2539002734 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_rand_intr_trigger.
2539002734
Directory /workspace/5.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/5.gpio_random_dout_din.2979716508
Short name T483
Test name
Test status
Simulation time 86915228 ps
CPU time 0.61 seconds
Started Dec 24 01:10:04 PM PST 23
Finished Dec 24 01:10:09 PM PST 23
Peak memory 194244 kb
Host smart-611b9c92-5575-4733-b35f-502983a79df5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2979716508 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_random_dout_din.2979716508
Directory /workspace/5.gpio_random_dout_din/latest

Test location /workspace/coverage/default/5.gpio_random_dout_din_no_pullup_pulldown.2289085536
Short name T312
Test name
Test status
Simulation time 111005101 ps
CPU time 0.97 seconds
Started Dec 24 01:10:07 PM PST 23
Finished Dec 24 01:10:15 PM PST 23
Peak memory 195908 kb
Host smart-22bad4af-1b63-4d0b-9c08-5128f17bfa09
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2289085536 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_random_dout_din_no_pullup
_pulldown.2289085536
Directory /workspace/5.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/5.gpio_random_long_reg_writes_reg_reads.4082165637
Short name T582
Test name
Test status
Simulation time 349828720 ps
CPU time 6.19 seconds
Started Dec 24 01:10:02 PM PST 23
Finished Dec 24 01:10:12 PM PST 23
Peak memory 198116 kb
Host smart-05071628-788f-41f3-960a-3ed82224aebe
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4082165637 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_ran
dom_long_reg_writes_reg_reads.4082165637
Directory /workspace/5.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/5.gpio_smoke.1178366217
Short name T848
Test name
Test status
Simulation time 54165404 ps
CPU time 1.03 seconds
Started Dec 24 01:10:05 PM PST 23
Finished Dec 24 01:10:10 PM PST 23
Peak memory 196684 kb
Host smart-c7e8740d-36b3-49d8-94be-fa682902affa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1178366217 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_smoke.1178366217
Directory /workspace/5.gpio_smoke/latest

Test location /workspace/coverage/default/5.gpio_smoke_no_pullup_pulldown.1264648971
Short name T847
Test name
Test status
Simulation time 148745811 ps
CPU time 0.95 seconds
Started Dec 24 01:10:10 PM PST 23
Finished Dec 24 01:10:17 PM PST 23
Peak memory 195856 kb
Host smart-dc37bb1a-5c3c-4c4d-aa9f-0d55991db65b
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1264648971 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_smoke_no_pullup_pulldown.1264648971
Directory /workspace/5.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/5.gpio_stress_all.774464934
Short name T324
Test name
Test status
Simulation time 31301216844 ps
CPU time 85.29 seconds
Started Dec 24 01:10:06 PM PST 23
Finished Dec 24 01:11:38 PM PST 23
Peak memory 198164 kb
Host smart-a1b2c8ee-abe5-4675-b7d0-7d8c6a241fae
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=774464934 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gp
io_stress_all.774464934
Directory /workspace/5.gpio_stress_all/latest

Test location /workspace/coverage/default/5.gpio_stress_all_with_rand_reset.728330778
Short name T779
Test name
Test status
Simulation time 150092380764 ps
CPU time 1038.64 seconds
Started Dec 24 01:10:18 PM PST 23
Finished Dec 24 01:27:41 PM PST 23
Peak memory 198308 kb
Host smart-67a13e5f-18d3-47e9-9c85-d160a154632b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=728330778 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_stress_all_with_rand_reset.728330778
Directory /workspace/5.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/6.gpio_alert_test.2736464602
Short name T599
Test name
Test status
Simulation time 20969167 ps
CPU time 0.59 seconds
Started Dec 24 01:10:05 PM PST 23
Finished Dec 24 01:10:11 PM PST 23
Peak memory 194052 kb
Host smart-a3c23d1f-a28c-49bb-a80c-31ebca5f7d76
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2736464602 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_alert_test.2736464602
Directory /workspace/6.gpio_alert_test/latest

Test location /workspace/coverage/default/6.gpio_dout_din_regs_random_rw.2488098423
Short name T850
Test name
Test status
Simulation time 25587589 ps
CPU time 0.79 seconds
Started Dec 24 01:10:08 PM PST 23
Finished Dec 24 01:10:15 PM PST 23
Peak memory 195552 kb
Host smart-1b95948d-81c5-4068-8b3c-5dc7912fd1c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2488098423 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_dout_din_regs_random_rw.2488098423
Directory /workspace/6.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/6.gpio_filter_stress.2668756515
Short name T506
Test name
Test status
Simulation time 335332655 ps
CPU time 6.2 seconds
Started Dec 24 01:10:21 PM PST 23
Finished Dec 24 01:10:30 PM PST 23
Peak memory 196740 kb
Host smart-914bbce9-6f50-4e98-8c22-4c4149926449
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2668756515 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_filter_stres
s.2668756515
Directory /workspace/6.gpio_filter_stress/latest

Test location /workspace/coverage/default/6.gpio_full_random.3109628793
Short name T64
Test name
Test status
Simulation time 132707088 ps
CPU time 0.74 seconds
Started Dec 24 01:10:13 PM PST 23
Finished Dec 24 01:10:18 PM PST 23
Peak memory 195900 kb
Host smart-8410f452-2c2c-4858-8f21-15727e51ac61
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3109628793 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_full_random.3109628793
Directory /workspace/6.gpio_full_random/latest

Test location /workspace/coverage/default/6.gpio_intr_rand_pgm.3797956144
Short name T456
Test name
Test status
Simulation time 99788878 ps
CPU time 0.79 seconds
Started Dec 24 01:10:05 PM PST 23
Finished Dec 24 01:10:12 PM PST 23
Peak memory 195616 kb
Host smart-93d890fb-f3ab-4b7d-a01b-ad7e4a519fd4
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3797956144 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_intr_rand_pgm.3797956144
Directory /workspace/6.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/6.gpio_intr_with_filter_rand_intr_event.3846112028
Short name T614
Test name
Test status
Simulation time 234386228 ps
CPU time 2.54 seconds
Started Dec 24 01:10:12 PM PST 23
Finished Dec 24 01:10:19 PM PST 23
Peak memory 198212 kb
Host smart-5b2c347d-a05a-40c5-970e-5216a82a88bf
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3846112028 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 6.gpio_intr_with_filter_rand_intr_event.3846112028
Directory /workspace/6.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/6.gpio_rand_intr_trigger.3711573915
Short name T672
Test name
Test status
Simulation time 313087071 ps
CPU time 3.06 seconds
Started Dec 24 01:10:03 PM PST 23
Finished Dec 24 01:10:10 PM PST 23
Peak memory 197440 kb
Host smart-90f0c9bf-82d1-4b7d-bc3b-7e4952ca9ec4
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3711573915 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_rand_intr_trigger.
3711573915
Directory /workspace/6.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/6.gpio_random_dout_din.4207468536
Short name T751
Test name
Test status
Simulation time 49417339 ps
CPU time 0.81 seconds
Started Dec 24 01:10:02 PM PST 23
Finished Dec 24 01:10:07 PM PST 23
Peak memory 195368 kb
Host smart-eb9fb21e-49a1-4644-9622-8da1abaf031a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4207468536 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_random_dout_din.4207468536
Directory /workspace/6.gpio_random_dout_din/latest

Test location /workspace/coverage/default/6.gpio_random_dout_din_no_pullup_pulldown.223865458
Short name T688
Test name
Test status
Simulation time 197179775 ps
CPU time 1.08 seconds
Started Dec 24 01:10:05 PM PST 23
Finished Dec 24 01:10:11 PM PST 23
Peak memory 195880 kb
Host smart-0677c62c-bddf-4cd9-a70d-3d8a08bcb6ae
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=223865458 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_random_dout_din_no_pullup_
pulldown.223865458
Directory /workspace/6.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/6.gpio_random_long_reg_writes_reg_reads.3076269937
Short name T647
Test name
Test status
Simulation time 53908730 ps
CPU time 1.29 seconds
Started Dec 24 01:10:07 PM PST 23
Finished Dec 24 01:10:15 PM PST 23
Peak memory 198128 kb
Host smart-79cfa74f-e268-49a0-89dd-3667a8cafc94
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3076269937 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_ran
dom_long_reg_writes_reg_reads.3076269937
Directory /workspace/6.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/6.gpio_smoke.1677286220
Short name T827
Test name
Test status
Simulation time 367972996 ps
CPU time 1.01 seconds
Started Dec 24 01:10:01 PM PST 23
Finished Dec 24 01:10:06 PM PST 23
Peak memory 195644 kb
Host smart-fcc0120a-a7f7-4129-93b1-db8d01038c5a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1677286220 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_smoke.1677286220
Directory /workspace/6.gpio_smoke/latest

Test location /workspace/coverage/default/6.gpio_smoke_no_pullup_pulldown.3444831075
Short name T331
Test name
Test status
Simulation time 998426975 ps
CPU time 1.45 seconds
Started Dec 24 01:10:01 PM PST 23
Finished Dec 24 01:10:06 PM PST 23
Peak memory 198044 kb
Host smart-d63fb49b-7b7f-4e01-a34b-7c2e97dc0765
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3444831075 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_smoke_no_pullup_pulldown.3444831075
Directory /workspace/6.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/6.gpio_stress_all.847345254
Short name T833
Test name
Test status
Simulation time 7063821882 ps
CPU time 103.49 seconds
Started Dec 24 01:10:12 PM PST 23
Finished Dec 24 01:12:00 PM PST 23
Peak memory 198172 kb
Host smart-89e84ed4-1b7c-4850-bca6-049f2e7848a6
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=847345254 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gp
io_stress_all.847345254
Directory /workspace/6.gpio_stress_all/latest

Test location /workspace/coverage/default/6.gpio_stress_all_with_rand_reset.79607929
Short name T737
Test name
Test status
Simulation time 249401856799 ps
CPU time 1644.48 seconds
Started Dec 24 01:10:07 PM PST 23
Finished Dec 24 01:37:38 PM PST 23
Peak memory 198324 kb
Host smart-291181ef-fa43-4712-846b-59d7b9b68893
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=79607929 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_stress_all_with_rand_reset.79607929
Directory /workspace/6.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/7.gpio_alert_test.2610982871
Short name T320
Test name
Test status
Simulation time 32403658 ps
CPU time 0.63 seconds
Started Dec 24 01:10:13 PM PST 23
Finished Dec 24 01:10:18 PM PST 23
Peak memory 193960 kb
Host smart-5857d34a-ec54-4b3b-96ff-67f663842ad2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2610982871 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_alert_test.2610982871
Directory /workspace/7.gpio_alert_test/latest

Test location /workspace/coverage/default/7.gpio_dout_din_regs_random_rw.2506240284
Short name T869
Test name
Test status
Simulation time 107868735 ps
CPU time 0.89 seconds
Started Dec 24 01:10:06 PM PST 23
Finished Dec 24 01:10:13 PM PST 23
Peak memory 196028 kb
Host smart-772ca450-fa31-46e8-bd16-de37a80c363d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2506240284 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_dout_din_regs_random_rw.2506240284
Directory /workspace/7.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/7.gpio_filter_stress.3547057067
Short name T634
Test name
Test status
Simulation time 3315441303 ps
CPU time 23.42 seconds
Started Dec 24 01:10:04 PM PST 23
Finished Dec 24 01:10:32 PM PST 23
Peak memory 196572 kb
Host smart-8bce8719-5de2-438e-8077-2e28d27688cf
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3547057067 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_filter_stres
s.3547057067
Directory /workspace/7.gpio_filter_stress/latest

Test location /workspace/coverage/default/7.gpio_full_random.3894306492
Short name T251
Test name
Test status
Simulation time 107417931 ps
CPU time 0.71 seconds
Started Dec 24 01:10:10 PM PST 23
Finished Dec 24 01:10:16 PM PST 23
Peak memory 194756 kb
Host smart-169f8479-76a9-4be2-8b88-306537aa2466
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3894306492 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_full_random.3894306492
Directory /workspace/7.gpio_full_random/latest

Test location /workspace/coverage/default/7.gpio_intr_rand_pgm.1961611880
Short name T804
Test name
Test status
Simulation time 51256794 ps
CPU time 0.7 seconds
Started Dec 24 01:10:20 PM PST 23
Finished Dec 24 01:10:28 PM PST 23
Peak memory 194448 kb
Host smart-18a0ee19-083a-4441-8af2-07c7e9a363d0
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1961611880 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_intr_rand_pgm.1961611880
Directory /workspace/7.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/7.gpio_intr_with_filter_rand_intr_event.1686519519
Short name T856
Test name
Test status
Simulation time 226168536 ps
CPU time 2.29 seconds
Started Dec 24 01:10:18 PM PST 23
Finished Dec 24 01:10:25 PM PST 23
Peak memory 198092 kb
Host smart-a9698c4b-5114-4711-9465-7d88fbf1d9a6
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1686519519 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 7.gpio_intr_with_filter_rand_intr_event.1686519519
Directory /workspace/7.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/7.gpio_rand_intr_trigger.1074741399
Short name T234
Test name
Test status
Simulation time 116169717 ps
CPU time 1.75 seconds
Started Dec 24 01:10:12 PM PST 23
Finished Dec 24 01:10:18 PM PST 23
Peak memory 195844 kb
Host smart-aa4ed799-dd49-42a9-8a0f-a53aa384907c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1074741399 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_rand_intr_trigger.
1074741399
Directory /workspace/7.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/7.gpio_random_dout_din.2495272455
Short name T709
Test name
Test status
Simulation time 390860006 ps
CPU time 1.22 seconds
Started Dec 24 01:10:04 PM PST 23
Finished Dec 24 01:10:09 PM PST 23
Peak memory 195976 kb
Host smart-a779e582-605a-48f2-ba2f-3c8db3163fe2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2495272455 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_random_dout_din.2495272455
Directory /workspace/7.gpio_random_dout_din/latest

Test location /workspace/coverage/default/7.gpio_random_dout_din_no_pullup_pulldown.1358630755
Short name T610
Test name
Test status
Simulation time 57738940 ps
CPU time 1.3 seconds
Started Dec 24 01:10:15 PM PST 23
Finished Dec 24 01:10:21 PM PST 23
Peak memory 196972 kb
Host smart-560c92c5-8013-4ab6-8a2f-ea1ff1568dc3
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1358630755 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_random_dout_din_no_pullup
_pulldown.1358630755
Directory /workspace/7.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/7.gpio_random_long_reg_writes_reg_reads.3568300950
Short name T635
Test name
Test status
Simulation time 829753845 ps
CPU time 3.52 seconds
Started Dec 24 01:10:14 PM PST 23
Finished Dec 24 01:10:22 PM PST 23
Peak memory 198100 kb
Host smart-7c0e3db2-16a7-4c4e-825c-af7082a31902
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3568300950 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_ran
dom_long_reg_writes_reg_reads.3568300950
Directory /workspace/7.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/7.gpio_smoke.2374075707
Short name T575
Test name
Test status
Simulation time 70455610 ps
CPU time 1.2 seconds
Started Dec 24 01:10:04 PM PST 23
Finished Dec 24 01:10:15 PM PST 23
Peak memory 195856 kb
Host smart-b808e2e8-2a8c-43b2-8e87-682afbd87ae2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2374075707 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_smoke.2374075707
Directory /workspace/7.gpio_smoke/latest

Test location /workspace/coverage/default/7.gpio_smoke_no_pullup_pulldown.497223738
Short name T346
Test name
Test status
Simulation time 114010869 ps
CPU time 0.8 seconds
Started Dec 24 01:10:24 PM PST 23
Finished Dec 24 01:10:28 PM PST 23
Peak memory 195956 kb
Host smart-86d80875-a351-448b-b484-742280637fd6
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=497223738 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_smoke_no_pullup_pulldown.497223738
Directory /workspace/7.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/7.gpio_stress_all.1788244762
Short name T288
Test name
Test status
Simulation time 40886554774 ps
CPU time 229.43 seconds
Started Dec 24 01:10:08 PM PST 23
Finished Dec 24 01:14:03 PM PST 23
Peak memory 198232 kb
Host smart-87df4978-352f-4395-baf2-73fca4a1040b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1788244762 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.g
pio_stress_all.1788244762
Directory /workspace/7.gpio_stress_all/latest

Test location /workspace/coverage/default/7.gpio_stress_all_with_rand_reset.4063694096
Short name T529
Test name
Test status
Simulation time 37613010359 ps
CPU time 1175.84 seconds
Started Dec 24 01:10:27 PM PST 23
Finished Dec 24 01:30:05 PM PST 23
Peak memory 198384 kb
Host smart-0b4cad41-a6c6-45a6-be83-a2a1b0a54bc2
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=4063694096 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_stress_all_with_rand_reset.4063694096
Directory /workspace/7.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/8.gpio_alert_test.2397625153
Short name T640
Test name
Test status
Simulation time 24486299 ps
CPU time 0.58 seconds
Started Dec 24 01:10:21 PM PST 23
Finished Dec 24 01:10:24 PM PST 23
Peak memory 194064 kb
Host smart-b7d23617-08ff-4ed6-8292-8c501b87c402
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2397625153 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_alert_test.2397625153
Directory /workspace/8.gpio_alert_test/latest

Test location /workspace/coverage/default/8.gpio_dout_din_regs_random_rw.4130206328
Short name T600
Test name
Test status
Simulation time 356402073 ps
CPU time 0.92 seconds
Started Dec 24 01:10:05 PM PST 23
Finished Dec 24 01:10:10 PM PST 23
Peak memory 196704 kb
Host smart-b7573d93-22e9-4cb4-ab28-7670e487fcfe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4130206328 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_dout_din_regs_random_rw.4130206328
Directory /workspace/8.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/8.gpio_filter_stress.651860464
Short name T798
Test name
Test status
Simulation time 2399710702 ps
CPU time 16.4 seconds
Started Dec 24 01:10:04 PM PST 23
Finished Dec 24 01:10:24 PM PST 23
Peak memory 196868 kb
Host smart-b1283e0e-0b4f-4433-9dc7-c10757958fd9
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=651860464 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_filter_stress
.651860464
Directory /workspace/8.gpio_filter_stress/latest

Test location /workspace/coverage/default/8.gpio_full_random.2602784340
Short name T295
Test name
Test status
Simulation time 83581132 ps
CPU time 0.98 seconds
Started Dec 24 01:10:10 PM PST 23
Finished Dec 24 01:10:16 PM PST 23
Peak memory 197112 kb
Host smart-1e3973b0-97cd-4cc1-b04c-c3f040b5955c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2602784340 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_full_random.2602784340
Directory /workspace/8.gpio_full_random/latest

Test location /workspace/coverage/default/8.gpio_intr_rand_pgm.2297100172
Short name T470
Test name
Test status
Simulation time 147954784 ps
CPU time 0.7 seconds
Started Dec 24 01:10:05 PM PST 23
Finished Dec 24 01:10:12 PM PST 23
Peak memory 195028 kb
Host smart-e90af464-a345-42af-a87d-f84797c27f0d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2297100172 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_intr_rand_pgm.2297100172
Directory /workspace/8.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/8.gpio_intr_with_filter_rand_intr_event.1183123421
Short name T282
Test name
Test status
Simulation time 165293509 ps
CPU time 3.21 seconds
Started Dec 24 01:10:21 PM PST 23
Finished Dec 24 01:10:27 PM PST 23
Peak memory 198276 kb
Host smart-51366387-f862-4d73-a4ca-059556c205a0
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1183123421 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 8.gpio_intr_with_filter_rand_intr_event.1183123421
Directory /workspace/8.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/8.gpio_rand_intr_trigger.702086532
Short name T267
Test name
Test status
Simulation time 275117389 ps
CPU time 2.07 seconds
Started Dec 24 01:10:07 PM PST 23
Finished Dec 24 01:10:15 PM PST 23
Peak memory 197140 kb
Host smart-6da4579b-f8b2-46d8-950a-4aaae00d127f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=702086532 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_rand_intr_trigger.702086532
Directory /workspace/8.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/8.gpio_random_dout_din.1714663564
Short name T503
Test name
Test status
Simulation time 68982134 ps
CPU time 0.66 seconds
Started Dec 24 01:10:04 PM PST 23
Finished Dec 24 01:10:09 PM PST 23
Peak memory 194388 kb
Host smart-f8545f0d-d3be-4890-afe7-1aa53f2fa46f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1714663564 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_random_dout_din.1714663564
Directory /workspace/8.gpio_random_dout_din/latest

Test location /workspace/coverage/default/8.gpio_random_dout_din_no_pullup_pulldown.3348591850
Short name T785
Test name
Test status
Simulation time 51671498 ps
CPU time 1.06 seconds
Started Dec 24 01:10:04 PM PST 23
Finished Dec 24 01:10:09 PM PST 23
Peak memory 196080 kb
Host smart-882a423d-842a-4791-b085-99973c3382f8
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3348591850 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_random_dout_din_no_pullup
_pulldown.3348591850
Directory /workspace/8.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/8.gpio_random_long_reg_writes_reg_reads.3600216790
Short name T390
Test name
Test status
Simulation time 1168536764 ps
CPU time 4.17 seconds
Started Dec 24 01:10:13 PM PST 23
Finished Dec 24 01:10:22 PM PST 23
Peak memory 197996 kb
Host smart-234c3368-a746-46a5-9d4a-86975b919186
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3600216790 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_ran
dom_long_reg_writes_reg_reads.3600216790
Directory /workspace/8.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/8.gpio_smoke.2681857829
Short name T468
Test name
Test status
Simulation time 33655256 ps
CPU time 1.11 seconds
Started Dec 24 01:10:08 PM PST 23
Finished Dec 24 01:10:15 PM PST 23
Peak memory 196524 kb
Host smart-ab5cac80-7b8d-4d15-867c-76fcedb6b280
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2681857829 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_smoke.2681857829
Directory /workspace/8.gpio_smoke/latest

Test location /workspace/coverage/default/8.gpio_smoke_no_pullup_pulldown.3115783523
Short name T442
Test name
Test status
Simulation time 59827658 ps
CPU time 1.16 seconds
Started Dec 24 01:10:08 PM PST 23
Finished Dec 24 01:10:15 PM PST 23
Peak memory 196384 kb
Host smart-4b1dce03-3638-46a4-9895-bc202ecc620c
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3115783523 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_smoke_no_pullup_pulldown.3115783523
Directory /workspace/8.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/8.gpio_stress_all.3203771465
Short name T755
Test name
Test status
Simulation time 4273353719 ps
CPU time 30.21 seconds
Started Dec 24 01:10:05 PM PST 23
Finished Dec 24 01:10:39 PM PST 23
Peak memory 198256 kb
Host smart-0b5b8760-cc8c-4bf8-a9a9-72f89c6e2cc7
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3203771465 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.g
pio_stress_all.3203771465
Directory /workspace/8.gpio_stress_all/latest

Test location /workspace/coverage/default/8.gpio_stress_all_with_rand_reset.3771012143
Short name T297
Test name
Test status
Simulation time 58429031371 ps
CPU time 806.45 seconds
Started Dec 24 01:10:28 PM PST 23
Finished Dec 24 01:23:57 PM PST 23
Peak memory 198408 kb
Host smart-eaef1d74-fd26-4ed7-9e7b-7dd8d018083c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=3771012143 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_stress_all_with_rand_reset.3771012143
Directory /workspace/8.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/9.gpio_alert_test.637905959
Short name T871
Test name
Test status
Simulation time 30196487 ps
CPU time 0.56 seconds
Started Dec 24 01:10:04 PM PST 23
Finished Dec 24 01:10:08 PM PST 23
Peak memory 194064 kb
Host smart-804e146c-b7a4-418b-9ca7-f11338654d67
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=637905959 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_alert_test.637905959
Directory /workspace/9.gpio_alert_test/latest

Test location /workspace/coverage/default/9.gpio_dout_din_regs_random_rw.3991782998
Short name T652
Test name
Test status
Simulation time 44441567 ps
CPU time 0.93 seconds
Started Dec 24 01:10:04 PM PST 23
Finished Dec 24 01:10:09 PM PST 23
Peak memory 196136 kb
Host smart-f21c2e4c-ceba-4cb0-a48f-62901a6d1572
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3991782998 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_dout_din_regs_random_rw.3991782998
Directory /workspace/9.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/9.gpio_filter_stress.688628033
Short name T623
Test name
Test status
Simulation time 2275389055 ps
CPU time 20.25 seconds
Started Dec 24 01:10:02 PM PST 23
Finished Dec 24 01:10:26 PM PST 23
Peak memory 196452 kb
Host smart-e62ed1c4-f804-4d4c-bdd5-8e549c3a5c6a
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=688628033 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_filter_stress
.688628033
Directory /workspace/9.gpio_filter_stress/latest

Test location /workspace/coverage/default/9.gpio_full_random.1493824070
Short name T531
Test name
Test status
Simulation time 62454182 ps
CPU time 0.93 seconds
Started Dec 24 01:10:20 PM PST 23
Finished Dec 24 01:10:24 PM PST 23
Peak memory 197012 kb
Host smart-4353e0bc-adbf-4cc2-8444-0b68ae053542
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1493824070 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_full_random.1493824070
Directory /workspace/9.gpio_full_random/latest

Test location /workspace/coverage/default/9.gpio_intr_rand_pgm.309063896
Short name T632
Test name
Test status
Simulation time 40507103 ps
CPU time 0.85 seconds
Started Dec 24 01:10:04 PM PST 23
Finished Dec 24 01:10:09 PM PST 23
Peak memory 196244 kb
Host smart-edbd852b-bdaf-49db-8bee-5c35b5e0d6b9
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=309063896 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_intr_rand_pgm.309063896
Directory /workspace/9.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/9.gpio_intr_with_filter_rand_intr_event.2301313232
Short name T580
Test name
Test status
Simulation time 48326641 ps
CPU time 2 seconds
Started Dec 24 01:10:20 PM PST 23
Finished Dec 24 01:10:25 PM PST 23
Peak memory 196628 kb
Host smart-d5860c58-7c9b-4cc0-8851-242d0e09beeb
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2301313232 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 9.gpio_intr_with_filter_rand_intr_event.2301313232
Directory /workspace/9.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/9.gpio_rand_intr_trigger.1031331659
Short name T318
Test name
Test status
Simulation time 348633137 ps
CPU time 3.15 seconds
Started Dec 24 01:10:07 PM PST 23
Finished Dec 24 01:10:17 PM PST 23
Peak memory 196656 kb
Host smart-04c0a200-7c5b-4cdf-ac25-355c0b8e4086
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1031331659 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_rand_intr_trigger.
1031331659
Directory /workspace/9.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/9.gpio_random_dout_din.792049050
Short name T592
Test name
Test status
Simulation time 38765602 ps
CPU time 0.69 seconds
Started Dec 24 01:10:13 PM PST 23
Finished Dec 24 01:10:18 PM PST 23
Peak memory 196156 kb
Host smart-8fa7cfaf-da59-4061-8ab6-db8d36cbda4e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=792049050 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_random_dout_din.792049050
Directory /workspace/9.gpio_random_dout_din/latest

Test location /workspace/coverage/default/9.gpio_random_dout_din_no_pullup_pulldown.3150209052
Short name T767
Test name
Test status
Simulation time 109754254 ps
CPU time 1.35 seconds
Started Dec 24 01:10:13 PM PST 23
Finished Dec 24 01:10:19 PM PST 23
Peak memory 197084 kb
Host smart-2ecdb490-0c69-472b-8183-c4634977dbf9
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3150209052 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_random_dout_din_no_pullup
_pulldown.3150209052
Directory /workspace/9.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/9.gpio_random_long_reg_writes_reg_reads.4271912020
Short name T309
Test name
Test status
Simulation time 455859980 ps
CPU time 5.04 seconds
Started Dec 24 01:10:07 PM PST 23
Finished Dec 24 01:10:18 PM PST 23
Peak memory 197980 kb
Host smart-40b792d1-6a35-4ada-affe-7ab0de0f4e7d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4271912020 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_ran
dom_long_reg_writes_reg_reads.4271912020
Directory /workspace/9.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/9.gpio_smoke.4189191258
Short name T393
Test name
Test status
Simulation time 1100662227 ps
CPU time 1.31 seconds
Started Dec 24 01:10:13 PM PST 23
Finished Dec 24 01:10:19 PM PST 23
Peak memory 196780 kb
Host smart-3aca6045-65f3-4386-8ac1-ef5442ec741e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4189191258 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_smoke.4189191258
Directory /workspace/9.gpio_smoke/latest

Test location /workspace/coverage/default/9.gpio_smoke_no_pullup_pulldown.3695174717
Short name T733
Test name
Test status
Simulation time 108813016 ps
CPU time 0.78 seconds
Started Dec 24 01:10:22 PM PST 23
Finished Dec 24 01:10:26 PM PST 23
Peak memory 195976 kb
Host smart-214e66a9-3844-4735-96ad-0ba860ce1297
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3695174717 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_smoke_no_pullup_pulldown.3695174717
Directory /workspace/9.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/9.gpio_stress_all.2640916062
Short name T835
Test name
Test status
Simulation time 74395902375 ps
CPU time 193.87 seconds
Started Dec 24 01:10:04 PM PST 23
Finished Dec 24 01:13:22 PM PST 23
Peak memory 198288 kb
Host smart-8faa3add-1bf0-4473-a5e5-aff243c5300f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2640916062 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.g
pio_stress_all.2640916062
Directory /workspace/9.gpio_stress_all/latest

Test location /workspace/coverage/default/9.gpio_stress_all_with_rand_reset.836426610
Short name T561
Test name
Test status
Simulation time 83982990939 ps
CPU time 598.12 seconds
Started Dec 24 01:10:05 PM PST 23
Finished Dec 24 01:20:07 PM PST 23
Peak memory 198216 kb
Host smart-ba118b46-7259-4958-bebe-32e5a6616c92
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=836426610 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_stress_all_with_rand_reset.836426610
Directory /workspace/9.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/en_cdc_prims/0.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2624862764
Short name T170
Test name
Test status
Simulation time 122689574 ps
CPU time 0.92 seconds
Started Dec 24 12:33:57 PM PST 23
Finished Dec 24 12:34:35 PM PST 23
Peak memory 197452 kb
Host smart-b6b592c2-acb4-4a27-aa22-2d813d240e72
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2624862764 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 0.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.2624862764
Directory /workspace/0.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/1.gpio_smoke_en_cdc_prim.2148107557
Short name T207
Test name
Test status
Simulation time 436874912 ps
CPU time 1.07 seconds
Started Dec 24 12:35:10 PM PST 23
Finished Dec 24 12:35:42 PM PST 23
Peak memory 194516 kb
Host smart-894cd010-7fb1-4298-90ac-700dfb6deacb
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2148107557 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 1.gpio_smoke_en_cdc_prim.2148107557
Directory /workspace/1.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/1.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1083437971
Short name T197
Test name
Test status
Simulation time 46380818 ps
CPU time 1.14 seconds
Started Dec 24 12:35:41 PM PST 23
Finished Dec 24 12:36:05 PM PST 23
Peak memory 195376 kb
Host smart-d2c9d1bf-ccfd-4f5a-ba9f-b0aaf52534ac
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1083437971 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 1.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.1083437971
Directory /workspace/1.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/10.gpio_smoke_en_cdc_prim.3925606977
Short name T145
Test name
Test status
Simulation time 49185300 ps
CPU time 1 seconds
Started Dec 24 12:33:59 PM PST 23
Finished Dec 24 12:34:38 PM PST 23
Peak memory 195404 kb
Host smart-070c85e4-ee19-48f9-b029-5a78d5369a33
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3925606977 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 10.gpio_smoke_en_cdc_prim.3925606977
Directory /workspace/10.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/10.gpio_smoke_no_pullup_pulldown_en_cdc_prim.29242843
Short name T155
Test name
Test status
Simulation time 126811842 ps
CPU time 0.9 seconds
Started Dec 24 12:33:58 PM PST 23
Finished Dec 24 12:34:37 PM PST 23
Peak memory 197652 kb
Host smart-c0ba19db-2fcb-40fc-b190-1ecf7747a071
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29242843 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 10.gpio_smoke_no_pullup_pulldown_e
n_cdc_prim.29242843
Directory /workspace/10.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/11.gpio_smoke_en_cdc_prim.2483028445
Short name T156
Test name
Test status
Simulation time 323010304 ps
CPU time 0.94 seconds
Started Dec 24 12:34:02 PM PST 23
Finished Dec 24 12:34:40 PM PST 23
Peak memory 195468 kb
Host smart-d0ca844a-4d2b-4f48-8343-f3ac7217dd6e
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2483028445 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 11.gpio_smoke_en_cdc_prim.2483028445
Directory /workspace/11.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/11.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1218109891
Short name T180
Test name
Test status
Simulation time 55312757 ps
CPU time 1.1 seconds
Started Dec 24 12:34:04 PM PST 23
Finished Dec 24 12:34:42 PM PST 23
Peak memory 197160 kb
Host smart-ad84a8b3-616f-4999-962a-4a36d62f5399
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1218109891 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 11.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.1218109891
Directory /workspace/11.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/12.gpio_smoke_en_cdc_prim.4001539453
Short name T161
Test name
Test status
Simulation time 246831904 ps
CPU time 1.07 seconds
Started Dec 24 12:34:07 PM PST 23
Finished Dec 24 12:34:45 PM PST 23
Peak memory 195408 kb
Host smart-4c0d7c90-bffc-4278-b93c-37ca54254577
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=4001539453 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 12.gpio_smoke_en_cdc_prim.4001539453
Directory /workspace/12.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/12.gpio_smoke_no_pullup_pulldown_en_cdc_prim.4025489081
Short name T164
Test name
Test status
Simulation time 294126493 ps
CPU time 1.22 seconds
Started Dec 24 12:33:58 PM PST 23
Finished Dec 24 12:34:37 PM PST 23
Peak memory 195592 kb
Host smart-1e4f5895-11a8-4d08-90ce-9da658972148
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4025489081 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 12.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.4025489081
Directory /workspace/12.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/13.gpio_smoke_en_cdc_prim.298366678
Short name T148
Test name
Test status
Simulation time 166871895 ps
CPU time 1.06 seconds
Started Dec 24 12:34:05 PM PST 23
Finished Dec 24 12:34:43 PM PST 23
Peak memory 195512 kb
Host smart-8671ad08-390e-4fdc-92c6-89d19a9e3ccf
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=298366678 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 13.gpio_smoke_en_cdc_prim.298366678
Directory /workspace/13.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/13.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1756391114
Short name T144
Test name
Test status
Simulation time 49921325 ps
CPU time 1.1 seconds
Started Dec 24 12:34:06 PM PST 23
Finished Dec 24 12:34:44 PM PST 23
Peak memory 196952 kb
Host smart-57076854-f2eb-48c7-b8b7-63c9e3cc20ff
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1756391114 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 13.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.1756391114
Directory /workspace/13.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/14.gpio_smoke_en_cdc_prim.3691645531
Short name T162
Test name
Test status
Simulation time 227804934 ps
CPU time 1.15 seconds
Started Dec 24 12:34:00 PM PST 23
Finished Dec 24 12:34:39 PM PST 23
Peak memory 196336 kb
Host smart-31fd8ec6-b4e3-42fa-a547-3f3022f852a7
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3691645531 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 14.gpio_smoke_en_cdc_prim.3691645531
Directory /workspace/14.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/14.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3795090966
Short name T127
Test name
Test status
Simulation time 58431472 ps
CPU time 1.21 seconds
Started Dec 24 12:34:18 PM PST 23
Finished Dec 24 12:34:53 PM PST 23
Peak memory 196548 kb
Host smart-ff3fc244-b56b-42f4-bb8b-51741ce2af17
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3795090966 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 14.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.3795090966
Directory /workspace/14.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/15.gpio_smoke_en_cdc_prim.3026533182
Short name T131
Test name
Test status
Simulation time 54685891 ps
CPU time 0.98 seconds
Started Dec 24 12:34:20 PM PST 23
Finished Dec 24 12:34:54 PM PST 23
Peak memory 196492 kb
Host smart-1fa690f3-d089-41e8-8b8a-d6e0b59cf0e7
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3026533182 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 15.gpio_smoke_en_cdc_prim.3026533182
Directory /workspace/15.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/15.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1927992013
Short name T177
Test name
Test status
Simulation time 256210134 ps
CPU time 1.12 seconds
Started Dec 24 12:33:45 PM PST 23
Finished Dec 24 12:34:23 PM PST 23
Peak memory 195164 kb
Host smart-0d2274d7-934e-4d21-bfe4-c9c313793f87
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1927992013 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 15.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.1927992013
Directory /workspace/15.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/16.gpio_smoke_en_cdc_prim.2173613788
Short name T213
Test name
Test status
Simulation time 45987013 ps
CPU time 0.93 seconds
Started Dec 24 12:34:00 PM PST 23
Finished Dec 24 12:34:39 PM PST 23
Peak memory 196900 kb
Host smart-9da33f76-9ac6-4c4b-8e27-99e27af68fbd
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2173613788 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 16.gpio_smoke_en_cdc_prim.2173613788
Directory /workspace/16.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/16.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2000226546
Short name T194
Test name
Test status
Simulation time 29265388 ps
CPU time 0.93 seconds
Started Dec 24 12:34:07 PM PST 23
Finished Dec 24 12:34:45 PM PST 23
Peak memory 196124 kb
Host smart-3c771b88-9dc7-4bf7-870d-36cc1800e7f3
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2000226546 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 16.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2000226546
Directory /workspace/16.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/17.gpio_smoke_en_cdc_prim.3197878452
Short name T195
Test name
Test status
Simulation time 75523870 ps
CPU time 1.16 seconds
Started Dec 24 12:34:11 PM PST 23
Finished Dec 24 12:34:48 PM PST 23
Peak memory 196488 kb
Host smart-2a3f0816-00db-458c-bfa3-fd66ccdf102d
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3197878452 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 17.gpio_smoke_en_cdc_prim.3197878452
Directory /workspace/17.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/17.gpio_smoke_no_pullup_pulldown_en_cdc_prim.578134157
Short name T129
Test name
Test status
Simulation time 41251177 ps
CPU time 0.75 seconds
Started Dec 24 12:34:00 PM PST 23
Finished Dec 24 12:34:38 PM PST 23
Peak memory 195056 kb
Host smart-b60111d7-2482-491b-a9d5-120934f3de3b
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=578134157 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 17.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.578134157
Directory /workspace/17.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/18.gpio_smoke_en_cdc_prim.1302527861
Short name T185
Test name
Test status
Simulation time 48977481 ps
CPU time 0.98 seconds
Started Dec 24 12:34:11 PM PST 23
Finished Dec 24 12:34:48 PM PST 23
Peak memory 195904 kb
Host smart-4fe42051-fef4-4f77-85bd-ff8c5e645785
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1302527861 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 18.gpio_smoke_en_cdc_prim.1302527861
Directory /workspace/18.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/18.gpio_smoke_no_pullup_pulldown_en_cdc_prim.4232758696
Short name T163
Test name
Test status
Simulation time 220060067 ps
CPU time 1.07 seconds
Started Dec 24 12:34:14 PM PST 23
Finished Dec 24 12:34:51 PM PST 23
Peak memory 196080 kb
Host smart-22e22ecd-2f5f-4d92-9155-95b79fa88b74
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4232758696 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 18.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.4232758696
Directory /workspace/18.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/19.gpio_smoke_en_cdc_prim.2034051119
Short name T198
Test name
Test status
Simulation time 73694555 ps
CPU time 1.18 seconds
Started Dec 24 12:34:17 PM PST 23
Finished Dec 24 12:34:53 PM PST 23
Peak memory 196340 kb
Host smart-60a68336-040a-47f7-9b37-6680fe7907d7
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2034051119 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 19.gpio_smoke_en_cdc_prim.2034051119
Directory /workspace/19.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/19.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3685896704
Short name T193
Test name
Test status
Simulation time 87827408 ps
CPU time 1.11 seconds
Started Dec 24 12:34:02 PM PST 23
Finished Dec 24 12:34:40 PM PST 23
Peak memory 196268 kb
Host smart-e7c34e18-77e3-4223-bbad-870428c1363c
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3685896704 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 19.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.3685896704
Directory /workspace/19.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/2.gpio_smoke_en_cdc_prim.1031337806
Short name T135
Test name
Test status
Simulation time 81065248 ps
CPU time 1.41 seconds
Started Dec 24 12:33:52 PM PST 23
Finished Dec 24 12:34:30 PM PST 23
Peak memory 195192 kb
Host smart-651268ce-2176-4775-83fe-647754b3ffd7
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1031337806 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 2.gpio_smoke_en_cdc_prim.1031337806
Directory /workspace/2.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/2.gpio_smoke_no_pullup_pulldown_en_cdc_prim.931158526
Short name T212
Test name
Test status
Simulation time 575996622 ps
CPU time 0.95 seconds
Started Dec 24 12:36:00 PM PST 23
Finished Dec 24 12:36:21 PM PST 23
Peak memory 195452 kb
Host smart-73019b3f-717d-4509-aba3-532d8cff051e
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=931158526 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 2.gpio_smoke_no_pullup_pulldown_e
n_cdc_prim.931158526
Directory /workspace/2.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/20.gpio_smoke_en_cdc_prim.3808808063
Short name T137
Test name
Test status
Simulation time 32277833 ps
CPU time 0.83 seconds
Started Dec 24 12:34:21 PM PST 23
Finished Dec 24 12:34:55 PM PST 23
Peak memory 195800 kb
Host smart-3b5b11c1-cc9d-4cdf-b141-786a2c530a1f
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3808808063 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 20.gpio_smoke_en_cdc_prim.3808808063
Directory /workspace/20.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/20.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1866771507
Short name T128
Test name
Test status
Simulation time 52746632 ps
CPU time 1.04 seconds
Started Dec 24 12:34:10 PM PST 23
Finished Dec 24 12:34:47 PM PST 23
Peak memory 195476 kb
Host smart-b130cfee-dad3-4c29-94ff-ca93e4dd96fa
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1866771507 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 20.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.1866771507
Directory /workspace/20.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/21.gpio_smoke_en_cdc_prim.387033547
Short name T142
Test name
Test status
Simulation time 882417084 ps
CPU time 1.31 seconds
Started Dec 24 12:34:27 PM PST 23
Finished Dec 24 12:35:00 PM PST 23
Peak memory 197772 kb
Host smart-cf3eab11-6a1e-46e9-941c-04fc4c5d6b7f
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=387033547 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 21.gpio_smoke_en_cdc_prim.387033547
Directory /workspace/21.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/21.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3173430773
Short name T206
Test name
Test status
Simulation time 57878535 ps
CPU time 1.01 seconds
Started Dec 24 12:34:08 PM PST 23
Finished Dec 24 12:34:45 PM PST 23
Peak memory 196224 kb
Host smart-fd4352dc-37d2-41a0-aedb-76c9803d9f37
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3173430773 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 21.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.3173430773
Directory /workspace/21.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/22.gpio_smoke_en_cdc_prim.2071327628
Short name T150
Test name
Test status
Simulation time 77369937 ps
CPU time 1.24 seconds
Started Dec 24 12:34:18 PM PST 23
Finished Dec 24 12:34:53 PM PST 23
Peak memory 196548 kb
Host smart-b9cd0c79-9a0c-4d98-b387-aa9f130c54d8
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2071327628 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 22.gpio_smoke_en_cdc_prim.2071327628
Directory /workspace/22.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/22.gpio_smoke_no_pullup_pulldown_en_cdc_prim.599006082
Short name T166
Test name
Test status
Simulation time 79152133 ps
CPU time 1.29 seconds
Started Dec 24 12:34:14 PM PST 23
Finished Dec 24 12:34:51 PM PST 23
Peak memory 196672 kb
Host smart-f5c70d3a-34d8-4f42-bec3-f7d884ffc793
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=599006082 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 22.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.599006082
Directory /workspace/22.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/23.gpio_smoke_en_cdc_prim.1548922369
Short name T53
Test name
Test status
Simulation time 265345457 ps
CPU time 0.98 seconds
Started Dec 24 12:34:11 PM PST 23
Finished Dec 24 12:34:48 PM PST 23
Peak memory 196172 kb
Host smart-8b766631-574d-449e-8ba3-ae015f88b225
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1548922369 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 23.gpio_smoke_en_cdc_prim.1548922369
Directory /workspace/23.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/23.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2170843894
Short name T168
Test name
Test status
Simulation time 160716535 ps
CPU time 1.04 seconds
Started Dec 24 12:33:48 PM PST 23
Finished Dec 24 12:34:26 PM PST 23
Peak memory 196392 kb
Host smart-eff0c97d-fc62-4b26-b94a-be180a0719ac
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2170843894 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 23.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2170843894
Directory /workspace/23.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/24.gpio_smoke_en_cdc_prim.1558762486
Short name T173
Test name
Test status
Simulation time 165209986 ps
CPU time 1.25 seconds
Started Dec 24 12:34:27 PM PST 23
Finished Dec 24 12:35:00 PM PST 23
Peak memory 196504 kb
Host smart-14499943-40b9-457d-adc9-86a5f5e64a03
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1558762486 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 24.gpio_smoke_en_cdc_prim.1558762486
Directory /workspace/24.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/24.gpio_smoke_no_pullup_pulldown_en_cdc_prim.625165012
Short name T184
Test name
Test status
Simulation time 33629868 ps
CPU time 0.75 seconds
Started Dec 24 12:34:09 PM PST 23
Finished Dec 24 12:34:46 PM PST 23
Peak memory 195060 kb
Host smart-96fab671-f9dd-4e13-aeb1-109eb1cb8b90
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=625165012 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 24.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.625165012
Directory /workspace/24.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/25.gpio_smoke_en_cdc_prim.4215418292
Short name T188
Test name
Test status
Simulation time 1029140800 ps
CPU time 1.05 seconds
Started Dec 24 12:34:07 PM PST 23
Finished Dec 24 12:34:45 PM PST 23
Peak memory 196096 kb
Host smart-f0262916-e4f5-42cb-9ec0-c51dc95809cb
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=4215418292 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 25.gpio_smoke_en_cdc_prim.4215418292
Directory /workspace/25.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/25.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3902137088
Short name T139
Test name
Test status
Simulation time 112171180 ps
CPU time 0.68 seconds
Started Dec 24 12:34:12 PM PST 23
Finished Dec 24 12:34:48 PM PST 23
Peak memory 194704 kb
Host smart-691c8c93-90d8-4304-a554-1d9d4455d24e
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3902137088 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 25.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.3902137088
Directory /workspace/25.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/26.gpio_smoke_en_cdc_prim.609858709
Short name T160
Test name
Test status
Simulation time 130902366 ps
CPU time 1.05 seconds
Started Dec 24 12:34:14 PM PST 23
Finished Dec 24 12:34:51 PM PST 23
Peak memory 195420 kb
Host smart-3b706228-8c3b-4525-aa49-cd7d071eadbf
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=609858709 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 26.gpio_smoke_en_cdc_prim.609858709
Directory /workspace/26.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/26.gpio_smoke_no_pullup_pulldown_en_cdc_prim.40052107
Short name T149
Test name
Test status
Simulation time 53070329 ps
CPU time 1.38 seconds
Started Dec 24 12:33:54 PM PST 23
Finished Dec 24 12:34:32 PM PST 23
Peak memory 196224 kb
Host smart-566fa385-4ed5-40ea-8e7a-6c75fa362db2
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40052107 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 26.gpio_smoke_no_pullup_pulldown_e
n_cdc_prim.40052107
Directory /workspace/26.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/27.gpio_smoke_en_cdc_prim.3225978016
Short name T196
Test name
Test status
Simulation time 40607509 ps
CPU time 1.26 seconds
Started Dec 24 12:34:28 PM PST 23
Finished Dec 24 12:35:01 PM PST 23
Peak memory 196604 kb
Host smart-8af730a2-f954-43d5-8cc8-01c317e3bd1c
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3225978016 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 27.gpio_smoke_en_cdc_prim.3225978016
Directory /workspace/27.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/27.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1590800141
Short name T171
Test name
Test status
Simulation time 542425466 ps
CPU time 1.3 seconds
Started Dec 24 12:34:11 PM PST 23
Finished Dec 24 12:34:48 PM PST 23
Peak memory 196348 kb
Host smart-ce90582d-54e6-4080-b17f-b4a23d4a0c5b
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1590800141 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 27.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.1590800141
Directory /workspace/27.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/28.gpio_smoke_en_cdc_prim.3207053730
Short name T71
Test name
Test status
Simulation time 90058529 ps
CPU time 1.28 seconds
Started Dec 24 12:34:12 PM PST 23
Finished Dec 24 12:34:49 PM PST 23
Peak memory 196620 kb
Host smart-9c8fba7a-ca3f-4ee3-bd10-cdfcd08ce00f
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3207053730 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 28.gpio_smoke_en_cdc_prim.3207053730
Directory /workspace/28.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/28.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2155516808
Short name T205
Test name
Test status
Simulation time 211758458 ps
CPU time 1.05 seconds
Started Dec 24 12:34:09 PM PST 23
Finished Dec 24 12:34:46 PM PST 23
Peak memory 195552 kb
Host smart-eff8216a-6e60-425c-9b63-4587f4670178
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2155516808 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 28.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2155516808
Directory /workspace/28.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/29.gpio_smoke_en_cdc_prim.3282497368
Short name T40
Test name
Test status
Simulation time 31796482 ps
CPU time 0.92 seconds
Started Dec 24 12:34:19 PM PST 23
Finished Dec 24 12:34:54 PM PST 23
Peak memory 196104 kb
Host smart-9dc56343-cdc1-4544-b8e0-991f1b91e9af
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3282497368 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 29.gpio_smoke_en_cdc_prim.3282497368
Directory /workspace/29.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/29.gpio_smoke_no_pullup_pulldown_en_cdc_prim.93472330
Short name T55
Test name
Test status
Simulation time 150991875 ps
CPU time 1.1 seconds
Started Dec 24 12:34:17 PM PST 23
Finished Dec 24 12:34:52 PM PST 23
Peak memory 195216 kb
Host smart-69ad4e9a-92b1-4ebd-bfc4-9f8ebc38640f
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=93472330 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 29.gpio_smoke_no_pullup_pulldown_e
n_cdc_prim.93472330
Directory /workspace/29.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/3.gpio_smoke_en_cdc_prim.1809138238
Short name T39
Test name
Test status
Simulation time 228371775 ps
CPU time 1.21 seconds
Started Dec 24 12:34:07 PM PST 23
Finished Dec 24 12:34:45 PM PST 23
Peak memory 196220 kb
Host smart-98eb41a4-0866-4bd7-a757-7abbaea00037
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1809138238 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 3.gpio_smoke_en_cdc_prim.1809138238
Directory /workspace/3.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/3.gpio_smoke_no_pullup_pulldown_en_cdc_prim.246241442
Short name T126
Test name
Test status
Simulation time 59134038 ps
CPU time 1.22 seconds
Started Dec 24 12:33:55 PM PST 23
Finished Dec 24 12:34:34 PM PST 23
Peak memory 195324 kb
Host smart-d1ba35eb-69c8-45ec-9e2b-8aee0719350b
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=246241442 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 3.gpio_smoke_no_pullup_pulldown_e
n_cdc_prim.246241442
Directory /workspace/3.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/30.gpio_smoke_en_cdc_prim.1911868238
Short name T181
Test name
Test status
Simulation time 194207644 ps
CPU time 1.07 seconds
Started Dec 24 12:34:18 PM PST 23
Finished Dec 24 12:34:53 PM PST 23
Peak memory 195964 kb
Host smart-327ea484-619b-42f0-bd68-d3eb64f8e4fa
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1911868238 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 30.gpio_smoke_en_cdc_prim.1911868238
Directory /workspace/30.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/30.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1705557550
Short name T191
Test name
Test status
Simulation time 61999350 ps
CPU time 0.68 seconds
Started Dec 24 12:34:22 PM PST 23
Finished Dec 24 12:34:55 PM PST 23
Peak memory 195768 kb
Host smart-05c658f3-35e3-4045-92d6-35a448960194
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1705557550 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 30.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.1705557550
Directory /workspace/30.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/31.gpio_smoke_en_cdc_prim.4136370158
Short name T147
Test name
Test status
Simulation time 149698523 ps
CPU time 1 seconds
Started Dec 24 12:34:15 PM PST 23
Finished Dec 24 12:34:51 PM PST 23
Peak memory 196248 kb
Host smart-3c20030e-7100-40ad-a1e1-8a39d93a3736
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=4136370158 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 31.gpio_smoke_en_cdc_prim.4136370158
Directory /workspace/31.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/32.gpio_smoke_en_cdc_prim.36698340
Short name T211
Test name
Test status
Simulation time 484254078 ps
CPU time 0.77 seconds
Started Dec 24 12:34:05 PM PST 23
Finished Dec 24 12:34:43 PM PST 23
Peak memory 195812 kb
Host smart-d5ff8f1d-0461-417b-81a2-5754d65a17b0
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=36698340 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 32.gpio_smoke_en_cdc_prim.36698340
Directory /workspace/32.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/32.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3488043280
Short name T165
Test name
Test status
Simulation time 97119236 ps
CPU time 0.91 seconds
Started Dec 24 12:34:23 PM PST 23
Finished Dec 24 12:34:57 PM PST 23
Peak memory 196064 kb
Host smart-83daae28-abb1-4c44-87b9-c04e994413e7
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3488043280 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 32.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.3488043280
Directory /workspace/32.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/33.gpio_smoke_en_cdc_prim.228102921
Short name T158
Test name
Test status
Simulation time 465236125 ps
CPU time 1.15 seconds
Started Dec 24 12:34:25 PM PST 23
Finished Dec 24 12:34:58 PM PST 23
Peak memory 197568 kb
Host smart-995990d2-5aa8-4a97-931b-79a6fb9db308
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=228102921 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 33.gpio_smoke_en_cdc_prim.228102921
Directory /workspace/33.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/33.gpio_smoke_no_pullup_pulldown_en_cdc_prim.141269050
Short name T130
Test name
Test status
Simulation time 231879969 ps
CPU time 1.42 seconds
Started Dec 24 12:34:12 PM PST 23
Finished Dec 24 12:34:49 PM PST 23
Peak memory 196516 kb
Host smart-2b8878ae-6a17-4e53-b0be-aa00769c298f
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=141269050 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 33.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.141269050
Directory /workspace/33.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/34.gpio_smoke_en_cdc_prim.890289974
Short name T133
Test name
Test status
Simulation time 241739994 ps
CPU time 1.42 seconds
Started Dec 24 12:34:20 PM PST 23
Finished Dec 24 12:34:54 PM PST 23
Peak memory 197700 kb
Host smart-be7c608d-cd41-40e6-a04a-b63143fc7775
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=890289974 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 34.gpio_smoke_en_cdc_prim.890289974
Directory /workspace/34.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/34.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1873516508
Short name T146
Test name
Test status
Simulation time 158653081 ps
CPU time 1.12 seconds
Started Dec 24 12:34:03 PM PST 23
Finished Dec 24 12:34:41 PM PST 23
Peak memory 197656 kb
Host smart-4f3355f1-40f6-4c1f-b942-0258c5b6d078
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1873516508 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 34.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.1873516508
Directory /workspace/34.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/35.gpio_smoke_en_cdc_prim.176258344
Short name T187
Test name
Test status
Simulation time 96764408 ps
CPU time 0.98 seconds
Started Dec 24 12:34:20 PM PST 23
Finished Dec 24 12:34:54 PM PST 23
Peak memory 196132 kb
Host smart-eb20b5a2-9aa1-4965-9b66-31b9d3802155
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=176258344 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 35.gpio_smoke_en_cdc_prim.176258344
Directory /workspace/35.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/35.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2264593892
Short name T132
Test name
Test status
Simulation time 49887129 ps
CPU time 1.02 seconds
Started Dec 24 12:34:33 PM PST 23
Finished Dec 24 12:35:07 PM PST 23
Peak memory 196208 kb
Host smart-7b5060b6-493d-4326-8195-b5c4c69544d8
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2264593892 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 35.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2264593892
Directory /workspace/35.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/36.gpio_smoke_en_cdc_prim.4087120336
Short name T154
Test name
Test status
Simulation time 161494452 ps
CPU time 1.16 seconds
Started Dec 24 12:34:20 PM PST 23
Finished Dec 24 12:34:54 PM PST 23
Peak memory 195252 kb
Host smart-4a64bcd5-739a-42b0-b1d5-ca219e99f77a
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=4087120336 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 36.gpio_smoke_en_cdc_prim.4087120336
Directory /workspace/36.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/36.gpio_smoke_no_pullup_pulldown_en_cdc_prim.959289026
Short name T182
Test name
Test status
Simulation time 292378968 ps
CPU time 1.17 seconds
Started Dec 24 12:34:09 PM PST 23
Finished Dec 24 12:34:47 PM PST 23
Peak memory 196316 kb
Host smart-bf206d2f-73cc-4d2d-ba29-41854f8c6e29
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=959289026 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 36.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.959289026
Directory /workspace/36.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/37.gpio_smoke_en_cdc_prim.884713789
Short name T169
Test name
Test status
Simulation time 46322521 ps
CPU time 0.82 seconds
Started Dec 24 12:34:14 PM PST 23
Finished Dec 24 12:34:51 PM PST 23
Peak memory 195056 kb
Host smart-74b092ca-3f2e-4093-8d87-908189b94109
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=884713789 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 37.gpio_smoke_en_cdc_prim.884713789
Directory /workspace/37.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/37.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1935151145
Short name T51
Test name
Test status
Simulation time 28011330 ps
CPU time 0.87 seconds
Started Dec 24 12:34:35 PM PST 23
Finished Dec 24 12:35:10 PM PST 23
Peak memory 195764 kb
Host smart-d2effb02-9550-4639-add0-d52e4be521d2
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1935151145 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 37.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.1935151145
Directory /workspace/37.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/38.gpio_smoke_en_cdc_prim.2184342078
Short name T141
Test name
Test status
Simulation time 68219257 ps
CPU time 1.17 seconds
Started Dec 24 12:34:20 PM PST 23
Finished Dec 24 12:34:55 PM PST 23
Peak memory 197620 kb
Host smart-39d7b6ea-7745-4be6-90b7-aec5924c83bc
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2184342078 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 38.gpio_smoke_en_cdc_prim.2184342078
Directory /workspace/38.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/38.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2194164418
Short name T172
Test name
Test status
Simulation time 500522355 ps
CPU time 0.84 seconds
Started Dec 24 12:34:23 PM PST 23
Finished Dec 24 12:34:57 PM PST 23
Peak memory 196312 kb
Host smart-b22a1c5e-2dea-48a6-a672-082f6f4ad78e
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2194164418 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 38.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2194164418
Directory /workspace/38.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/39.gpio_smoke_en_cdc_prim.4051129747
Short name T186
Test name
Test status
Simulation time 37328960 ps
CPU time 1.05 seconds
Started Dec 24 12:34:11 PM PST 23
Finished Dec 24 12:34:48 PM PST 23
Peak memory 195596 kb
Host smart-49b5be99-99cf-4a4a-a4de-6bd0261ba22e
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=4051129747 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 39.gpio_smoke_en_cdc_prim.4051129747
Directory /workspace/39.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/39.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1801859484
Short name T209
Test name
Test status
Simulation time 54699703 ps
CPU time 1.03 seconds
Started Dec 24 12:34:19 PM PST 23
Finished Dec 24 12:34:54 PM PST 23
Peak memory 196096 kb
Host smart-65d9b805-61ef-4b38-8972-6f979c3473f0
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1801859484 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 39.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.1801859484
Directory /workspace/39.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/4.gpio_smoke_en_cdc_prim.521125449
Short name T202
Test name
Test status
Simulation time 29623166 ps
CPU time 0.85 seconds
Started Dec 24 12:33:54 PM PST 23
Finished Dec 24 12:34:32 PM PST 23
Peak memory 196320 kb
Host smart-563e3c5a-683e-421f-9142-518fdacb0467
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=521125449 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 4.gpio_smoke_en_cdc_prim.521125449
Directory /workspace/4.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/4.gpio_smoke_no_pullup_pulldown_en_cdc_prim.864362533
Short name T157
Test name
Test status
Simulation time 409164662 ps
CPU time 1.1 seconds
Started Dec 24 12:33:57 PM PST 23
Finished Dec 24 12:34:35 PM PST 23
Peak memory 196088 kb
Host smart-a20e9d55-b386-4e5b-8742-114613412364
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=864362533 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 4.gpio_smoke_no_pullup_pulldown_e
n_cdc_prim.864362533
Directory /workspace/4.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/40.gpio_smoke_en_cdc_prim.1655022993
Short name T175
Test name
Test status
Simulation time 66897269 ps
CPU time 1.04 seconds
Started Dec 24 12:34:03 PM PST 23
Finished Dec 24 12:34:42 PM PST 23
Peak memory 197340 kb
Host smart-0a38e8c8-60fb-4bac-892f-33fc1d19b9be
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1655022993 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 40.gpio_smoke_en_cdc_prim.1655022993
Directory /workspace/40.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/40.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2156794728
Short name T208
Test name
Test status
Simulation time 23392659 ps
CPU time 0.71 seconds
Started Dec 24 12:34:17 PM PST 23
Finished Dec 24 12:34:52 PM PST 23
Peak memory 194040 kb
Host smart-7cd66f63-095f-4f72-89af-1199c71dcad7
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2156794728 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 40.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2156794728
Directory /workspace/40.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/41.gpio_smoke_en_cdc_prim.3968441870
Short name T143
Test name
Test status
Simulation time 252896291 ps
CPU time 1.2 seconds
Started Dec 24 12:34:13 PM PST 23
Finished Dec 24 12:34:50 PM PST 23
Peak memory 196240 kb
Host smart-f6855a52-95bf-406e-a846-d83234e17279
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3968441870 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 41.gpio_smoke_en_cdc_prim.3968441870
Directory /workspace/41.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/41.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2007258195
Short name T201
Test name
Test status
Simulation time 128981860 ps
CPU time 1.09 seconds
Started Dec 24 12:34:17 PM PST 23
Finished Dec 24 12:34:52 PM PST 23
Peak memory 196216 kb
Host smart-aa3f6524-8ca0-4950-8ce4-dca3892ef2f2
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2007258195 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 41.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2007258195
Directory /workspace/41.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/42.gpio_smoke_en_cdc_prim.487406875
Short name T159
Test name
Test status
Simulation time 138700015 ps
CPU time 1.12 seconds
Started Dec 24 12:34:15 PM PST 23
Finished Dec 24 12:34:51 PM PST 23
Peak memory 195548 kb
Host smart-3322e05c-5028-4bc7-bea5-a41eb9488f18
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=487406875 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 42.gpio_smoke_en_cdc_prim.487406875
Directory /workspace/42.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/42.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1035248002
Short name T151
Test name
Test status
Simulation time 184950202 ps
CPU time 0.88 seconds
Started Dec 24 12:34:30 PM PST 23
Finished Dec 24 12:35:03 PM PST 23
Peak memory 195860 kb
Host smart-9b89a0e1-1138-46d9-bda8-de839f2cb658
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1035248002 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 42.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.1035248002
Directory /workspace/42.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/43.gpio_smoke_en_cdc_prim.1273847340
Short name T192
Test name
Test status
Simulation time 599312664 ps
CPU time 1.2 seconds
Started Dec 24 12:34:20 PM PST 23
Finished Dec 24 12:34:54 PM PST 23
Peak memory 196156 kb
Host smart-b63a6016-b102-4bed-bae4-928e35659bb7
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1273847340 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 43.gpio_smoke_en_cdc_prim.1273847340
Directory /workspace/43.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/43.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2803855233
Short name T134
Test name
Test status
Simulation time 81609955 ps
CPU time 1.24 seconds
Started Dec 24 12:34:17 PM PST 23
Finished Dec 24 12:34:53 PM PST 23
Peak memory 197640 kb
Host smart-70f587ed-6e38-4583-8382-da2fcf69c6f6
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2803855233 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 43.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2803855233
Directory /workspace/43.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/44.gpio_smoke_en_cdc_prim.3572678503
Short name T204
Test name
Test status
Simulation time 266880542 ps
CPU time 1.17 seconds
Started Dec 24 12:34:27 PM PST 23
Finished Dec 24 12:35:00 PM PST 23
Peak memory 196064 kb
Host smart-0141a8f4-b8c4-44b1-a576-1b6507e0f26d
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3572678503 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 44.gpio_smoke_en_cdc_prim.3572678503
Directory /workspace/44.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/44.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2562310253
Short name T167
Test name
Test status
Simulation time 106281041 ps
CPU time 0.9 seconds
Started Dec 24 12:35:40 PM PST 23
Finished Dec 24 12:36:04 PM PST 23
Peak memory 195900 kb
Host smart-42a22553-3731-415f-9d51-b8989e86a7ec
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2562310253 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 44.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2562310253
Directory /workspace/44.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/45.gpio_smoke_en_cdc_prim.2744371836
Short name T189
Test name
Test status
Simulation time 186975275 ps
CPU time 1.01 seconds
Started Dec 24 12:34:18 PM PST 23
Finished Dec 24 12:34:53 PM PST 23
Peak memory 197084 kb
Host smart-e793783b-6fc1-4e4b-a76e-612ab0a11593
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2744371836 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 45.gpio_smoke_en_cdc_prim.2744371836
Directory /workspace/45.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/45.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3344998812
Short name T199
Test name
Test status
Simulation time 62468842 ps
CPU time 1.05 seconds
Started Dec 24 12:35:41 PM PST 23
Finished Dec 24 12:36:05 PM PST 23
Peak memory 195956 kb
Host smart-ae336c08-c712-4f4d-8e2b-ee3fe7587d13
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3344998812 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 45.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.3344998812
Directory /workspace/45.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/46.gpio_smoke_en_cdc_prim.2113970659
Short name T190
Test name
Test status
Simulation time 114285986 ps
CPU time 0.82 seconds
Started Dec 24 12:34:22 PM PST 23
Finished Dec 24 12:34:56 PM PST 23
Peak memory 196276 kb
Host smart-e6ad19b9-48a8-4ce3-a609-671ab86708eb
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2113970659 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 46.gpio_smoke_en_cdc_prim.2113970659
Directory /workspace/46.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/46.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2009985007
Short name T203
Test name
Test status
Simulation time 67967478 ps
CPU time 1.22 seconds
Started Dec 24 12:34:20 PM PST 23
Finished Dec 24 12:34:54 PM PST 23
Peak memory 196276 kb
Host smart-23eff0b1-9fe5-4469-8572-7e2e558a7f1a
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2009985007 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 46.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2009985007
Directory /workspace/46.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/47.gpio_smoke_en_cdc_prim.2554267442
Short name T54
Test name
Test status
Simulation time 30236656 ps
CPU time 0.96 seconds
Started Dec 24 12:34:08 PM PST 23
Finished Dec 24 12:34:45 PM PST 23
Peak memory 195472 kb
Host smart-74ba74d3-d000-4870-934c-414f8f1d0185
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2554267442 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 47.gpio_smoke_en_cdc_prim.2554267442
Directory /workspace/47.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/47.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1256808657
Short name T152
Test name
Test status
Simulation time 1002347738 ps
CPU time 1.42 seconds
Started Dec 24 12:34:01 PM PST 23
Finished Dec 24 12:34:40 PM PST 23
Peak memory 196256 kb
Host smart-bca1ef89-750e-4815-a25c-37abeb5ba1e6
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1256808657 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 47.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.1256808657
Directory /workspace/47.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/48.gpio_smoke_en_cdc_prim.591314447
Short name T179
Test name
Test status
Simulation time 47905045 ps
CPU time 1.22 seconds
Started Dec 24 12:34:41 PM PST 23
Finished Dec 24 12:35:15 PM PST 23
Peak memory 196352 kb
Host smart-b3829c84-baab-4920-89fd-bf4e11ab7b53
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=591314447 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 48.gpio_smoke_en_cdc_prim.591314447
Directory /workspace/48.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/48.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1974721991
Short name T178
Test name
Test status
Simulation time 198851323 ps
CPU time 0.88 seconds
Started Dec 24 12:34:17 PM PST 23
Finished Dec 24 12:34:52 PM PST 23
Peak memory 196912 kb
Host smart-7c5e7bed-b1f8-46b7-a012-2017779d1080
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1974721991 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 48.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.1974721991
Directory /workspace/48.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/49.gpio_smoke_en_cdc_prim.907434369
Short name T200
Test name
Test status
Simulation time 297970112 ps
CPU time 1.25 seconds
Started Dec 24 12:34:12 PM PST 23
Finished Dec 24 12:34:49 PM PST 23
Peak memory 196628 kb
Host smart-b42ab701-32ff-4c50-8930-7c1d1c14d40d
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=907434369 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 49.gpio_smoke_en_cdc_prim.907434369
Directory /workspace/49.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/49.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1169960215
Short name T52
Test name
Test status
Simulation time 366892903 ps
CPU time 1.06 seconds
Started Dec 24 12:34:08 PM PST 23
Finished Dec 24 12:34:45 PM PST 23
Peak memory 195412 kb
Host smart-bd2a2408-4e7e-4037-a7fb-7a56d5f90629
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1169960215 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 49.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.1169960215
Directory /workspace/49.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/5.gpio_smoke_en_cdc_prim.2254704846
Short name T153
Test name
Test status
Simulation time 132601851 ps
CPU time 0.81 seconds
Started Dec 24 12:33:56 PM PST 23
Finished Dec 24 12:34:34 PM PST 23
Peak memory 194880 kb
Host smart-ff51dbb5-baee-40db-a17f-b6763ffe33f2
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2254704846 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 5.gpio_smoke_en_cdc_prim.2254704846
Directory /workspace/5.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/5.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1002364354
Short name T183
Test name
Test status
Simulation time 63040954 ps
CPU time 1.15 seconds
Started Dec 24 12:33:56 PM PST 23
Finished Dec 24 12:34:35 PM PST 23
Peak memory 196320 kb
Host smart-0ccefd00-780b-408d-ad1f-ae6704319073
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1002364354 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 5.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.1002364354
Directory /workspace/5.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/6.gpio_smoke_en_cdc_prim.1207453761
Short name T50
Test name
Test status
Simulation time 149554207 ps
CPU time 0.9 seconds
Started Dec 24 12:34:24 PM PST 23
Finished Dec 24 12:34:58 PM PST 23
Peak memory 196240 kb
Host smart-bb0a5a60-4bb1-4c05-9deb-207636c755a1
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1207453761 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 6.gpio_smoke_en_cdc_prim.1207453761
Directory /workspace/6.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/6.gpio_smoke_no_pullup_pulldown_en_cdc_prim.46741869
Short name T214
Test name
Test status
Simulation time 24103152 ps
CPU time 0.79 seconds
Started Dec 24 12:34:12 PM PST 23
Finished Dec 24 12:34:49 PM PST 23
Peak memory 195860 kb
Host smart-07b3f15d-58ea-4cf4-870c-c716df395c38
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=46741869 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 6.gpio_smoke_no_pullup_pulldown_en
_cdc_prim.46741869
Directory /workspace/6.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/7.gpio_smoke_en_cdc_prim.3417981957
Short name T41
Test name
Test status
Simulation time 36329315 ps
CPU time 1.01 seconds
Started Dec 24 12:34:08 PM PST 23
Finished Dec 24 12:34:45 PM PST 23
Peak memory 197584 kb
Host smart-0c3f9242-e973-4703-b042-ea1d57cd74ea
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3417981957 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 7.gpio_smoke_en_cdc_prim.3417981957
Directory /workspace/7.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/7.gpio_smoke_no_pullup_pulldown_en_cdc_prim.485063825
Short name T176
Test name
Test status
Simulation time 139426560 ps
CPU time 0.84 seconds
Started Dec 24 12:34:13 PM PST 23
Finished Dec 24 12:34:49 PM PST 23
Peak memory 197000 kb
Host smart-710371ea-dc32-4b80-a8d4-4bba61b9f669
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=485063825 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 7.gpio_smoke_no_pullup_pulldown_e
n_cdc_prim.485063825
Directory /workspace/7.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/8.gpio_smoke_en_cdc_prim.936948259
Short name T138
Test name
Test status
Simulation time 39637084 ps
CPU time 1.02 seconds
Started Dec 24 12:34:06 PM PST 23
Finished Dec 24 12:34:45 PM PST 23
Peak memory 196188 kb
Host smart-043aced4-7826-4642-bdbd-5cf7f259b705
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=936948259 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 8.gpio_smoke_en_cdc_prim.936948259
Directory /workspace/8.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/8.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3138571990
Short name T174
Test name
Test status
Simulation time 126533896 ps
CPU time 1.28 seconds
Started Dec 24 12:33:56 PM PST 23
Finished Dec 24 12:34:34 PM PST 23
Peak memory 197696 kb
Host smart-3fc6c39a-5924-4107-b9ac-ada7c1710650
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3138571990 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 8.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.3138571990
Directory /workspace/8.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/9.gpio_smoke_en_cdc_prim.3435244313
Short name T210
Test name
Test status
Simulation time 193892503 ps
CPU time 1.02 seconds
Started Dec 24 12:34:17 PM PST 23
Finished Dec 24 12:34:52 PM PST 23
Peak memory 197596 kb
Host smart-3649460a-1200-46fc-9a61-66d20b056683
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3435244313 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 9.gpio_smoke_en_cdc_prim.3435244313
Directory /workspace/9.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/9.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3239182077
Short name T140
Test name
Test status
Simulation time 123001760 ps
CPU time 0.87 seconds
Started Dec 24 12:34:10 PM PST 23
Finished Dec 24 12:34:47 PM PST 23
Peak memory 195328 kb
Host smart-3f9e691b-dd7b-4e60-88a1-9ebf155a9757
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3239182077 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 9.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.3239182077
Directory /workspace/9.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest
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