Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=31}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=31}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=31}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	36	0	36	100.00
Crosses	128	0	128	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=31}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	32	0	32	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=31}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	128	0	128	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	32	0	32	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	6128245	1			T22	12		T23	2		T19	9
all_pins[1]	6128245	1			T22	12		T23	2		T19	9
all_pins[2]	6128245	1			T22	12		T23	2		T19	9
all_pins[3]	6128245	1			T22	12		T23	2		T19	9
all_pins[4]	6128245	1			T22	12		T23	2		T19	9
all_pins[5]	6128245	1			T22	12		T23	2		T19	9
all_pins[6]	6128245	1			T22	12		T23	2		T19	9
all_pins[7]	6128245	1			T22	12		T23	2		T19	9
all_pins[8]	6128245	1			T22	12		T23	2		T19	9
all_pins[9]	6128245	1			T22	12		T23	2		T19	9
all_pins[10]	6128245	1			T22	12		T23	2		T19	9
all_pins[11]	6128245	1			T22	12		T23	2		T19	9
all_pins[12]	6128245	1			T22	12		T23	2		T19	9
all_pins[13]	6128245	1			T22	12		T23	2		T19	9
all_pins[14]	6128245	1			T22	12		T23	2		T19	9
all_pins[15]	6128245	1			T22	12		T23	2		T19	9
all_pins[16]	6128245	1			T22	12		T23	2		T19	9
all_pins[17]	6128245	1			T22	12		T23	2		T19	9
all_pins[18]	6128245	1			T22	12		T23	2		T19	9
all_pins[19]	6128245	1			T22	12		T23	2		T19	9
all_pins[20]	6128245	1			T22	12		T23	2		T19	9
all_pins[21]	6128245	1			T22	12		T23	2		T19	9
all_pins[22]	6128245	1			T22	12		T23	2		T19	9
all_pins[23]	6128245	1			T22	12		T23	2		T19	9
all_pins[24]	6128245	1			T22	12		T23	2		T19	9
all_pins[25]	6128245	1			T22	12		T23	2		T19	9
all_pins[26]	6128245	1			T22	12		T23	2		T19	9
all_pins[27]	6128245	1			T22	12		T23	2		T19	9
all_pins[28]	6128245	1			T22	12		T23	2		T19	9
all_pins[29]	6128245	1			T22	12		T23	2		T19	9
all_pins[30]	6128245	1			T22	12		T23	2		T19	9
all_pins[31]	6128245	1			T22	12		T23	2		T19	9

---

Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	121549326	1			T22	271		T23	55		T19	245
values[0x1]	74554514	1			T22	113		T23	9		T19	43
transitions[0x0=>0x1]	44598112	1			T22	75		T23	9		T19	33
transitions[0x1=>0x0]	44597961	1			T22	75		T23	9		T19	33

---

Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	128	0	128	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	3790104	1			T22	3		T23	2		T19	9
all_pins[0]	values[0x1]	2338141	1			T22	9		T21	1		T1	6
all_pins[0]	transitions[0x0=>0x1]	1447093	1			T22	9		T21	1		T1	1
all_pins[0]	transitions[0x1=>0x0]	1435497	1			T1	1		T12	3		T13	1
all_pins[1]	values[0x0]	3801996	1			T22	7		T23	2		T19	9
all_pins[1]	values[0x1]	2326249	1			T22	5		T21	10		T1	2
all_pins[1]	transitions[0x0=>0x1]	1386206	1			T21	10		T11	3		T12	2
all_pins[1]	transitions[0x1=>0x0]	1398098	1			T22	4		T21	1		T1	4
all_pins[2]	values[0x0]	3805657	1			T22	9		T23	2		T19	7
all_pins[2]	values[0x1]	2322588	1			T22	3		T19	2		T21	14
all_pins[2]	transitions[0x0=>0x1]	1387078	1			T19	2		T21	8		T1	5
all_pins[2]	transitions[0x1=>0x0]	1390739	1			T22	2		T21	4		T11	1
all_pins[3]	values[0x0]	3795660	1			T22	7		T23	1		T19	7
all_pins[3]	values[0x1]	2332585	1			T22	5		T23	1		T19	2
all_pins[3]	transitions[0x0=>0x1]	1395898	1			T22	2		T23	1		T21	6
all_pins[3]	transitions[0x1=>0x0]	1385901	1			T21	8		T1	3		T11	1
all_pins[4]	values[0x0]	3798273	1			T22	12		T23	2		T19	9
all_pins[4]	values[0x1]	2329972	1			T21	4		T11	2		T12	6
all_pins[4]	transitions[0x0=>0x1]	1392022	1			T21	1		T11	1		T12	1
all_pins[4]	transitions[0x1=>0x0]	1394635	1			T22	5		T23	1		T19	2
all_pins[5]	values[0x0]	3801812	1			T22	6		T23	2		T19	9
all_pins[5]	values[0x1]	2326433	1			T22	6		T21	8		T1	8
all_pins[5]	transitions[0x0=>0x1]	1389004	1			T22	6		T21	5		T1	8
all_pins[5]	transitions[0x1=>0x0]	1392543	1			T21	1		T12	1		T14	11
all_pins[6]	values[0x0]	3792413	1			T22	10		T23	1		T19	7
all_pins[6]	values[0x1]	2335832	1			T22	2		T23	1		T19	2
all_pins[6]	transitions[0x0=>0x1]	1395504	1			T22	2		T23	1		T19	2
all_pins[6]	transitions[0x1=>0x0]	1386105	1			T22	6		T21	8		T1	8
all_pins[7]	values[0x0]	3798762	1			T22	9		T23	2		T19	7
all_pins[7]	values[0x1]	2329483	1			T22	3		T19	2		T21	11
all_pins[7]	transitions[0x0=>0x1]	1388833	1			T22	3		T19	2		T21	11
all_pins[7]	transitions[0x1=>0x0]	1395182	1			T22	2		T23	1		T19	2
all_pins[8]	values[0x0]	3799494	1			T22	10		T23	2		T19	6
all_pins[8]	values[0x1]	2328751	1			T22	2		T19	3		T21	6
all_pins[8]	transitions[0x0=>0x1]	1392218	1			T22	2		T19	2		T21	2
all_pins[8]	transitions[0x1=>0x0]	1392950	1			T22	3		T19	1		T21	7
all_pins[9]	values[0x0]	3803106	1			T22	7		T23	2		T19	7
all_pins[9]	values[0x1]	2325139	1			T22	5		T19	2		T21	4
all_pins[9]	transitions[0x0=>0x1]	1388714	1			T22	3		T19	2		T21	3
all_pins[9]	transitions[0x1=>0x0]	1392326	1			T19	3		T21	5		T1	2
all_pins[10]	values[0x0]	3800409	1			T22	2		T23	2		T19	8
all_pins[10]	values[0x1]	2327836	1			T22	10		T19	1		T21	8
all_pins[10]	transitions[0x0=>0x1]	1394666	1			T22	5		T19	1		T21	7
all_pins[10]	transitions[0x1=>0x0]	1391969	1			T19	2		T21	3		T1	2
all_pins[11]	values[0x0]	3793156	1			T22	9		T23	2		T19	9
all_pins[11]	values[0x1]	2335089	1			T22	3		T21	10		T1	4
all_pins[11]	transitions[0x0=>0x1]	1395258	1			T21	6		T1	4		T11	1
all_pins[11]	transitions[0x1=>0x0]	1388005	1			T22	7		T19	1		T21	4
all_pins[12]	values[0x0]	3796285	1			T22	9		T23	2		T19	9
all_pins[12]	values[0x1]	2331960	1			T22	3		T21	7		T12	4
all_pins[12]	transitions[0x0=>0x1]	1392327	1			T22	2		T21	3		T12	1
all_pins[12]	transitions[0x1=>0x0]	1395456	1			T22	2		T21	6		T1	4
all_pins[13]	values[0x0]	3795378	1			T22	7		T23	1		T19	8
all_pins[13]	values[0x1]	2332867	1			T22	5		T23	1		T19	1
all_pins[13]	transitions[0x0=>0x1]	1391577	1			T22	2		T23	1		T19	1
all_pins[13]	transitions[0x1=>0x0]	1390670	1			T21	4		T12	2		T13	2
all_pins[14]	values[0x0]	3800182	1			T22	11		T23	2		T19	4
all_pins[14]	values[0x1]	2328063	1			T22	1		T19	5		T21	6
all_pins[14]	transitions[0x0=>0x1]	1391835	1			T19	4		T21	5		T1	1
all_pins[14]	transitions[0x1=>0x0]	1396639	1			T22	4		T23	1		T21	7
all_pins[15]	values[0x0]	3798871	1			T22	9		T23	2		T19	7
all_pins[15]	values[0x1]	2329374	1			T22	3		T19	2		T21	1
all_pins[15]	transitions[0x0=>0x1]	1394288	1			T22	2		T1	1		T12	2
all_pins[15]	transitions[0x1=>0x0]	1392977	1			T19	3		T21	5		T1	2
all_pins[16]	values[0x0]	3796373	1			T22	9		T23	2		T19	7
all_pins[16]	values[0x1]	2331872	1			T22	3		T19	2		T21	9
all_pins[16]	transitions[0x0=>0x1]	1393341	1			T22	3		T19	1		T21	9
all_pins[16]	transitions[0x1=>0x0]	1390843	1			T22	3		T19	1		T21	1
all_pins[17]	values[0x0]	3791887	1			T22	9		T23	1		T19	8
all_pins[17]	values[0x1]	2336358	1			T22	3		T23	1		T19	1
all_pins[17]	transitions[0x0=>0x1]	1395263	1			T22	3		T23	1		T19	1
all_pins[17]	transitions[0x1=>0x0]	1390777	1			T22	3		T19	2		T21	6
all_pins[18]	values[0x0]	3798423	1			T22	12		T23	2		T19	8
all_pins[18]	values[0x1]	2329822	1			T19	1		T21	4		T1	2
all_pins[18]	transitions[0x0=>0x1]	1390017	1			T19	1		T21	3		T11	2
all_pins[18]	transitions[0x1=>0x0]	1396553	1			T22	3		T23	1		T19	1
all_pins[19]	values[0x0]	3802530	1			T22	3		T23	2		T19	9
all_pins[19]	values[0x1]	2325715	1			T22	9		T21	1		T1	6
all_pins[19]	transitions[0x0=>0x1]	1390670	1			T22	9		T1	4		T12	3
all_pins[19]	transitions[0x1=>0x0]	1394777	1			T19	1		T21	3		T11	2
all_pins[20]	values[0x0]	3797193	1			T22	6		T23	1		T19	7
all_pins[20]	values[0x1]	2331052	1			T22	6		T23	1		T19	2
all_pins[20]	transitions[0x0=>0x1]	1396567	1			T23	1		T19	2		T21	6
all_pins[20]	transitions[0x1=>0x0]	1391230	1			T22	3		T1	6		T12	3
all_pins[21]	values[0x0]	3801504	1			T22	9		T23	2		T19	7
all_pins[21]	values[0x1]	2326741	1			T22	3		T19	2		T21	6
all_pins[21]	transitions[0x0=>0x1]	1389241	1			T22	3		T19	2		T21	4
all_pins[21]	transitions[0x1=>0x0]	1393552	1			T22	6		T23	1		T19	2
all_pins[22]	values[0x0]	3792773	1			T22	12		T23	1		T19	5
all_pins[22]	values[0x1]	2335472	1			T23	1		T19	4		T21	8
all_pins[22]	transitions[0x0=>0x1]	1396909	1			T23	1		T19	3		T21	6
all_pins[22]	transitions[0x1=>0x0]	1388178	1			T22	3		T19	1		T21	4
all_pins[23]	values[0x0]	3795491	1			T22	6		T23	2		T19	9
all_pins[23]	values[0x1]	2332754	1			T22	6		T21	11		T1	6
all_pins[23]	transitions[0x0=>0x1]	1391954	1			T22	6		T21	8		T1	4
all_pins[23]	transitions[0x1=>0x0]	1394672	1			T23	1		T19	4		T21	5
all_pins[24]	values[0x0]	3799664	1			T22	12		T23	2		T19	7
all_pins[24]	values[0x1]	2328581	1			T19	2		T21	3		T1	8
all_pins[24]	transitions[0x0=>0x1]	1389242	1			T19	2		T1	2		T12	7
all_pins[24]	transitions[0x1=>0x0]	1393415	1			T22	6		T21	8		T11	1
all_pins[25]	values[0x0]	3799005	1			T22	9		T23	1		T19	9
all_pins[25]	values[0x1]	2329240	1			T22	3		T23	1		T21	4
all_pins[25]	transitions[0x0=>0x1]	1391230	1			T22	3		T23	1		T21	4
all_pins[25]	transitions[0x1=>0x0]	1390571	1			T19	2		T21	3		T12	7
all_pins[26]	values[0x0]	3802272	1			T22	8		T23	2		T19	8
all_pins[26]	values[0x1]	2325973	1			T22	4		T19	1		T21	2
all_pins[26]	transitions[0x0=>0x1]	1389587	1			T22	2		T19	1		T21	2
all_pins[26]	transitions[0x1=>0x0]	1392854	1			T22	1		T23	1		T21	4
all_pins[27]	values[0x0]	3808178	1			T22	8		T23	1		T19	7
all_pins[27]	values[0x1]	2320067	1			T22	4		T23	1		T19	2
all_pins[27]	transitions[0x0=>0x1]	1387754	1			T22	2		T23	1		T19	2
all_pins[27]	transitions[0x1=>0x0]	1393660	1			T22	2		T19	1		T21	2
all_pins[28]	values[0x0]	3799096	1			T22	11		T23	2		T19	5
all_pins[28]	values[0x1]	2329149	1			T22	1		T19	4		T21	7
all_pins[28]	transitions[0x0=>0x1]	1394130	1			T19	2		T21	5		T11	1
all_pins[28]	transitions[0x1=>0x0]	1385048	1			T22	3		T23	1		T21	2
all_pins[29]	values[0x0]	3797708	1			T22	12		T23	1		T19	9
all_pins[29]	values[0x1]	2330537	1			T23	1		T21	8		T1	1
all_pins[29]	transitions[0x0=>0x1]	1395243	1			T23	1		T21	4		T12	2
all_pins[29]	transitions[0x1=>0x0]	1393855	1			T22	1		T19	4		T21	3
all_pins[30]	values[0x0]	3794122	1			T22	6		T23	2		T19	9
all_pins[30]	values[0x1]	2334123	1			T22	6		T21	8		T1	2
all_pins[30]	transitions[0x0=>0x1]	1395885	1			T22	6		T21	7		T1	1
all_pins[30]	transitions[0x1=>0x0]	1392299	1			T23	1		T21	7		T12	1
all_pins[31]	values[0x0]	3801549	1			T22	12		T23	2		T19	9
all_pins[31]	values[0x1]	2326696	1			T1	6		T12	4		T13	1
all_pins[31]	transitions[0x0=>0x1]	1388558	1			T1	6		T12	2		T13	1
all_pins[31]	transitions[0x1=>0x0]	1395985	1			T22	6		T21	8		T1	2