Unified Coverage Report :: Group :: cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=31}

Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=31}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=31}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	192	0	192	100.00

Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=31}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	32	0	32	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2
cp_intr_test	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=31}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_test_cg_cc	192	0	192	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	32	0	32	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	20866284	1			T22	6		T23	2		T19	12
all_values[1]	20866284	1			T22	6		T23	2		T19	12
all_values[2]	20866284	1			T22	6		T23	2		T19	12
all_values[3]	20866284	1			T22	6		T23	2		T19	12
all_values[4]	20866284	1			T22	6		T23	2		T19	12
all_values[5]	20866284	1			T22	6		T23	2		T19	12
all_values[6]	20866284	1			T22	6		T23	2		T19	12
all_values[7]	20866284	1			T22	6		T23	2		T19	12
all_values[8]	20866284	1			T22	6		T23	2		T19	12
all_values[9]	20866284	1			T22	6		T23	2		T19	12
all_values[10]	20866284	1			T22	6		T23	2		T19	12
all_values[11]	20866284	1			T22	6		T23	2		T19	12
all_values[12]	20866284	1			T22	6		T23	2		T19	12
all_values[13]	20866284	1			T22	6		T23	2		T19	12
all_values[14]	20866284	1			T22	6		T23	2		T19	12
all_values[15]	20866284	1			T22	6		T23	2		T19	12
all_values[16]	20866284	1			T22	6		T23	2		T19	12
all_values[17]	20866284	1			T22	6		T23	2		T19	12
all_values[18]	20866284	1			T22	6		T23	2		T19	12
all_values[19]	20866284	1			T22	6		T23	2		T19	12
all_values[20]	20866284	1			T22	6		T23	2		T19	12
all_values[21]	20866284	1			T22	6		T23	2		T19	12
all_values[22]	20866284	1			T22	6		T23	2		T19	12
all_values[23]	20866284	1			T22	6		T23	2		T19	12
all_values[24]	20866284	1			T22	6		T23	2		T19	12
all_values[25]	20866284	1			T22	6		T23	2		T19	12
all_values[26]	20866284	1			T22	6		T23	2		T19	12
all_values[27]	20866284	1			T22	6		T23	2		T19	12
all_values[28]	20866284	1			T22	6		T23	2		T19	12
all_values[29]	20866284	1			T22	6		T23	2		T19	12
all_values[30]	20866284	1			T22	6		T23	2		T19	12
all_values[31]	20866284	1			T22	6		T23	2		T19	12

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

369327803

1

T22

95

T23

49

T19

231

auto[1]

298393285

1

T22

97

T23

15

T19

153

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

125192519

1

T22

89

T23

49

T19

259

auto[1]

542528569

1

T22

103

T23

15

T19

125

---

Summary for Variable cp_intr_test

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_test

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

660142755

1

T22

192

T23

64

T19

338

auto[1]

7578333

1

T19

46

T13

99

T14

144

---

Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	192	0	192	100.00
Automatically Generated Cross Bins	192	0	192	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for intr_test_cg_cc

Bins

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	auto[0]	3064513	1			T22	1		T23	2		T19	5
all_values[0]	auto[0]	auto[0]	auto[1]	8328588	1			T21	2		T1	1		T12	10
all_values[0]	auto[0]	auto[1]	auto[0]	855269	1			T19	6		T21	2		T1	2
all_values[0]	auto[0]	auto[1]	auto[1]	8381076	1			T22	5		T1	2		T13	3
all_values[0]	auto[1]	auto[0]	auto[1]	118791	1			T19	1		T13	5		T14	1
all_values[0]	auto[1]	auto[1]	auto[1]	118047	1			T14	4		T16	4		T99	2
all_values[1]	auto[0]	auto[0]	auto[0]	3061362	1			T22	1		T23	2		T19	3
all_values[1]	auto[0]	auto[0]	auto[1]	8359043	1			T21	1		T1	1		T12	6
all_values[1]	auto[0]	auto[1]	auto[0]	860347	1			T22	1		T19	9		T1	2
all_values[1]	auto[0]	auto[1]	auto[1]	8348597	1			T22	4		T21	4		T1	1
all_values[1]	auto[1]	auto[0]	auto[1]	118851	1			T13	2		T14	2		T74	1
all_values[1]	auto[1]	auto[1]	auto[1]	118084	1			T14	2		T16	2		T100	1
all_values[2]	auto[0]	auto[0]	auto[0]	3048138	1			T22	1		T23	1		T19	3
all_values[2]	auto[0]	auto[0]	auto[1]	8365139	1			T23	1		T19	4		T21	3
all_values[2]	auto[0]	auto[1]	auto[0]	858064	1			T22	2		T19	2		T13	7
all_values[2]	auto[0]	auto[1]	auto[1]	8358497	1			T22	3		T19	1		T21	3
all_values[2]	auto[1]	auto[0]	auto[1]	118072	1			T19	1		T14	2		T99	3
all_values[2]	auto[1]	auto[1]	auto[1]	118374	1			T19	1		T13	2		T14	2
all_values[3]	auto[0]	auto[0]	auto[0]	3048645	1			T22	1		T23	1		T19	3
all_values[3]	auto[0]	auto[0]	auto[1]	8413212	1			T19	4		T21	1		T13	4
all_values[3]	auto[0]	auto[1]	auto[0]	852864	1			T22	3		T19	2		T21	2
all_values[3]	auto[0]	auto[1]	auto[1]	8314804	1			T22	2		T23	1		T19	1
all_values[3]	auto[1]	auto[0]	auto[1]	118162	1			T19	1		T13	4		T14	1
all_values[3]	auto[1]	auto[1]	auto[1]	118597	1			T19	1		T14	5		T16	2
all_values[4]	auto[0]	auto[0]	auto[0]	3058908	1			T22	1		T23	1		T19	7
all_values[4]	auto[0]	auto[0]	auto[1]	8381091	1			T22	5		T21	1		T11	1
all_values[4]	auto[0]	auto[1]	auto[0]	862619	1			T23	1		T19	5		T13	3
all_values[4]	auto[0]	auto[1]	auto[1]	8326656	1			T21	1		T11	2		T12	11
all_values[4]	auto[1]	auto[0]	auto[1]	118697	1			T13	2		T14	5		T16	1
all_values[4]	auto[1]	auto[1]	auto[1]	118313	1			T13	1		T14	3		T99	2
all_values[5]	auto[0]	auto[0]	auto[0]	3053285	1			T22	1		T23	2		T19	7
all_values[5]	auto[0]	auto[0]	auto[1]	8385287	1			T22	1		T21	1		T12	2
all_values[5]	auto[0]	auto[1]	auto[0]	852282	1			T19	5		T21	2		T12	8
all_values[5]	auto[0]	auto[1]	auto[1]	8338838	1			T22	4		T21	2		T1	5
all_values[5]	auto[1]	auto[0]	auto[1]	118358	1			T13	1		T14	2		T16	2
all_values[5]	auto[1]	auto[1]	auto[1]	118234	1			T13	4		T14	1		T16	1
all_values[6]	auto[0]	auto[0]	auto[0]	3054240	1			T22	3		T23	1		T19	7
all_values[6]	auto[0]	auto[0]	auto[1]	8321114	1			T22	3		T1	5		T11	3
all_values[6]	auto[0]	auto[1]	auto[0]	864289	1			T19	2		T21	2		T13	6
all_values[6]	auto[0]	auto[1]	auto[1]	8389494	1			T23	1		T19	2		T13	3
all_values[6]	auto[1]	auto[0]	auto[1]	118695	1			T13	1		T14	2		T16	1
all_values[6]	auto[1]	auto[1]	auto[1]	118452	1			T19	1		T13	2		T16	3
all_values[7]	auto[0]	auto[0]	auto[0]	3065818	1			T22	1		T23	1		T19	4
all_values[7]	auto[0]	auto[0]	auto[1]	8395827	1			T22	4		T19	4		T21	2
all_values[7]	auto[0]	auto[1]	auto[0]	845855	1			T23	1		T19	2		T11	1
all_values[7]	auto[0]	auto[1]	auto[1]	8322070	1			T22	1		T19	1		T21	2
all_values[7]	auto[1]	auto[0]	auto[1]	119017	1			T13	1		T14	2		T16	1
all_values[7]	auto[1]	auto[1]	auto[1]	117697	1			T19	1		T14	2		T16	3
all_values[8]	auto[0]	auto[0]	auto[0]	3065506	1			T22	1		T23	1		T19	6
all_values[8]	auto[0]	auto[0]	auto[1]	8358902	1			T22	5		T23	1		T19	1
all_values[8]	auto[0]	auto[1]	auto[0]	861710	1			T19	1		T1	1		T12	3
all_values[8]	auto[0]	auto[1]	auto[1]	8343095	1			T19	2		T21	1		T1	1
all_values[8]	auto[1]	auto[0]	auto[1]	118842	1			T19	1		T13	1		T14	3
all_values[8]	auto[1]	auto[1]	auto[1]	118229	1			T19	1		T13	2		T14	1
all_values[9]	auto[0]	auto[0]	auto[0]	3052452	1			T22	1		T23	2		T19	7
all_values[9]	auto[0]	auto[0]	auto[1]	8396340	1			T21	2		T1	4		T13	6
all_values[9]	auto[0]	auto[1]	auto[0]	856452	1			T22	5		T19	2		T21	1
all_values[9]	auto[0]	auto[1]	auto[1]	8324427	1			T19	2		T21	1		T1	1
all_values[9]	auto[1]	auto[0]	auto[1]	118729	1			T13	4		T16	1		T99	1
all_values[9]	auto[1]	auto[1]	auto[1]	117884	1			T19	1		T13	1		T14	5
all_values[10]	auto[0]	auto[0]	auto[0]	3056394	1			T22	1		T23	2		T19	9
all_values[10]	auto[0]	auto[0]	auto[1]	8355941	1			T21	1		T13	8		T14	2
all_values[10]	auto[0]	auto[1]	auto[0]	854122	1			T19	2		T12	11		T14	6
all_values[10]	auto[0]	auto[1]	auto[1]	8363248	1			T22	5		T21	2		T11	2
all_values[10]	auto[1]	auto[0]	auto[1]	118878	1			T13	4		T14	5		T16	2
all_values[10]	auto[1]	auto[1]	auto[1]	117701	1			T19	1		T14	2		T16	2
all_values[11]	auto[0]	auto[0]	auto[0]	3052526	1			T22	2		T23	1		T19	2
all_values[11]	auto[0]	auto[0]	auto[1]	8336313	1			T23	1		T19	4		T21	3
all_values[11]	auto[0]	auto[1]	auto[0]	861472	1			T22	3		T19	5		T12	18
all_values[11]	auto[0]	auto[1]	auto[1]	8379519	1			T22	1		T21	2		T1	3
all_values[11]	auto[1]	auto[0]	auto[1]	118362	1			T19	1		T13	1		T14	2
all_values[11]	auto[1]	auto[1]	auto[1]	118092	1			T13	1		T14	1		T16	1
all_values[12]	auto[0]	auto[0]	auto[0]	3052874	1			T22	1		T23	1		T19	6
all_values[12]	auto[0]	auto[0]	auto[1]	8332183	1			T19	2		T1	5		T11	3
all_values[12]	auto[0]	auto[1]	auto[0]	855310	1			T22	3		T23	1		T19	3
all_values[12]	auto[0]	auto[1]	auto[1]	8389037	1			T22	2		T21	2		T13	2
all_values[12]	auto[1]	auto[0]	auto[1]	118462	1			T19	1		T13	3		T14	1
all_values[12]	auto[1]	auto[1]	auto[1]	118418	1			T13	1		T14	3		T74	1
all_values[13]	auto[0]	auto[0]	auto[0]	3053580	1			T22	2		T23	1		T19	4
all_values[13]	auto[0]	auto[0]	auto[1]	8372009	1			T19	4		T21	4		T12	13
all_values[13]	auto[0]	auto[1]	auto[0]	859727	1			T22	2		T1	2		T12	7
all_values[13]	auto[0]	auto[1]	auto[1]	8344258	1			T22	2		T23	1		T19	1
all_values[13]	auto[1]	auto[0]	auto[1]	118511	1			T19	3		T13	2		T14	3
all_values[13]	auto[1]	auto[1]	auto[1]	118199	1			T13	3		T14	1		T16	3
all_values[14]	auto[0]	auto[0]	auto[0]	3072511	1			T22	1		T23	1		T19	1
all_values[14]	auto[0]	auto[0]	auto[1]	8392575	1			T23	1		T19	1		T11	2
all_values[14]	auto[0]	auto[1]	auto[0]	849363	1			T22	3		T19	3		T21	2
all_values[14]	auto[0]	auto[1]	auto[1]	8314653	1			T22	2		T19	4		T21	2
all_values[14]	auto[1]	auto[0]	auto[1]	118704	1			T19	1		T13	1		T14	4
all_values[14]	auto[1]	auto[1]	auto[1]	118478	1			T19	2		T13	1		T74	1
all_values[15]	auto[0]	auto[0]	auto[0]	3055922	1			T22	2		T23	1		T19	3
all_values[15]	auto[0]	auto[0]	auto[1]	8385507	1			T23	1		T21	1		T1	1
all_values[15]	auto[0]	auto[1]	auto[0]	855044	1			T22	2		T19	6		T1	1
all_values[15]	auto[0]	auto[1]	auto[1]	8333091	1			T22	2		T21	1		T1	2
all_values[15]	auto[1]	auto[0]	auto[1]	118288	1			T19	1		T13	1		T14	3
all_values[15]	auto[1]	auto[1]	auto[1]	118432	1			T19	2		T13	2		T14	1
all_values[16]	auto[0]	auto[0]	auto[0]	3058937	1			T22	1		T23	2		T19	7
all_values[16]	auto[0]	auto[0]	auto[1]	8332554	1			T22	4		T19	1		T21	5
all_values[16]	auto[0]	auto[1]	auto[0]	850487	1			T19	1		T1	5		T13	9
all_values[16]	auto[0]	auto[1]	auto[1]	8387749	1			T22	1		T19	1		T21	1
all_values[16]	auto[1]	auto[0]	auto[1]	117976	1			T19	1		T13	1		T14	3
all_values[16]	auto[1]	auto[1]	auto[1]	118581	1			T19	1		T13	2		T14	2
all_values[17]	auto[0]	auto[0]	auto[0]	3054994	1			T22	2		T23	1		T19	3
all_values[17]	auto[0]	auto[0]	auto[1]	8289165	1			T21	2		T1	2		T11	3
all_values[17]	auto[0]	auto[1]	auto[0]	866525	1			T22	4		T19	8		T21	1
all_values[17]	auto[0]	auto[1]	auto[1]	8418787	1			T23	1		T21	1		T1	3
all_values[17]	auto[1]	auto[0]	auto[1]	118172	1			T13	4		T74	1		T99	1
all_values[17]	auto[1]	auto[1]	auto[1]	118641	1			T19	1		T14	4		T16	4
all_values[18]	auto[0]	auto[0]	auto[0]	3050421	1			T22	2		T23	1		T19	2
all_values[18]	auto[0]	auto[0]	auto[1]	8362293	1			T19	8		T1	1		T11	1
all_values[18]	auto[0]	auto[1]	auto[0]	863041	1			T22	4		T23	1		T21	3
all_values[18]	auto[0]	auto[1]	auto[1]	8353741	1			T19	1		T21	1		T1	2
all_values[18]	auto[1]	auto[0]	auto[1]	118995	1			T19	1		T13	1		T14	5
all_values[18]	auto[1]	auto[1]	auto[1]	117793	1			T13	3		T14	2		T16	3
all_values[19]	auto[0]	auto[0]	auto[0]	3054426	1			T22	1		T23	1		T19	8
all_values[19]	auto[0]	auto[0]	auto[1]	8387249	1			T23	1		T19	2		T21	2
all_values[19]	auto[0]	auto[1]	auto[0]	854267	1			T19	1		T21	1		T11	3
all_values[19]	auto[0]	auto[1]	auto[1]	8333678	1			T22	5		T1	4		T13	1
all_values[19]	auto[1]	auto[0]	auto[1]	118707	1			T19	1		T13	2		T14	2
all_values[19]	auto[1]	auto[1]	auto[1]	117957	1			T13	2		T14	3		T74	1
all_values[20]	auto[0]	auto[0]	auto[0]	3054351	1			T22	2		T23	1		T19	3
all_values[20]	auto[0]	auto[0]	auto[1]	8381171	1			T21	1		T1	5		T12	11
all_values[20]	auto[0]	auto[1]	auto[0]	851319	1			T22	4		T19	6		T11	3
all_values[20]	auto[0]	auto[1]	auto[1]	8342235	1			T23	1		T19	2		T21	1
all_values[20]	auto[1]	auto[0]	auto[1]	118384	1			T13	1		T14	2		T16	2
all_values[20]	auto[1]	auto[1]	auto[1]	118824	1			T19	1		T13	1		T14	5
all_values[21]	auto[0]	auto[0]	auto[0]	3061419	1			T22	1		T23	2		T19	5
all_values[21]	auto[0]	auto[0]	auto[1]	8400097	1			T22	4		T19	2		T21	1
all_values[21]	auto[0]	auto[1]	auto[0]	855341	1			T19	1		T21	1		T11	1
all_values[21]	auto[0]	auto[1]	auto[1]	8312764	1			T22	1		T19	2		T21	2
all_values[21]	auto[1]	auto[0]	auto[1]	118438	1			T19	2		T13	1		T14	2
all_values[21]	auto[1]	auto[1]	auto[1]	118225	1			T13	1		T14	1		T16	1
all_values[22]	auto[0]	auto[0]	auto[0]	3056378	1			T22	1		T23	1		T19	4
all_values[22]	auto[0]	auto[0]	auto[1]	8367078	1			T21	2		T1	3		T11	1
all_values[22]	auto[0]	auto[1]	auto[0]	850440	1			T22	5		T23	1		T19	4
all_values[22]	auto[0]	auto[1]	auto[1]	8355274	1			T19	2		T21	3		T1	2
all_values[22]	auto[1]	auto[0]	auto[1]	119219	1			T14	2		T16	2		T99	3
all_values[22]	auto[1]	auto[1]	auto[1]	117895	1			T19	2		T13	4		T14	3
all_values[23]	auto[0]	auto[0]	auto[0]	3051504	1			T22	1		T23	2		T19	5
all_values[23]	auto[0]	auto[0]	auto[1]	8377504	1			T22	1		T19	2		T21	4
all_values[23]	auto[0]	auto[1]	auto[0]	855123	1			T19	4		T12	11		T13	4
all_values[23]	auto[0]	auto[1]	auto[1]	8345273	1			T22	4		T21	2		T1	4
all_values[23]	auto[1]	auto[0]	auto[1]	118861	1			T19	1		T13	3		T14	5
all_values[23]	auto[1]	auto[1]	auto[1]	118019	1			T14	1		T16	4		T74	2
all_values[24]	auto[0]	auto[0]	auto[0]	3052355	1			T22	1		T23	1		T19	3
all_values[24]	auto[0]	auto[0]	auto[1]	8356594	1			T22	5		T23	1		T19	1
all_values[24]	auto[0]	auto[1]	auto[0]	854884	1			T19	4		T12	7		T14	10
all_values[24]	auto[0]	auto[1]	auto[1]	8365728	1			T19	2		T21	1		T1	5
all_values[24]	auto[1]	auto[0]	auto[1]	118915	1			T19	2		T13	1		T14	3
all_values[24]	auto[1]	auto[1]	auto[1]	117808	1			T14	1		T16	1		T99	3
all_values[25]	auto[0]	auto[0]	auto[0]	3049014	1			T22	1		T23	1		T19	6
all_values[25]	auto[0]	auto[0]	auto[1]	8361366	1			T22	4		T21	3		T12	11
all_values[25]	auto[0]	auto[1]	auto[0]	849279	1			T23	1		T19	5		T21	1
all_values[25]	auto[0]	auto[1]	auto[1]	8370117	1			T22	1		T21	1		T1	5
all_values[25]	auto[1]	auto[0]	auto[1]	118483	1			T19	1		T13	3		T14	4
all_values[25]	auto[1]	auto[1]	auto[1]	118025	1			T13	1		T14	1		T16	4
all_values[26]	auto[0]	auto[0]	auto[0]	3061601	1			T22	1		T23	1		T19	2
all_values[26]	auto[0]	auto[0]	auto[1]	8384605	1			T22	4		T19	2		T21	2
all_values[26]	auto[0]	auto[1]	auto[0]	852593	1			T23	1		T19	5		T21	4
all_values[26]	auto[0]	auto[1]	auto[1]	8330201	1			T22	1		T19	1		T13	4
all_values[26]	auto[1]	auto[0]	auto[1]	118963	1			T19	2		T13	2		T14	3
all_values[26]	auto[1]	auto[1]	auto[1]	118321	1			T16	2		T74	1		T99	1
all_values[27]	auto[0]	auto[0]	auto[0]	3063725	1			T22	2		T23	1		T19	5
all_values[27]	auto[0]	auto[0]	auto[1]	8390101	1			T19	1		T21	2		T13	3
all_values[27]	auto[0]	auto[1]	auto[0]	848121	1			T22	1		T19	3		T21	1
all_values[27]	auto[0]	auto[1]	auto[1]	8326965	1			T22	3		T23	1		T19	1
all_values[27]	auto[1]	auto[0]	auto[1]	119462	1			T19	1		T13	2		T14	1
all_values[27]	auto[1]	auto[1]	auto[1]	117910	1			T19	1		T13	2		T14	1
all_values[28]	auto[0]	auto[0]	auto[0]	3050964	1			T22	1		T23	1		T19	1
all_values[28]	auto[0]	auto[0]	auto[1]	8373062	1			T22	4		T23	1		T19	4
all_values[28]	auto[0]	auto[1]	auto[0]	864373	1			T22	1		T19	1		T21	1
all_values[28]	auto[0]	auto[1]	auto[1]	8340910	1			T19	4		T21	2		T1	1
all_values[28]	auto[1]	auto[0]	auto[1]	118464	1			T19	1		T13	1		T14	2
all_values[28]	auto[1]	auto[1]	auto[1]	118511	1			T19	1		T13	2		T16	3
all_values[29]	auto[0]	auto[0]	auto[0]	3056954	1			T22	5		T23	1		T19	10
all_values[29]	auto[0]	auto[0]	auto[1]	8375466	1			T21	2		T11	2		T12	11
all_values[29]	auto[0]	auto[1]	auto[0]	857094	1			T22	1		T19	1		T1	4
all_values[29]	auto[0]	auto[1]	auto[1]	8340258	1			T23	1		T21	2		T1	1
all_values[29]	auto[1]	auto[0]	auto[1]	118429	1			T19	1		T13	4		T14	3
all_values[29]	auto[1]	auto[1]	auto[1]	118083	1			T14	3		T99	3		T101	1
all_values[30]	auto[0]	auto[0]	auto[0]	3044236	1			T22	1		T23	1		T19	6
all_values[30]	auto[0]	auto[0]	auto[1]	8352667	1			T22	1		T21	2		T1	1
all_values[30]	auto[0]	auto[1]	auto[0]	862135	1			T23	1		T19	5		T21	1
all_values[30]	auto[0]	auto[1]	auto[1]	8370887	1			T22	4		T21	2		T1	1
all_values[30]	auto[1]	auto[0]	auto[1]	118028	1			T19	1		T13	1		T14	4
all_values[30]	auto[1]	auto[1]	auto[1]	118331	1			T16	3		T74	2		T99	2
all_values[31]	auto[0]	auto[0]	auto[0]	3053378	1			T22	1		T23	2		T19	7
all_values[31]	auto[0]	auto[0]	auto[1]	8370574	1			T22	5		T19	2		T21	4
all_values[31]	auto[0]	auto[1]	auto[0]	861377	1			T19	1		T21	1		T11	1
all_values[31]	auto[0]	auto[1]	auto[1]	8343692	1			T1	4		T12	11		T14	5
all_values[31]	auto[1]	auto[0]	auto[1]	118940	1			T19	2		T14	4		T16	1
all_values[31]	auto[1]	auto[1]	auto[1]	118323	1			T13	1		T14	1		T16	1

User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins

NAME	COUNT	STATUS
test_1_state_0	0	Illegal