Unified Coverage Report :: Group :: gpio_env_pkg::gpio_env_cov::data_out_data_oe_data_in_cross_cg

Group : gpio_env_pkg::gpio_env_cov::data_out_data_oe_data_in_cross_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_gpio_env_0.1/gpio_env_cov.sv

---

Summary for Group gpio_env_pkg::gpio_env_cov::data_out_data_oe_data_in_cross_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	192	0	192	100.00

Variables for Group gpio_env_pkg::gpio_env_cov::data_out_data_oe_data_in_cross_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_pin	32	0	32	100.00	100	1	1	0
data_in	2	0	2	100.00	100	1	1	2
data_oe	2	0	2	100.00	100	1	1	2
data_out	2	0	2	100.00	100	1	1	2

Crosses for Group gpio_env_pkg::gpio_env_cov::data_out_data_oe_data_in_cross_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_cross_all	192	0	192	100.00	100	1	1	0

Summary for Variable cp_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	32	0	32	100.00

User Defined Bins for cp_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
bins_for_gpio_bits[0]	20608402	1			T22	6		T23	2		T19	1
bins_for_gpio_bits[1]	20608402	1			T22	6		T23	2		T19	1
bins_for_gpio_bits[2]	20608402	1			T22	6		T23	2		T19	1
bins_for_gpio_bits[3]	20608402	1			T22	6		T23	2		T19	1
bins_for_gpio_bits[4]	20608402	1			T22	6		T23	2		T19	1
bins_for_gpio_bits[5]	20608402	1			T22	6		T23	2		T19	1
bins_for_gpio_bits[6]	20608402	1			T22	6		T23	2		T19	1
bins_for_gpio_bits[7]	20608402	1			T22	6		T23	2		T19	1
bins_for_gpio_bits[8]	20608402	1			T22	6		T23	2		T19	1
bins_for_gpio_bits[9]	20608402	1			T22	6		T23	2		T19	1
bins_for_gpio_bits[10]	20608402	1			T22	6		T23	2		T19	1
bins_for_gpio_bits[11]	20608402	1			T22	6		T23	2		T19	1
bins_for_gpio_bits[12]	20608402	1			T22	6		T23	2		T19	1
bins_for_gpio_bits[13]	20608402	1			T22	6		T23	2		T19	1
bins_for_gpio_bits[14]	20608402	1			T22	6		T23	2		T19	1
bins_for_gpio_bits[15]	20608402	1			T22	6		T23	2		T19	1
bins_for_gpio_bits[16]	20608402	1			T22	6		T23	2		T19	1
bins_for_gpio_bits[17]	20608402	1			T22	6		T23	2		T19	1
bins_for_gpio_bits[18]	20608402	1			T22	6		T23	2		T19	1
bins_for_gpio_bits[19]	20608402	1			T22	6		T23	2		T19	1
bins_for_gpio_bits[20]	20608402	1			T22	6		T23	2		T19	1
bins_for_gpio_bits[21]	20608402	1			T22	6		T23	2		T19	1
bins_for_gpio_bits[22]	20608402	1			T22	6		T23	2		T19	1
bins_for_gpio_bits[23]	20608402	1			T22	6		T23	2		T19	1
bins_for_gpio_bits[24]	20608402	1			T22	6		T23	2		T19	1
bins_for_gpio_bits[25]	20608402	1			T22	6		T23	2		T19	1
bins_for_gpio_bits[26]	20608402	1			T22	6		T23	2		T19	1
bins_for_gpio_bits[27]	20608402	1			T22	6		T23	2		T19	1
bins_for_gpio_bits[28]	20608402	1			T22	6		T23	2		T19	1
bins_for_gpio_bits[29]	20608402	1			T22	6		T23	2		T19	1
bins_for_gpio_bits[30]	20608402	1			T22	6		T23	2		T19	1
bins_for_gpio_bits[31]	20608402	1			T22	6		T23	2		T19	1

---

Summary for Variable data_in

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for data_in

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

406465091

1

T22

192

T23

64

T19

32

auto[1]

253003773

1

T44

4342

T45

4027

T46

5049

---

Summary for Variable data_oe

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for data_oe

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

524958782

1

T22

192

T23

64

T19

32

auto[1]

134510082

1

T44

6300

T45

6708

T46

9485

---

Summary for Variable data_out

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for data_out

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

485064427

1

T22

192

T23

64

T19

32

auto[1]

174404437

1

T44

6322

T45

6778

T46

9496

---

Summary for Cross cp_cross_all

Samples crossed: cp_pin data_out data_oe data_in

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	192	0	192	100.00
Automatically Generated Cross Bins	192	0	192	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cp_cross_all

Bins

cp_pin	data_out	data_oe	data_in	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
bins_for_gpio_bits[0]	auto[0]	auto[0]	auto[0]	7720925	1			T22	6		T23	2		T19	1
bins_for_gpio_bits[0]	auto[0]	auto[0]	auto[1]	5318439	1			T44	43		T45	19		T46	7
bins_for_gpio_bits[0]	auto[0]	auto[1]	auto[0]	2114004	1			T44	116		T45	82		T46	162
bins_for_gpio_bits[0]	auto[1]	auto[0]	auto[0]	2854815	1			T44	84		T45	157		T46	142
bins_for_gpio_bits[0]	auto[1]	auto[0]	auto[1]	500755	1			T59	169		T102	86		T103	175
bins_for_gpio_bits[0]	auto[1]	auto[1]	auto[1]	2099464	1			T44	104		T45	82		T46	166
bins_for_gpio_bits[1]	auto[0]	auto[0]	auto[0]	7728873	1			T22	6		T23	2		T19	1
bins_for_gpio_bits[1]	auto[0]	auto[0]	auto[1]	5311141	1			T44	42		T45	23		T46	8
bins_for_gpio_bits[1]	auto[0]	auto[1]	auto[0]	2112632	1			T44	83		T45	78		T46	168
bins_for_gpio_bits[1]	auto[1]	auto[0]	auto[0]	2853303	1			T44	138		T45	112		T46	159
bins_for_gpio_bits[1]	auto[1]	auto[0]	auto[1]	504645	1			T59	235		T102	68		T103	135
bins_for_gpio_bits[1]	auto[1]	auto[1]	auto[1]	2097808	1			T44	78		T45	95		T46	120
bins_for_gpio_bits[2]	auto[0]	auto[0]	auto[0]	7745211	1			T22	6		T23	2		T19	1
bins_for_gpio_bits[2]	auto[0]	auto[0]	auto[1]	5303949	1			T44	39		T45	19		T46	8
bins_for_gpio_bits[2]	auto[0]	auto[1]	auto[0]	2109565	1			T44	120		T45	116		T46	122
bins_for_gpio_bits[2]	auto[1]	auto[0]	auto[0]	2850894	1			T44	83		T45	119		T46	152
bins_for_gpio_bits[2]	auto[1]	auto[0]	auto[1]	501061	1			T59	173		T102	86		T103	112
bins_for_gpio_bits[2]	auto[1]	auto[1]	auto[1]	2097722	1			T44	80		T45	84		T46	143
bins_for_gpio_bits[3]	auto[0]	auto[0]	auto[0]	7736606	1			T22	6		T23	2		T19	1
bins_for_gpio_bits[3]	auto[0]	auto[0]	auto[1]	5303591	1			T44	39		T45	21		T46	10
bins_for_gpio_bits[3]	auto[0]	auto[1]	auto[0]	2116354	1			T44	86		T45	80		T46	153
bins_for_gpio_bits[3]	auto[1]	auto[0]	auto[0]	2850471	1			T44	96		T45	106		T46	124
bins_for_gpio_bits[3]	auto[1]	auto[0]	auto[1]	502527	1			T59	168		T102	90		T103	116
bins_for_gpio_bits[3]	auto[1]	auto[1]	auto[1]	2098853	1			T44	79		T45	105		T46	164
bins_for_gpio_bits[4]	auto[0]	auto[0]	auto[0]	7724372	1			T22	6		T23	2		T19	1
bins_for_gpio_bits[4]	auto[0]	auto[0]	auto[1]	5315179	1			T44	42		T45	26		T46	12
bins_for_gpio_bits[4]	auto[0]	auto[1]	auto[0]	2115874	1			T44	100		T45	84		T46	150
bins_for_gpio_bits[4]	auto[1]	auto[0]	auto[0]	2852973	1			T44	95		T45	126		T46	124
bins_for_gpio_bits[4]	auto[1]	auto[0]	auto[1]	500990	1			T59	228		T102	96		T103	125
bins_for_gpio_bits[4]	auto[1]	auto[1]	auto[1]	2099014	1			T44	76		T45	109		T46	183
bins_for_gpio_bits[5]	auto[0]	auto[0]	auto[0]	7738198	1			T22	6		T23	2		T19	1
bins_for_gpio_bits[5]	auto[0]	auto[0]	auto[1]	5303026	1			T44	40		T45	24		T46	8
bins_for_gpio_bits[5]	auto[0]	auto[1]	auto[0]	2114115	1			T44	80		T45	67		T46	174
bins_for_gpio_bits[5]	auto[1]	auto[0]	auto[0]	2847594	1			T44	96		T45	142		T46	134
bins_for_gpio_bits[5]	auto[1]	auto[0]	auto[1]	502129	1			T59	204		T102	94		T103	122
bins_for_gpio_bits[5]	auto[1]	auto[1]	auto[1]	2103340	1			T44	92		T45	142		T46	138
bins_for_gpio_bits[6]	auto[0]	auto[0]	auto[0]	7746062	1			T22	6		T23	2		T19	1
bins_for_gpio_bits[6]	auto[0]	auto[0]	auto[1]	5301781	1			T44	38		T45	24		T46	12
bins_for_gpio_bits[6]	auto[0]	auto[1]	auto[0]	2116630	1			T44	106		T45	119		T46	143
bins_for_gpio_bits[6]	auto[1]	auto[0]	auto[0]	2844773	1			T44	86		T45	90		T46	158
bins_for_gpio_bits[6]	auto[1]	auto[0]	auto[1]	500908	1			T59	206		T102	118		T103	115
bins_for_gpio_bits[6]	auto[1]	auto[1]	auto[1]	2098248	1			T44	122		T45	110		T46	162
bins_for_gpio_bits[7]	auto[0]	auto[0]	auto[0]	7741359	1			T22	6		T23	2		T19	1
bins_for_gpio_bits[7]	auto[0]	auto[0]	auto[1]	5301185	1			T44	35		T45	21		T46	16
bins_for_gpio_bits[7]	auto[0]	auto[1]	auto[0]	2114336	1			T44	92		T45	90		T46	115
bins_for_gpio_bits[7]	auto[1]	auto[0]	auto[0]	2852207	1			T44	102		T45	118		T46	162
bins_for_gpio_bits[7]	auto[1]	auto[0]	auto[1]	501738	1			T59	226		T102	94		T103	118
bins_for_gpio_bits[7]	auto[1]	auto[1]	auto[1]	2097577	1			T44	129		T45	122		T46	150
bins_for_gpio_bits[8]	auto[0]	auto[0]	auto[0]	7743482	1			T22	6		T23	2		T19	1
bins_for_gpio_bits[8]	auto[0]	auto[0]	auto[1]	5298415	1			T44	32		T45	23		T46	8
bins_for_gpio_bits[8]	auto[0]	auto[1]	auto[0]	2118655	1			T44	94		T45	110		T46	130
bins_for_gpio_bits[8]	auto[1]	auto[0]	auto[0]	2841734	1			T44	89		T45	90		T46	146
bins_for_gpio_bits[8]	auto[1]	auto[0]	auto[1]	503275	1			T59	192		T102	93		T103	96
bins_for_gpio_bits[8]	auto[1]	auto[1]	auto[1]	2102841	1			T44	134		T45	110		T46	182
bins_for_gpio_bits[9]	auto[0]	auto[0]	auto[0]	7728665	1			T22	6		T23	2		T19	1
bins_for_gpio_bits[9]	auto[0]	auto[0]	auto[1]	5318607	1			T44	38		T45	19		T46	9
bins_for_gpio_bits[9]	auto[0]	auto[1]	auto[0]	2115188	1			T44	107		T45	115		T46	160
bins_for_gpio_bits[9]	auto[1]	auto[0]	auto[0]	2844356	1			T44	102		T45	102		T46	158
bins_for_gpio_bits[9]	auto[1]	auto[0]	auto[1]	502536	1			T59	176		T102	79		T103	108
bins_for_gpio_bits[9]	auto[1]	auto[1]	auto[1]	2099050	1			T44	90		T45	106		T46	141
bins_for_gpio_bits[10]	auto[0]	auto[0]	auto[0]	7733227	1			T22	6		T23	2		T19	1
bins_for_gpio_bits[10]	auto[0]	auto[0]	auto[1]	5314363	1			T44	41		T45	22		T46	7
bins_for_gpio_bits[10]	auto[0]	auto[1]	auto[0]	2111949	1			T44	112		T45	115		T46	136
bins_for_gpio_bits[10]	auto[1]	auto[0]	auto[0]	2850869	1			T44	98		T45	110		T46	160
bins_for_gpio_bits[10]	auto[1]	auto[0]	auto[1]	503650	1			T59	226		T102	98		T103	86
bins_for_gpio_bits[10]	auto[1]	auto[1]	auto[1]	2094344	1			T44	113		T45	106		T46	152
bins_for_gpio_bits[11]	auto[0]	auto[0]	auto[0]	7732247	1			T22	6		T23	2		T19	1
bins_for_gpio_bits[11]	auto[0]	auto[0]	auto[1]	5308660	1			T44	34		T45	25		T46	9
bins_for_gpio_bits[11]	auto[0]	auto[1]	auto[0]	2118255	1			T44	72		T45	134		T46	164
bins_for_gpio_bits[11]	auto[1]	auto[0]	auto[0]	2851176	1			T44	148		T45	90		T46	135
bins_for_gpio_bits[11]	auto[1]	auto[0]	auto[1]	503186	1			T59	158		T102	70		T103	123
bins_for_gpio_bits[11]	auto[1]	auto[1]	auto[1]	2094878	1			T44	100		T45	86		T46	136
bins_for_gpio_bits[12]	auto[0]	auto[0]	auto[0]	7734097	1			T22	6		T23	2		T19	1
bins_for_gpio_bits[12]	auto[0]	auto[0]	auto[1]	5315127	1			T44	38		T45	19		T46	10
bins_for_gpio_bits[12]	auto[0]	auto[1]	auto[0]	2120345	1			T44	110		T45	104		T46	110
bins_for_gpio_bits[12]	auto[1]	auto[0]	auto[0]	2847230	1			T44	76		T45	99		T46	205
bins_for_gpio_bits[12]	auto[1]	auto[0]	auto[1]	501229	1			T59	174		T102	95		T103	102
bins_for_gpio_bits[12]	auto[1]	auto[1]	auto[1]	2090374	1			T44	83		T45	128		T46	146
bins_for_gpio_bits[13]	auto[0]	auto[0]	auto[0]	7726593	1			T22	6		T23	2		T19	1
bins_for_gpio_bits[13]	auto[0]	auto[0]	auto[1]	5320429	1			T44	39		T45	26		T46	13
bins_for_gpio_bits[13]	auto[0]	auto[1]	auto[0]	2109025	1			T44	74		T45	117		T46	154
bins_for_gpio_bits[13]	auto[1]	auto[0]	auto[0]	2857316	1			T44	141		T45	92		T46	137
bins_for_gpio_bits[13]	auto[1]	auto[0]	auto[1]	501437	1			T59	237		T102	102		T103	155
bins_for_gpio_bits[13]	auto[1]	auto[1]	auto[1]	2093602	1			T44	86		T45	100		T46	134
bins_for_gpio_bits[14]	auto[0]	auto[0]	auto[0]	7741918	1			T22	6		T23	2		T19	1
bins_for_gpio_bits[14]	auto[0]	auto[0]	auto[1]	5306447	1			T44	44		T45	24		T46	7
bins_for_gpio_bits[14]	auto[0]	auto[1]	auto[0]	2119159	1			T44	119		T45	111		T46	176
bins_for_gpio_bits[14]	auto[1]	auto[0]	auto[0]	2850984	1			T44	74		T45	106		T46	106
bins_for_gpio_bits[14]	auto[1]	auto[0]	auto[1]	498910	1			T59	221		T102	104		T103	120
bins_for_gpio_bits[14]	auto[1]	auto[1]	auto[1]	2090984	1			T44	90		T45	94		T46	129
bins_for_gpio_bits[15]	auto[0]	auto[0]	auto[0]	7721734	1			T22	6		T23	2		T19	1
bins_for_gpio_bits[15]	auto[0]	auto[0]	auto[1]	5318504	1			T44	33		T45	14		T46	11
bins_for_gpio_bits[15]	auto[0]	auto[1]	auto[0]	2112295	1			T44	110		T45	89		T46	146
bins_for_gpio_bits[15]	auto[1]	auto[0]	auto[0]	2851463	1			T44	100		T45	124		T46	173
bins_for_gpio_bits[15]	auto[1]	auto[0]	auto[1]	504508	1			T59	204		T102	80		T103	116
bins_for_gpio_bits[15]	auto[1]	auto[1]	auto[1]	2099898	1			T44	83		T45	108		T46	154
bins_for_gpio_bits[16]	auto[0]	auto[0]	auto[0]	7743264	1			T22	6		T23	2		T19	1
bins_for_gpio_bits[16]	auto[0]	auto[0]	auto[1]	5308355	1			T44	40		T45	27		T46	13
bins_for_gpio_bits[16]	auto[0]	auto[1]	auto[0]	2102572	1			T44	102		T45	110		T46	162
bins_for_gpio_bits[16]	auto[1]	auto[0]	auto[0]	2861895	1			T44	101		T45	96		T46	146
bins_for_gpio_bits[16]	auto[1]	auto[0]	auto[1]	502966	1			T59	206		T102	71		T103	130
bins_for_gpio_bits[16]	auto[1]	auto[1]	auto[1]	2089350	1			T44	94		T45	107		T46	138
bins_for_gpio_bits[17]	auto[0]	auto[0]	auto[0]	7735936	1			T22	6		T23	2		T19	1
bins_for_gpio_bits[17]	auto[0]	auto[0]	auto[1]	5314016	1			T44	36		T45	23		T46	12
bins_for_gpio_bits[17]	auto[0]	auto[1]	auto[0]	2101903	1			T44	85		T45	92		T46	132
bins_for_gpio_bits[17]	auto[1]	auto[0]	auto[0]	2859566	1			T44	128		T45	122		T46	154
bins_for_gpio_bits[17]	auto[1]	auto[0]	auto[1]	506493	1			T59	206		T102	98		T103	160
bins_for_gpio_bits[17]	auto[1]	auto[1]	auto[1]	2090488	1			T44	84		T45	97		T46	153
bins_for_gpio_bits[18]	auto[0]	auto[0]	auto[0]	7743398	1			T22	6		T23	2		T19	1
bins_for_gpio_bits[18]	auto[0]	auto[0]	auto[1]	5310898	1			T44	38		T45	23		T46	9
bins_for_gpio_bits[18]	auto[0]	auto[1]	auto[0]	2101911	1			T44	135		T45	109		T46	152
bins_for_gpio_bits[18]	auto[1]	auto[0]	auto[0]	2859297	1			T44	78		T45	104		T46	172
bins_for_gpio_bits[18]	auto[1]	auto[0]	auto[1]	503954	1			T59	212		T102	76		T103	127
bins_for_gpio_bits[18]	auto[1]	auto[1]	auto[1]	2088944	1			T44	86		T45	96		T46	132
bins_for_gpio_bits[19]	auto[0]	auto[0]	auto[0]	7738035	1			T22	6		T23	2		T19	1
bins_for_gpio_bits[19]	auto[0]	auto[0]	auto[1]	5313365	1			T44	36		T45	18		T46	10
bins_for_gpio_bits[19]	auto[0]	auto[1]	auto[0]	2109150	1			T44	96		T45	116		T46	149
bins_for_gpio_bits[19]	auto[1]	auto[0]	auto[0]	2852498	1			T44	104		T45	110		T46	156
bins_for_gpio_bits[19]	auto[1]	auto[0]	auto[1]	505853	1			T59	206		T102	56		T103	146
bins_for_gpio_bits[19]	auto[1]	auto[1]	auto[1]	2089501	1			T44	104		T45	97		T46	132
bins_for_gpio_bits[20]	auto[0]	auto[0]	auto[0]	7740658	1			T22	6		T23	2		T19	1
bins_for_gpio_bits[20]	auto[0]	auto[0]	auto[1]	5312327	1			T44	35		T45	18		T46	7
bins_for_gpio_bits[20]	auto[0]	auto[1]	auto[0]	2106071	1			T44	114		T45	135		T46	127
bins_for_gpio_bits[20]	auto[1]	auto[0]	auto[0]	2854336	1			T44	90		T45	82		T46	142
bins_for_gpio_bits[20]	auto[1]	auto[0]	auto[1]	503985	1			T59	204		T102	82		T103	118
bins_for_gpio_bits[20]	auto[1]	auto[1]	auto[1]	2091025	1			T44	82		T45	110		T46	158
bins_for_gpio_bits[21]	auto[0]	auto[0]	auto[0]	7745239	1			T22	6		T23	2		T19	1
bins_for_gpio_bits[21]	auto[0]	auto[0]	auto[1]	5309069	1			T44	38		T45	17		T46	10
bins_for_gpio_bits[21]	auto[0]	auto[1]	auto[0]	2108253	1			T44	61		T45	123		T46	152
bins_for_gpio_bits[21]	auto[1]	auto[0]	auto[0]	2860011	1			T44	128		T45	122		T46	147
bins_for_gpio_bits[21]	auto[1]	auto[0]	auto[1]	505643	1			T59	227		T102	72		T103	124
bins_for_gpio_bits[21]	auto[1]	auto[1]	auto[1]	2080187	1			T44	100		T45	94		T46	128
bins_for_gpio_bits[22]	auto[0]	auto[0]	auto[0]	7754849	1			T22	6		T23	2		T19	1
bins_for_gpio_bits[22]	auto[0]	auto[0]	auto[1]	5306638	1			T44	38		T45	17		T46	8
bins_for_gpio_bits[22]	auto[0]	auto[1]	auto[0]	2101408	1			T44	100		T45	94		T46	136
bins_for_gpio_bits[22]	auto[1]	auto[0]	auto[0]	2854599	1			T44	88		T45	121		T46	148
bins_for_gpio_bits[22]	auto[1]	auto[0]	auto[1]	502643	1			T59	208		T102	100		T103	86
bins_for_gpio_bits[22]	auto[1]	auto[1]	auto[1]	2088265	1			T44	96		T45	110		T46	164
bins_for_gpio_bits[23]	auto[0]	auto[0]	auto[0]	7750740	1			T22	6		T23	2		T19	1
bins_for_gpio_bits[23]	auto[0]	auto[0]	auto[1]	5292543	1			T44	31		T45	21		T46	9
bins_for_gpio_bits[23]	auto[0]	auto[1]	auto[0]	2105862	1			T44	84		T45	124		T46	138
bins_for_gpio_bits[23]	auto[1]	auto[0]	auto[0]	2863049	1			T44	114		T45	99		T46	161
bins_for_gpio_bits[23]	auto[1]	auto[0]	auto[1]	505332	1			T59	156		T102	88		T103	114
bins_for_gpio_bits[23]	auto[1]	auto[1]	auto[1]	2090876	1			T44	117		T45	108		T46	134
bins_for_gpio_bits[24]	auto[0]	auto[0]	auto[0]	7751554	1			T22	6		T23	2		T19	1
bins_for_gpio_bits[24]	auto[0]	auto[0]	auto[1]	5301715	1			T44	44		T45	20		T46	6
bins_for_gpio_bits[24]	auto[0]	auto[1]	auto[0]	2108276	1			T44	75		T45	98		T46	144
bins_for_gpio_bits[24]	auto[1]	auto[0]	auto[0]	2860776	1			T44	102		T45	113		T46	144
bins_for_gpio_bits[24]	auto[1]	auto[0]	auto[1]	503440	1			T59	210		T102	84		T103	117
bins_for_gpio_bits[24]	auto[1]	auto[1]	auto[1]	2082641	1			T44	126		T45	98		T46	172
bins_for_gpio_bits[25]	auto[0]	auto[0]	auto[0]	7736651	1			T22	6		T23	2		T19	1
bins_for_gpio_bits[25]	auto[0]	auto[0]	auto[1]	5319048	1			T44	29		T45	22		T46	12
bins_for_gpio_bits[25]	auto[0]	auto[1]	auto[0]	2103891	1			T44	80		T45	129		T46	182
bins_for_gpio_bits[25]	auto[1]	auto[0]	auto[0]	2858001	1			T44	103		T45	64		T46	101
bins_for_gpio_bits[25]	auto[1]	auto[0]	auto[1]	504423	1			T59	219		T102	66		T103	154
bins_for_gpio_bits[25]	auto[1]	auto[1]	auto[1]	2086388	1			T44	80		T45	128		T46	158
bins_for_gpio_bits[26]	auto[0]	auto[0]	auto[0]	7728371	1			T22	6		T23	2		T19	1
bins_for_gpio_bits[26]	auto[0]	auto[0]	auto[1]	5316746	1			T44	42		T45	16		T46	12
bins_for_gpio_bits[26]	auto[0]	auto[1]	auto[0]	2103927	1			T44	116		T45	143		T46	157
bins_for_gpio_bits[26]	auto[1]	auto[0]	auto[0]	2862496	1			T44	88		T45	94		T46	132
bins_for_gpio_bits[26]	auto[1]	auto[0]	auto[1]	504003	1			T59	180		T102	95		T103	124
bins_for_gpio_bits[26]	auto[1]	auto[1]	auto[1]	2092859	1			T44	92		T45	70		T46	152
bins_for_gpio_bits[27]	auto[0]	auto[0]	auto[0]	7741345	1			T22	6		T23	2		T19	1
bins_for_gpio_bits[27]	auto[0]	auto[0]	auto[1]	5310014	1			T44	38		T45	20		T46	7
bins_for_gpio_bits[27]	auto[0]	auto[1]	auto[0]	2106343	1			T44	115		T45	74		T46	116
bins_for_gpio_bits[27]	auto[1]	auto[0]	auto[0]	2855925	1			T44	82		T45	118		T46	174
bins_for_gpio_bits[27]	auto[1]	auto[0]	auto[1]	503028	1			T59	194		T102	110		T103	144
bins_for_gpio_bits[27]	auto[1]	auto[1]	auto[1]	2091747	1			T44	110		T45	114		T46	153
bins_for_gpio_bits[28]	auto[0]	auto[0]	auto[0]	7742077	1			T22	6		T23	2		T19	1
bins_for_gpio_bits[28]	auto[0]	auto[0]	auto[1]	5317494	1			T44	34		T45	21		T46	8
bins_for_gpio_bits[28]	auto[0]	auto[1]	auto[0]	2108616	1			T44	92		T45	91		T46	191
bins_for_gpio_bits[28]	auto[1]	auto[0]	auto[0]	2852434	1			T44	111		T45	118		T46	138
bins_for_gpio_bits[28]	auto[1]	auto[0]	auto[1]	503750	1			T59	189		T102	100		T103	121
bins_for_gpio_bits[28]	auto[1]	auto[1]	auto[1]	2084031	1			T44	104		T45	74		T46	162
bins_for_gpio_bits[29]	auto[0]	auto[0]	auto[0]	7744498	1			T22	6		T23	2		T19	1
bins_for_gpio_bits[29]	auto[0]	auto[0]	auto[1]	5308090	1			T44	40		T45	28		T46	9
bins_for_gpio_bits[29]	auto[0]	auto[1]	auto[0]	2110415	1			T44	102		T45	114		T46	156
bins_for_gpio_bits[29]	auto[1]	auto[0]	auto[0]	2851329	1			T44	84		T45	102		T46	163
bins_for_gpio_bits[29]	auto[1]	auto[0]	auto[1]	502953	1			T59	205		T102	112		T103	120
bins_for_gpio_bits[29]	auto[1]	auto[1]	auto[1]	2091117	1			T44	123		T45	106		T46	116
bins_for_gpio_bits[30]	auto[0]	auto[0]	auto[0]	7739201	1			T22	6		T23	2		T19	1
bins_for_gpio_bits[30]	auto[0]	auto[0]	auto[1]	5313116	1			T44	36		T45	18		T46	12
bins_for_gpio_bits[30]	auto[0]	auto[1]	auto[0]	2105375	1			T44	114		T45	102		T46	136
bins_for_gpio_bits[30]	auto[1]	auto[0]	auto[0]	2854725	1			T44	74		T45	96		T46	159
bins_for_gpio_bits[30]	auto[1]	auto[0]	auto[1]	503264	1			T59	182		T102	84		T103	150
bins_for_gpio_bits[30]	auto[1]	auto[1]	auto[1]	2092721	1			T44	98		T45	111		T46	144
bins_for_gpio_bits[31]	auto[0]	auto[0]	auto[0]	7726592	1			T22	6		T23	2		T19	1
bins_for_gpio_bits[31]	auto[0]	auto[0]	auto[1]	5313167	1			T44	27		T45	22		T46	14
bins_for_gpio_bits[31]	auto[0]	auto[1]	auto[0]	2110652	1			T44	105		T45	96		T46	156
bins_for_gpio_bits[31]	auto[1]	auto[0]	auto[0]	2863013	1			T44	96		T45	87		T46	148
bins_for_gpio_bits[31]	auto[1]	auto[0]	auto[1]	506039	1			T59	198		T102	106		T103	130
bins_for_gpio_bits[31]	auto[1]	auto[1]	auto[1]	2088939	1			T44	108		T45	140		T46	140

User Defined Cross Bins for cp_cross_all

Excluded/Illegal bins

NAME	COUNT	STATUS
data_oe_1_data_out_0_data_in_1	0	Illegal
data_oe_1_data_out_1_data_in_0	0	Illegal