Unified Coverage Report :: Group :: gpio_env_pkg::gpio_env_cov::gpio_pins_data_in_cross_cg

Group : gpio_env_pkg::gpio_env_cov::gpio_pins_data_in_cross_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_gpio_env_0.1/gpio_env_cov.sv

---

Summary for Group gpio_env_pkg::gpio_env_cov::gpio_pins_data_in_cross_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	36	0	36	100.00
Crosses	128	0	128	100.00

Variables for Group gpio_env_pkg::gpio_env_cov::gpio_pins_data_in_cross_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_pin	32	0	32	100.00	100	1	1	0
data_in	2	0	2	100.00	100	1	1	2
gpio_value	2	0	2	100.00	100	1	1	2

Crosses for Group gpio_env_pkg::gpio_env_cov::gpio_pins_data_in_cross_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_cross_pins_data_in	128	0	128	100.00	100	1	1	0

Summary for Variable cp_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	32	0	32	100.00

User Defined Bins for cp_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
bins_for_gpio_bits[0]	20608402	1			T22	6		T23	2		T19	1
bins_for_gpio_bits[1]	20608402	1			T22	6		T23	2		T19	1
bins_for_gpio_bits[2]	20608402	1			T22	6		T23	2		T19	1
bins_for_gpio_bits[3]	20608402	1			T22	6		T23	2		T19	1
bins_for_gpio_bits[4]	20608402	1			T22	6		T23	2		T19	1
bins_for_gpio_bits[5]	20608402	1			T22	6		T23	2		T19	1
bins_for_gpio_bits[6]	20608402	1			T22	6		T23	2		T19	1
bins_for_gpio_bits[7]	20608402	1			T22	6		T23	2		T19	1
bins_for_gpio_bits[8]	20608402	1			T22	6		T23	2		T19	1
bins_for_gpio_bits[9]	20608402	1			T22	6		T23	2		T19	1
bins_for_gpio_bits[10]	20608402	1			T22	6		T23	2		T19	1
bins_for_gpio_bits[11]	20608402	1			T22	6		T23	2		T19	1
bins_for_gpio_bits[12]	20608402	1			T22	6		T23	2		T19	1
bins_for_gpio_bits[13]	20608402	1			T22	6		T23	2		T19	1
bins_for_gpio_bits[14]	20608402	1			T22	6		T23	2		T19	1
bins_for_gpio_bits[15]	20608402	1			T22	6		T23	2		T19	1
bins_for_gpio_bits[16]	20608402	1			T22	6		T23	2		T19	1
bins_for_gpio_bits[17]	20608402	1			T22	6		T23	2		T19	1
bins_for_gpio_bits[18]	20608402	1			T22	6		T23	2		T19	1
bins_for_gpio_bits[19]	20608402	1			T22	6		T23	2		T19	1
bins_for_gpio_bits[20]	20608402	1			T22	6		T23	2		T19	1
bins_for_gpio_bits[21]	20608402	1			T22	6		T23	2		T19	1
bins_for_gpio_bits[22]	20608402	1			T22	6		T23	2		T19	1
bins_for_gpio_bits[23]	20608402	1			T22	6		T23	2		T19	1
bins_for_gpio_bits[24]	20608402	1			T22	6		T23	2		T19	1
bins_for_gpio_bits[25]	20608402	1			T22	6		T23	2		T19	1
bins_for_gpio_bits[26]	20608402	1			T22	6		T23	2		T19	1
bins_for_gpio_bits[27]	20608402	1			T22	6		T23	2		T19	1
bins_for_gpio_bits[28]	20608402	1			T22	6		T23	2		T19	1
bins_for_gpio_bits[29]	20608402	1			T22	6		T23	2		T19	1
bins_for_gpio_bits[30]	20608402	1			T22	6		T23	2		T19	1
bins_for_gpio_bits[31]	20608402	1			T22	6		T23	2		T19	1

---

Summary for Variable data_in

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for data_in

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

406465091

1

T22

192

T23

64

T19

32

auto[1]

253003773

1

T44

4342

T45

4027

T46

5049

---

Summary for Variable gpio_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for gpio_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

406457458

1

T22

147

T23

59

T19

32

auto[1]

253011406

1

T22

45

T23

5

T21

57

---

Summary for Cross cp_cross_pins_data_in

Samples crossed: cp_pin gpio_value data_in

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	128	0	128	100.00

Automatically Generated Cross Bins for cp_cross_pins_data_in

Bins

cp_pin	gpio_value	data_in	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
bins_for_gpio_bits[0]	auto[0]	auto[0]	12313603	1			T22	4		T23	2		T19	1
bins_for_gpio_bits[0]	auto[0]	auto[1]	375928	1			T44	25		T45	24		T46	44
bins_for_gpio_bits[0]	auto[1]	auto[0]	376141	1			T22	2		T21	1		T1	2
bins_for_gpio_bits[0]	auto[1]	auto[1]	7542730	1			T44	122		T45	77		T46	129
bins_for_gpio_bits[1]	auto[0]	auto[0]	12318626	1			T22	3		T23	2		T19	1
bins_for_gpio_bits[1]	auto[0]	auto[1]	375924	1			T44	27		T45	21		T46	35
bins_for_gpio_bits[1]	auto[1]	auto[0]	376182	1			T22	3		T21	5		T12	5
bins_for_gpio_bits[1]	auto[1]	auto[1]	7537670	1			T44	93		T45	97		T46	93
bins_for_gpio_bits[2]	auto[0]	auto[0]	12330250	1			T22	3		T23	2		T19	1
bins_for_gpio_bits[2]	auto[0]	auto[1]	375168	1			T44	22		T45	27		T46	31
bins_for_gpio_bits[2]	auto[1]	auto[0]	375420	1			T22	3		T21	2		T1	2
bins_for_gpio_bits[2]	auto[1]	auto[1]	7527564	1			T44	97		T45	76		T46	120
bins_for_gpio_bits[3]	auto[0]	auto[0]	12327609	1			T22	6		T23	2		T19	1
bins_for_gpio_bits[3]	auto[0]	auto[1]	375616	1			T44	17		T45	23		T46	36
bins_for_gpio_bits[3]	auto[1]	auto[0]	375822	1			T21	3		T1	1		T3	1
bins_for_gpio_bits[3]	auto[1]	auto[1]	7529355	1			T44	101		T45	103		T46	138
bins_for_gpio_bits[4]	auto[0]	auto[0]	12317314	1			T22	5		T23	2		T19	1
bins_for_gpio_bits[4]	auto[0]	auto[1]	375645	1			T44	22		T45	27		T46	40
bins_for_gpio_bits[4]	auto[1]	auto[0]	375905	1			T22	1		T21	2		T11	2
bins_for_gpio_bits[4]	auto[1]	auto[1]	7539538	1			T44	96		T45	108		T46	155
bins_for_gpio_bits[5]	auto[0]	auto[0]	12323405	1			T22	4		T23	2		T19	1
bins_for_gpio_bits[5]	auto[0]	auto[1]	376293	1			T44	23		T45	28		T46	39
bins_for_gpio_bits[5]	auto[1]	auto[0]	376502	1			T22	2		T21	1		T11	3
bins_for_gpio_bits[5]	auto[1]	auto[1]	7532202	1			T44	109		T45	138		T46	107
bins_for_gpio_bits[6]	auto[0]	auto[0]	12331929	1			T22	5		T23	2		T19	1
bins_for_gpio_bits[6]	auto[0]	auto[1]	375324	1			T44	27		T45	28		T46	41
bins_for_gpio_bits[6]	auto[1]	auto[0]	375536	1			T22	1		T21	2		T12	8
bins_for_gpio_bits[6]	auto[1]	auto[1]	7525613	1			T44	133		T45	106		T46	133
bins_for_gpio_bits[7]	auto[0]	auto[0]	12331862	1			T22	3		T23	2		T19	1
bins_for_gpio_bits[7]	auto[0]	auto[1]	375765	1			T44	22		T45	28		T46	33
bins_for_gpio_bits[7]	auto[1]	auto[0]	376040	1			T22	3		T21	3		T11	1
bins_for_gpio_bits[7]	auto[1]	auto[1]	7524735	1			T44	142		T45	115		T46	133
bins_for_gpio_bits[8]	auto[0]	auto[0]	12327832	1			T22	2		T23	2		T19	1
bins_for_gpio_bits[8]	auto[0]	auto[1]	375815	1			T44	28		T45	30		T46	40
bins_for_gpio_bits[8]	auto[1]	auto[0]	376039	1			T22	4		T21	2		T11	3
bins_for_gpio_bits[8]	auto[1]	auto[1]	7528716	1			T44	138		T45	103		T46	150
bins_for_gpio_bits[9]	auto[0]	auto[0]	12312418	1			T22	6		T23	2		T19	1
bins_for_gpio_bits[9]	auto[0]	auto[1]	375533	1			T44	24		T45	30		T46	32
bins_for_gpio_bits[9]	auto[1]	auto[0]	375791	1			T12	1		T3	1		T15	1
bins_for_gpio_bits[9]	auto[1]	auto[1]	7544660	1			T44	104		T45	95		T46	118
bins_for_gpio_bits[10]	auto[0]	auto[0]	12320949	1			T22	5		T23	2		T19	1
bins_for_gpio_bits[10]	auto[0]	auto[1]	374883	1			T44	26		T45	29		T46	40
bins_for_gpio_bits[10]	auto[1]	auto[0]	375096	1			T22	1		T21	2		T12	4
bins_for_gpio_bits[10]	auto[1]	auto[1]	7537474	1			T44	128		T45	99		T46	119
bins_for_gpio_bits[11]	auto[0]	auto[0]	12325376	1			T22	5		T23	2		T19	1
bins_for_gpio_bits[11]	auto[0]	auto[1]	376037	1			T44	28		T45	26		T46	42
bins_for_gpio_bits[11]	auto[1]	auto[0]	376302	1			T22	1		T21	3		T1	1
bins_for_gpio_bits[11]	auto[1]	auto[1]	7530687	1			T44	106		T45	85		T46	103
bins_for_gpio_bits[12]	auto[0]	auto[0]	12327494	1			T22	6		T23	2		T19	1
bins_for_gpio_bits[12]	auto[0]	auto[1]	373962	1			T44	24		T45	35		T46	35
bins_for_gpio_bits[12]	auto[1]	auto[0]	374178	1			T21	1		T1	2		T12	9
bins_for_gpio_bits[12]	auto[1]	auto[1]	7532768	1			T44	97		T45	112		T46	121
bins_for_gpio_bits[13]	auto[0]	auto[0]	12317025	1			T22	4		T23	2		T19	1
bins_for_gpio_bits[13]	auto[0]	auto[1]	375657	1			T44	25		T45	23		T46	30
bins_for_gpio_bits[13]	auto[1]	auto[0]	375909	1			T22	2		T21	1		T11	1
bins_for_gpio_bits[13]	auto[1]	auto[1]	7539811	1			T44	100		T45	103		T46	117
bins_for_gpio_bits[14]	auto[0]	auto[0]	12336539	1			T22	6		T23	2		T19	1
bins_for_gpio_bits[14]	auto[0]	auto[1]	375296	1			T44	25		T45	25		T46	35
bins_for_gpio_bits[14]	auto[1]	auto[0]	375522	1			T21	2		T11	1		T12	3
bins_for_gpio_bits[14]	auto[1]	auto[1]	7521045	1			T44	109		T45	93		T46	101
bins_for_gpio_bits[15]	auto[0]	auto[0]	12309049	1			T22	6		T23	2		T19	1
bins_for_gpio_bits[15]	auto[0]	auto[1]	376262	1			T44	21		T45	29		T46	36
bins_for_gpio_bits[15]	auto[1]	auto[0]	376443	1			T21	1		T1	4		T12	11
bins_for_gpio_bits[15]	auto[1]	auto[1]	7546648	1			T44	95		T45	93		T46	129
bins_for_gpio_bits[16]	auto[0]	auto[0]	12332505	1			T22	5		T23	2		T19	1
bins_for_gpio_bits[16]	auto[0]	auto[1]	375000	1			T44	21		T45	30		T46	39
bins_for_gpio_bits[16]	auto[1]	auto[0]	375226	1			T22	1		T21	2		T1	2
bins_for_gpio_bits[16]	auto[1]	auto[1]	7525671	1			T44	113		T45	104		T46	112
bins_for_gpio_bits[17]	auto[0]	auto[0]	12321747	1			T22	6		T23	2		T19	1
bins_for_gpio_bits[17]	auto[0]	auto[1]	375439	1			T44	21		T45	26		T46	36
bins_for_gpio_bits[17]	auto[1]	auto[0]	375658	1			T21	1		T1	2		T11	1
bins_for_gpio_bits[17]	auto[1]	auto[1]	7535558	1			T44	99		T45	94		T46	129
bins_for_gpio_bits[18]	auto[0]	auto[0]	12329277	1			T22	6		T23	2		T19	1
bins_for_gpio_bits[18]	auto[0]	auto[1]	375084	1			T44	27		T45	25		T46	36
bins_for_gpio_bits[18]	auto[1]	auto[0]	375329	1			T21	2		T1	3		T11	2
bins_for_gpio_bits[18]	auto[1]	auto[1]	7528712	1			T44	97		T45	94		T46	105
bins_for_gpio_bits[19]	auto[0]	auto[0]	12323841	1			T22	3		T23	2		T19	1
bins_for_gpio_bits[19]	auto[0]	auto[1]	375614	1			T44	26		T45	27		T46	36
bins_for_gpio_bits[19]	auto[1]	auto[0]	375842	1			T22	3		T21	2		T1	3
bins_for_gpio_bits[19]	auto[1]	auto[1]	7533105	1			T44	114		T45	88		T46	106
bins_for_gpio_bits[20]	auto[0]	auto[0]	12325487	1			T22	5		T23	2		T19	1
bins_for_gpio_bits[20]	auto[0]	auto[1]	375362	1			T44	24		T45	23		T46	39
bins_for_gpio_bits[20]	auto[1]	auto[0]	375578	1			T22	1		T21	2		T1	2
bins_for_gpio_bits[20]	auto[1]	auto[1]	7531975	1			T44	93		T45	105		T46	126
bins_for_gpio_bits[21]	auto[0]	auto[0]	12339495	1			T22	1		T23	2		T19	1
bins_for_gpio_bits[21]	auto[0]	auto[1]	373780	1			T44	24		T45	24		T46	34
bins_for_gpio_bits[21]	auto[1]	auto[0]	374008	1			T22	5		T21	2		T1	3
bins_for_gpio_bits[21]	auto[1]	auto[1]	7521119	1			T44	114		T45	87		T46	104
bins_for_gpio_bits[22]	auto[0]	auto[0]	12335817	1			T22	6		T23	1		T19	1
bins_for_gpio_bits[22]	auto[0]	auto[1]	374784	1			T44	28		T45	28		T46	37
bins_for_gpio_bits[22]	auto[1]	auto[0]	375039	1			T23	1		T21	1		T1	4
bins_for_gpio_bits[22]	auto[1]	auto[1]	7522762	1			T44	106		T45	99		T46	135
bins_for_gpio_bits[23]	auto[0]	auto[0]	12343784	1			T22	4		T23	2		T19	1
bins_for_gpio_bits[23]	auto[0]	auto[1]	375626	1			T44	27		T45	26		T46	37
bins_for_gpio_bits[23]	auto[1]	auto[0]	375867	1			T22	2		T12	1		T3	1
bins_for_gpio_bits[23]	auto[1]	auto[1]	7513125	1			T44	121		T45	103		T46	106
bins_for_gpio_bits[24]	auto[0]	auto[0]	12345107	1			T22	6		T23	1		T19	1
bins_for_gpio_bits[24]	auto[0]	auto[1]	375242	1			T44	24		T45	26		T46	38
bins_for_gpio_bits[24]	auto[1]	auto[0]	375499	1			T23	1		T21	1		T1	3
bins_for_gpio_bits[24]	auto[1]	auto[1]	7512554	1			T44	146		T45	92		T46	140
bins_for_gpio_bits[25]	auto[0]	auto[0]	12322997	1			T22	4		T23	1		T19	1
bins_for_gpio_bits[25]	auto[0]	auto[1]	375322	1			T44	22		T45	25		T46	39
bins_for_gpio_bits[25]	auto[1]	auto[0]	375546	1			T22	2		T23	1		T21	3
bins_for_gpio_bits[25]	auto[1]	auto[1]	7534537	1			T44	87		T45	125		T46	131
bins_for_gpio_bits[26]	auto[0]	auto[0]	12318515	1			T22	5		T23	2		T19	1
bins_for_gpio_bits[26]	auto[0]	auto[1]	375983	1			T44	21		T45	22		T46	39
bins_for_gpio_bits[26]	auto[1]	auto[0]	376279	1			T22	1		T21	1		T1	1
bins_for_gpio_bits[26]	auto[1]	auto[1]	7537625	1			T44	113		T45	64		T46	125
bins_for_gpio_bits[27]	auto[0]	auto[0]	12327339	1			T22	5		T23	2		T19	1
bins_for_gpio_bits[27]	auto[0]	auto[1]	376016	1			T44	21		T45	26		T46	40
bins_for_gpio_bits[27]	auto[1]	auto[0]	376274	1			T22	1		T21	1		T1	3
bins_for_gpio_bits[27]	auto[1]	auto[1]	7528773	1			T44	127		T45	108		T46	120
bins_for_gpio_bits[28]	auto[0]	auto[0]	12327683	1			T22	3		T23	1		T19	1
bins_for_gpio_bits[28]	auto[0]	auto[1]	375166	1			T44	27		T45	21		T46	40
bins_for_gpio_bits[28]	auto[1]	auto[0]	375444	1			T22	3		T23	1		T21	1
bins_for_gpio_bits[28]	auto[1]	auto[1]	7530109	1			T44	111		T45	74		T46	130
bins_for_gpio_bits[29]	auto[0]	auto[0]	12330264	1			T22	6		T23	2		T19	1
bins_for_gpio_bits[29]	auto[0]	auto[1]	375729	1			T44	25		T45	24		T46	34
bins_for_gpio_bits[29]	auto[1]	auto[0]	375978	1			T21	1		T1	2		T11	1
bins_for_gpio_bits[29]	auto[1]	auto[1]	7526431	1			T44	138		T45	110		T46	91
bins_for_gpio_bits[30]	auto[0]	auto[0]	12324244	1			T22	4		T23	1		T19	1
bins_for_gpio_bits[30]	auto[0]	auto[1]	374857	1			T44	21		T45	21		T46	35
bins_for_gpio_bits[30]	auto[1]	auto[0]	375057	1			T22	2		T23	1		T21	4
bins_for_gpio_bits[30]	auto[1]	auto[1]	7534244	1			T44	113		T45	108		T46	121
bins_for_gpio_bits[31]	auto[0]	auto[0]	12324388	1			T22	5		T23	2		T19	1
bins_for_gpio_bits[31]	auto[0]	auto[1]	375576	1			T44	24		T45	22		T46	36
bins_for_gpio_bits[31]	auto[1]	auto[0]	375869	1			T22	1		T21	2		T1	3
bins_for_gpio_bits[31]	auto[1]	auto[1]	7532569	1			T44	111		T45	140		T46	118