Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11511892 |
1 |
|
|
T22 |
1 |
|
T23 |
2 |
|
T19 |
6 |
| auto[1] |
9354392 |
1 |
|
|
T22 |
5 |
|
T19 |
6 |
|
T21 |
2 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
19661507 |
1 |
|
|
T22 |
5 |
|
T23 |
2 |
|
T19 |
12 |
| auto[1] |
1204777 |
1 |
|
|
T22 |
1 |
|
T1 |
1 |
|
T12 |
4 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11562596 |
1 |
|
|
T22 |
4 |
|
T23 |
2 |
|
T19 |
12 |
| auto[1] |
9303688 |
1 |
|
|
T22 |
2 |
|
T21 |
1 |
|
T1 |
2 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
4025666 |
1 |
|
|
T12 |
7 |
|
T24 |
9 |
|
T75 |
7 |
| auto[1] |
auto[0] |
auto[1] |
597844 |
1 |
|
|
T12 |
4 |
|
T75 |
1 |
|
T77 |
1 |
| auto[1] |
auto[1] |
auto[0] |
4073245 |
1 |
|
|
T22 |
1 |
|
T21 |
1 |
|
T1 |
1 |
| auto[1] |
auto[1] |
auto[1] |
606933 |
1 |
|
|
T22 |
1 |
|
T1 |
1 |
|
T39 |
5834 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11539256 |
1 |
|
|
T22 |
1 |
|
T23 |
2 |
|
T19 |
3 |
| auto[1] |
9327028 |
1 |
|
|
T22 |
5 |
|
T19 |
9 |
|
T21 |
4 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
19656325 |
1 |
|
|
T22 |
6 |
|
T23 |
2 |
|
T19 |
12 |
| auto[1] |
1209959 |
1 |
|
|
T78 |
1 |
|
T104 |
1 |
|
T39 |
11768 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11541164 |
1 |
|
|
T22 |
6 |
|
T23 |
2 |
|
T19 |
12 |
| auto[1] |
9325120 |
1 |
|
|
T21 |
3 |
|
T1 |
2 |
|
T11 |
1 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
4090337 |
1 |
|
|
T21 |
1 |
|
T24 |
7 |
|
T76 |
5 |
| auto[1] |
auto[0] |
auto[1] |
610680 |
1 |
|
|
T78 |
1 |
|
T104 |
1 |
|
T39 |
5760 |
| auto[1] |
auto[1] |
auto[0] |
4024824 |
1 |
|
|
T21 |
2 |
|
T1 |
2 |
|
T11 |
1 |
| auto[1] |
auto[1] |
auto[1] |
599279 |
1 |
|
|
T39 |
6008 |
|
T98 |
11 |
|
T97 |
700 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11531213 |
1 |
|
|
T22 |
1 |
|
T23 |
2 |
|
T19 |
9 |
| auto[1] |
9335071 |
1 |
|
|
T22 |
5 |
|
T19 |
3 |
|
T21 |
2 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
19657046 |
1 |
|
|
T22 |
5 |
|
T23 |
2 |
|
T19 |
12 |
| auto[1] |
1209238 |
1 |
|
|
T22 |
1 |
|
T76 |
1 |
|
T77 |
2 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11547250 |
1 |
|
|
T22 |
2 |
|
T23 |
2 |
|
T19 |
12 |
| auto[1] |
9319034 |
1 |
|
|
T22 |
4 |
|
T21 |
2 |
|
T2 |
1 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
4056849 |
1 |
|
|
T21 |
1 |
|
T2 |
1 |
|
T24 |
9 |
| auto[1] |
auto[0] |
auto[1] |
606086 |
1 |
|
|
T104 |
1 |
|
T39 |
6029 |
|
T98 |
1 |
| auto[1] |
auto[1] |
auto[0] |
4052947 |
1 |
|
|
T22 |
3 |
|
T21 |
1 |
|
T24 |
2 |
| auto[1] |
auto[1] |
auto[1] |
603152 |
1 |
|
|
T22 |
1 |
|
T76 |
1 |
|
T77 |
2 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11507201 |
1 |
|
|
T22 |
2 |
|
T23 |
2 |
|
T19 |
7 |
| auto[1] |
9359083 |
1 |
|
|
T22 |
4 |
|
T19 |
5 |
|
T21 |
2 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
19654733 |
1 |
|
|
T22 |
5 |
|
T23 |
2 |
|
T19 |
12 |
| auto[1] |
1211551 |
1 |
|
|
T22 |
1 |
|
T11 |
1 |
|
T77 |
4 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11537930 |
1 |
|
|
T22 |
2 |
|
T23 |
2 |
|
T19 |
12 |
| auto[1] |
9328354 |
1 |
|
|
T22 |
4 |
|
T21 |
3 |
|
T1 |
2 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
4067460 |
1 |
|
|
T21 |
2 |
|
T1 |
1 |
|
T11 |
1 |
| auto[1] |
auto[0] |
auto[1] |
606861 |
1 |
|
|
T77 |
4 |
|
T9 |
1 |
|
T39 |
5611 |
| auto[1] |
auto[1] |
auto[0] |
4049343 |
1 |
|
|
T22 |
3 |
|
T21 |
1 |
|
T1 |
1 |
| auto[1] |
auto[1] |
auto[1] |
604690 |
1 |
|
|
T22 |
1 |
|
T11 |
1 |
|
T79 |
1 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11503519 |
1 |
|
|
T22 |
1 |
|
T23 |
1 |
|
T19 |
9 |
| auto[1] |
9362765 |
1 |
|
|
T22 |
5 |
|
T23 |
1 |
|
T19 |
3 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
19659001 |
1 |
|
|
T22 |
6 |
|
T23 |
2 |
|
T19 |
12 |
| auto[1] |
1207283 |
1 |
|
|
T1 |
1 |
|
T75 |
1 |
|
T77 |
2 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11563919 |
1 |
|
|
T22 |
6 |
|
T23 |
2 |
|
T19 |
12 |
| auto[1] |
9302365 |
1 |
|
|
T21 |
3 |
|
T1 |
2 |
|
T11 |
3 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
4032167 |
1 |
|
|
T21 |
1 |
|
T1 |
1 |
|
T11 |
3 |
| auto[1] |
auto[0] |
auto[1] |
601530 |
1 |
|
|
T1 |
1 |
|
T75 |
1 |
|
T104 |
1 |
| auto[1] |
auto[1] |
auto[0] |
4062915 |
1 |
|
|
T21 |
2 |
|
T24 |
3 |
|
T77 |
13 |
| auto[1] |
auto[1] |
auto[1] |
605753 |
1 |
|
|
T77 |
2 |
|
T39 |
5633 |
|
T98 |
8 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11544100 |
1 |
|
|
T22 |
2 |
|
T23 |
1 |
|
T19 |
11 |
| auto[1] |
9322184 |
1 |
|
|
T22 |
4 |
|
T23 |
1 |
|
T19 |
1 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
19659476 |
1 |
|
|
T22 |
6 |
|
T23 |
2 |
|
T19 |
12 |
| auto[1] |
1206808 |
1 |
|
|
T12 |
2 |
|
T75 |
2 |
|
T76 |
1 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11568809 |
1 |
|
|
T22 |
2 |
|
T23 |
2 |
|
T19 |
12 |
| auto[1] |
9297475 |
1 |
|
|
T22 |
4 |
|
T21 |
3 |
|
T1 |
4 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
4046742 |
1 |
|
|
T21 |
2 |
|
T12 |
9 |
|
T3 |
1 |
| auto[1] |
auto[0] |
auto[1] |
604480 |
1 |
|
|
T12 |
2 |
|
T75 |
2 |
|
T39 |
6082 |
| auto[1] |
auto[1] |
auto[0] |
4043925 |
1 |
|
|
T22 |
4 |
|
T21 |
1 |
|
T1 |
4 |
| auto[1] |
auto[1] |
auto[1] |
602328 |
1 |
|
|
T76 |
1 |
|
T39 |
6162 |
|
T98 |
6 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11583790 |
1 |
|
|
T22 |
1 |
|
T23 |
2 |
|
T19 |
3 |
| auto[1] |
9282494 |
1 |
|
|
T22 |
5 |
|
T19 |
9 |
|
T21 |
4 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
19658887 |
1 |
|
|
T22 |
6 |
|
T23 |
2 |
|
T19 |
12 |
| auto[1] |
1207397 |
1 |
|
|
T11 |
1 |
|
T77 |
3 |
|
T78 |
1 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11558395 |
1 |
|
|
T22 |
4 |
|
T23 |
2 |
|
T19 |
12 |
| auto[1] |
9307889 |
1 |
|
|
T22 |
2 |
|
T21 |
4 |
|
T11 |
3 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
4057778 |
1 |
|
|
T11 |
1 |
|
T12 |
11 |
|
T24 |
7 |
| auto[1] |
auto[0] |
auto[1] |
604922 |
1 |
|
|
T11 |
1 |
|
T39 |
6222 |
|
T98 |
4 |
| auto[1] |
auto[1] |
auto[0] |
4042714 |
1 |
|
|
T22 |
2 |
|
T21 |
4 |
|
T11 |
1 |
| auto[1] |
auto[1] |
auto[1] |
602475 |
1 |
|
|
T77 |
3 |
|
T78 |
1 |
|
T39 |
5827 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11559717 |
1 |
|
|
T22 |
2 |
|
T23 |
2 |
|
T19 |
4 |
| auto[1] |
9306567 |
1 |
|
|
T22 |
4 |
|
T19 |
8 |
|
T21 |
1 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
19653754 |
1 |
|
|
T22 |
6 |
|
T23 |
2 |
|
T19 |
12 |
| auto[1] |
1212530 |
1 |
|
|
T1 |
1 |
|
T75 |
2 |
|
T39 |
12002 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11531441 |
1 |
|
|
T22 |
4 |
|
T23 |
2 |
|
T19 |
12 |
| auto[1] |
9334843 |
1 |
|
|
T22 |
2 |
|
T21 |
2 |
|
T1 |
2 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
4068272 |
1 |
|
|
T21 |
2 |
|
T24 |
6 |
|
T75 |
6 |
| auto[1] |
auto[0] |
auto[1] |
607313 |
1 |
|
|
T75 |
2 |
|
T39 |
6067 |
|
T98 |
10 |
| auto[1] |
auto[1] |
auto[0] |
4054041 |
1 |
|
|
T22 |
2 |
|
T1 |
1 |
|
T11 |
1 |
| auto[1] |
auto[1] |
auto[1] |
605217 |
1 |
|
|
T1 |
1 |
|
T39 |
5935 |
|
T98 |
3 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11509467 |
1 |
|
|
T22 |
5 |
|
T23 |
2 |
|
T19 |
9 |
| auto[1] |
9356817 |
1 |
|
|
T22 |
1 |
|
T19 |
3 |
|
T21 |
1 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
19654755 |
1 |
|
|
T22 |
6 |
|
T23 |
2 |
|
T19 |
12 |
| auto[1] |
1211529 |
1 |
|
|
T12 |
3 |
|
T76 |
1 |
|
T104 |
1 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11526527 |
1 |
|
|
T22 |
4 |
|
T23 |
2 |
|
T19 |
12 |
| auto[1] |
9339757 |
1 |
|
|
T22 |
2 |
|
T11 |
3 |
|
T12 |
11 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
4061368 |
1 |
|
|
T22 |
2 |
|
T11 |
3 |
|
T12 |
8 |
| auto[1] |
auto[0] |
auto[1] |
605277 |
1 |
|
|
T12 |
3 |
|
T76 |
1 |
|
T104 |
1 |
| auto[1] |
auto[1] |
auto[0] |
4066860 |
1 |
|
|
T24 |
4 |
|
T76 |
3 |
|
T32 |
1 |
| auto[1] |
auto[1] |
auto[1] |
606252 |
1 |
|
|
T39 |
6262 |
|
T98 |
6 |
|
T97 |
783 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11462331 |
1 |
|
|
T22 |
2 |
|
T23 |
1 |
|
T19 |
3 |
| auto[1] |
9403953 |
1 |
|
|
T22 |
4 |
|
T23 |
1 |
|
T19 |
9 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
19652707 |
1 |
|
|
T22 |
6 |
|
T23 |
2 |
|
T19 |
12 |
| auto[1] |
1213577 |
1 |
|
|
T75 |
2 |
|
T76 |
1 |
|
T79 |
1 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11522448 |
1 |
|
|
T22 |
6 |
|
T23 |
2 |
|
T19 |
12 |
| auto[1] |
9343836 |
1 |
|
|
T21 |
3 |
|
T1 |
2 |
|
T11 |
3 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
4036823 |
1 |
|
|
T21 |
2 |
|
T1 |
1 |
|
T11 |
3 |
| auto[1] |
auto[0] |
auto[1] |
601736 |
1 |
|
|
T39 |
6178 |
|
T47 |
1 |
|
T98 |
3 |
| auto[1] |
auto[1] |
auto[0] |
4093436 |
1 |
|
|
T21 |
1 |
|
T1 |
1 |
|
T12 |
11 |
| auto[1] |
auto[1] |
auto[1] |
611841 |
1 |
|
|
T75 |
2 |
|
T76 |
1 |
|
T79 |
1 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11531709 |
1 |
|
|
T22 |
2 |
|
T23 |
1 |
|
T19 |
11 |
| auto[1] |
9334575 |
1 |
|
|
T22 |
4 |
|
T23 |
1 |
|
T19 |
1 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
19660186 |
1 |
|
|
T22 |
6 |
|
T23 |
2 |
|
T19 |
12 |
| auto[1] |
1206098 |
1 |
|
|
T75 |
1 |
|
T76 |
1 |
|
T80 |
1 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11568737 |
1 |
|
|
T22 |
2 |
|
T23 |
2 |
|
T19 |
12 |
| auto[1] |
9297547 |
1 |
|
|
T22 |
4 |
|
T21 |
2 |
|
T1 |
4 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
4042182 |
1 |
|
|
T21 |
1 |
|
T1 |
1 |
|
T11 |
1 |
| auto[1] |
auto[0] |
auto[1] |
602206 |
1 |
|
|
T76 |
1 |
|
T80 |
1 |
|
T9 |
1 |
| auto[1] |
auto[1] |
auto[0] |
4049267 |
1 |
|
|
T22 |
4 |
|
T21 |
1 |
|
T1 |
3 |
| auto[1] |
auto[1] |
auto[1] |
603892 |
1 |
|
|
T75 |
1 |
|
T39 |
6127 |
|
T98 |
9 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11560382 |
1 |
|
|
T22 |
1 |
|
T23 |
2 |
|
T19 |
11 |
| auto[1] |
9305902 |
1 |
|
|
T22 |
5 |
|
T19 |
1 |
|
T21 |
1 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
19655187 |
1 |
|
|
T22 |
6 |
|
T23 |
2 |
|
T19 |
12 |
| auto[1] |
1211097 |
1 |
|
|
T1 |
1 |
|
T12 |
2 |
|
T80 |
1 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11525769 |
1 |
|
|
T22 |
6 |
|
T23 |
2 |
|
T19 |
12 |
| auto[1] |
9340515 |
1 |
|
|
T21 |
4 |
|
T1 |
4 |
|
T11 |
2 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
4085589 |
1 |
|
|
T21 |
3 |
|
T12 |
16 |
|
T24 |
7 |
| auto[1] |
auto[0] |
auto[1] |
608795 |
1 |
|
|
T12 |
2 |
|
T80 |
1 |
|
T81 |
1 |
| auto[1] |
auto[1] |
auto[0] |
4043829 |
1 |
|
|
T21 |
1 |
|
T1 |
3 |
|
T11 |
2 |
| auto[1] |
auto[1] |
auto[1] |
602302 |
1 |
|
|
T1 |
1 |
|
T39 |
5609 |
|
T97 |
705 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11531349 |
1 |
|
|
T22 |
1 |
|
T23 |
2 |
|
T19 |
8 |
| auto[1] |
9334935 |
1 |
|
|
T22 |
5 |
|
T19 |
4 |
|
T21 |
3 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
19647466 |
1 |
|
|
T22 |
6 |
|
T23 |
2 |
|
T19 |
12 |
| auto[1] |
1218818 |
1 |
|
|
T1 |
1 |
|
T76 |
1 |
|
T78 |
1 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11496214 |
1 |
|
|
T22 |
6 |
|
T23 |
2 |
|
T19 |
12 |
| auto[1] |
9370070 |
1 |
|
|
T21 |
6 |
|
T1 |
2 |
|
T24 |
13 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
4081264 |
1 |
|
|
T21 |
3 |
|
T24 |
11 |
|
T76 |
4 |
| auto[1] |
auto[0] |
auto[1] |
609922 |
1 |
|
|
T76 |
1 |
|
T78 |
1 |
|
T39 |
5940 |
| auto[1] |
auto[1] |
auto[0] |
4069988 |
1 |
|
|
T21 |
3 |
|
T1 |
1 |
|
T24 |
2 |
| auto[1] |
auto[1] |
auto[1] |
608896 |
1 |
|
|
T1 |
1 |
|
T39 |
6392 |
|
T98 |
7 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11553906 |
1 |
|
|
T22 |
2 |
|
T23 |
1 |
|
T19 |
3 |
| auto[1] |
9312378 |
1 |
|
|
T22 |
4 |
|
T23 |
1 |
|
T19 |
9 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
19659222 |
1 |
|
|
T22 |
6 |
|
T23 |
2 |
|
T19 |
12 |
| auto[1] |
1207062 |
1 |
|
|
T39 |
11726 |
|
T98 |
12 |
|
T97 |
1517 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11546209 |
1 |
|
|
T22 |
6 |
|
T23 |
2 |
|
T19 |
12 |
| auto[1] |
9320075 |
1 |
|
|
T21 |
5 |
|
T11 |
3 |
|
T12 |
18 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
4062829 |
1 |
|
|
T21 |
5 |
|
T12 |
18 |
|
T3 |
1 |
| auto[1] |
auto[0] |
auto[1] |
604882 |
1 |
|
|
T39 |
5972 |
|
T98 |
10 |
|
T97 |
829 |
| auto[1] |
auto[1] |
auto[0] |
4050184 |
1 |
|
|
T11 |
3 |
|
T24 |
5 |
|
T25 |
3 |
| auto[1] |
auto[1] |
auto[1] |
602180 |
1 |
|
|
T39 |
5754 |
|
T98 |
2 |
|
T97 |
688 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11579954 |
1 |
|
|
T22 |
5 |
|
T23 |
2 |
|
T19 |
9 |
| auto[1] |
9286330 |
1 |
|
|
T22 |
1 |
|
T19 |
3 |
|
T21 |
3 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
19668076 |
1 |
|
|
T22 |
6 |
|
T23 |
2 |
|
T19 |
12 |
| auto[1] |
1198208 |
1 |
|
|
T1 |
1 |
|
T75 |
2 |
|
T39 |
12145 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11599927 |
1 |
|
|
T22 |
2 |
|
T23 |
2 |
|
T19 |
12 |
| auto[1] |
9266357 |
1 |
|
|
T22 |
4 |
|
T21 |
4 |
|
T1 |
2 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
4046779 |
1 |
|
|
T22 |
4 |
|
T21 |
2 |
|
T1 |
1 |
| auto[1] |
auto[0] |
auto[1] |
601000 |
1 |
|
|
T1 |
1 |
|
T39 |
6366 |
|
T47 |
1 |
| auto[1] |
auto[1] |
auto[0] |
4021370 |
1 |
|
|
T21 |
2 |
|
T11 |
3 |
|
T24 |
5 |
| auto[1] |
auto[1] |
auto[1] |
597208 |
1 |
|
|
T75 |
2 |
|
T39 |
5779 |
|
T98 |
6 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11542675 |
1 |
|
|
T22 |
1 |
|
T23 |
1 |
|
T19 |
4 |
| auto[1] |
9323609 |
1 |
|
|
T22 |
5 |
|
T23 |
1 |
|
T19 |
8 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
19656548 |
1 |
|
|
T22 |
6 |
|
T23 |
2 |
|
T19 |
12 |
| auto[1] |
1209736 |
1 |
|
|
T39 |
12347 |
|
T98 |
6 |
|
T97 |
1499 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11542566 |
1 |
|
|
T22 |
4 |
|
T23 |
2 |
|
T19 |
12 |
| auto[1] |
9323718 |
1 |
|
|
T22 |
2 |
|
T21 |
6 |
|
T1 |
2 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
4075501 |
1 |
|
|
T21 |
3 |
|
T1 |
2 |
|
T11 |
1 |
| auto[1] |
auto[0] |
auto[1] |
608105 |
1 |
|
|
T39 |
6408 |
|
T98 |
3 |
|
T97 |
693 |
| auto[1] |
auto[1] |
auto[0] |
4038481 |
1 |
|
|
T22 |
2 |
|
T21 |
3 |
|
T11 |
2 |
| auto[1] |
auto[1] |
auto[1] |
601631 |
1 |
|
|
T39 |
5939 |
|
T98 |
3 |
|
T97 |
806 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11547869 |
1 |
|
|
T22 |
2 |
|
T23 |
2 |
|
T19 |
8 |
| auto[1] |
9318415 |
1 |
|
|
T22 |
4 |
|
T19 |
4 |
|
T21 |
2 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
19652216 |
1 |
|
|
T22 |
6 |
|
T23 |
2 |
|
T19 |
12 |
| auto[1] |
1214068 |
1 |
|
|
T76 |
1 |
|
T78 |
1 |
|
T39 |
12863 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11521671 |
1 |
|
|
T22 |
4 |
|
T23 |
2 |
|
T19 |
12 |
| auto[1] |
9344613 |
1 |
|
|
T22 |
2 |
|
T21 |
1 |
|
T11 |
2 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
4060753 |
1 |
|
|
T21 |
1 |
|
T11 |
2 |
|
T24 |
6 |
| auto[1] |
auto[0] |
auto[1] |
605740 |
1 |
|
|
T76 |
1 |
|
T78 |
1 |
|
T39 |
6524 |
| auto[1] |
auto[1] |
auto[0] |
4069792 |
1 |
|
|
T22 |
2 |
|
T24 |
5 |
|
T25 |
1 |
| auto[1] |
auto[1] |
auto[1] |
608328 |
1 |
|
|
T39 |
6339 |
|
T47 |
1 |
|
T98 |
4 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11527864 |
1 |
|
|
T22 |
6 |
|
T23 |
2 |
|
T19 |
6 |
| auto[1] |
9338420 |
1 |
|
|
T19 |
6 |
|
T21 |
1 |
|
T1 |
5 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
19658367 |
1 |
|
|
T22 |
6 |
|
T23 |
2 |
|
T19 |
12 |
| auto[1] |
1207917 |
1 |
|
|
T12 |
1 |
|
T76 |
2 |
|
T77 |
2 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11551662 |
1 |
|
|
T22 |
4 |
|
T23 |
2 |
|
T19 |
12 |
| auto[1] |
9314622 |
1 |
|
|
T22 |
2 |
|
T21 |
3 |
|
T11 |
1 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
4033119 |
1 |
|
|
T22 |
2 |
|
T21 |
3 |
|
T11 |
1 |
| auto[1] |
auto[0] |
auto[1] |
600955 |
1 |
|
|
T12 |
1 |
|
T76 |
2 |
|
T77 |
2 |
| auto[1] |
auto[1] |
auto[0] |
4073586 |
1 |
|
|
T24 |
5 |
|
T75 |
8 |
|
T25 |
2 |
| auto[1] |
auto[1] |
auto[1] |
606962 |
1 |
|
|
T39 |
5880 |
|
T98 |
7 |
|
T97 |
763 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11528863 |
1 |
|
|
T22 |
5 |
|
T23 |
1 |
|
T19 |
7 |
| auto[1] |
9337421 |
1 |
|
|
T22 |
1 |
|
T23 |
1 |
|
T19 |
5 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
19652369 |
1 |
|
|
T22 |
5 |
|
T23 |
2 |
|
T19 |
12 |
| auto[1] |
1213915 |
1 |
|
|
T22 |
1 |
|
T1 |
1 |
|
T12 |
2 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11518024 |
1 |
|
|
T22 |
4 |
|
T23 |
2 |
|
T19 |
12 |
| auto[1] |
9348260 |
1 |
|
|
T22 |
2 |
|
T21 |
1 |
|
T1 |
2 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
4072850 |
1 |
|
|
T22 |
1 |
|
T21 |
1 |
|
T12 |
16 |
| auto[1] |
auto[0] |
auto[1] |
607308 |
1 |
|
|
T22 |
1 |
|
T12 |
2 |
|
T77 |
2 |
| auto[1] |
auto[1] |
auto[0] |
4061495 |
1 |
|
|
T1 |
1 |
|
T11 |
1 |
|
T24 |
2 |
| auto[1] |
auto[1] |
auto[1] |
606607 |
1 |
|
|
T1 |
1 |
|
T75 |
3 |
|
T104 |
1 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11565169 |
1 |
|
|
T22 |
5 |
|
T23 |
1 |
|
T19 |
6 |
| auto[1] |
9301115 |
1 |
|
|
T22 |
1 |
|
T23 |
1 |
|
T19 |
6 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
19657263 |
1 |
|
|
T22 |
5 |
|
T23 |
2 |
|
T19 |
12 |
| auto[1] |
1209021 |
1 |
|
|
T22 |
1 |
|
T12 |
2 |
|
T79 |
1 |