Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11536798 |
1 |
|
|
T22 |
4 |
|
T23 |
2 |
|
T19 |
12 |
| auto[1] |
9329486 |
1 |
|
|
T22 |
2 |
|
T21 |
4 |
|
T1 |
2 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
4060402 |
1 |
|
|
T22 |
1 |
|
T21 |
2 |
|
T1 |
2 |
| auto[1] |
auto[0] |
auto[1] |
604908 |
1 |
|
|
T22 |
1 |
|
T12 |
2 |
|
T79 |
1 |
| auto[1] |
auto[1] |
auto[0] |
4060063 |
1 |
|
|
T21 |
2 |
|
T3 |
1 |
|
T24 |
3 |
| auto[1] |
auto[1] |
auto[1] |
604113 |
1 |
|
|
T39 |
6360 |
|
T98 |
11 |
|
T97 |
842 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |