Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11542490 |
1 |
|
|
T22 |
5 |
|
T23 |
2 |
|
T19 |
6 |
| auto[1] |
9323794 |
1 |
|
|
T22 |
1 |
|
T19 |
6 |
|
T21 |
3 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
19653844 |
1 |
|
|
T22 |
6 |
|
T23 |
2 |
|
T19 |
12 |
| auto[1] |
1212440 |
1 |
|
|
T75 |
2 |
|
T76 |
1 |
|
T39 |
11958 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11526533 |
1 |
|
|
T22 |
4 |
|
T23 |
2 |
|
T19 |
12 |
| auto[1] |
9339751 |
1 |
|
|
T22 |
2 |
|
T21 |
3 |
|
T11 |
1 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
4081684 |
1 |
|
|
T22 |
2 |
|
T21 |
2 |
|
T3 |
1 |
| auto[1] |
auto[0] |
auto[1] |
609849 |
1 |
|
|
T75 |
2 |
|
T76 |
1 |
|
T39 |
5861 |
| auto[1] |
auto[1] |
auto[0] |
4045627 |
1 |
|
|
T21 |
1 |
|
T11 |
1 |
|
T12 |
11 |
| auto[1] |
auto[1] |
auto[1] |
602591 |
1 |
|
|
T39 |
6097 |
|
T98 |
10 |
|
T97 |
826 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |