Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11567521 |
1 |
|
|
T22 |
1 |
|
T23 |
2 |
|
T19 |
7 |
| auto[1] |
9298763 |
1 |
|
|
T22 |
5 |
|
T19 |
5 |
|
T21 |
2 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
15278449 |
1 |
|
|
T22 |
6 |
|
T23 |
2 |
|
T19 |
12 |
| auto[1] |
5587835 |
1 |
|
|
T21 |
3 |
|
T1 |
5 |
|
T2 |
1 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11561432 |
1 |
|
|
T22 |
6 |
|
T23 |
2 |
|
T19 |
12 |
| auto[1] |
9304852 |
1 |
|
|
T21 |
3 |
|
T1 |
5 |
|
T2 |
1 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
1868055 |
1 |
|
|
T24 |
1 |
|
T77 |
5 |
|
T25 |
1 |
| auto[1] |
auto[0] |
auto[1] |
2801123 |
1 |
|
|
T21 |
2 |
|
T1 |
4 |
|
T2 |
1 |
| auto[1] |
auto[1] |
auto[0] |
1848962 |
1 |
|
|
T24 |
1 |
|
T9 |
3 |
|
T36 |
1 |
| auto[1] |
auto[1] |
auto[1] |
2786712 |
1 |
|
|
T21 |
1 |
|
T1 |
1 |
|
T24 |
1 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11511892 |
1 |
|
|
T22 |
1 |
|
T23 |
2 |
|
T19 |
6 |
| auto[1] |
9354392 |
1 |
|
|
T22 |
5 |
|
T19 |
6 |
|
T21 |
2 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
19658366 |
1 |
|
|
T22 |
5 |
|
T23 |
2 |
|
T19 |
12 |
| auto[1] |
1207918 |
1 |
|
|
T22 |
1 |
|
T21 |
1 |
|
T2 |
1 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11550729 |
1 |
|
|
T22 |
4 |
|
T23 |
2 |
|
T19 |
12 |
| auto[1] |
9315555 |
1 |
|
|
T22 |
2 |
|
T21 |
2 |
|
T1 |
3 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
4040170 |
1 |
|
|
T21 |
1 |
|
T1 |
1 |
|
T24 |
5 |
| auto[1] |
auto[0] |
auto[1] |
601977 |
1 |
|
|
T21 |
1 |
|
T24 |
1 |
|
T77 |
1 |
| auto[1] |
auto[1] |
auto[0] |
4067467 |
1 |
|
|
T22 |
1 |
|
T1 |
2 |
|
T11 |
1 |
| auto[1] |
auto[1] |
auto[1] |
605941 |
1 |
|
|
T22 |
1 |
|
T2 |
1 |
|
T24 |
3 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11539256 |
1 |
|
|
T22 |
1 |
|
T23 |
2 |
|
T19 |
3 |
| auto[1] |
9327028 |
1 |
|
|
T22 |
5 |
|
T19 |
9 |
|
T21 |
4 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
19658441 |
1 |
|
|
T22 |
5 |
|
T23 |
2 |
|
T19 |
12 |
| auto[1] |
1207843 |
1 |
|
|
T22 |
1 |
|
T21 |
2 |
|
T12 |
2 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11556627 |
1 |
|
|
T22 |
4 |
|
T23 |
2 |
|
T19 |
12 |
| auto[1] |
9309657 |
1 |
|
|
T22 |
2 |
|
T21 |
4 |
|
T1 |
2 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
4049904 |
1 |
|
|
T21 |
2 |
|
T1 |
1 |
|
T12 |
16 |
| auto[1] |
auto[0] |
auto[1] |
602851 |
1 |
|
|
T12 |
2 |
|
T24 |
1 |
|
T32 |
1 |
| auto[1] |
auto[1] |
auto[0] |
4051910 |
1 |
|
|
T22 |
1 |
|
T1 |
1 |
|
T24 |
4 |
| auto[1] |
auto[1] |
auto[1] |
604992 |
1 |
|
|
T22 |
1 |
|
T21 |
2 |
|
T24 |
2 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11531213 |
1 |
|
|
T22 |
1 |
|
T23 |
2 |
|
T19 |
9 |
| auto[1] |
9335071 |
1 |
|
|
T22 |
5 |
|
T19 |
3 |
|
T21 |
2 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
19660008 |
1 |
|
|
T22 |
5 |
|
T23 |
2 |
|
T19 |
12 |
| auto[1] |
1206276 |
1 |
|
|
T22 |
1 |
|
T12 |
2 |
|
T24 |
3 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11558276 |
1 |
|
|
T22 |
1 |
|
T23 |
2 |
|
T19 |
12 |
| auto[1] |
9308008 |
1 |
|
|
T22 |
5 |
|
T21 |
2 |
|
T1 |
2 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
4045394 |
1 |
|
|
T21 |
1 |
|
T1 |
2 |
|
T11 |
1 |
| auto[1] |
auto[0] |
auto[1] |
602048 |
1 |
|
|
T24 |
1 |
|
T35 |
1 |
|
T79 |
1 |
| auto[1] |
auto[1] |
auto[0] |
4056338 |
1 |
|
|
T22 |
4 |
|
T21 |
1 |
|
T12 |
16 |
| auto[1] |
auto[1] |
auto[1] |
604228 |
1 |
|
|
T22 |
1 |
|
T12 |
2 |
|
T24 |
2 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11507201 |
1 |
|
|
T22 |
2 |
|
T23 |
2 |
|
T19 |
7 |
| auto[1] |
9359083 |
1 |
|
|
T22 |
4 |
|
T19 |
5 |
|
T21 |
2 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
19649181 |
1 |
|
|
T22 |
6 |
|
T23 |
2 |
|
T19 |
12 |
| auto[1] |
1217103 |
1 |
|
|
T21 |
1 |
|
T24 |
1 |
|
T77 |
1 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11498034 |
1 |
|
|
T22 |
3 |
|
T23 |
2 |
|
T19 |
12 |
| auto[1] |
9368250 |
1 |
|
|
T22 |
3 |
|
T21 |
2 |
|
T12 |
18 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
4060590 |
1 |
|
|
T22 |
1 |
|
T24 |
8 |
|
T76 |
5 |
| auto[1] |
auto[0] |
auto[1] |
605634 |
1 |
|
|
T21 |
1 |
|
T77 |
1 |
|
T25 |
1 |
| auto[1] |
auto[1] |
auto[0] |
4090557 |
1 |
|
|
T22 |
2 |
|
T21 |
1 |
|
T12 |
18 |
| auto[1] |
auto[1] |
auto[1] |
611469 |
1 |
|
|
T24 |
1 |
|
T32 |
2 |
|
T36 |
2 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11503519 |
1 |
|
|
T22 |
1 |
|
T23 |
1 |
|
T19 |
9 |
| auto[1] |
9362765 |
1 |
|
|
T22 |
5 |
|
T23 |
1 |
|
T19 |
3 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
19647640 |
1 |
|
|
T22 |
6 |
|
T23 |
2 |
|
T19 |
12 |
| auto[1] |
1218644 |
1 |
|
|
T1 |
1 |
|
T12 |
5 |
|
T24 |
1 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11490185 |
1 |
|
|
T22 |
4 |
|
T23 |
2 |
|
T19 |
12 |
| auto[1] |
9376099 |
1 |
|
|
T22 |
2 |
|
T21 |
1 |
|
T1 |
2 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
4057181 |
1 |
|
|
T21 |
1 |
|
T1 |
1 |
|
T11 |
2 |
| auto[1] |
auto[0] |
auto[1] |
605695 |
1 |
|
|
T1 |
1 |
|
T12 |
5 |
|
T24 |
1 |
| auto[1] |
auto[1] |
auto[0] |
4100274 |
1 |
|
|
T22 |
2 |
|
T24 |
3 |
|
T76 |
3 |
| auto[1] |
auto[1] |
auto[1] |
612949 |
1 |
|
|
T105 |
1 |
|
T36 |
2 |
|
T104 |
1 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11544100 |
1 |
|
|
T22 |
2 |
|
T23 |
1 |
|
T19 |
11 |
| auto[1] |
9322184 |
1 |
|
|
T22 |
4 |
|
T23 |
1 |
|
T19 |
1 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
19654623 |
1 |
|
|
T22 |
5 |
|
T23 |
2 |
|
T19 |
12 |
| auto[1] |
1211661 |
1 |
|
|
T22 |
1 |
|
T21 |
1 |
|
T12 |
1 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11534613 |
1 |
|
|
T22 |
2 |
|
T23 |
2 |
|
T19 |
12 |
| auto[1] |
9331671 |
1 |
|
|
T22 |
4 |
|
T21 |
1 |
|
T1 |
3 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
4067731 |
1 |
|
|
T12 |
1 |
|
T24 |
10 |
|
T75 |
5 |
| auto[1] |
auto[0] |
auto[1] |
607709 |
1 |
|
|
T12 |
1 |
|
T24 |
2 |
|
T75 |
3 |
| auto[1] |
auto[1] |
auto[0] |
4052279 |
1 |
|
|
T22 |
3 |
|
T1 |
3 |
|
T12 |
7 |
| auto[1] |
auto[1] |
auto[1] |
603952 |
1 |
|
|
T22 |
1 |
|
T21 |
1 |
|
T24 |
1 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11583790 |
1 |
|
|
T22 |
1 |
|
T23 |
2 |
|
T19 |
3 |
| auto[1] |
9282494 |
1 |
|
|
T22 |
5 |
|
T19 |
9 |
|
T21 |
4 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
19655180 |
1 |
|
|
T22 |
6 |
|
T23 |
2 |
|
T19 |
12 |
| auto[1] |
1211104 |
1 |
|
|
T11 |
1 |
|
T12 |
2 |
|
T24 |
3 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11535840 |
1 |
|
|
T22 |
3 |
|
T23 |
2 |
|
T19 |
12 |
| auto[1] |
9330444 |
1 |
|
|
T22 |
3 |
|
T21 |
2 |
|
T11 |
3 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
4093486 |
1 |
|
|
T21 |
1 |
|
T11 |
2 |
|
T12 |
18 |
| auto[1] |
auto[0] |
auto[1] |
611237 |
1 |
|
|
T12 |
2 |
|
T24 |
2 |
|
T25 |
3 |
| auto[1] |
auto[1] |
auto[0] |
4025854 |
1 |
|
|
T22 |
3 |
|
T21 |
1 |
|
T24 |
2 |
| auto[1] |
auto[1] |
auto[1] |
599867 |
1 |
|
|
T11 |
1 |
|
T24 |
1 |
|
T32 |
1 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11559717 |
1 |
|
|
T22 |
2 |
|
T23 |
2 |
|
T19 |
4 |
| auto[1] |
9306567 |
1 |
|
|
T22 |
4 |
|
T19 |
8 |
|
T21 |
1 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
19650108 |
1 |
|
|
T22 |
6 |
|
T23 |
2 |
|
T19 |
12 |
| auto[1] |
1216176 |
1 |
|
|
T12 |
2 |
|
T24 |
4 |
|
T26 |
1 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11506345 |
1 |
|
|
T22 |
4 |
|
T23 |
2 |
|
T19 |
12 |
| auto[1] |
9359939 |
1 |
|
|
T22 |
2 |
|
T21 |
3 |
|
T11 |
1 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
4083956 |
1 |
|
|
T21 |
3 |
|
T12 |
9 |
|
T24 |
8 |
| auto[1] |
auto[0] |
auto[1] |
609636 |
1 |
|
|
T12 |
2 |
|
T24 |
3 |
|
T26 |
1 |
| auto[1] |
auto[1] |
auto[0] |
4059807 |
1 |
|
|
T22 |
2 |
|
T11 |
1 |
|
T24 |
2 |
| auto[1] |
auto[1] |
auto[1] |
606540 |
1 |
|
|
T24 |
1 |
|
T32 |
1 |
|
T42 |
1 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11509467 |
1 |
|
|
T22 |
5 |
|
T23 |
2 |
|
T19 |
9 |
| auto[1] |
9356817 |
1 |
|
|
T22 |
1 |
|
T19 |
3 |
|
T21 |
1 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
19658058 |
1 |
|
|
T22 |
5 |
|
T23 |
2 |
|
T19 |
12 |
| auto[1] |
1208226 |
1 |
|
|
T22 |
1 |
|
T21 |
1 |
|
T12 |
6 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11556563 |
1 |
|
|
T22 |
4 |
|
T23 |
2 |
|
T19 |
12 |
| auto[1] |
9309721 |
1 |
|
|
T22 |
2 |
|
T21 |
3 |
|
T11 |
3 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
4033387 |
1 |
|
|
T22 |
1 |
|
T21 |
2 |
|
T11 |
3 |
| auto[1] |
auto[0] |
auto[1] |
599910 |
1 |
|
|
T22 |
1 |
|
T21 |
1 |
|
T12 |
4 |
| auto[1] |
auto[1] |
auto[0] |
4068108 |
1 |
|
|
T12 |
5 |
|
T24 |
5 |
|
T6 |
2 |
| auto[1] |
auto[1] |
auto[1] |
608316 |
1 |
|
|
T12 |
2 |
|
T2 |
1 |
|
T25 |
1 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11462331 |
1 |
|
|
T22 |
2 |
|
T23 |
1 |
|
T19 |
3 |
| auto[1] |
9403953 |
1 |
|
|
T22 |
4 |
|
T23 |
1 |
|
T19 |
9 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
19660849 |
1 |
|
|
T22 |
6 |
|
T23 |
2 |
|
T19 |
12 |
| auto[1] |
1205435 |
1 |
|
|
T1 |
2 |
|
T24 |
3 |
|
T76 |
1 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11570348 |
1 |
|
|
T22 |
2 |
|
T23 |
2 |
|
T19 |
12 |
| auto[1] |
9295936 |
1 |
|
|
T22 |
4 |
|
T21 |
4 |
|
T1 |
5 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
4014298 |
1 |
|
|
T21 |
3 |
|
T11 |
1 |
|
T12 |
2 |
| auto[1] |
auto[0] |
auto[1] |
596739 |
1 |
|
|
T1 |
2 |
|
T24 |
3 |
|
T25 |
1 |
| auto[1] |
auto[1] |
auto[0] |
4076203 |
1 |
|
|
T22 |
4 |
|
T21 |
1 |
|
T1 |
3 |
| auto[1] |
auto[1] |
auto[1] |
608696 |
1 |
|
|
T76 |
1 |
|
T78 |
1 |
|
T18 |
1 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11531709 |
1 |
|
|
T22 |
2 |
|
T23 |
1 |
|
T19 |
11 |
| auto[1] |
9334575 |
1 |
|
|
T22 |
4 |
|
T23 |
1 |
|
T19 |
1 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
19653224 |
1 |
|
|
T22 |
6 |
|
T23 |
2 |
|
T19 |
12 |
| auto[1] |
1213060 |
1 |
|
|
T11 |
1 |
|
T2 |
1 |
|
T24 |
4 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11515943 |
1 |
|
|
T22 |
2 |
|
T23 |
2 |
|
T19 |
12 |
| auto[1] |
9350341 |
1 |
|
|
T22 |
4 |
|
T1 |
2 |
|
T11 |
3 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
4070925 |
1 |
|
|
T12 |
7 |
|
T24 |
7 |
|
T26 |
1 |
| auto[1] |
auto[0] |
auto[1] |
606383 |
1 |
|
|
T11 |
1 |
|
T24 |
4 |
|
T25 |
2 |
| auto[1] |
auto[1] |
auto[0] |
4066356 |
1 |
|
|
T22 |
4 |
|
T1 |
2 |
|
T11 |
2 |
| auto[1] |
auto[1] |
auto[1] |
606677 |
1 |
|
|
T2 |
1 |
|
T25 |
1 |
|
T36 |
2 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11560382 |
1 |
|
|
T22 |
1 |
|
T23 |
2 |
|
T19 |
11 |
| auto[1] |
9305902 |
1 |
|
|
T22 |
5 |
|
T19 |
1 |
|
T21 |
1 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
19665297 |
1 |
|
|
T22 |
4 |
|
T23 |
2 |
|
T19 |
12 |
| auto[1] |
1200987 |
1 |
|
|
T22 |
2 |
|
T21 |
1 |
|
T12 |
3 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11597728 |
1 |
|
|
T22 |
1 |
|
T23 |
2 |
|
T19 |
12 |
| auto[1] |
9268556 |
1 |
|
|
T22 |
5 |
|
T21 |
2 |
|
T1 |
3 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
4035660 |
1 |
|
|
T21 |
1 |
|
T12 |
17 |
|
T24 |
5 |
| auto[1] |
auto[0] |
auto[1] |
601746 |
1 |
|
|
T21 |
1 |
|
T12 |
3 |
|
T24 |
3 |
| auto[1] |
auto[1] |
auto[0] |
4031909 |
1 |
|
|
T22 |
3 |
|
T1 |
3 |
|
T11 |
2 |
| auto[1] |
auto[1] |
auto[1] |
599241 |
1 |
|
|
T22 |
2 |
|
T75 |
1 |
|
T25 |
1 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11531349 |
1 |
|
|
T22 |
1 |
|
T23 |
2 |
|
T19 |
8 |
| auto[1] |
9334935 |
1 |
|
|
T22 |
5 |
|
T19 |
4 |
|
T21 |
3 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
19658295 |
1 |
|
|
T22 |
5 |
|
T23 |
2 |
|
T19 |
12 |
| auto[1] |
1207989 |
1 |
|
|
T22 |
1 |
|
T21 |
2 |
|
T1 |
1 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11552637 |
1 |
|
|
T22 |
3 |
|
T23 |
2 |
|
T19 |
12 |
| auto[1] |
9313647 |
1 |
|
|
T22 |
3 |
|
T21 |
3 |
|
T1 |
2 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
4082690 |
1 |
|
|
T2 |
1 |
|
T24 |
6 |
|
T76 |
4 |
| auto[1] |
auto[0] |
auto[1] |
609816 |
1 |
|
|
T21 |
2 |
|
T24 |
1 |
|
T76 |
1 |
| auto[1] |
auto[1] |
auto[0] |
4022968 |
1 |
|
|
T22 |
2 |
|
T21 |
1 |
|
T1 |
1 |
| auto[1] |
auto[1] |
auto[1] |
598173 |
1 |
|
|
T22 |
1 |
|
T1 |
1 |
|
T12 |
4 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11553906 |
1 |
|
|
T22 |
2 |
|
T23 |
1 |
|
T19 |
3 |
| auto[1] |
9312378 |
1 |
|
|
T22 |
4 |
|
T23 |
1 |
|
T19 |
9 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
19650803 |
1 |
|
|
T22 |
6 |
|
T23 |
2 |
|
T19 |
12 |
| auto[1] |
1215481 |
1 |
|
|
T1 |
1 |
|
T24 |
2 |
|
T75 |
1 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11505450 |
1 |
|
|
T22 |
6 |
|
T23 |
2 |
|
T19 |
12 |
| auto[1] |
9360834 |
1 |
|
|
T21 |
1 |
|
T1 |
2 |
|
T11 |
1 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
4085486 |
1 |
|
|
T21 |
1 |
|
T1 |
1 |
|
T12 |
11 |
| auto[1] |
auto[0] |
auto[1] |
611037 |
1 |
|
|
T1 |
1 |
|
T24 |
1 |
|
T75 |
1 |
| auto[1] |
auto[1] |
auto[0] |
4059867 |
1 |
|
|
T11 |
1 |
|
T24 |
2 |
|
T76 |
3 |
| auto[1] |
auto[1] |
auto[1] |
604444 |
1 |
|
|
T24 |
1 |
|
T39 |
6059 |
|
T98 |
4 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |