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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
99.61 99.06 99.10 100.00 99.80 99.68 100.00


Total test records in report: 970
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T767 /workspace/coverage/default/37.gpio_stress_all.2449709434 Dec 27 01:23:55 PM PST 23 Dec 27 01:26:46 PM PST 23 6325337834 ps
T768 /workspace/coverage/default/45.gpio_dout_din_regs_random_rw.750145669 Dec 27 01:24:23 PM PST 23 Dec 27 01:24:24 PM PST 23 132254198 ps
T769 /workspace/coverage/default/43.gpio_smoke.1586371669 Dec 27 01:24:36 PM PST 23 Dec 27 01:24:38 PM PST 23 341057599 ps
T770 /workspace/coverage/default/25.gpio_filter_stress.4198614721 Dec 27 01:24:48 PM PST 23 Dec 27 01:25:16 PM PST 23 2039867123 ps
T771 /workspace/coverage/default/9.gpio_random_long_reg_writes_reg_reads.3492821328 Dec 27 01:22:08 PM PST 23 Dec 27 01:22:18 PM PST 23 717242252 ps
T772 /workspace/coverage/default/26.gpio_random_dout_din.3407628469 Dec 27 01:24:49 PM PST 23 Dec 27 01:24:52 PM PST 23 406310098 ps
T773 /workspace/coverage/default/30.gpio_filter_stress.2217303075 Dec 27 01:24:16 PM PST 23 Dec 27 01:24:26 PM PST 23 659574726 ps
T774 /workspace/coverage/default/8.gpio_smoke_no_pullup_pulldown.791560986 Dec 27 01:22:26 PM PST 23 Dec 27 01:22:29 PM PST 23 139468394 ps
T775 /workspace/coverage/default/33.gpio_intr_rand_pgm.3648488853 Dec 27 01:23:51 PM PST 23 Dec 27 01:23:53 PM PST 23 83573107 ps
T776 /workspace/coverage/default/1.gpio_random_dout_din.2905170074 Dec 27 01:21:19 PM PST 23 Dec 27 01:21:21 PM PST 23 73098577 ps
T777 /workspace/coverage/default/48.gpio_random_dout_din_no_pullup_pulldown.97689702 Dec 27 01:25:07 PM PST 23 Dec 27 01:25:11 PM PST 23 62131443 ps
T778 /workspace/coverage/default/8.gpio_intr_with_filter_rand_intr_event.505568030 Dec 27 01:23:19 PM PST 23 Dec 27 01:23:21 PM PST 23 75613802 ps
T779 /workspace/coverage/default/13.gpio_smoke_no_pullup_pulldown.2613015929 Dec 27 01:24:18 PM PST 23 Dec 27 01:24:21 PM PST 23 37976432 ps
T780 /workspace/coverage/default/39.gpio_random_dout_din.227755619 Dec 27 01:24:26 PM PST 23 Dec 27 01:24:28 PM PST 23 33713183 ps
T781 /workspace/coverage/default/32.gpio_smoke_no_pullup_pulldown.404921723 Dec 27 01:23:53 PM PST 23 Dec 27 01:23:55 PM PST 23 21878881 ps
T782 /workspace/coverage/default/14.gpio_stress_all.3310617308 Dec 27 01:22:30 PM PST 23 Dec 27 01:23:59 PM PST 23 25640444650 ps
T783 /workspace/coverage/default/3.gpio_random_long_reg_writes_reg_reads.1816554136 Dec 27 01:21:52 PM PST 23 Dec 27 01:21:57 PM PST 23 109798665 ps
T784 /workspace/coverage/default/7.gpio_intr_rand_pgm.815165786 Dec 27 01:22:06 PM PST 23 Dec 27 01:22:08 PM PST 23 129150190 ps
T62 /workspace/coverage/default/3.gpio_sec_cm.2848590741 Dec 27 01:21:11 PM PST 23 Dec 27 01:21:13 PM PST 23 247729840 ps
T785 /workspace/coverage/default/35.gpio_smoke.2030172337 Dec 27 01:24:47 PM PST 23 Dec 27 01:24:51 PM PST 23 26048507 ps
T786 /workspace/coverage/default/26.gpio_rand_intr_trigger.492420401 Dec 27 01:24:55 PM PST 23 Dec 27 01:24:58 PM PST 23 87254734 ps
T787 /workspace/coverage/default/25.gpio_stress_all.2684492399 Dec 27 01:24:40 PM PST 23 Dec 27 01:27:32 PM PST 23 23812453032 ps
T788 /workspace/coverage/default/35.gpio_stress_all.885828464 Dec 27 01:25:05 PM PST 23 Dec 27 01:27:16 PM PST 23 37405057057 ps
T789 /workspace/coverage/default/5.gpio_rand_intr_trigger.2572442998 Dec 27 01:21:17 PM PST 23 Dec 27 01:21:19 PM PST 23 108880067 ps
T790 /workspace/coverage/default/27.gpio_stress_all_with_rand_reset.3375831627 Dec 27 01:25:09 PM PST 23 Dec 27 01:51:55 PM PST 23 102132302169 ps
T791 /workspace/coverage/default/23.gpio_smoke_no_pullup_pulldown.2950953636 Dec 27 01:23:56 PM PST 23 Dec 27 01:23:58 PM PST 23 276331422 ps
T792 /workspace/coverage/default/35.gpio_alert_test.3088676048 Dec 27 01:25:07 PM PST 23 Dec 27 01:25:11 PM PST 23 12961332 ps
T793 /workspace/coverage/default/0.gpio_full_random.3772469056 Dec 27 01:22:30 PM PST 23 Dec 27 01:22:35 PM PST 23 118319347 ps
T794 /workspace/coverage/default/44.gpio_smoke.1598063889 Dec 27 01:24:10 PM PST 23 Dec 27 01:24:12 PM PST 23 38608261 ps
T795 /workspace/coverage/default/14.gpio_dout_din_regs_random_rw.358996968 Dec 27 01:22:45 PM PST 23 Dec 27 01:22:47 PM PST 23 104839083 ps
T796 /workspace/coverage/default/4.gpio_random_dout_din_no_pullup_pulldown.2795378965 Dec 27 01:21:18 PM PST 23 Dec 27 01:21:19 PM PST 23 105239549 ps
T797 /workspace/coverage/default/36.gpio_random_dout_din_no_pullup_pulldown.2565539337 Dec 27 01:24:49 PM PST 23 Dec 27 01:24:52 PM PST 23 241332970 ps
T798 /workspace/coverage/default/0.gpio_alert_test.3544765269 Dec 27 01:22:08 PM PST 23 Dec 27 01:22:13 PM PST 23 32279839 ps
T799 /workspace/coverage/default/46.gpio_dout_din_regs_random_rw.1592618408 Dec 27 01:24:14 PM PST 23 Dec 27 01:24:15 PM PST 23 48554836 ps
T800 /workspace/coverage/default/45.gpio_full_random.3344399745 Dec 27 01:24:45 PM PST 23 Dec 27 01:24:51 PM PST 23 43689344 ps
T801 /workspace/coverage/default/15.gpio_filter_stress.2321557890 Dec 27 01:23:16 PM PST 23 Dec 27 01:23:30 PM PST 23 1103663119 ps
T802 /workspace/coverage/default/15.gpio_intr_with_filter_rand_intr_event.570047163 Dec 27 01:22:58 PM PST 23 Dec 27 01:23:01 PM PST 23 126875093 ps
T803 /workspace/coverage/default/41.gpio_alert_test.874332692 Dec 27 01:25:09 PM PST 23 Dec 27 01:25:12 PM PST 23 41710550 ps
T804 /workspace/coverage/default/22.gpio_rand_intr_trigger.3156266725 Dec 27 01:24:15 PM PST 23 Dec 27 01:24:18 PM PST 23 54295867 ps
T805 /workspace/coverage/default/17.gpio_filter_stress.4013445959 Dec 27 01:23:19 PM PST 23 Dec 27 01:23:39 PM PST 23 2272010657 ps
T806 /workspace/coverage/default/46.gpio_alert_test.1848348029 Dec 27 01:24:31 PM PST 23 Dec 27 01:24:33 PM PST 23 43020782 ps
T807 /workspace/coverage/default/44.gpio_random_dout_din_no_pullup_pulldown.2034259913 Dec 27 01:24:17 PM PST 23 Dec 27 01:24:19 PM PST 23 26079947 ps
T808 /workspace/coverage/default/31.gpio_intr_with_filter_rand_intr_event.1887415371 Dec 27 01:23:46 PM PST 23 Dec 27 01:23:48 PM PST 23 60503242 ps
T809 /workspace/coverage/default/4.gpio_intr_rand_pgm.4012778702 Dec 27 01:21:24 PM PST 23 Dec 27 01:21:26 PM PST 23 85200804 ps
T810 /workspace/coverage/default/18.gpio_intr_rand_pgm.3073093014 Dec 27 01:23:18 PM PST 23 Dec 27 01:23:19 PM PST 23 20862580 ps
T811 /workspace/coverage/default/5.gpio_intr_with_filter_rand_intr_event.2004931145 Dec 27 01:21:17 PM PST 23 Dec 27 01:21:21 PM PST 23 326189887 ps
T812 /workspace/coverage/default/23.gpio_stress_all_with_rand_reset.1810211174 Dec 27 01:24:28 PM PST 23 Dec 27 01:34:34 PM PST 23 232152507972 ps
T813 /workspace/coverage/default/30.gpio_full_random.3188288795 Dec 27 01:23:46 PM PST 23 Dec 27 01:23:47 PM PST 23 132398533 ps
T814 /workspace/coverage/default/28.gpio_smoke.3533304439 Dec 27 01:25:15 PM PST 23 Dec 27 01:25:17 PM PST 23 76157039 ps
T815 /workspace/coverage/default/7.gpio_smoke_no_pullup_pulldown.2369447997 Dec 27 01:21:31 PM PST 23 Dec 27 01:21:33 PM PST 23 116473432 ps
T816 /workspace/coverage/default/23.gpio_full_random.1916569943 Dec 27 01:24:51 PM PST 23 Dec 27 01:24:54 PM PST 23 113507839 ps
T817 /workspace/coverage/default/5.gpio_full_random.1086701155 Dec 27 01:22:00 PM PST 23 Dec 27 01:22:01 PM PST 23 154504061 ps
T818 /workspace/coverage/default/34.gpio_intr_rand_pgm.1071352510 Dec 27 01:23:54 PM PST 23 Dec 27 01:23:57 PM PST 23 60972167 ps
T819 /workspace/coverage/default/11.gpio_smoke_no_pullup_pulldown.3149146491 Dec 27 01:22:29 PM PST 23 Dec 27 01:22:31 PM PST 23 86739495 ps
T820 /workspace/coverage/default/38.gpio_stress_all.947916061 Dec 27 01:23:48 PM PST 23 Dec 27 01:25:20 PM PST 23 7759120787 ps
T821 /workspace/coverage/default/2.gpio_smoke.2259853422 Dec 27 01:21:18 PM PST 23 Dec 27 01:21:20 PM PST 23 64773635 ps
T822 /workspace/coverage/default/9.gpio_random_dout_din.973618490 Dec 27 01:22:06 PM PST 23 Dec 27 01:22:08 PM PST 23 73520710 ps
T823 /workspace/coverage/default/28.gpio_rand_intr_trigger.1196709260 Dec 27 01:23:30 PM PST 23 Dec 27 01:23:33 PM PST 23 850891118 ps
T824 /workspace/coverage/default/20.gpio_rand_intr_trigger.3869469518 Dec 27 01:23:52 PM PST 23 Dec 27 01:23:55 PM PST 23 91361431 ps
T825 /workspace/coverage/default/8.gpio_filter_stress.1980290934 Dec 27 01:21:50 PM PST 23 Dec 27 01:22:13 PM PST 23 437423036 ps
T826 /workspace/coverage/default/48.gpio_smoke.2609105517 Dec 27 01:25:05 PM PST 23 Dec 27 01:25:10 PM PST 23 111635613 ps
T827 /workspace/coverage/default/38.gpio_full_random.2987381813 Dec 27 01:24:16 PM PST 23 Dec 27 01:24:18 PM PST 23 273462592 ps
T828 /workspace/coverage/default/23.gpio_filter_stress.74683004 Dec 27 01:24:48 PM PST 23 Dec 27 01:25:12 PM PST 23 2385883688 ps
T829 /workspace/coverage/default/32.gpio_smoke.2786196351 Dec 27 01:23:52 PM PST 23 Dec 27 01:23:55 PM PST 23 111946827 ps
T830 /workspace/coverage/default/35.gpio_random_long_reg_writes_reg_reads.1455551509 Dec 27 01:24:47 PM PST 23 Dec 27 01:24:53 PM PST 23 425309781 ps
T831 /workspace/coverage/default/37.gpio_intr_rand_pgm.1966534479 Dec 27 01:24:15 PM PST 23 Dec 27 01:24:17 PM PST 23 174917542 ps
T832 /workspace/coverage/default/9.gpio_stress_all_with_rand_reset.3391720423 Dec 27 01:21:56 PM PST 23 Dec 27 01:34:52 PM PST 23 474788783752 ps
T833 /workspace/coverage/default/48.gpio_stress_all_with_rand_reset.1689184245 Dec 27 01:26:01 PM PST 23 Dec 27 01:35:20 PM PST 23 68746381189 ps
T834 /workspace/coverage/default/36.gpio_rand_intr_trigger.2800051680 Dec 27 01:24:17 PM PST 23 Dec 27 01:24:21 PM PST 23 371182885 ps
T835 /workspace/coverage/default/47.gpio_smoke_no_pullup_pulldown.1099043282 Dec 27 01:25:08 PM PST 23 Dec 27 01:25:12 PM PST 23 188747513 ps
T836 /workspace/coverage/default/29.gpio_intr_rand_pgm.4065831688 Dec 27 01:23:52 PM PST 23 Dec 27 01:23:54 PM PST 23 173924982 ps
T837 /workspace/coverage/default/48.gpio_smoke_no_pullup_pulldown.167202318 Dec 27 01:24:40 PM PST 23 Dec 27 01:24:43 PM PST 23 36940899 ps
T838 /workspace/coverage/default/36.gpio_intr_with_filter_rand_intr_event.669993347 Dec 27 01:23:55 PM PST 23 Dec 27 01:23:59 PM PST 23 184970075 ps
T839 /workspace/coverage/default/1.gpio_random_long_reg_writes_reg_reads.1797015227 Dec 27 01:21:18 PM PST 23 Dec 27 01:21:22 PM PST 23 204123124 ps
T840 /workspace/coverage/default/20.gpio_intr_with_filter_rand_intr_event.870204082 Dec 27 01:23:56 PM PST 23 Dec 27 01:24:01 PM PST 23 164925346 ps
T841 /workspace/coverage/default/40.gpio_intr_rand_pgm.1066515948 Dec 27 01:24:31 PM PST 23 Dec 27 01:24:33 PM PST 23 1495568429 ps
T842 /workspace/coverage/default/10.gpio_full_random.3565996785 Dec 27 01:22:52 PM PST 23 Dec 27 01:22:53 PM PST 23 58325965 ps
T843 /workspace/coverage/default/35.gpio_random_dout_din_no_pullup_pulldown.2578131638 Dec 27 01:25:03 PM PST 23 Dec 27 01:25:05 PM PST 23 21196634 ps
T844 /workspace/coverage/default/36.gpio_random_dout_din.1826676723 Dec 27 01:25:06 PM PST 23 Dec 27 01:25:11 PM PST 23 18770996 ps
T845 /workspace/coverage/default/35.gpio_dout_din_regs_random_rw.643959884 Dec 27 01:24:50 PM PST 23 Dec 27 01:24:54 PM PST 23 123180900 ps
T846 /workspace/coverage/default/39.gpio_filter_stress.1512121629 Dec 27 01:23:55 PM PST 23 Dec 27 01:24:03 PM PST 23 120293580 ps
T847 /workspace/coverage/default/40.gpio_smoke_no_pullup_pulldown.2838717719 Dec 27 01:23:56 PM PST 23 Dec 27 01:23:58 PM PST 23 244139204 ps
T848 /workspace/coverage/default/1.gpio_alert_test.514242287 Dec 27 01:21:56 PM PST 23 Dec 27 01:21:57 PM PST 23 127907443 ps
T849 /workspace/coverage/default/49.gpio_smoke_no_pullup_pulldown.2903260546 Dec 27 01:25:08 PM PST 23 Dec 27 01:25:12 PM PST 23 57809882 ps
T850 /workspace/coverage/default/19.gpio_filter_stress.706558965 Dec 27 01:23:28 PM PST 23 Dec 27 01:23:52 PM PST 23 482126390 ps
T851 /workspace/coverage/default/7.gpio_rand_intr_trigger.300289324 Dec 27 01:21:49 PM PST 23 Dec 27 01:21:51 PM PST 23 70481916 ps
T852 /workspace/coverage/default/39.gpio_random_dout_din_no_pullup_pulldown.2449836448 Dec 27 01:24:27 PM PST 23 Dec 27 01:24:29 PM PST 23 78370542 ps
T853 /workspace/coverage/default/4.gpio_alert_test.3601319627 Dec 27 01:22:29 PM PST 23 Dec 27 01:22:31 PM PST 23 42057630 ps
T854 /workspace/coverage/default/24.gpio_stress_all_with_rand_reset.2467800554 Dec 27 01:23:51 PM PST 23 Dec 27 01:27:24 PM PST 23 12732249194 ps
T855 /workspace/coverage/default/26.gpio_smoke.265693358 Dec 27 01:24:50 PM PST 23 Dec 27 01:24:54 PM PST 23 89589968 ps
T856 /workspace/coverage/default/7.gpio_full_random.3873725825 Dec 27 01:22:09 PM PST 23 Dec 27 01:22:17 PM PST 23 94902578 ps
T857 /workspace/coverage/default/27.gpio_smoke.1148891090 Dec 27 01:24:10 PM PST 23 Dec 27 01:24:12 PM PST 23 275783947 ps
T858 /workspace/coverage/default/30.gpio_smoke.2225945548 Dec 27 01:24:29 PM PST 23 Dec 27 01:24:30 PM PST 23 233595043 ps
T859 /workspace/coverage/default/0.gpio_smoke_no_pullup_pulldown.265926261 Dec 27 01:21:17 PM PST 23 Dec 27 01:21:19 PM PST 23 179720275 ps
T860 /workspace/coverage/default/27.gpio_rand_intr_trigger.1159405147 Dec 27 01:25:02 PM PST 23 Dec 27 01:25:06 PM PST 23 500242897 ps
T861 /workspace/coverage/default/29.gpio_intr_with_filter_rand_intr_event.544320039 Dec 27 01:23:50 PM PST 23 Dec 27 01:23:52 PM PST 23 37407618 ps
T862 /workspace/coverage/default/42.gpio_random_dout_din.2700193365 Dec 27 01:23:50 PM PST 23 Dec 27 01:23:52 PM PST 23 129112144 ps
T863 /workspace/coverage/default/10.gpio_rand_intr_trigger.3732661343 Dec 27 01:22:05 PM PST 23 Dec 27 01:22:07 PM PST 23 131111843 ps
T864 /workspace/coverage/default/12.gpio_smoke.13792779 Dec 27 01:22:51 PM PST 23 Dec 27 01:22:53 PM PST 23 137126352 ps
T865 /workspace/coverage/default/28.gpio_intr_with_filter_rand_intr_event.1535339104 Dec 27 01:23:48 PM PST 23 Dec 27 01:23:51 PM PST 23 73702724 ps
T866 /workspace/coverage/default/6.gpio_random_dout_din.3366683014 Dec 27 01:22:01 PM PST 23 Dec 27 01:22:03 PM PST 23 166349863 ps
T867 /workspace/coverage/default/25.gpio_stress_all_with_rand_reset.384597975 Dec 27 01:24:34 PM PST 23 Dec 27 01:48:25 PM PST 23 238249208912 ps
T868 /workspace/coverage/default/47.gpio_alert_test.2232617041 Dec 27 01:24:52 PM PST 23 Dec 27 01:24:54 PM PST 23 12353221 ps
T869 /workspace/coverage/default/42.gpio_stress_all.3066158464 Dec 27 01:24:11 PM PST 23 Dec 27 01:25:42 PM PST 23 10812011627 ps
T870 /workspace/coverage/default/18.gpio_smoke_no_pullup_pulldown.2798414265 Dec 27 01:22:54 PM PST 23 Dec 27 01:22:56 PM PST 23 567850267 ps
T871 /workspace/coverage/default/8.gpio_random_dout_din_no_pullup_pulldown.1415201589 Dec 27 01:22:30 PM PST 23 Dec 27 01:22:36 PM PST 23 26060257 ps
T872 /workspace/coverage/default/44.gpio_intr_rand_pgm.674767372 Dec 27 01:24:42 PM PST 23 Dec 27 01:24:45 PM PST 23 78515404 ps
T873 /workspace/coverage/default/26.gpio_intr_rand_pgm.1097850796 Dec 27 01:24:28 PM PST 23 Dec 27 01:24:30 PM PST 23 551967240 ps
T874 /workspace/coverage/default/46.gpio_smoke_no_pullup_pulldown.1985503230 Dec 27 01:24:18 PM PST 23 Dec 27 01:24:20 PM PST 23 89043532 ps
T875 /workspace/coverage/default/28.gpio_filter_stress.97246707 Dec 27 01:23:52 PM PST 23 Dec 27 01:24:07 PM PST 23 239535181 ps
T876 /workspace/coverage/default/32.gpio_alert_test.4060694209 Dec 27 01:23:49 PM PST 23 Dec 27 01:23:51 PM PST 23 47433154 ps
T877 /workspace/coverage/default/18.gpio_full_random.3761929250 Dec 27 01:22:54 PM PST 23 Dec 27 01:22:56 PM PST 23 233972579 ps
T878 /workspace/coverage/default/16.gpio_stress_all.108174147 Dec 27 01:22:51 PM PST 23 Dec 27 01:24:52 PM PST 23 11979747455 ps
T879 /workspace/coverage/default/0.gpio_filter_stress.2661246529 Dec 27 01:22:04 PM PST 23 Dec 27 01:22:26 PM PST 23 3759073409 ps
T880 /workspace/coverage/default/34.gpio_alert_test.86403462 Dec 27 01:24:49 PM PST 23 Dec 27 01:24:52 PM PST 23 15150850 ps
T881 /workspace/coverage/default/31.gpio_random_dout_din.956954103 Dec 27 01:24:11 PM PST 23 Dec 27 01:24:13 PM PST 23 82894234 ps
T882 /workspace/coverage/default/38.gpio_stress_all_with_rand_reset.1669117157 Dec 27 01:23:51 PM PST 23 Dec 27 01:34:48 PM PST 23 118552902421 ps
T883 /workspace/coverage/default/26.gpio_filter_stress.978356764 Dec 27 01:23:48 PM PST 23 Dec 27 01:24:04 PM PST 23 822804926 ps
T884 /workspace/coverage/default/9.gpio_full_random.1799242285 Dec 27 01:22:05 PM PST 23 Dec 27 01:22:06 PM PST 23 191227948 ps
T885 /workspace/coverage/default/48.gpio_dout_din_regs_random_rw.2957903139 Dec 27 01:24:49 PM PST 23 Dec 27 01:24:52 PM PST 23 103386612 ps
T886 /workspace/coverage/default/28.gpio_dout_din_regs_random_rw.424786099 Dec 27 01:23:51 PM PST 23 Dec 27 01:23:54 PM PST 23 29835366 ps
T887 /workspace/coverage/default/11.gpio_random_dout_din.757797215 Dec 27 01:22:54 PM PST 23 Dec 27 01:22:57 PM PST 23 284162130 ps
T888 /workspace/coverage/default/18.gpio_random_dout_din_no_pullup_pulldown.1574314434 Dec 27 01:22:53 PM PST 23 Dec 27 01:22:55 PM PST 23 33976080 ps
T889 /workspace/coverage/default/7.gpio_random_long_reg_writes_reg_reads.2847349173 Dec 27 01:22:11 PM PST 23 Dec 27 01:22:15 PM PST 23 487434701 ps
T890 /workspace/coverage/default/20.gpio_stress_all.3547894016 Dec 27 01:23:53 PM PST 23 Dec 27 01:26:15 PM PST 23 25514190994 ps
T891 /workspace/coverage/cover_reg_top/24.gpio_intr_test.662237392 Dec 27 12:32:08 PM PST 23 Dec 27 12:32:53 PM PST 23 52765772 ps
T91 /workspace/coverage/cover_reg_top/4.gpio_csr_aliasing.3040983254 Dec 27 12:32:41 PM PST 23 Dec 27 12:33:19 PM PST 23 16949986 ps
T892 /workspace/coverage/cover_reg_top/9.gpio_tl_errors.2327895807 Dec 27 12:32:07 PM PST 23 Dec 27 12:32:53 PM PST 23 51201231 ps
T92 /workspace/coverage/cover_reg_top/3.gpio_same_csr_outstanding.3147556441 Dec 27 12:32:44 PM PST 23 Dec 27 12:33:21 PM PST 23 18589075 ps
T893 /workspace/coverage/cover_reg_top/4.gpio_csr_mem_rw_with_rand_reset.2109482453 Dec 27 12:31:59 PM PST 23 Dec 27 12:32:45 PM PST 23 17051847 ps
T894 /workspace/coverage/cover_reg_top/8.gpio_csr_rw.2391229359 Dec 27 12:31:48 PM PST 23 Dec 27 12:32:37 PM PST 23 15560406 ps
T895 /workspace/coverage/cover_reg_top/5.gpio_intr_test.420788843 Dec 27 12:32:09 PM PST 23 Dec 27 12:32:53 PM PST 23 42830872 ps
T896 /workspace/coverage/cover_reg_top/5.gpio_csr_rw.596769558 Dec 27 12:32:06 PM PST 23 Dec 27 12:32:51 PM PST 23 35153285 ps
T897 /workspace/coverage/cover_reg_top/18.gpio_csr_rw.3374340505 Dec 27 12:31:49 PM PST 23 Dec 27 12:32:37 PM PST 23 173066728 ps
T93 /workspace/coverage/cover_reg_top/17.gpio_same_csr_outstanding.706597359 Dec 27 12:32:00 PM PST 23 Dec 27 12:32:46 PM PST 23 17910778 ps
T898 /workspace/coverage/cover_reg_top/45.gpio_intr_test.1646974391 Dec 27 12:32:05 PM PST 23 Dec 27 12:32:50 PM PST 23 202832427 ps
T40 /workspace/coverage/cover_reg_top/12.gpio_tl_intg_err.343112703 Dec 27 12:31:54 PM PST 23 Dec 27 12:32:40 PM PST 23 163098670 ps
T899 /workspace/coverage/cover_reg_top/47.gpio_intr_test.3954941768 Dec 27 12:32:42 PM PST 23 Dec 27 12:33:20 PM PST 23 38242954 ps
T94 /workspace/coverage/cover_reg_top/10.gpio_same_csr_outstanding.3489432205 Dec 27 12:31:42 PM PST 23 Dec 27 12:32:32 PM PST 23 166433753 ps
T900 /workspace/coverage/cover_reg_top/8.gpio_tl_intg_err.2191331748 Dec 27 12:32:00 PM PST 23 Dec 27 12:32:46 PM PST 23 67005441 ps
T901 /workspace/coverage/cover_reg_top/1.gpio_tl_errors.1248401834 Dec 27 12:32:15 PM PST 23 Dec 27 12:33:01 PM PST 23 277790884 ps
T86 /workspace/coverage/cover_reg_top/1.gpio_csr_rw.1324895261 Dec 27 12:34:46 PM PST 23 Dec 27 12:35:06 PM PST 23 14369039 ps
T902 /workspace/coverage/cover_reg_top/4.gpio_intr_test.1941092112 Dec 27 12:32:16 PM PST 23 Dec 27 12:33:00 PM PST 23 32258167 ps
T903 /workspace/coverage/cover_reg_top/3.gpio_intr_test.718288101 Dec 27 12:32:20 PM PST 23 Dec 27 12:33:03 PM PST 23 17721580 ps
T904 /workspace/coverage/cover_reg_top/33.gpio_intr_test.2639521206 Dec 27 12:31:53 PM PST 23 Dec 27 12:32:40 PM PST 23 13026417 ps
T905 /workspace/coverage/cover_reg_top/8.gpio_tl_errors.1582709334 Dec 27 12:32:01 PM PST 23 Dec 27 12:32:48 PM PST 23 135441822 ps
T906 /workspace/coverage/cover_reg_top/11.gpio_tl_errors.414449130 Dec 27 12:32:02 PM PST 23 Dec 27 12:32:50 PM PST 23 141760412 ps
T33 /workspace/coverage/cover_reg_top/11.gpio_tl_intg_err.147734356 Dec 27 12:32:06 PM PST 23 Dec 27 12:32:52 PM PST 23 481551677 ps
T907 /workspace/coverage/cover_reg_top/2.gpio_tl_intg_err.1011760921 Dec 27 12:32:48 PM PST 23 Dec 27 12:33:24 PM PST 23 182540120 ps
T908 /workspace/coverage/cover_reg_top/13.gpio_tl_errors.1038037063 Dec 27 12:31:52 PM PST 23 Dec 27 12:32:40 PM PST 23 227980334 ps
T909 /workspace/coverage/cover_reg_top/5.gpio_tl_errors.444535167 Dec 27 12:31:52 PM PST 23 Dec 27 12:32:40 PM PST 23 61526142 ps
T95 /workspace/coverage/cover_reg_top/8.gpio_same_csr_outstanding.3967283704 Dec 27 12:32:13 PM PST 23 Dec 27 12:32:58 PM PST 23 230831056 ps
T910 /workspace/coverage/cover_reg_top/21.gpio_intr_test.75730014 Dec 27 12:32:32 PM PST 23 Dec 27 12:33:13 PM PST 23 29204347 ps
T911 /workspace/coverage/cover_reg_top/12.gpio_csr_mem_rw_with_rand_reset.2338507607 Dec 27 12:32:07 PM PST 23 Dec 27 12:32:53 PM PST 23 19157185 ps
T96 /workspace/coverage/cover_reg_top/4.gpio_same_csr_outstanding.3015099783 Dec 27 12:32:01 PM PST 23 Dec 27 12:32:47 PM PST 23 55792945 ps
T912 /workspace/coverage/cover_reg_top/15.gpio_tl_errors.3113661260 Dec 27 12:32:08 PM PST 23 Dec 27 12:32:55 PM PST 23 391696304 ps
T87 /workspace/coverage/cover_reg_top/1.gpio_csr_aliasing.2950285178 Dec 27 12:32:02 PM PST 23 Dec 27 12:32:48 PM PST 23 116355103 ps
T913 /workspace/coverage/cover_reg_top/8.gpio_csr_mem_rw_with_rand_reset.49916614 Dec 27 12:31:54 PM PST 23 Dec 27 12:32:41 PM PST 23 137782765 ps
T914 /workspace/coverage/cover_reg_top/1.gpio_csr_bit_bash.2445282199 Dec 27 12:32:08 PM PST 23 Dec 27 12:32:55 PM PST 23 210586161 ps
T915 /workspace/coverage/cover_reg_top/19.gpio_same_csr_outstanding.1659171322 Dec 27 12:31:53 PM PST 23 Dec 27 12:32:40 PM PST 23 153590759 ps
T916 /workspace/coverage/cover_reg_top/2.gpio_csr_aliasing.2771555287 Dec 27 12:32:40 PM PST 23 Dec 27 12:33:19 PM PST 23 34448311 ps
T917 /workspace/coverage/cover_reg_top/16.gpio_tl_intg_err.2934091286 Dec 27 12:32:04 PM PST 23 Dec 27 12:32:50 PM PST 23 2324859225 ps
T918 /workspace/coverage/cover_reg_top/14.gpio_tl_errors.4277022791 Dec 27 12:31:41 PM PST 23 Dec 27 12:32:33 PM PST 23 652738579 ps
T919 /workspace/coverage/cover_reg_top/1.gpio_same_csr_outstanding.110769726 Dec 27 12:33:05 PM PST 23 Dec 27 12:33:37 PM PST 23 38403535 ps
T920 /workspace/coverage/cover_reg_top/11.gpio_intr_test.1679917141 Dec 27 12:32:01 PM PST 23 Dec 27 12:32:47 PM PST 23 35437335 ps
T921 /workspace/coverage/cover_reg_top/19.gpio_csr_mem_rw_with_rand_reset.1719830416 Dec 27 12:32:00 PM PST 23 Dec 27 12:32:46 PM PST 23 127317759 ps
T922 /workspace/coverage/cover_reg_top/1.gpio_tl_intg_err.2933633996 Dec 27 12:32:10 PM PST 23 Dec 27 12:32:55 PM PST 23 159004469 ps
T923 /workspace/coverage/cover_reg_top/34.gpio_intr_test.1230733882 Dec 27 12:32:08 PM PST 23 Dec 27 12:32:53 PM PST 23 49317791 ps
T924 /workspace/coverage/cover_reg_top/3.gpio_csr_bit_bash.1305939667 Dec 27 12:32:26 PM PST 23 Dec 27 12:33:13 PM PST 23 33942316 ps
T925 /workspace/coverage/cover_reg_top/4.gpio_tl_errors.2003296252 Dec 27 12:32:06 PM PST 23 Dec 27 12:32:53 PM PST 23 88472014 ps
T926 /workspace/coverage/cover_reg_top/0.gpio_csr_mem_rw_with_rand_reset.397177354 Dec 27 12:32:02 PM PST 23 Dec 27 12:32:53 PM PST 23 51004092 ps
T927 /workspace/coverage/cover_reg_top/26.gpio_intr_test.2688325824 Dec 27 12:31:56 PM PST 23 Dec 27 12:32:42 PM PST 23 14390933 ps
T928 /workspace/coverage/cover_reg_top/2.gpio_tl_errors.788421800 Dec 27 12:32:04 PM PST 23 Dec 27 12:32:50 PM PST 23 136335918 ps
T929 /workspace/coverage/cover_reg_top/40.gpio_intr_test.3089579664 Dec 27 12:32:10 PM PST 23 Dec 27 12:32:55 PM PST 23 13325301 ps
T930 /workspace/coverage/cover_reg_top/12.gpio_tl_errors.3856122458 Dec 27 12:32:00 PM PST 23 Dec 27 12:32:46 PM PST 23 68888586 ps
T931 /workspace/coverage/cover_reg_top/18.gpio_intr_test.2215299799 Dec 27 12:32:10 PM PST 23 Dec 27 12:32:55 PM PST 23 14587758 ps
T932 /workspace/coverage/cover_reg_top/14.gpio_same_csr_outstanding.3170944250 Dec 27 12:32:06 PM PST 23 Dec 27 12:32:52 PM PST 23 193931094 ps
T84 /workspace/coverage/cover_reg_top/14.gpio_csr_rw.3130441163 Dec 27 12:31:59 PM PST 23 Dec 27 12:32:45 PM PST 23 30418040 ps
T933 /workspace/coverage/cover_reg_top/32.gpio_intr_test.294845682 Dec 27 12:32:02 PM PST 23 Dec 27 12:32:47 PM PST 23 37179231 ps
T934 /workspace/coverage/cover_reg_top/1.gpio_csr_hw_reset.1071847788 Dec 27 12:33:07 PM PST 23 Dec 27 12:33:39 PM PST 23 92621220 ps
T935 /workspace/coverage/cover_reg_top/18.gpio_csr_mem_rw_with_rand_reset.2331652682 Dec 27 12:32:00 PM PST 23 Dec 27 12:32:46 PM PST 23 47254275 ps
T936 /workspace/coverage/cover_reg_top/14.gpio_csr_mem_rw_with_rand_reset.774160 Dec 27 12:32:06 PM PST 23 Dec 27 12:32:51 PM PST 23 48028133 ps
T937 /workspace/coverage/cover_reg_top/4.gpio_csr_hw_reset.1194532777 Dec 27 12:32:32 PM PST 23 Dec 27 12:33:13 PM PST 23 68970056 ps
T938 /workspace/coverage/cover_reg_top/46.gpio_intr_test.376216758 Dec 27 12:32:07 PM PST 23 Dec 27 12:32:52 PM PST 23 38783074 ps
T939 /workspace/coverage/cover_reg_top/0.gpio_tl_intg_err.2427972742 Dec 27 12:32:33 PM PST 23 Dec 27 12:33:14 PM PST 23 353919429 ps
T940 /workspace/coverage/cover_reg_top/6.gpio_same_csr_outstanding.2068323571 Dec 27 12:32:01 PM PST 23 Dec 27 12:32:47 PM PST 23 53040508 ps
T941 /workspace/coverage/cover_reg_top/16.gpio_intr_test.781474389 Dec 27 12:31:53 PM PST 23 Dec 27 12:32:40 PM PST 23 35147215 ps
T942 /workspace/coverage/cover_reg_top/3.gpio_csr_rw.3214254983 Dec 27 12:32:14 PM PST 23 Dec 27 12:32:59 PM PST 23 92473956 ps
T88 /workspace/coverage/cover_reg_top/3.gpio_csr_hw_reset.2745293099 Dec 27 12:32:06 PM PST 23 Dec 27 12:32:51 PM PST 23 68341141 ps
T943 /workspace/coverage/cover_reg_top/17.gpio_intr_test.2717254551 Dec 27 12:32:04 PM PST 23 Dec 27 12:32:49 PM PST 23 28140278 ps
T89 /workspace/coverage/cover_reg_top/6.gpio_csr_rw.2915409835 Dec 27 12:31:44 PM PST 23 Dec 27 12:32:32 PM PST 23 37000089 ps
T944 /workspace/coverage/cover_reg_top/13.gpio_intr_test.4218198299 Dec 27 12:31:57 PM PST 23 Dec 27 12:32:43 PM PST 23 118237008 ps
T945 /workspace/coverage/cover_reg_top/12.gpio_same_csr_outstanding.491457559 Dec 27 12:32:28 PM PST 23 Dec 27 12:33:09 PM PST 23 232368555 ps
T946 /workspace/coverage/cover_reg_top/2.gpio_same_csr_outstanding.3535124083 Dec 27 12:32:36 PM PST 23 Dec 27 12:33:16 PM PST 23 61329698 ps
T947 /workspace/coverage/cover_reg_top/9.gpio_same_csr_outstanding.2235440113 Dec 27 12:32:20 PM PST 23 Dec 27 12:33:04 PM PST 23 44465813 ps
T948 /workspace/coverage/cover_reg_top/19.gpio_tl_errors.3920206721 Dec 27 12:32:11 PM PST 23 Dec 27 12:32:57 PM PST 23 89000118 ps
T949 /workspace/coverage/cover_reg_top/15.gpio_same_csr_outstanding.1801345591 Dec 27 12:32:05 PM PST 23 Dec 27 12:32:50 PM PST 23 39358115 ps
T950 /workspace/coverage/cover_reg_top/0.gpio_intr_test.1519366275 Dec 27 12:31:58 PM PST 23 Dec 27 12:32:44 PM PST 23 25723335 ps
T951 /workspace/coverage/cover_reg_top/18.gpio_same_csr_outstanding.40883187 Dec 27 12:32:06 PM PST 23 Dec 27 12:32:51 PM PST 23 23504933 ps
T952 /workspace/coverage/cover_reg_top/0.gpio_csr_bit_bash.828702138 Dec 27 12:32:08 PM PST 23 Dec 27 12:32:54 PM PST 23 219679110 ps
T953 /workspace/coverage/cover_reg_top/38.gpio_intr_test.4203174649 Dec 27 12:32:05 PM PST 23 Dec 27 12:32:50 PM PST 23 13147543 ps
T90 /workspace/coverage/cover_reg_top/12.gpio_csr_rw.3204726720 Dec 27 12:32:06 PM PST 23 Dec 27 12:32:50 PM PST 23 17367036 ps
T954 /workspace/coverage/cover_reg_top/4.gpio_csr_rw.701026509 Dec 27 12:33:04 PM PST 23 Dec 27 12:33:36 PM PST 23 47732601 ps
T955 /workspace/coverage/cover_reg_top/8.gpio_intr_test.373560390 Dec 27 12:31:54 PM PST 23 Dec 27 12:32:40 PM PST 23 51075013 ps
T34 /workspace/coverage/cover_reg_top/19.gpio_tl_intg_err.2290434402 Dec 27 12:32:07 PM PST 23 Dec 27 12:32:53 PM PST 23 326111026 ps
T956 /workspace/coverage/cover_reg_top/10.gpio_intr_test.1959621474 Dec 27 12:32:37 PM PST 23 Dec 27 12:33:16 PM PST 23 44381569 ps
T957 /workspace/coverage/cover_reg_top/36.gpio_intr_test.3878015582 Dec 27 12:32:01 PM PST 23 Dec 27 12:32:46 PM PST 23 14476015 ps
T958 /workspace/coverage/cover_reg_top/5.gpio_tl_intg_err.2671501228 Dec 27 12:31:49 PM PST 23 Dec 27 12:32:38 PM PST 23 127346094 ps
T959 /workspace/coverage/cover_reg_top/15.gpio_csr_rw.660949188 Dec 27 12:32:05 PM PST 23 Dec 27 12:32:50 PM PST 23 14326436 ps
T960 /workspace/coverage/cover_reg_top/16.gpio_csr_mem_rw_with_rand_reset.3477783187 Dec 27 12:31:49 PM PST 23 Dec 27 12:32:37 PM PST 23 21548687 ps
T961 /workspace/coverage/cover_reg_top/5.gpio_same_csr_outstanding.2748955608 Dec 27 12:32:34 PM PST 23 Dec 27 12:33:14 PM PST 23 122814930 ps
T962 /workspace/coverage/cover_reg_top/14.gpio_intr_test.828171204 Dec 27 12:32:06 PM PST 23 Dec 27 12:32:51 PM PST 23 161738697 ps
T963 /workspace/coverage/cover_reg_top/7.gpio_csr_mem_rw_with_rand_reset.2116943194 Dec 27 12:32:05 PM PST 23 Dec 27 12:32:51 PM PST 23 111651510 ps
T964 /workspace/coverage/cover_reg_top/31.gpio_intr_test.2672228866 Dec 27 12:32:01 PM PST 23 Dec 27 12:32:47 PM PST 23 11608520 ps
T965 /workspace/coverage/cover_reg_top/10.gpio_tl_intg_err.2235891354 Dec 27 12:32:04 PM PST 23 Dec 27 12:32:49 PM PST 23 71574798 ps
T966 /workspace/coverage/cover_reg_top/41.gpio_intr_test.2735707332 Dec 27 12:32:41 PM PST 23 Dec 27 12:33:19 PM PST 23 57119350 ps
T967 /workspace/coverage/cover_reg_top/3.gpio_tl_intg_err.1580743826 Dec 27 12:31:59 PM PST 23 Dec 27 12:32:45 PM PST 23 102614687 ps
T968 /workspace/coverage/cover_reg_top/2.gpio_csr_mem_rw_with_rand_reset.2778692294 Dec 27 12:32:00 PM PST 23 Dec 27 12:32:46 PM PST 23 23558144 ps
T969 /workspace/coverage/cover_reg_top/0.gpio_tl_errors.30215788 Dec 27 12:32:08 PM PST 23 Dec 27 12:32:53 PM PST 23 99521261 ps
T970 /workspace/coverage/cover_reg_top/17.gpio_csr_rw.3236665357 Dec 27 12:32:06 PM PST 23 Dec 27 12:32:52 PM PST 23 12678578 ps

Test location /workspace/coverage/cover_reg_top/7.gpio_tl_intg_err.344716802
Short name T21
Test name
Test status
Simulation time 92437877 ps
CPU time 0.85 seconds
Started Dec 27 12:31:58 PM PST 23
Finished Dec 27 12:32:49 PM PST 23
Peak memory 197048 kb
Host smart-285083b8-234a-4ebb-addc-2c04f20935c5
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=344716802 -assert nopostproc +UVM_TESTNAME=gpio_base_test +U
VM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam
e 7.gpio_tl_intg_err.344716802
Directory /workspace/7.gpio_tl_intg_err/latest

Test location /workspace/coverage/en_cdc_prims/24.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3239363672
Short name T45
Test name
Test status
Simulation time 90588673 ps
CPU time 0.98 seconds
Started Dec 27 12:31:21 PM PST 23
Finished Dec 27 12:32:12 PM PST 23
Peak memory 197032 kb
Host smart-382f838d-58a0-4916-bbac-25330c768ce5
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3239363672 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 24.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.3239363672
Directory /workspace/24.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/default/33.gpio_intr_with_filter_rand_intr_event.1619229989
Short name T107
Test name
Test status
Simulation time 1226620184 ps
CPU time 2.78 seconds
Started Dec 27 01:23:52 PM PST 23
Finished Dec 27 01:23:56 PM PST 23
Peak memory 198012 kb
Host smart-29897744-5856-457d-8c54-d881dd632b7e
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1619229989 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 33.gpio_intr_with_filter_rand_intr_event.1619229989
Directory /workspace/33.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/15.gpio_stress_all_with_rand_reset.1330847261
Short name T39
Test name
Test status
Simulation time 312192153912 ps
CPU time 629.26 seconds
Started Dec 27 01:23:15 PM PST 23
Finished Dec 27 01:33:45 PM PST 23
Peak memory 206592 kb
Host smart-aed84a59-7942-4680-8f69-cd704d0c6d4b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=1330847261 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_stress_all_with_rand_reset.1330847261
Directory /workspace/15.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.gpio_tl_intg_err.2450814460
Short name T24
Test name
Test status
Simulation time 115696574 ps
CPU time 1.33 seconds
Started Dec 27 12:31:58 PM PST 23
Finished Dec 27 12:32:45 PM PST 23
Peak memory 198192 kb
Host smart-08ae90e3-6d34-4783-8a47-8f18e7ce19b5
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2450814460 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 13.gpio_tl_intg_err.2450814460
Directory /workspace/13.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.gpio_csr_rw.2696192157
Short name T1
Test name
Test status
Simulation time 49095708 ps
CPU time 0.61 seconds
Started Dec 27 12:32:06 PM PST 23
Finished Dec 27 12:33:06 PM PST 23
Peak memory 195008 kb
Host smart-1b1f84d3-f239-499d-a8cf-04e633b50ab9
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2696192157 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.gpi
o_csr_rw.2696192157
Directory /workspace/10.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.gpio_csr_mem_rw_with_rand_reset.649851897
Short name T26
Test name
Test status
Simulation time 24583366 ps
CPU time 1.16 seconds
Started Dec 27 12:31:58 PM PST 23
Finished Dec 27 12:32:44 PM PST 23
Peak memory 198452 kb
Host smart-36179b49-1a4c-4893-8879-e837229d6af3
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=649851897 -asser
t nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage
/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.gpio_csr_mem_rw_with_rand_reset.649851897
Directory /workspace/17.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/20.gpio_intr_test.4177317728
Short name T14
Test name
Test status
Simulation time 12613487 ps
CPU time 0.58 seconds
Started Dec 27 12:32:10 PM PST 23
Finished Dec 27 12:32:54 PM PST 23
Peak memory 193916 kb
Host smart-b2138e13-2d5a-4ec9-a4d1-59ecefc205a4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4177317728 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.gpio_intr_test.4177317728
Directory /workspace/20.gpio_intr_test/latest

Test location /workspace/coverage/default/0.gpio_sec_cm.4217087135
Short name T27
Test name
Test status
Simulation time 258183643 ps
CPU time 0.89 seconds
Started Dec 27 01:22:17 PM PST 23
Finished Dec 27 01:22:19 PM PST 23
Peak memory 213548 kb
Host smart-9ca566cd-2c4b-4af7-ac17-63a44ad7c5f0
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4217087135 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_sec_cm.4217087135
Directory /workspace/0.gpio_sec_cm/latest

Test location /workspace/coverage/cover_reg_top/0.gpio_csr_aliasing.322637402
Short name T11
Test name
Test status
Simulation time 47743006 ps
CPU time 0.72 seconds
Started Dec 27 12:31:43 PM PST 23
Finished Dec 27 12:32:32 PM PST 23
Peak memory 196928 kb
Host smart-97b62964-159b-4f26-95c1-3556b6f43fa2
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=322637402 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0
.gpio_csr_aliasing.322637402
Directory /workspace/0.gpio_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/11.gpio_same_csr_outstanding.163898766
Short name T12
Test name
Test status
Simulation time 111755689 ps
CPU time 0.81 seconds
Started Dec 27 12:31:52 PM PST 23
Finished Dec 27 12:32:39 PM PST 23
Peak memory 196552 kb
Host smart-a3004cdc-0403-4ccb-a195-a214dd68b2cc
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=163898766 -assert nopostproc +UVM_TESTNAME=gpio_bas
e_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul
l -cm_name 11.gpio_same_csr_outstanding.163898766
Directory /workspace/11.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/en_cdc_prims/1.gpio_smoke_en_cdc_prim.1559698999
Short name T149
Test name
Test status
Simulation time 118866171 ps
CPU time 0.96 seconds
Started Dec 27 12:31:27 PM PST 23
Finished Dec 27 12:32:23 PM PST 23
Peak memory 195272 kb
Host smart-abb2a7c4-f2c9-48b2-8beb-a42870c139e3
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1559698999 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 1.gpio_smoke_en_cdc_prim.1559698999
Directory /workspace/1.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/cover_reg_top/11.gpio_tl_intg_err.147734356
Short name T33
Test name
Test status
Simulation time 481551677 ps
CPU time 1.35 seconds
Started Dec 27 12:32:06 PM PST 23
Finished Dec 27 12:32:52 PM PST 23
Peak memory 198236 kb
Host smart-c57a40ae-d9eb-4bba-9a95-97b41eda8078
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=147734356 -assert nopostproc +UVM_TESTNAME=gpio_base_test +U
VM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam
e 11.gpio_tl_intg_err.147734356
Directory /workspace/11.gpio_tl_intg_err/latest

Test location /workspace/coverage/default/11.gpio_alert_test.2450233385
Short name T247
Test name
Test status
Simulation time 16462539 ps
CPU time 0.59 seconds
Started Dec 27 01:22:51 PM PST 23
Finished Dec 27 01:22:52 PM PST 23
Peak memory 194056 kb
Host smart-bde3926f-808f-4139-a138-885b78990c2a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2450233385 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_alert_test.2450233385
Directory /workspace/11.gpio_alert_test/latest

Test location /workspace/coverage/cover_reg_top/30.gpio_intr_test.203678151
Short name T110
Test name
Test status
Simulation time 16434500 ps
CPU time 0.55 seconds
Started Dec 27 12:32:09 PM PST 23
Finished Dec 27 12:32:53 PM PST 23
Peak memory 193916 kb
Host smart-e853a7b3-9b4c-4044-9804-8acb318d74c9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=203678151 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.gpio_intr_test.203678151
Directory /workspace/30.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.gpio_tl_intg_err.2153519045
Short name T25
Test name
Test status
Simulation time 98935082 ps
CPU time 1.11 seconds
Started Dec 27 12:31:54 PM PST 23
Finished Dec 27 12:32:41 PM PST 23
Peak memory 197948 kb
Host smart-cbedddbb-fbcf-4854-8c9e-3cd71d9a8d02
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2153519045 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 6.gpio_tl_intg_err.2153519045
Directory /workspace/6.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.gpio_intr_test.1836065187
Short name T112
Test name
Test status
Simulation time 22543556 ps
CPU time 0.63 seconds
Started Dec 27 12:31:46 PM PST 23
Finished Dec 27 12:32:34 PM PST 23
Peak memory 193956 kb
Host smart-5bf7fefa-4ae2-41d8-ae8a-b7a850a1afec
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1836065187 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.gpio_intr_test.1836065187
Directory /workspace/1.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.gpio_csr_bit_bash.828702138
Short name T952
Test name
Test status
Simulation time 219679110 ps
CPU time 2.22 seconds
Started Dec 27 12:32:08 PM PST 23
Finished Dec 27 12:32:54 PM PST 23
Peak memory 197168 kb
Host smart-b01c7361-2e28-4876-b915-d3385b65a3e8
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=828702138 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.gpio_csr_bit_bash.828702138
Directory /workspace/0.gpio_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.gpio_csr_hw_reset.926975053
Short name T38
Test name
Test status
Simulation time 24255170 ps
CPU time 0.62 seconds
Started Dec 27 12:32:38 PM PST 23
Finished Dec 27 12:33:17 PM PST 23
Peak memory 194736 kb
Host smart-48f61e24-716d-480c-b62d-4b80f38cc669
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=926975053 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.gpio_csr_hw_reset.926975053
Directory /workspace/0.gpio_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.gpio_csr_mem_rw_with_rand_reset.397177354
Short name T926
Test name
Test status
Simulation time 51004092 ps
CPU time 1.42 seconds
Started Dec 27 12:32:02 PM PST 23
Finished Dec 27 12:32:53 PM PST 23
Peak memory 198320 kb
Host smart-e8def8eb-20ae-4bd8-9e3d-d3593616cb70
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=397177354 -asser
t nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage
/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.gpio_csr_mem_rw_with_rand_reset.397177354
Directory /workspace/0.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.gpio_csr_rw.2233180230
Short name T80
Test name
Test status
Simulation time 21884683 ps
CPU time 0.62 seconds
Started Dec 27 12:32:03 PM PST 23
Finished Dec 27 12:32:49 PM PST 23
Peak memory 195168 kb
Host smart-69536202-395f-4035-a027-a3e6917087f2
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2233180230 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.gpio
_csr_rw.2233180230
Directory /workspace/0.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.gpio_intr_test.1519366275
Short name T950
Test name
Test status
Simulation time 25723335 ps
CPU time 0.58 seconds
Started Dec 27 12:31:58 PM PST 23
Finished Dec 27 12:32:44 PM PST 23
Peak memory 194684 kb
Host smart-8602f512-c49c-4af4-b8d9-6768bef01d49
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1519366275 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.gpio_intr_test.1519366275
Directory /workspace/0.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.gpio_same_csr_outstanding.1091047003
Short name T76
Test name
Test status
Simulation time 87633950 ps
CPU time 0.71 seconds
Started Dec 27 12:31:41 PM PST 23
Finished Dec 27 12:32:31 PM PST 23
Peak memory 196940 kb
Host smart-29f6f902-2429-4782-8cb2-794475ea86e6
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1091047003 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 0.gpio_same_csr_outstanding.1091047003
Directory /workspace/0.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.gpio_tl_errors.30215788
Short name T969
Test name
Test status
Simulation time 99521261 ps
CPU time 1.21 seconds
Started Dec 27 12:32:08 PM PST 23
Finished Dec 27 12:32:53 PM PST 23
Peak memory 198392 kb
Host smart-6103175e-8003-4d94-988e-b726b115f081
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30215788 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.gpio_tl_errors.30215788
Directory /workspace/0.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.gpio_tl_intg_err.2427972742
Short name T939
Test name
Test status
Simulation time 353919429 ps
CPU time 1.37 seconds
Started Dec 27 12:32:33 PM PST 23
Finished Dec 27 12:33:14 PM PST 23
Peak memory 198348 kb
Host smart-3b12f37d-39a8-422f-a383-8817f731a0b0
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2427972742 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 0.gpio_tl_intg_err.2427972742
Directory /workspace/0.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.gpio_csr_aliasing.2950285178
Short name T87
Test name
Test status
Simulation time 116355103 ps
CPU time 0.79 seconds
Started Dec 27 12:32:02 PM PST 23
Finished Dec 27 12:32:48 PM PST 23
Peak memory 196468 kb
Host smart-6392cba8-9440-4c47-a6f8-2e1887db5915
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2950285178 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM
_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name
1.gpio_csr_aliasing.2950285178
Directory /workspace/1.gpio_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.gpio_csr_bit_bash.2445282199
Short name T914
Test name
Test status
Simulation time 210586161 ps
CPU time 2.09 seconds
Started Dec 27 12:32:08 PM PST 23
Finished Dec 27 12:32:55 PM PST 23
Peak memory 197024 kb
Host smart-e489e3c2-8c5a-4135-95e6-1b0b3b2ae081
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2445282199 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.gpio_csr_bit_bash.2445282199
Directory /workspace/1.gpio_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.gpio_csr_hw_reset.1071847788
Short name T934
Test name
Test status
Simulation time 92621220 ps
CPU time 0.64 seconds
Started Dec 27 12:33:07 PM PST 23
Finished Dec 27 12:33:39 PM PST 23
Peak memory 194992 kb
Host smart-3df190e7-3e73-45d2-92e5-21dd8c4473bd
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1071847788 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.gpio_csr_hw_reset.1071847788
Directory /workspace/1.gpio_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.gpio_csr_mem_rw_with_rand_reset.351705144
Short name T2
Test name
Test status
Simulation time 94972326 ps
CPU time 0.8 seconds
Started Dec 27 12:32:04 PM PST 23
Finished Dec 27 12:32:50 PM PST 23
Peak memory 198120 kb
Host smart-f892e6f0-2e7f-4035-b176-3230c804a4a3
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=351705144 -asser
t nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage
/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.gpio_csr_mem_rw_with_rand_reset.351705144
Directory /workspace/1.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.gpio_csr_rw.1324895261
Short name T86
Test name
Test status
Simulation time 14369039 ps
CPU time 0.6 seconds
Started Dec 27 12:34:46 PM PST 23
Finished Dec 27 12:35:06 PM PST 23
Peak memory 194852 kb
Host smart-1551d592-b125-40fc-afb9-16f224d32b47
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1324895261 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.gpio
_csr_rw.1324895261
Directory /workspace/1.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.gpio_same_csr_outstanding.110769726
Short name T919
Test name
Test status
Simulation time 38403535 ps
CPU time 0.68 seconds
Started Dec 27 12:33:05 PM PST 23
Finished Dec 27 12:33:37 PM PST 23
Peak memory 194884 kb
Host smart-ad38aed6-66e6-4f78-b417-1c7e4499f821
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=110769726 -assert nopostproc +UVM_TESTNAME=gpio_bas
e_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul
l -cm_name 1.gpio_same_csr_outstanding.110769726
Directory /workspace/1.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.gpio_tl_errors.1248401834
Short name T901
Test name
Test status
Simulation time 277790884 ps
CPU time 2.84 seconds
Started Dec 27 12:32:15 PM PST 23
Finished Dec 27 12:33:01 PM PST 23
Peak memory 198364 kb
Host smart-0e562ca4-6b23-4b83-9288-aeaa0e71956f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1248401834 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.gpio_tl_errors.1248401834
Directory /workspace/1.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.gpio_tl_intg_err.2933633996
Short name T922
Test name
Test status
Simulation time 159004469 ps
CPU time 0.84 seconds
Started Dec 27 12:32:10 PM PST 23
Finished Dec 27 12:32:55 PM PST 23
Peak memory 197516 kb
Host smart-1fe458d5-b663-4cbc-8b46-02ff452fbfc2
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2933633996 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 1.gpio_tl_intg_err.2933633996
Directory /workspace/1.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.gpio_csr_mem_rw_with_rand_reset.3400692767
Short name T3
Test name
Test status
Simulation time 37815195 ps
CPU time 0.75 seconds
Started Dec 27 12:32:03 PM PST 23
Finished Dec 27 12:32:48 PM PST 23
Peak memory 198072 kb
Host smart-830978b0-faf0-4882-bccd-7e6c50fa4b30
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3400692767 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.gpio_csr_mem_rw_with_rand_reset.3400692767
Directory /workspace/10.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.gpio_intr_test.1959621474
Short name T956
Test name
Test status
Simulation time 44381569 ps
CPU time 0.58 seconds
Started Dec 27 12:32:37 PM PST 23
Finished Dec 27 12:33:16 PM PST 23
Peak memory 193936 kb
Host smart-87dd1dae-eba4-4084-af9a-bcff8aba3def
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1959621474 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.gpio_intr_test.1959621474
Directory /workspace/10.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.gpio_same_csr_outstanding.3489432205
Short name T94
Test name
Test status
Simulation time 166433753 ps
CPU time 0.86 seconds
Started Dec 27 12:31:42 PM PST 23
Finished Dec 27 12:32:32 PM PST 23
Peak memory 196616 kb
Host smart-d1073f44-2c24-4357-87b1-cc4d27f9e461
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3489432205 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 10.gpio_same_csr_outstanding.3489432205
Directory /workspace/10.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.gpio_tl_errors.1976964343
Short name T43
Test name
Test status
Simulation time 172747327 ps
CPU time 2.08 seconds
Started Dec 27 12:31:58 PM PST 23
Finished Dec 27 12:32:45 PM PST 23
Peak memory 198328 kb
Host smart-faac4c4c-52ac-4f93-a45c-644f6a5bb661
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1976964343 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.gpio_tl_errors.1976964343
Directory /workspace/10.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.gpio_tl_intg_err.2235891354
Short name T965
Test name
Test status
Simulation time 71574798 ps
CPU time 1.12 seconds
Started Dec 27 12:32:04 PM PST 23
Finished Dec 27 12:32:49 PM PST 23
Peak memory 198304 kb
Host smart-44974b5d-d666-49dd-bc02-d175a6fe0fdb
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2235891354 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 10.gpio_tl_intg_err.2235891354
Directory /workspace/10.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.gpio_csr_mem_rw_with_rand_reset.3007160265
Short name T15
Test name
Test status
Simulation time 123381939 ps
CPU time 0.59 seconds
Started Dec 27 12:32:03 PM PST 23
Finished Dec 27 12:32:48 PM PST 23
Peak memory 197208 kb
Host smart-f196630a-5e0c-4a4b-8fa2-d8371e0dcb61
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3007160265 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.gpio_csr_mem_rw_with_rand_reset.3007160265
Directory /workspace/11.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.gpio_csr_rw.1836339181
Short name T104
Test name
Test status
Simulation time 16986054 ps
CPU time 0.62 seconds
Started Dec 27 12:32:10 PM PST 23
Finished Dec 27 12:32:55 PM PST 23
Peak memory 195240 kb
Host smart-d0de9075-c138-4c17-bcc3-64a6504acb63
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1836339181 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.gpi
o_csr_rw.1836339181
Directory /workspace/11.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.gpio_intr_test.1679917141
Short name T920
Test name
Test status
Simulation time 35437335 ps
CPU time 0.6 seconds
Started Dec 27 12:32:01 PM PST 23
Finished Dec 27 12:32:47 PM PST 23
Peak memory 194632 kb
Host smart-def1433e-c80f-4538-ae33-5a34159e91ae
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1679917141 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.gpio_intr_test.1679917141
Directory /workspace/11.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.gpio_tl_errors.414449130
Short name T906
Test name
Test status
Simulation time 141760412 ps
CPU time 2.92 seconds
Started Dec 27 12:32:02 PM PST 23
Finished Dec 27 12:32:50 PM PST 23
Peak memory 198304 kb
Host smart-ac07204a-f6ee-440b-9378-9f6fd8c0c32a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=414449130 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.gpio_tl_errors.414449130
Directory /workspace/11.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.gpio_csr_mem_rw_with_rand_reset.2338507607
Short name T911
Test name
Test status
Simulation time 19157185 ps
CPU time 0.71 seconds
Started Dec 27 12:32:07 PM PST 23
Finished Dec 27 12:32:53 PM PST 23
Peak memory 198124 kb
Host smart-e7c6dba4-b904-45b8-b912-1cfe125687a2
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2338507607 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.gpio_csr_mem_rw_with_rand_reset.2338507607
Directory /workspace/12.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.gpio_csr_rw.3204726720
Short name T90
Test name
Test status
Simulation time 17367036 ps
CPU time 0.59 seconds
Started Dec 27 12:32:06 PM PST 23
Finished Dec 27 12:32:50 PM PST 23
Peak memory 194992 kb
Host smart-356cff15-0e7f-42d3-85e5-6aff066cf443
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3204726720 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.gpi
o_csr_rw.3204726720
Directory /workspace/12.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.gpio_intr_test.2910729838
Short name T118
Test name
Test status
Simulation time 124224231 ps
CPU time 0.58 seconds
Started Dec 27 12:31:59 PM PST 23
Finished Dec 27 12:32:45 PM PST 23
Peak memory 193900 kb
Host smart-3b0f5375-ce54-46da-b512-7681120a2f6e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2910729838 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.gpio_intr_test.2910729838
Directory /workspace/12.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.gpio_same_csr_outstanding.491457559
Short name T945
Test name
Test status
Simulation time 232368555 ps
CPU time 0.62 seconds
Started Dec 27 12:32:28 PM PST 23
Finished Dec 27 12:33:09 PM PST 23
Peak memory 194708 kb
Host smart-d2cc059e-2e33-476c-8ec4-371c15514728
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=491457559 -assert nopostproc +UVM_TESTNAME=gpio_bas
e_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul
l -cm_name 12.gpio_same_csr_outstanding.491457559
Directory /workspace/12.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.gpio_tl_errors.3856122458
Short name T930
Test name
Test status
Simulation time 68888586 ps
CPU time 1.15 seconds
Started Dec 27 12:32:00 PM PST 23
Finished Dec 27 12:32:46 PM PST 23
Peak memory 198472 kb
Host smart-b4cee5c6-7673-44c7-8092-e4d94c73cacc
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3856122458 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.gpio_tl_errors.3856122458
Directory /workspace/12.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.gpio_tl_intg_err.343112703
Short name T40
Test name
Test status
Simulation time 163098670 ps
CPU time 0.82 seconds
Started Dec 27 12:31:54 PM PST 23
Finished Dec 27 12:32:40 PM PST 23
Peak memory 197840 kb
Host smart-a857b700-0278-493d-abb4-821677300267
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=343112703 -assert nopostproc +UVM_TESTNAME=gpio_base_test +U
VM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam
e 12.gpio_tl_intg_err.343112703
Directory /workspace/12.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.gpio_csr_mem_rw_with_rand_reset.976083643
Short name T121
Test name
Test status
Simulation time 59149890 ps
CPU time 0.95 seconds
Started Dec 27 12:32:04 PM PST 23
Finished Dec 27 12:32:50 PM PST 23
Peak memory 198140 kb
Host smart-3d61f82c-8c51-408c-9533-1c0d04e14037
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=976083643 -asser
t nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage
/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.gpio_csr_mem_rw_with_rand_reset.976083643
Directory /workspace/13.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.gpio_csr_rw.1041533978
Short name T9
Test name
Test status
Simulation time 30342497 ps
CPU time 0.63 seconds
Started Dec 27 12:32:00 PM PST 23
Finished Dec 27 12:32:46 PM PST 23
Peak memory 194924 kb
Host smart-47737485-2378-413c-bffc-492b8e950378
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1041533978 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.gpi
o_csr_rw.1041533978
Directory /workspace/13.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.gpio_intr_test.4218198299
Short name T944
Test name
Test status
Simulation time 118237008 ps
CPU time 0.58 seconds
Started Dec 27 12:31:57 PM PST 23
Finished Dec 27 12:32:43 PM PST 23
Peak memory 193956 kb
Host smart-0ef6115b-2324-4ee4-b675-1b9b39f67cb3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4218198299 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.gpio_intr_test.4218198299
Directory /workspace/13.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.gpio_same_csr_outstanding.2960235342
Short name T4
Test name
Test status
Simulation time 228216657 ps
CPU time 0.64 seconds
Started Dec 27 12:32:32 PM PST 23
Finished Dec 27 12:33:13 PM PST 23
Peak memory 195724 kb
Host smart-087cb5e7-d5f2-42e8-b144-1204ecffd9ae
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2960235342 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 13.gpio_same_csr_outstanding.2960235342
Directory /workspace/13.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.gpio_tl_errors.1038037063
Short name T908
Test name
Test status
Simulation time 227980334 ps
CPU time 2.1 seconds
Started Dec 27 12:31:52 PM PST 23
Finished Dec 27 12:32:40 PM PST 23
Peak memory 198404 kb
Host smart-7a71425b-0e28-4d6b-98a4-b8b566dab606
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1038037063 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.gpio_tl_errors.1038037063
Directory /workspace/13.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.gpio_csr_mem_rw_with_rand_reset.774160
Short name T936
Test name
Test status
Simulation time 48028133 ps
CPU time 1.21 seconds
Started Dec 27 12:32:06 PM PST 23
Finished Dec 27 12:32:51 PM PST 23
Peak memory 198440 kb
Host smart-bf33f422-2026-4b86-bd0c-20b6de207e17
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=774160 -assert n
opostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/co
ver_reg_top.vdb -cm_log /dev/null -cm_name 14.gpio_csr_mem_rw_with_rand_reset.774160
Directory /workspace/14.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.gpio_csr_rw.3130441163
Short name T84
Test name
Test status
Simulation time 30418040 ps
CPU time 0.61 seconds
Started Dec 27 12:31:59 PM PST 23
Finished Dec 27 12:32:45 PM PST 23
Peak memory 195004 kb
Host smart-0f992fee-089f-420a-9ecf-807abeef3eeb
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3130441163 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.gpi
o_csr_rw.3130441163
Directory /workspace/14.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.gpio_intr_test.828171204
Short name T962
Test name
Test status
Simulation time 161738697 ps
CPU time 0.57 seconds
Started Dec 27 12:32:06 PM PST 23
Finished Dec 27 12:32:51 PM PST 23
Peak memory 194068 kb
Host smart-9992b60e-7e3a-4e62-91f8-c1e580d58dd4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=828171204 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.gpio_intr_test.828171204
Directory /workspace/14.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.gpio_same_csr_outstanding.3170944250
Short name T932
Test name
Test status
Simulation time 193931094 ps
CPU time 0.81 seconds
Started Dec 27 12:32:06 PM PST 23
Finished Dec 27 12:32:52 PM PST 23
Peak memory 196492 kb
Host smart-6b98eafa-9639-46b3-9d66-f02fb9e89b15
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3170944250 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 14.gpio_same_csr_outstanding.3170944250
Directory /workspace/14.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.gpio_tl_errors.4277022791
Short name T918
Test name
Test status
Simulation time 652738579 ps
CPU time 2.49 seconds
Started Dec 27 12:31:41 PM PST 23
Finished Dec 27 12:32:33 PM PST 23
Peak memory 198440 kb
Host smart-36162626-9180-4077-91be-be876a789baa
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4277022791 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.gpio_tl_errors.4277022791
Directory /workspace/14.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.gpio_tl_intg_err.562409448
Short name T42
Test name
Test status
Simulation time 183314245 ps
CPU time 1.1 seconds
Started Dec 27 12:32:15 PM PST 23
Finished Dec 27 12:32:59 PM PST 23
Peak memory 198236 kb
Host smart-4551be8e-72e5-4ce4-934b-cbc98bd4b509
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=562409448 -assert nopostproc +UVM_TESTNAME=gpio_base_test +U
VM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_nam
e 14.gpio_tl_intg_err.562409448
Directory /workspace/14.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.gpio_csr_mem_rw_with_rand_reset.3372843457
Short name T105
Test name
Test status
Simulation time 34509280 ps
CPU time 0.73 seconds
Started Dec 27 12:32:08 PM PST 23
Finished Dec 27 12:32:53 PM PST 23
Peak memory 198080 kb
Host smart-5d66449e-e28f-4f47-8661-3b9ed3048e1c
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3372843457 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.gpio_csr_mem_rw_with_rand_reset.3372843457
Directory /workspace/15.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.gpio_csr_rw.660949188
Short name T959
Test name
Test status
Simulation time 14326436 ps
CPU time 0.57 seconds
Started Dec 27 12:32:05 PM PST 23
Finished Dec 27 12:32:50 PM PST 23
Peak memory 194772 kb
Host smart-953c5e7f-5e05-455f-abbf-549434e7862c
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=660949188 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_S
EQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.gpio
_csr_rw.660949188
Directory /workspace/15.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.gpio_intr_test.2107395381
Short name T74
Test name
Test status
Simulation time 13846525 ps
CPU time 0.57 seconds
Started Dec 27 12:31:53 PM PST 23
Finished Dec 27 12:32:40 PM PST 23
Peak memory 193876 kb
Host smart-87589a0a-54ba-428a-80b1-41cecf9d337f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2107395381 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.gpio_intr_test.2107395381
Directory /workspace/15.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.gpio_same_csr_outstanding.1801345591
Short name T949
Test name
Test status
Simulation time 39358115 ps
CPU time 0.82 seconds
Started Dec 27 12:32:05 PM PST 23
Finished Dec 27 12:32:50 PM PST 23
Peak memory 197160 kb
Host smart-2ff18eb6-9b1f-4446-a495-c20cfff75f1a
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1801345591 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 15.gpio_same_csr_outstanding.1801345591
Directory /workspace/15.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.gpio_tl_errors.3113661260
Short name T912
Test name
Test status
Simulation time 391696304 ps
CPU time 1.9 seconds
Started Dec 27 12:32:08 PM PST 23
Finished Dec 27 12:32:55 PM PST 23
Peak memory 198292 kb
Host smart-b0e5a30d-25a9-41cf-9c94-a4f83dc3fe8c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3113661260 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.gpio_tl_errors.3113661260
Directory /workspace/15.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.gpio_tl_intg_err.3670496483
Short name T32
Test name
Test status
Simulation time 197348455 ps
CPU time 1.36 seconds
Started Dec 27 12:32:05 PM PST 23
Finished Dec 27 12:32:51 PM PST 23
Peak memory 198260 kb
Host smart-ffa05abc-523d-4276-8c73-0f7a3f32b210
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3670496483 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 15.gpio_tl_intg_err.3670496483
Directory /workspace/15.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.gpio_csr_mem_rw_with_rand_reset.3477783187
Short name T960
Test name
Test status
Simulation time 21548687 ps
CPU time 0.99 seconds
Started Dec 27 12:31:49 PM PST 23
Finished Dec 27 12:32:37 PM PST 23
Peak memory 198240 kb
Host smart-f74ad036-7a02-409c-9c92-aa0650e631f5
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3477783187 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.gpio_csr_mem_rw_with_rand_reset.3477783187
Directory /workspace/16.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.gpio_csr_rw.4039242579
Short name T106
Test name
Test status
Simulation time 20447796 ps
CPU time 0.57 seconds
Started Dec 27 12:32:00 PM PST 23
Finished Dec 27 12:32:46 PM PST 23
Peak memory 195344 kb
Host smart-19b82f56-531b-4975-b1ca-e878ac77ff4d
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4039242579 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.gpi
o_csr_rw.4039242579
Directory /workspace/16.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.gpio_intr_test.781474389
Short name T941
Test name
Test status
Simulation time 35147215 ps
CPU time 0.57 seconds
Started Dec 27 12:31:53 PM PST 23
Finished Dec 27 12:32:40 PM PST 23
Peak memory 194044 kb
Host smart-1291acfb-b026-4362-b095-f92a660cf863
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=781474389 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.gpio_intr_test.781474389
Directory /workspace/16.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.gpio_same_csr_outstanding.3298386910
Short name T75
Test name
Test status
Simulation time 13327740 ps
CPU time 0.63 seconds
Started Dec 27 12:31:54 PM PST 23
Finished Dec 27 12:32:40 PM PST 23
Peak memory 194976 kb
Host smart-1ce3f9ad-d205-440c-ab1d-c4f5b0165eb7
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3298386910 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 16.gpio_same_csr_outstanding.3298386910
Directory /workspace/16.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.gpio_tl_errors.3364005204
Short name T7
Test name
Test status
Simulation time 1349996148 ps
CPU time 1.91 seconds
Started Dec 27 12:32:12 PM PST 23
Finished Dec 27 12:32:58 PM PST 23
Peak memory 198472 kb
Host smart-4c14df78-7286-4b16-92bd-e3cd263b9cce
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3364005204 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.gpio_tl_errors.3364005204
Directory /workspace/16.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.gpio_tl_intg_err.2934091286
Short name T917
Test name
Test status
Simulation time 2324859225 ps
CPU time 1.33 seconds
Started Dec 27 12:32:04 PM PST 23
Finished Dec 27 12:32:50 PM PST 23
Peak memory 198340 kb
Host smart-3fff6896-48be-413f-a990-2cdb550118d6
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2934091286 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 16.gpio_tl_intg_err.2934091286
Directory /workspace/16.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.gpio_csr_rw.3236665357
Short name T970
Test name
Test status
Simulation time 12678578 ps
CPU time 0.57 seconds
Started Dec 27 12:32:06 PM PST 23
Finished Dec 27 12:32:52 PM PST 23
Peak memory 194136 kb
Host smart-f09498d4-5b80-48d7-925a-01efb1ebf0cc
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3236665357 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.gpi
o_csr_rw.3236665357
Directory /workspace/17.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.gpio_intr_test.2717254551
Short name T943
Test name
Test status
Simulation time 28140278 ps
CPU time 0.58 seconds
Started Dec 27 12:32:04 PM PST 23
Finished Dec 27 12:32:49 PM PST 23
Peak memory 193908 kb
Host smart-9853d0b9-4a76-4c82-b942-5553c96f7f1c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2717254551 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.gpio_intr_test.2717254551
Directory /workspace/17.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.gpio_same_csr_outstanding.706597359
Short name T93
Test name
Test status
Simulation time 17910778 ps
CPU time 0.64 seconds
Started Dec 27 12:32:00 PM PST 23
Finished Dec 27 12:32:46 PM PST 23
Peak memory 194840 kb
Host smart-b6ac5db7-3daf-49cf-84c2-43e9a071b38d
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=706597359 -assert nopostproc +UVM_TESTNAME=gpio_bas
e_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul
l -cm_name 17.gpio_same_csr_outstanding.706597359
Directory /workspace/17.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.gpio_tl_errors.4124349072
Short name T117
Test name
Test status
Simulation time 46301670 ps
CPU time 1.23 seconds
Started Dec 27 12:32:10 PM PST 23
Finished Dec 27 12:32:55 PM PST 23
Peak memory 198400 kb
Host smart-9c2646ff-004b-418a-9e7c-ed92860c803f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4124349072 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.gpio_tl_errors.4124349072
Directory /workspace/17.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.gpio_tl_intg_err.1525016310
Short name T41
Test name
Test status
Simulation time 55848951 ps
CPU time 0.82 seconds
Started Dec 27 12:32:12 PM PST 23
Finished Dec 27 12:32:57 PM PST 23
Peak memory 197328 kb
Host smart-5a87241e-a9e8-4856-9921-a4f6cd47c0ec
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1525016310 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 17.gpio_tl_intg_err.1525016310
Directory /workspace/17.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.gpio_csr_mem_rw_with_rand_reset.2331652682
Short name T935
Test name
Test status
Simulation time 47254275 ps
CPU time 0.83 seconds
Started Dec 27 12:32:00 PM PST 23
Finished Dec 27 12:32:46 PM PST 23
Peak memory 198096 kb
Host smart-5e6e3d0d-22f8-43f0-9c96-d090181e3deb
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2331652682 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.gpio_csr_mem_rw_with_rand_reset.2331652682
Directory /workspace/18.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.gpio_csr_rw.3374340505
Short name T897
Test name
Test status
Simulation time 173066728 ps
CPU time 0.59 seconds
Started Dec 27 12:31:49 PM PST 23
Finished Dec 27 12:32:37 PM PST 23
Peak memory 194860 kb
Host smart-938d7bbe-799b-414b-84e8-947b35de381a
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3374340505 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.gpi
o_csr_rw.3374340505
Directory /workspace/18.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.gpio_intr_test.2215299799
Short name T931
Test name
Test status
Simulation time 14587758 ps
CPU time 0.58 seconds
Started Dec 27 12:32:10 PM PST 23
Finished Dec 27 12:32:55 PM PST 23
Peak memory 194528 kb
Host smart-1d5161c0-b91d-4a74-9d90-1f856fcdca90
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2215299799 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.gpio_intr_test.2215299799
Directory /workspace/18.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.gpio_same_csr_outstanding.40883187
Short name T951
Test name
Test status
Simulation time 23504933 ps
CPU time 0.7 seconds
Started Dec 27 12:32:06 PM PST 23
Finished Dec 27 12:32:51 PM PST 23
Peak memory 195916 kb
Host smart-0ff20399-8e09-42a1-bc58-f3d7fbcfde08
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40883187 -assert nopostproc +UVM_TESTNAME=gpio_base
_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 18.gpio_same_csr_outstanding.40883187
Directory /workspace/18.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.gpio_tl_errors.1660274894
Short name T31
Test name
Test status
Simulation time 117801515 ps
CPU time 1.5 seconds
Started Dec 27 12:31:55 PM PST 23
Finished Dec 27 12:32:43 PM PST 23
Peak memory 198360 kb
Host smart-de9b9972-492f-48b2-91e1-27d7500b97f3
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1660274894 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.gpio_tl_errors.1660274894
Directory /workspace/18.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.gpio_tl_intg_err.1238766573
Short name T122
Test name
Test status
Simulation time 48604372 ps
CPU time 0.9 seconds
Started Dec 27 12:31:59 PM PST 23
Finished Dec 27 12:32:46 PM PST 23
Peak memory 197128 kb
Host smart-3203ad99-fcde-4e7a-a0c1-cf8083a5916f
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1238766573 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 18.gpio_tl_intg_err.1238766573
Directory /workspace/18.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.gpio_csr_mem_rw_with_rand_reset.1719830416
Short name T921
Test name
Test status
Simulation time 127317759 ps
CPU time 0.99 seconds
Started Dec 27 12:32:00 PM PST 23
Finished Dec 27 12:32:46 PM PST 23
Peak memory 197980 kb
Host smart-9e685403-6ac6-42bc-9924-1688b2459a79
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1719830416 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.gpio_csr_mem_rw_with_rand_reset.1719830416
Directory /workspace/19.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.gpio_csr_rw.1396526393
Short name T22
Test name
Test status
Simulation time 16144578 ps
CPU time 0.6 seconds
Started Dec 27 12:32:10 PM PST 23
Finished Dec 27 12:32:55 PM PST 23
Peak memory 195164 kb
Host smart-4dad6882-d21e-4358-9fbd-f70dada42fa7
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1396526393 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.gpi
o_csr_rw.1396526393
Directory /workspace/19.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.gpio_intr_test.3164391675
Short name T101
Test name
Test status
Simulation time 12706375 ps
CPU time 0.58 seconds
Started Dec 27 12:31:56 PM PST 23
Finished Dec 27 12:32:43 PM PST 23
Peak memory 194108 kb
Host smart-55591533-9c68-46e2-9baf-e8b308f23fc1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3164391675 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.gpio_intr_test.3164391675
Directory /workspace/19.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.gpio_same_csr_outstanding.1659171322
Short name T915
Test name
Test status
Simulation time 153590759 ps
CPU time 0.83 seconds
Started Dec 27 12:31:53 PM PST 23
Finished Dec 27 12:32:40 PM PST 23
Peak memory 196476 kb
Host smart-b339fc0f-2317-4f0c-8c77-bbf00e4be75a
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1659171322 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 19.gpio_same_csr_outstanding.1659171322
Directory /workspace/19.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.gpio_tl_errors.3920206721
Short name T948
Test name
Test status
Simulation time 89000118 ps
CPU time 2.34 seconds
Started Dec 27 12:32:11 PM PST 23
Finished Dec 27 12:32:57 PM PST 23
Peak memory 198360 kb
Host smart-23e2986f-3d36-4830-ac69-71d6890dc060
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3920206721 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.gpio_tl_errors.3920206721
Directory /workspace/19.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.gpio_tl_intg_err.2290434402
Short name T34
Test name
Test status
Simulation time 326111026 ps
CPU time 1.1 seconds
Started Dec 27 12:32:07 PM PST 23
Finished Dec 27 12:32:53 PM PST 23
Peak memory 198380 kb
Host smart-2d82e5fe-5e76-4916-aa09-1049633199f7
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2290434402 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 19.gpio_tl_intg_err.2290434402
Directory /workspace/19.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.gpio_csr_aliasing.2771555287
Short name T916
Test name
Test status
Simulation time 34448311 ps
CPU time 0.65 seconds
Started Dec 27 12:32:40 PM PST 23
Finished Dec 27 12:33:19 PM PST 23
Peak memory 194956 kb
Host smart-bf244287-3844-441d-a076-661667f34590
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2771555287 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM
_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name
2.gpio_csr_aliasing.2771555287
Directory /workspace/2.gpio_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.gpio_csr_bit_bash.3437839694
Short name T17
Test name
Test status
Simulation time 112685072 ps
CPU time 2.05 seconds
Started Dec 27 12:32:05 PM PST 23
Finished Dec 27 12:32:51 PM PST 23
Peak memory 196960 kb
Host smart-523df96e-5d35-45f7-93f2-3d930916441a
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3437839694 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.gpio_csr_bit_bash.3437839694
Directory /workspace/2.gpio_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.gpio_csr_hw_reset.4048428110
Short name T37
Test name
Test status
Simulation time 23893950 ps
CPU time 0.58 seconds
Started Dec 27 12:32:42 PM PST 23
Finished Dec 27 12:33:20 PM PST 23
Peak memory 194876 kb
Host smart-ccffcec2-bef5-4b91-a800-029f89d47ee1
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4048428110 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.gpio_csr_hw_reset.4048428110
Directory /workspace/2.gpio_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.gpio_csr_mem_rw_with_rand_reset.2778692294
Short name T968
Test name
Test status
Simulation time 23558144 ps
CPU time 0.76 seconds
Started Dec 27 12:32:00 PM PST 23
Finished Dec 27 12:32:46 PM PST 23
Peak memory 198220 kb
Host smart-066aba7a-f589-4c76-97ec-0cf9920ab87d
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2778692294 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.gpio_csr_mem_rw_with_rand_reset.2778692294
Directory /workspace/2.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.gpio_csr_rw.1677494378
Short name T79
Test name
Test status
Simulation time 14009849 ps
CPU time 0.6 seconds
Started Dec 27 12:32:07 PM PST 23
Finished Dec 27 12:32:52 PM PST 23
Peak memory 194608 kb
Host smart-c1458553-d26d-4934-af75-bafd3cd8fb29
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1677494378 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.gpio
_csr_rw.1677494378
Directory /workspace/2.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.gpio_intr_test.3546628083
Short name T19
Test name
Test status
Simulation time 24172235 ps
CPU time 0.57 seconds
Started Dec 27 12:31:44 PM PST 23
Finished Dec 27 12:32:32 PM PST 23
Peak memory 194576 kb
Host smart-8bb2b42b-7f52-47f5-a171-3b9895b10baa
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3546628083 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.gpio_intr_test.3546628083
Directory /workspace/2.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.gpio_same_csr_outstanding.3535124083
Short name T946
Test name
Test status
Simulation time 61329698 ps
CPU time 0.64 seconds
Started Dec 27 12:32:36 PM PST 23
Finished Dec 27 12:33:16 PM PST 23
Peak memory 194848 kb
Host smart-f45fc50d-5beb-4c87-8a06-bf9ace66c9df
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3535124083 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 2.gpio_same_csr_outstanding.3535124083
Directory /workspace/2.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.gpio_tl_errors.788421800
Short name T928
Test name
Test status
Simulation time 136335918 ps
CPU time 1.4 seconds
Started Dec 27 12:32:04 PM PST 23
Finished Dec 27 12:32:50 PM PST 23
Peak memory 198292 kb
Host smart-ab263d12-f69f-49b1-8f90-7891564cea45
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=788421800 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.gpio_tl_errors.788421800
Directory /workspace/2.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.gpio_tl_intg_err.1011760921
Short name T907
Test name
Test status
Simulation time 182540120 ps
CPU time 0.81 seconds
Started Dec 27 12:32:48 PM PST 23
Finished Dec 27 12:33:24 PM PST 23
Peak memory 197292 kb
Host smart-fa776e0f-3f24-40e9-821c-5446d685ec38
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1011760921 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 2.gpio_tl_intg_err.1011760921
Directory /workspace/2.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/21.gpio_intr_test.75730014
Short name T910
Test name
Test status
Simulation time 29204347 ps
CPU time 0.6 seconds
Started Dec 27 12:32:32 PM PST 23
Finished Dec 27 12:33:13 PM PST 23
Peak memory 194036 kb
Host smart-5c558bdb-2d85-414c-a666-3813348e1f42
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=75730014 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.gpio_intr_test.75730014
Directory /workspace/21.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.gpio_intr_test.2266778464
Short name T16
Test name
Test status
Simulation time 15745882 ps
CPU time 0.58 seconds
Started Dec 27 12:31:51 PM PST 23
Finished Dec 27 12:32:37 PM PST 23
Peak memory 193908 kb
Host smart-4b85d28a-4d6c-49f8-8b8b-9a55ed218203
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2266778464 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.gpio_intr_test.2266778464
Directory /workspace/22.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.gpio_intr_test.1856708800
Short name T100
Test name
Test status
Simulation time 22918336 ps
CPU time 0.56 seconds
Started Dec 27 12:32:07 PM PST 23
Finished Dec 27 12:32:56 PM PST 23
Peak memory 193928 kb
Host smart-58fafc24-ce6e-4992-82ce-b648a05cc920
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1856708800 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.gpio_intr_test.1856708800
Directory /workspace/23.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.gpio_intr_test.662237392
Short name T891
Test name
Test status
Simulation time 52765772 ps
CPU time 0.56 seconds
Started Dec 27 12:32:08 PM PST 23
Finished Dec 27 12:32:53 PM PST 23
Peak memory 193888 kb
Host smart-fb0ffb69-15c9-46c9-af9d-01a28ec35a3b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=662237392 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.gpio_intr_test.662237392
Directory /workspace/24.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.gpio_intr_test.1522901269
Short name T114
Test name
Test status
Simulation time 36729516 ps
CPU time 0.56 seconds
Started Dec 27 12:31:56 PM PST 23
Finished Dec 27 12:32:43 PM PST 23
Peak memory 193928 kb
Host smart-8554ebea-f832-4dac-b17a-c453b6d561a7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1522901269 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.gpio_intr_test.1522901269
Directory /workspace/25.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.gpio_intr_test.2688325824
Short name T927
Test name
Test status
Simulation time 14390933 ps
CPU time 0.58 seconds
Started Dec 27 12:31:56 PM PST 23
Finished Dec 27 12:32:42 PM PST 23
Peak memory 193904 kb
Host smart-2e5c68cf-ae74-4368-bb3c-f290b1f6c322
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2688325824 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.gpio_intr_test.2688325824
Directory /workspace/26.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.gpio_intr_test.1916098012
Short name T119
Test name
Test status
Simulation time 24607161 ps
CPU time 0.57 seconds
Started Dec 27 12:31:53 PM PST 23
Finished Dec 27 12:32:40 PM PST 23
Peak memory 193972 kb
Host smart-ce30e6e8-8ad7-4808-8839-2d9e83f85c36
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1916098012 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.gpio_intr_test.1916098012
Directory /workspace/27.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.gpio_intr_test.3847282911
Short name T124
Test name
Test status
Simulation time 26351757 ps
CPU time 0.61 seconds
Started Dec 27 12:32:00 PM PST 23
Finished Dec 27 12:32:46 PM PST 23
Peak memory 194068 kb
Host smart-eb99a6dc-e120-4ac2-b135-876de126d8a3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3847282911 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.gpio_intr_test.3847282911
Directory /workspace/28.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.gpio_intr_test.967965925
Short name T13
Test name
Test status
Simulation time 13641859 ps
CPU time 0.58 seconds
Started Dec 27 12:31:44 PM PST 23
Finished Dec 27 12:32:32 PM PST 23
Peak memory 194604 kb
Host smart-3bedb579-dee2-4286-9c05-15f9f5ebb2f3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=967965925 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.gpio_intr_test.967965925
Directory /workspace/29.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.gpio_csr_aliasing.414188264
Short name T23
Test name
Test status
Simulation time 33684185 ps
CPU time 0.64 seconds
Started Dec 27 12:31:45 PM PST 23
Finished Dec 27 12:32:33 PM PST 23
Peak memory 195548 kb
Host smart-826edc78-89e2-454b-9e5a-b8e75b1df252
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=414188264 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3
.gpio_csr_aliasing.414188264
Directory /workspace/3.gpio_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.gpio_csr_bit_bash.1305939667
Short name T924
Test name
Test status
Simulation time 33942316 ps
CPU time 1.31 seconds
Started Dec 27 12:32:26 PM PST 23
Finished Dec 27 12:33:13 PM PST 23
Peak memory 197008 kb
Host smart-7ba56241-0d75-4a69-9c45-e4befeb97b38
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1305939667 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.gpio_csr_bit_bash.1305939667
Directory /workspace/3.gpio_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.gpio_csr_hw_reset.2745293099
Short name T88
Test name
Test status
Simulation time 68341141 ps
CPU time 0.64 seconds
Started Dec 27 12:32:06 PM PST 23
Finished Dec 27 12:32:51 PM PST 23
Peak memory 194948 kb
Host smart-4b251ab4-44e4-4a79-8ca3-5bd61ace3934
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2745293099 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.gpio_csr_hw_reset.2745293099
Directory /workspace/3.gpio_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.gpio_csr_mem_rw_with_rand_reset.2629036637
Short name T6
Test name
Test status
Simulation time 98068482 ps
CPU time 0.88 seconds
Started Dec 27 12:32:52 PM PST 23
Finished Dec 27 12:33:27 PM PST 23
Peak memory 198112 kb
Host smart-6480a211-21ff-4975-92b3-fd6d82fac503
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2629036637 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.gpio_csr_mem_rw_with_rand_reset.2629036637
Directory /workspace/3.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.gpio_csr_rw.3214254983
Short name T942
Test name
Test status
Simulation time 92473956 ps
CPU time 0.61 seconds
Started Dec 27 12:32:14 PM PST 23
Finished Dec 27 12:32:59 PM PST 23
Peak memory 195768 kb
Host smart-984582c4-7e9b-47c9-8f40-108fb105de31
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3214254983 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.gpio
_csr_rw.3214254983
Directory /workspace/3.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.gpio_intr_test.718288101
Short name T903
Test name
Test status
Simulation time 17721580 ps
CPU time 0.6 seconds
Started Dec 27 12:32:20 PM PST 23
Finished Dec 27 12:33:03 PM PST 23
Peak memory 194012 kb
Host smart-8a077537-3681-440f-890c-b6118344ee70
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=718288101 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.gpio_intr_test.718288101
Directory /workspace/3.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.gpio_same_csr_outstanding.3147556441
Short name T92
Test name
Test status
Simulation time 18589075 ps
CPU time 0.77 seconds
Started Dec 27 12:32:44 PM PST 23
Finished Dec 27 12:33:21 PM PST 23
Peak memory 197120 kb
Host smart-93c6cb01-929e-45c0-88a7-e3031aab8252
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3147556441 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 3.gpio_same_csr_outstanding.3147556441
Directory /workspace/3.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.gpio_tl_errors.4006126584
Short name T5
Test name
Test status
Simulation time 59984062 ps
CPU time 1.35 seconds
Started Dec 27 12:33:10 PM PST 23
Finished Dec 27 12:33:42 PM PST 23
Peak memory 198348 kb
Host smart-16a8dbe6-34ac-415c-a85e-5a54d47eb9b1
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4006126584 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.gpio_tl_errors.4006126584
Directory /workspace/3.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.gpio_tl_intg_err.1580743826
Short name T967
Test name
Test status
Simulation time 102614687 ps
CPU time 1.09 seconds
Started Dec 27 12:31:59 PM PST 23
Finished Dec 27 12:32:45 PM PST 23
Peak memory 198304 kb
Host smart-3b2319ee-a2c7-4bc5-b806-21417b6bbdf9
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1580743826 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 3.gpio_tl_intg_err.1580743826
Directory /workspace/3.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/31.gpio_intr_test.2672228866
Short name T964
Test name
Test status
Simulation time 11608520 ps
CPU time 0.56 seconds
Started Dec 27 12:32:01 PM PST 23
Finished Dec 27 12:32:47 PM PST 23
Peak memory 193840 kb
Host smart-a76a1dae-8229-4aa1-a8f4-98f26657e3bd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2672228866 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.gpio_intr_test.2672228866
Directory /workspace/31.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.gpio_intr_test.294845682
Short name T933
Test name
Test status
Simulation time 37179231 ps
CPU time 0.6 seconds
Started Dec 27 12:32:02 PM PST 23
Finished Dec 27 12:32:47 PM PST 23
Peak memory 193872 kb
Host smart-25e0ff0e-28b4-4f05-85eb-b13beeacfb17
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=294845682 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.gpio_intr_test.294845682
Directory /workspace/32.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.gpio_intr_test.2639521206
Short name T904
Test name
Test status
Simulation time 13026417 ps
CPU time 0.61 seconds
Started Dec 27 12:31:53 PM PST 23
Finished Dec 27 12:32:40 PM PST 23
Peak memory 194624 kb
Host smart-f53a3cce-76eb-42ce-bb36-c8208a630df1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2639521206 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.gpio_intr_test.2639521206
Directory /workspace/33.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.gpio_intr_test.1230733882
Short name T923
Test name
Test status
Simulation time 49317791 ps
CPU time 0.58 seconds
Started Dec 27 12:32:08 PM PST 23
Finished Dec 27 12:32:53 PM PST 23
Peak memory 193996 kb
Host smart-efed9097-001d-4e8d-95a7-6b385d84d5ed
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1230733882 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.gpio_intr_test.1230733882
Directory /workspace/34.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.gpio_intr_test.823315514
Short name T116
Test name
Test status
Simulation time 18346618 ps
CPU time 0.57 seconds
Started Dec 27 12:32:03 PM PST 23
Finished Dec 27 12:32:48 PM PST 23
Peak memory 194564 kb
Host smart-9512fc3b-01e6-4f57-b618-59a3bf5a32fd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=823315514 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.gpio_intr_test.823315514
Directory /workspace/35.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.gpio_intr_test.3878015582
Short name T957
Test name
Test status
Simulation time 14476015 ps
CPU time 0.57 seconds
Started Dec 27 12:32:01 PM PST 23
Finished Dec 27 12:32:46 PM PST 23
Peak memory 193904 kb
Host smart-ca98b630-6268-488a-820e-8276eb1909a7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3878015582 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.gpio_intr_test.3878015582
Directory /workspace/36.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.gpio_intr_test.3338842141
Short name T120
Test name
Test status
Simulation time 16357287 ps
CPU time 0.58 seconds
Started Dec 27 12:32:40 PM PST 23
Finished Dec 27 12:33:18 PM PST 23
Peak memory 193940 kb
Host smart-fe9d5c6c-2623-4436-b141-5210aea35d6b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3338842141 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.gpio_intr_test.3338842141
Directory /workspace/37.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.gpio_intr_test.4203174649
Short name T953
Test name
Test status
Simulation time 13147543 ps
CPU time 0.57 seconds
Started Dec 27 12:32:05 PM PST 23
Finished Dec 27 12:32:50 PM PST 23
Peak memory 193968 kb
Host smart-ed87ad69-72f1-4d9a-9352-0ea79f8cda0d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4203174649 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.gpio_intr_test.4203174649
Directory /workspace/38.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.gpio_intr_test.3749055715
Short name T111
Test name
Test status
Simulation time 32599472 ps
CPU time 0.55 seconds
Started Dec 27 12:32:07 PM PST 23
Finished Dec 27 12:32:52 PM PST 23
Peak memory 193880 kb
Host smart-268038ad-0797-4617-b83a-cfaa68591e38
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3749055715 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.gpio_intr_test.3749055715
Directory /workspace/39.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.gpio_csr_aliasing.3040983254
Short name T91
Test name
Test status
Simulation time 16949986 ps
CPU time 0.74 seconds
Started Dec 27 12:32:41 PM PST 23
Finished Dec 27 12:33:19 PM PST 23
Peak memory 195976 kb
Host smart-33d315c9-f6fd-4e0f-ade0-f13f8f0c5420
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LO
W -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3040983254 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM
_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name
4.gpio_csr_aliasing.3040983254
Directory /workspace/4.gpio_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.gpio_csr_bit_bash.2136040532
Short name T8
Test name
Test status
Simulation time 1003524230 ps
CPU time 2.46 seconds
Started Dec 27 12:32:02 PM PST 23
Finished Dec 27 12:32:49 PM PST 23
Peak memory 197120 kb
Host smart-125d3290-404e-444a-96fc-b38802259baa
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2136040532 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.gpio_csr_bit_bash.2136040532
Directory /workspace/4.gpio_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.gpio_csr_hw_reset.1194532777
Short name T937
Test name
Test status
Simulation time 68970056 ps
CPU time 0.66 seconds
Started Dec 27 12:32:32 PM PST 23
Finished Dec 27 12:33:13 PM PST 23
Peak memory 195000 kb
Host smart-b59466bc-d048-4b2c-9e24-d24592f53954
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1194532777 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.gpio_csr_hw_reset.1194532777
Directory /workspace/4.gpio_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.gpio_csr_mem_rw_with_rand_reset.2109482453
Short name T893
Test name
Test status
Simulation time 17051847 ps
CPU time 0.77 seconds
Started Dec 27 12:31:59 PM PST 23
Finished Dec 27 12:32:45 PM PST 23
Peak memory 198052 kb
Host smart-ea294866-f42b-478e-aa94-54d6bae86afc
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2109482453 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.gpio_csr_mem_rw_with_rand_reset.2109482453
Directory /workspace/4.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.gpio_csr_rw.701026509
Short name T954
Test name
Test status
Simulation time 47732601 ps
CPU time 0.59 seconds
Started Dec 27 12:33:04 PM PST 23
Finished Dec 27 12:33:36 PM PST 23
Peak memory 195040 kb
Host smart-65b39eaa-b663-4de9-bb56-13f5e213385f
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=701026509 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_S
EQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.gpio_
csr_rw.701026509
Directory /workspace/4.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.gpio_intr_test.1941092112
Short name T902
Test name
Test status
Simulation time 32258167 ps
CPU time 0.58 seconds
Started Dec 27 12:32:16 PM PST 23
Finished Dec 27 12:33:00 PM PST 23
Peak memory 193984 kb
Host smart-f6241138-9eaa-46e6-9d95-fcbad6adc1b7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1941092112 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.gpio_intr_test.1941092112
Directory /workspace/4.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.gpio_same_csr_outstanding.3015099783
Short name T96
Test name
Test status
Simulation time 55792945 ps
CPU time 0.79 seconds
Started Dec 27 12:32:01 PM PST 23
Finished Dec 27 12:32:47 PM PST 23
Peak memory 196448 kb
Host smart-c7376c7f-8576-42c1-b140-1b13069e8206
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3015099783 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 4.gpio_same_csr_outstanding.3015099783
Directory /workspace/4.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.gpio_tl_errors.2003296252
Short name T925
Test name
Test status
Simulation time 88472014 ps
CPU time 1.76 seconds
Started Dec 27 12:32:06 PM PST 23
Finished Dec 27 12:32:53 PM PST 23
Peak memory 198304 kb
Host smart-1b3a9f94-23b9-48b6-99fe-7bc75f185bcb
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2003296252 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.gpio_tl_errors.2003296252
Directory /workspace/4.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.gpio_tl_intg_err.1885482943
Short name T36
Test name
Test status
Simulation time 128561301 ps
CPU time 1.05 seconds
Started Dec 27 12:31:47 PM PST 23
Finished Dec 27 12:32:35 PM PST 23
Peak memory 198408 kb
Host smart-eec7da56-3ec1-43a1-bac4-02c19359f2bf
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1885482943 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 4.gpio_tl_intg_err.1885482943
Directory /workspace/4.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.gpio_intr_test.3089579664
Short name T929
Test name
Test status
Simulation time 13325301 ps
CPU time 0.56 seconds
Started Dec 27 12:32:10 PM PST 23
Finished Dec 27 12:32:55 PM PST 23
Peak memory 193936 kb
Host smart-3150f9fb-db47-46c4-93b0-575c550d0f46
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3089579664 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.gpio_intr_test.3089579664
Directory /workspace/40.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.gpio_intr_test.2735707332
Short name T966
Test name
Test status
Simulation time 57119350 ps
CPU time 0.57 seconds
Started Dec 27 12:32:41 PM PST 23
Finished Dec 27 12:33:19 PM PST 23
Peak memory 194544 kb
Host smart-459f85d6-100c-432e-aad6-1e4db8ddc8d5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2735707332 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.gpio_intr_test.2735707332
Directory /workspace/41.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.gpio_intr_test.1197966714
Short name T126
Test name
Test status
Simulation time 35627693 ps
CPU time 0.55 seconds
Started Dec 27 12:32:05 PM PST 23
Finished Dec 27 12:32:50 PM PST 23
Peak memory 193992 kb
Host smart-5103dfc4-87e9-4b88-93ef-921f0c81dc12
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1197966714 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.gpio_intr_test.1197966714
Directory /workspace/42.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.gpio_intr_test.3692257663
Short name T123
Test name
Test status
Simulation time 37731956 ps
CPU time 0.61 seconds
Started Dec 27 12:31:54 PM PST 23
Finished Dec 27 12:32:41 PM PST 23
Peak memory 194036 kb
Host smart-010b0f14-39d2-4cc3-93ba-df3bae1e8f71
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3692257663 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.gpio_intr_test.3692257663
Directory /workspace/43.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.gpio_intr_test.1918325850
Short name T108
Test name
Test status
Simulation time 63690917 ps
CPU time 0.57 seconds
Started Dec 27 12:32:04 PM PST 23
Finished Dec 27 12:32:49 PM PST 23
Peak memory 194700 kb
Host smart-68088577-8f43-4d2e-9ce9-11cbd3d8cad5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1918325850 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.gpio_intr_test.1918325850
Directory /workspace/44.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.gpio_intr_test.1646974391
Short name T898
Test name
Test status
Simulation time 202832427 ps
CPU time 0.58 seconds
Started Dec 27 12:32:05 PM PST 23
Finished Dec 27 12:32:50 PM PST 23
Peak memory 193996 kb
Host smart-f81b1abd-8760-4433-b985-5cd3cd1e21f9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1646974391 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.gpio_intr_test.1646974391
Directory /workspace/45.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.gpio_intr_test.376216758
Short name T938
Test name
Test status
Simulation time 38783074 ps
CPU time 0.63 seconds
Started Dec 27 12:32:07 PM PST 23
Finished Dec 27 12:32:52 PM PST 23
Peak memory 194660 kb
Host smart-1be738e2-fe69-483d-8732-b5f910de2f1a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=376216758 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.gpio_intr_test.376216758
Directory /workspace/46.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.gpio_intr_test.3954941768
Short name T899
Test name
Test status
Simulation time 38242954 ps
CPU time 0.58 seconds
Started Dec 27 12:32:42 PM PST 23
Finished Dec 27 12:33:20 PM PST 23
Peak memory 193972 kb
Host smart-f5e60ff0-3446-47ca-aa55-e7456234fbbd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3954941768 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.gpio_intr_test.3954941768
Directory /workspace/47.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.gpio_intr_test.4145453703
Short name T125
Test name
Test status
Simulation time 62484578 ps
CPU time 0.57 seconds
Started Dec 27 12:32:38 PM PST 23
Finished Dec 27 12:33:17 PM PST 23
Peak memory 194008 kb
Host smart-c1e29fb6-fbce-4b44-a52b-36c471d582b2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4145453703 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.gpio_intr_test.4145453703
Directory /workspace/48.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.gpio_intr_test.3066824147
Short name T127
Test name
Test status
Simulation time 20421800 ps
CPU time 0.56 seconds
Started Dec 27 12:32:42 PM PST 23
Finished Dec 27 12:33:20 PM PST 23
Peak memory 193852 kb
Host smart-72abc52d-b350-42df-b2cf-81677670c626
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3066824147 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.gpio_intr_test.3066824147
Directory /workspace/49.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.gpio_csr_mem_rw_with_rand_reset.3529118930
Short name T109
Test name
Test status
Simulation time 157232448 ps
CPU time 0.82 seconds
Started Dec 27 12:32:06 PM PST 23
Finished Dec 27 12:32:52 PM PST 23
Peak memory 198120 kb
Host smart-ad691873-06f4-4c34-9a49-d09273b05dff
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3529118930 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.gpio_csr_mem_rw_with_rand_reset.3529118930
Directory /workspace/5.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.gpio_csr_rw.596769558
Short name T896
Test name
Test status
Simulation time 35153285 ps
CPU time 0.58 seconds
Started Dec 27 12:32:06 PM PST 23
Finished Dec 27 12:32:51 PM PST 23
Peak memory 194892 kb
Host smart-5e622d1d-1ed6-47b2-86ad-5ef6a01c7566
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=596769558 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_S
EQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.gpio_
csr_rw.596769558
Directory /workspace/5.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.gpio_intr_test.420788843
Short name T895
Test name
Test status
Simulation time 42830872 ps
CPU time 0.56 seconds
Started Dec 27 12:32:09 PM PST 23
Finished Dec 27 12:32:53 PM PST 23
Peak memory 194672 kb
Host smart-2e0ac558-54ee-4ac8-8227-236110131eba
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=420788843 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.gpio_intr_test.420788843
Directory /workspace/5.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.gpio_same_csr_outstanding.2748955608
Short name T961
Test name
Test status
Simulation time 122814930 ps
CPU time 0.82 seconds
Started Dec 27 12:32:34 PM PST 23
Finished Dec 27 12:33:14 PM PST 23
Peak memory 197200 kb
Host smart-5893f88e-0530-4203-a2e1-9b567d15867f
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2748955608 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 5.gpio_same_csr_outstanding.2748955608
Directory /workspace/5.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.gpio_tl_errors.444535167
Short name T909
Test name
Test status
Simulation time 61526142 ps
CPU time 1.37 seconds
Started Dec 27 12:31:52 PM PST 23
Finished Dec 27 12:32:40 PM PST 23
Peak memory 198260 kb
Host smart-511b9e40-8db8-45b5-8d2d-de5872815744
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=444535167 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.gpio_tl_errors.444535167
Directory /workspace/5.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.gpio_tl_intg_err.2671501228
Short name T958
Test name
Test status
Simulation time 127346094 ps
CPU time 1.42 seconds
Started Dec 27 12:31:49 PM PST 23
Finished Dec 27 12:32:38 PM PST 23
Peak memory 198276 kb
Host smart-89999dac-73a7-4cd1-b616-30e21a68569f
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2671501228 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 5.gpio_tl_intg_err.2671501228
Directory /workspace/5.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.gpio_csr_mem_rw_with_rand_reset.2638265332
Short name T18
Test name
Test status
Simulation time 19397592 ps
CPU time 0.74 seconds
Started Dec 27 12:32:05 PM PST 23
Finished Dec 27 12:32:50 PM PST 23
Peak memory 198096 kb
Host smart-ddd05e15-a118-4b01-a33a-85e5b3aa25f5
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2638265332 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.gpio_csr_mem_rw_with_rand_reset.2638265332
Directory /workspace/6.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.gpio_csr_rw.2915409835
Short name T89
Test name
Test status
Simulation time 37000089 ps
CPU time 0.6 seconds
Started Dec 27 12:31:44 PM PST 23
Finished Dec 27 12:32:32 PM PST 23
Peak memory 195616 kb
Host smart-398711d4-a4e2-4404-8995-78972d5bddfe
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2915409835 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.gpio
_csr_rw.2915409835
Directory /workspace/6.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.gpio_intr_test.3519733786
Short name T99
Test name
Test status
Simulation time 47258846 ps
CPU time 0.59 seconds
Started Dec 27 12:32:04 PM PST 23
Finished Dec 27 12:32:49 PM PST 23
Peak memory 193976 kb
Host smart-114854c5-0f20-44a7-b7b3-97b6c1a25d2a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3519733786 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.gpio_intr_test.3519733786
Directory /workspace/6.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.gpio_same_csr_outstanding.2068323571
Short name T940
Test name
Test status
Simulation time 53040508 ps
CPU time 0.78 seconds
Started Dec 27 12:32:01 PM PST 23
Finished Dec 27 12:32:47 PM PST 23
Peak memory 196472 kb
Host smart-36d3cce6-27ee-40d6-81dd-47b1b4a6b646
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2068323571 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 6.gpio_same_csr_outstanding.2068323571
Directory /workspace/6.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.gpio_tl_errors.998090667
Short name T30
Test name
Test status
Simulation time 87762621 ps
CPU time 1.89 seconds
Started Dec 27 12:31:56 PM PST 23
Finished Dec 27 12:32:44 PM PST 23
Peak memory 198244 kb
Host smart-d7af5291-5444-4cd1-baf4-b204f61766e5
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=998090667 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.gpio_tl_errors.998090667
Directory /workspace/6.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.gpio_csr_mem_rw_with_rand_reset.2116943194
Short name T963
Test name
Test status
Simulation time 111651510 ps
CPU time 1.44 seconds
Started Dec 27 12:32:05 PM PST 23
Finished Dec 27 12:32:51 PM PST 23
Peak memory 198280 kb
Host smart-7acaafd7-8b10-412d-a210-866463617fcb
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2116943194 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.gpio_csr_mem_rw_with_rand_reset.2116943194
Directory /workspace/7.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.gpio_csr_rw.17837281
Short name T78
Test name
Test status
Simulation time 38110968 ps
CPU time 0.6 seconds
Started Dec 27 12:32:00 PM PST 23
Finished Dec 27 12:32:45 PM PST 23
Peak memory 195576 kb
Host smart-a22ac50a-07ba-498d-9847-8ed1b112a4bb
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17837281 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SE
Q=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.gpio_c
sr_rw.17837281
Directory /workspace/7.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.gpio_intr_test.3656411403
Short name T113
Test name
Test status
Simulation time 129592045 ps
CPU time 0.58 seconds
Started Dec 27 12:32:05 PM PST 23
Finished Dec 27 12:32:50 PM PST 23
Peak memory 193940 kb
Host smart-9e566e53-e7b5-47da-a0b7-e734eba1d6d1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3656411403 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.gpio_intr_test.3656411403
Directory /workspace/7.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.gpio_same_csr_outstanding.847492927
Short name T77
Test name
Test status
Simulation time 16333887 ps
CPU time 0.71 seconds
Started Dec 27 12:31:48 PM PST 23
Finished Dec 27 12:32:37 PM PST 23
Peak memory 197000 kb
Host smart-abdccf2d-46ea-478b-b5df-74a662125f8a
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=847492927 -assert nopostproc +UVM_TESTNAME=gpio_bas
e_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nul
l -cm_name 7.gpio_same_csr_outstanding.847492927
Directory /workspace/7.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.gpio_tl_errors.735875583
Short name T10
Test name
Test status
Simulation time 94367723 ps
CPU time 1.69 seconds
Started Dec 27 12:32:07 PM PST 23
Finished Dec 27 12:32:54 PM PST 23
Peak memory 198372 kb
Host smart-8c570b55-7eeb-4393-beac-9acf999653df
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=735875583 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.gpio_tl_errors.735875583
Directory /workspace/7.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.gpio_csr_mem_rw_with_rand_reset.49916614
Short name T913
Test name
Test status
Simulation time 137782765 ps
CPU time 1.46 seconds
Started Dec 27 12:31:54 PM PST 23
Finished Dec 27 12:32:41 PM PST 23
Peak memory 198288 kb
Host smart-2e670b7a-7b3e-487d-a194-ff93822227c9
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=49916614 -assert
nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/
cover_reg_top.vdb -cm_log /dev/null -cm_name 8.gpio_csr_mem_rw_with_rand_reset.49916614
Directory /workspace/8.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.gpio_csr_rw.2391229359
Short name T894
Test name
Test status
Simulation time 15560406 ps
CPU time 0.59 seconds
Started Dec 27 12:31:48 PM PST 23
Finished Dec 27 12:32:37 PM PST 23
Peak memory 194644 kb
Host smart-ced0df3a-a0fb-44b6-bd08-7ce51fffffa7
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2391229359 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.gpio
_csr_rw.2391229359
Directory /workspace/8.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.gpio_intr_test.373560390
Short name T955
Test name
Test status
Simulation time 51075013 ps
CPU time 0.59 seconds
Started Dec 27 12:31:54 PM PST 23
Finished Dec 27 12:32:40 PM PST 23
Peak memory 193904 kb
Host smart-0dbcf412-b2f0-4385-9d85-3f5d212d5489
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=373560390 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.gpio_intr_test.373560390
Directory /workspace/8.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.gpio_same_csr_outstanding.3967283704
Short name T95
Test name
Test status
Simulation time 230831056 ps
CPU time 0.62 seconds
Started Dec 27 12:32:13 PM PST 23
Finished Dec 27 12:32:58 PM PST 23
Peak memory 194820 kb
Host smart-30ab5c4b-e997-4ece-9712-baa9d20b6baf
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3967283704 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 8.gpio_same_csr_outstanding.3967283704
Directory /workspace/8.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.gpio_tl_errors.1582709334
Short name T905
Test name
Test status
Simulation time 135441822 ps
CPU time 2.24 seconds
Started Dec 27 12:32:01 PM PST 23
Finished Dec 27 12:32:48 PM PST 23
Peak memory 198336 kb
Host smart-110e75fe-c0eb-4dfa-9f88-e954e6e4e74c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1582709334 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.gpio_tl_errors.1582709334
Directory /workspace/8.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.gpio_tl_intg_err.2191331748
Short name T900
Test name
Test status
Simulation time 67005441 ps
CPU time 0.86 seconds
Started Dec 27 12:32:00 PM PST 23
Finished Dec 27 12:32:46 PM PST 23
Peak memory 197248 kb
Host smart-8d041830-3d84-4801-b9a9-c33579d15997
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2191331748 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 8.gpio_tl_intg_err.2191331748
Directory /workspace/8.gpio_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.gpio_csr_mem_rw_with_rand_reset.1208934705
Short name T115
Test name
Test status
Simulation time 31113423 ps
CPU time 1.01 seconds
Started Dec 27 12:32:12 PM PST 23
Finished Dec 27 12:32:57 PM PST 23
Peak memory 198104 kb
Host smart-56d42a3a-c514-4636-9454-c80ba48e14cf
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_e
nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1208934705 -asse
rt nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag
e/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.gpio_csr_mem_rw_with_rand_reset.1208934705
Directory /workspace/9.gpio_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.gpio_csr_rw.2144125824
Short name T81
Test name
Test status
Simulation time 14073565 ps
CPU time 0.58 seconds
Started Dec 27 12:31:53 PM PST 23
Finished Dec 27 12:32:40 PM PST 23
Peak memory 194852 kb
Host smart-bc9b5e28-bb17-428c-9bf7-870df3027394
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2144125824 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.gpio
_csr_rw.2144125824
Directory /workspace/9.gpio_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.gpio_intr_test.2049317925
Short name T20
Test name
Test status
Simulation time 37043760 ps
CPU time 0.55 seconds
Started Dec 27 12:31:48 PM PST 23
Finished Dec 27 12:32:36 PM PST 23
Peak memory 194028 kb
Host smart-291f5ceb-57bf-48e3-925d-70455a183091
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2049317925 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.gpio_intr_test.2049317925
Directory /workspace/9.gpio_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.gpio_same_csr_outstanding.2235440113
Short name T947
Test name
Test status
Simulation time 44465813 ps
CPU time 0.71 seconds
Started Dec 27 12:32:20 PM PST 23
Finished Dec 27 12:33:04 PM PST 23
Peak memory 196208 kb
Host smart-4d86b556-54b1-4b2f-8664-ee72facd06f9
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2235440113 -assert nopostproc +UVM_TESTNAME=gpio_ba
se_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/nu
ll -cm_name 9.gpio_same_csr_outstanding.2235440113
Directory /workspace/9.gpio_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.gpio_tl_errors.2327895807
Short name T892
Test name
Test status
Simulation time 51201231 ps
CPU time 1.22 seconds
Started Dec 27 12:32:07 PM PST 23
Finished Dec 27 12:32:53 PM PST 23
Peak memory 198412 kb
Host smart-b97f03b0-1ad9-4233-a459-237c86c8aa2e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2327895807 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.gpio_tl_errors.2327895807
Directory /workspace/9.gpio_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.gpio_tl_intg_err.3327124364
Short name T35
Test name
Test status
Simulation time 54263943 ps
CPU time 0.83 seconds
Started Dec 27 12:32:01 PM PST 23
Finished Dec 27 12:32:47 PM PST 23
Peak memory 197504 kb
Host smart-6dc3e0d3-45bd-40c6-8063-460817f7397b
User root
Command /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM
_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3327124364 -assert nopostproc +UVM_TESTNAME=gpio_base_test +
UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 9.gpio_tl_intg_err.3327124364
Directory /workspace/9.gpio_tl_intg_err/latest

Test location /workspace/coverage/default/0.gpio_alert_test.3544765269
Short name T798
Test name
Test status
Simulation time 32279839 ps
CPU time 0.58 seconds
Started Dec 27 01:22:08 PM PST 23
Finished Dec 27 01:22:13 PM PST 23
Peak memory 194272 kb
Host smart-1d70b197-857b-4c95-a79b-bd5fe3f5aeb1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3544765269 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_alert_test.3544765269
Directory /workspace/0.gpio_alert_test/latest

Test location /workspace/coverage/default/0.gpio_dout_din_regs_random_rw.2313764584
Short name T759
Test name
Test status
Simulation time 225904540 ps
CPU time 0.96 seconds
Started Dec 27 01:21:24 PM PST 23
Finished Dec 27 01:21:25 PM PST 23
Peak memory 196024 kb
Host smart-feeb8ebf-4a52-457d-9a73-f8923d12d129
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2313764584 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_dout_din_regs_random_rw.2313764584
Directory /workspace/0.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/0.gpio_filter_stress.2661246529
Short name T879
Test name
Test status
Simulation time 3759073409 ps
CPU time 20.92 seconds
Started Dec 27 01:22:04 PM PST 23
Finished Dec 27 01:22:26 PM PST 23
Peak memory 197532 kb
Host smart-e27c9999-c44c-4569-a02e-d64cf4adfcb2
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2661246529 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_filter_stres
s.2661246529
Directory /workspace/0.gpio_filter_stress/latest

Test location /workspace/coverage/default/0.gpio_full_random.3772469056
Short name T793
Test name
Test status
Simulation time 118319347 ps
CPU time 0.98 seconds
Started Dec 27 01:22:30 PM PST 23
Finished Dec 27 01:22:35 PM PST 23
Peak memory 198020 kb
Host smart-516eff14-bc26-4d7e-8c1b-8a4d49a69dde
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3772469056 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_full_random.3772469056
Directory /workspace/0.gpio_full_random/latest

Test location /workspace/coverage/default/0.gpio_intr_rand_pgm.2915817561
Short name T243
Test name
Test status
Simulation time 99149275 ps
CPU time 0.82 seconds
Started Dec 27 01:21:32 PM PST 23
Finished Dec 27 01:21:34 PM PST 23
Peak memory 195448 kb
Host smart-30c1377c-f7cc-4fee-a22f-85503f6f1230
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2915817561 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_intr_rand_pgm.2915817561
Directory /workspace/0.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/0.gpio_intr_with_filter_rand_intr_event.2789835181
Short name T302
Test name
Test status
Simulation time 246947678 ps
CPU time 2.69 seconds
Started Dec 27 01:21:50 PM PST 23
Finished Dec 27 01:21:53 PM PST 23
Peak memory 196620 kb
Host smart-9cd78fb6-22a3-4e4d-bc2a-ae47cae912b4
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2789835181 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 0.gpio_intr_with_filter_rand_intr_event.2789835181
Directory /workspace/0.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/0.gpio_rand_intr_trigger.3386839903
Short name T501
Test name
Test status
Simulation time 120461290 ps
CPU time 0.84 seconds
Started Dec 27 01:22:03 PM PST 23
Finished Dec 27 01:22:05 PM PST 23
Peak memory 194488 kb
Host smart-e233fd26-1613-48d0-b0cc-0d5d7824aad4
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3386839903 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_rand_intr_trigger.
3386839903
Directory /workspace/0.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/0.gpio_random_dout_din.2361022958
Short name T722
Test name
Test status
Simulation time 323188600 ps
CPU time 1.17 seconds
Started Dec 27 01:22:01 PM PST 23
Finished Dec 27 01:22:03 PM PST 23
Peak memory 196972 kb
Host smart-53796b2c-0711-434d-9be5-3e62ce0bd606
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2361022958 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_random_dout_din.2361022958
Directory /workspace/0.gpio_random_dout_din/latest

Test location /workspace/coverage/default/0.gpio_random_dout_din_no_pullup_pulldown.1094126767
Short name T415
Test name
Test status
Simulation time 34117494 ps
CPU time 0.83 seconds
Started Dec 27 01:21:59 PM PST 23
Finished Dec 27 01:22:00 PM PST 23
Peak memory 195448 kb
Host smart-74715ba2-838d-41dc-8b7a-a6c5766142c2
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1094126767 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_random_dout_din_no_pullup
_pulldown.1094126767
Directory /workspace/0.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/0.gpio_random_long_reg_writes_reg_reads.3196458384
Short name T726
Test name
Test status
Simulation time 310727473 ps
CPU time 4.3 seconds
Started Dec 27 01:22:02 PM PST 23
Finished Dec 27 01:22:07 PM PST 23
Peak memory 198032 kb
Host smart-66a01f89-267c-42e5-8eaa-388f4c81fb25
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3196458384 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_ran
dom_long_reg_writes_reg_reads.3196458384
Directory /workspace/0.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/0.gpio_smoke.1760258823
Short name T270
Test name
Test status
Simulation time 75826982 ps
CPU time 1.14 seconds
Started Dec 27 01:21:18 PM PST 23
Finished Dec 27 01:21:20 PM PST 23
Peak memory 195544 kb
Host smart-e87fac6f-c65d-4eb2-8d68-d3ee0381cc1d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1760258823 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_smoke.1760258823
Directory /workspace/0.gpio_smoke/latest

Test location /workspace/coverage/default/0.gpio_smoke_no_pullup_pulldown.265926261
Short name T859
Test name
Test status
Simulation time 179720275 ps
CPU time 1.26 seconds
Started Dec 27 01:21:17 PM PST 23
Finished Dec 27 01:21:19 PM PST 23
Peak memory 196884 kb
Host smart-17ff08c6-528a-4f09-a2bf-119acf651888
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=265926261 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_smoke_no_pullup_pulldown.265926261
Directory /workspace/0.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/0.gpio_stress_all.2771736235
Short name T277
Test name
Test status
Simulation time 29292365044 ps
CPU time 151.97 seconds
Started Dec 27 01:22:20 PM PST 23
Finished Dec 27 01:24:56 PM PST 23
Peak memory 198168 kb
Host smart-f506efd9-e260-463a-b03c-d078fcc82d80
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2771736235 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.g
pio_stress_all.2771736235
Directory /workspace/0.gpio_stress_all/latest

Test location /workspace/coverage/default/0.gpio_stress_all_with_rand_reset.3377314645
Short name T451
Test name
Test status
Simulation time 52012687917 ps
CPU time 178.97 seconds
Started Dec 27 01:22:07 PM PST 23
Finished Dec 27 01:25:11 PM PST 23
Peak memory 198416 kb
Host smart-25a4aba5-8e5c-4b10-95ab-6d0b80bf11d0
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=3377314645 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.gpio_stress_all_with_rand_reset.3377314645
Directory /workspace/0.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/1.gpio_alert_test.514242287
Short name T848
Test name
Test status
Simulation time 127907443 ps
CPU time 0.55 seconds
Started Dec 27 01:21:56 PM PST 23
Finished Dec 27 01:21:57 PM PST 23
Peak memory 194296 kb
Host smart-29eb705b-c17f-4c84-9d2b-9c7c10a322b9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=514242287 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_alert_test.514242287
Directory /workspace/1.gpio_alert_test/latest

Test location /workspace/coverage/default/1.gpio_dout_din_regs_random_rw.3578304398
Short name T536
Test name
Test status
Simulation time 128307673 ps
CPU time 0.86 seconds
Started Dec 27 01:21:27 PM PST 23
Finished Dec 27 01:21:28 PM PST 23
Peak memory 195440 kb
Host smart-d7e38525-fb11-45eb-b82d-5babbdf8ece5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3578304398 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_dout_din_regs_random_rw.3578304398
Directory /workspace/1.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/1.gpio_filter_stress.4147597925
Short name T331
Test name
Test status
Simulation time 1975472314 ps
CPU time 15.69 seconds
Started Dec 27 01:21:15 PM PST 23
Finished Dec 27 01:21:31 PM PST 23
Peak memory 198124 kb
Host smart-7fe321d5-f360-4f21-89b0-709735f4a7c9
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4147597925 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_filter_stres
s.4147597925
Directory /workspace/1.gpio_filter_stress/latest

Test location /workspace/coverage/default/1.gpio_full_random.237060088
Short name T646
Test name
Test status
Simulation time 611269892 ps
CPU time 1.11 seconds
Started Dec 27 01:21:15 PM PST 23
Finished Dec 27 01:21:17 PM PST 23
Peak memory 196736 kb
Host smart-739c08f1-500e-4bed-9ea4-fdfa6a2d80f5
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=237060088 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_full_random.237060088
Directory /workspace/1.gpio_full_random/latest

Test location /workspace/coverage/default/1.gpio_intr_rand_pgm.1008920431
Short name T98
Test name
Test status
Simulation time 85591081 ps
CPU time 1.35 seconds
Started Dec 27 01:21:15 PM PST 23
Finished Dec 27 01:21:17 PM PST 23
Peak memory 197168 kb
Host smart-769f67e6-dbfe-4b65-8f27-63b710970afa
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1008920431 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_intr_rand_pgm.1008920431
Directory /workspace/1.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/1.gpio_intr_with_filter_rand_intr_event.4149114729
Short name T345
Test name
Test status
Simulation time 90739611 ps
CPU time 3.36 seconds
Started Dec 27 01:21:19 PM PST 23
Finished Dec 27 01:21:23 PM PST 23
Peak memory 198160 kb
Host smart-8498de61-cbc9-453f-ba9d-9c6599a48a15
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4149114729 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 1.gpio_intr_with_filter_rand_intr_event.4149114729
Directory /workspace/1.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/1.gpio_rand_intr_trigger.1300602541
Short name T313
Test name
Test status
Simulation time 39866241 ps
CPU time 1.3 seconds
Started Dec 27 01:21:27 PM PST 23
Finished Dec 27 01:21:28 PM PST 23
Peak memory 196008 kb
Host smart-818f07a4-a356-4712-b715-3ccbd64cf658
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1300602541 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_rand_intr_trigger.
1300602541
Directory /workspace/1.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/1.gpio_random_dout_din.2905170074
Short name T776
Test name
Test status
Simulation time 73098577 ps
CPU time 1.14 seconds
Started Dec 27 01:21:19 PM PST 23
Finished Dec 27 01:21:21 PM PST 23
Peak memory 196128 kb
Host smart-2275c2b9-5120-4727-8d0c-521349568d47
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2905170074 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_random_dout_din.2905170074
Directory /workspace/1.gpio_random_dout_din/latest

Test location /workspace/coverage/default/1.gpio_random_dout_din_no_pullup_pulldown.100892066
Short name T509
Test name
Test status
Simulation time 44865720 ps
CPU time 1.04 seconds
Started Dec 27 01:21:21 PM PST 23
Finished Dec 27 01:21:22 PM PST 23
Peak memory 196168 kb
Host smart-9ff5fd19-0b85-4c1b-b8bc-95a43acb220e
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=100892066 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_random_dout_din_no_pullup_
pulldown.100892066
Directory /workspace/1.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/1.gpio_random_long_reg_writes_reg_reads.1797015227
Short name T839
Test name
Test status
Simulation time 204123124 ps
CPU time 3.55 seconds
Started Dec 27 01:21:18 PM PST 23
Finished Dec 27 01:21:22 PM PST 23
Peak memory 198136 kb
Host smart-1272e31a-a7ef-4dad-8fdf-f76760d0d075
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1797015227 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_ran
dom_long_reg_writes_reg_reads.1797015227
Directory /workspace/1.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/1.gpio_sec_cm.258104423
Short name T61
Test name
Test status
Simulation time 124689802 ps
CPU time 0.75 seconds
Started Dec 27 01:21:13 PM PST 23
Finished Dec 27 01:21:14 PM PST 23
Peak memory 213476 kb
Host smart-ecc178a2-1f5e-47f0-81e1-014bccbf9221
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=258104423 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_sec_cm.258104423
Directory /workspace/1.gpio_sec_cm/latest

Test location /workspace/coverage/default/1.gpio_smoke.164213774
Short name T283
Test name
Test status
Simulation time 71052500 ps
CPU time 0.77 seconds
Started Dec 27 01:22:33 PM PST 23
Finished Dec 27 01:22:37 PM PST 23
Peak memory 196036 kb
Host smart-ee81e413-d7c6-4802-87ac-4d024c25a5fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=164213774 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_smoke.164213774
Directory /workspace/1.gpio_smoke/latest

Test location /workspace/coverage/default/1.gpio_smoke_no_pullup_pulldown.1878920962
Short name T585
Test name
Test status
Simulation time 132957677 ps
CPU time 1.3 seconds
Started Dec 27 01:21:17 PM PST 23
Finished Dec 27 01:21:18 PM PST 23
Peak memory 198088 kb
Host smart-6a590694-b424-4223-84d9-571a44918047
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1878920962 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_smoke_no_pullup_pulldown.1878920962
Directory /workspace/1.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/1.gpio_stress_all.3133076612
Short name T338
Test name
Test status
Simulation time 5340953101 ps
CPU time 34.12 seconds
Started Dec 27 01:21:17 PM PST 23
Finished Dec 27 01:21:52 PM PST 23
Peak memory 198232 kb
Host smart-c3be04b2-2220-4400-bade-1d126671877f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3133076612 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.g
pio_stress_all.3133076612
Directory /workspace/1.gpio_stress_all/latest

Test location /workspace/coverage/default/1.gpio_stress_all_with_rand_reset.390576123
Short name T83
Test name
Test status
Simulation time 45769187196 ps
CPU time 1216.44 seconds
Started Dec 27 01:21:12 PM PST 23
Finished Dec 27 01:41:29 PM PST 23
Peak memory 198296 kb
Host smart-45215581-678c-4940-a1be-eea6aa11b4d2
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=390576123 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.gpio_stress_all_with_rand_reset.390576123
Directory /workspace/1.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/10.gpio_alert_test.1135540931
Short name T317
Test name
Test status
Simulation time 12374080 ps
CPU time 0.55 seconds
Started Dec 27 01:22:44 PM PST 23
Finished Dec 27 01:22:46 PM PST 23
Peak memory 194724 kb
Host smart-02fcd748-8af7-4234-9d55-ffa90c881128
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1135540931 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_alert_test.1135540931
Directory /workspace/10.gpio_alert_test/latest

Test location /workspace/coverage/default/10.gpio_dout_din_regs_random_rw.1721389366
Short name T605
Test name
Test status
Simulation time 81088207 ps
CPU time 0.98 seconds
Started Dec 27 01:22:04 PM PST 23
Finished Dec 27 01:22:06 PM PST 23
Peak memory 196600 kb
Host smart-56309456-eca0-4d55-b673-2cccf68dd958
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1721389366 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_dout_din_regs_random_rw.1721389366
Directory /workspace/10.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/10.gpio_filter_stress.386259516
Short name T552
Test name
Test status
Simulation time 445356191 ps
CPU time 20.51 seconds
Started Dec 27 01:22:06 PM PST 23
Finished Dec 27 01:22:28 PM PST 23
Peak memory 198000 kb
Host smart-88417656-bb78-4873-8ece-73c7ee9badbd
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=386259516 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_filter_stres
s.386259516
Directory /workspace/10.gpio_filter_stress/latest

Test location /workspace/coverage/default/10.gpio_full_random.3565996785
Short name T842
Test name
Test status
Simulation time 58325965 ps
CPU time 0.61 seconds
Started Dec 27 01:22:52 PM PST 23
Finished Dec 27 01:22:53 PM PST 23
Peak memory 194556 kb
Host smart-94a4d400-be71-4d63-9107-c450ea1b1200
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3565996785 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_full_random.3565996785
Directory /workspace/10.gpio_full_random/latest

Test location /workspace/coverage/default/10.gpio_intr_rand_pgm.522347716
Short name T497
Test name
Test status
Simulation time 97564082 ps
CPU time 0.72 seconds
Started Dec 27 01:22:04 PM PST 23
Finished Dec 27 01:22:05 PM PST 23
Peak memory 195512 kb
Host smart-a5230d9e-faaa-4f10-bfdc-40e8b8982bd0
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=522347716 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_intr_rand_pgm.522347716
Directory /workspace/10.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/10.gpio_intr_with_filter_rand_intr_event.3917450076
Short name T677
Test name
Test status
Simulation time 180891972 ps
CPU time 1.32 seconds
Started Dec 27 01:21:51 PM PST 23
Finished Dec 27 01:21:53 PM PST 23
Peak memory 196928 kb
Host smart-adedf7a0-e52e-4398-89aa-6c3dad676c10
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3917450076 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 10.gpio_intr_with_filter_rand_intr_event.3917450076
Directory /workspace/10.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/10.gpio_rand_intr_trigger.3732661343
Short name T863
Test name
Test status
Simulation time 131111843 ps
CPU time 1.86 seconds
Started Dec 27 01:22:05 PM PST 23
Finished Dec 27 01:22:07 PM PST 23
Peak memory 196176 kb
Host smart-97c61051-030d-43fd-a49c-c0c570bdf821
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3732661343 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_rand_intr_trigger
.3732661343
Directory /workspace/10.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/10.gpio_random_dout_din.687693095
Short name T304
Test name
Test status
Simulation time 37909285 ps
CPU time 0.8 seconds
Started Dec 27 01:22:05 PM PST 23
Finished Dec 27 01:22:06 PM PST 23
Peak memory 196616 kb
Host smart-741bda45-ba9a-4cce-b105-5511a33f07ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=687693095 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_random_dout_din.687693095
Directory /workspace/10.gpio_random_dout_din/latest

Test location /workspace/coverage/default/10.gpio_random_dout_din_no_pullup_pulldown.3833449392
Short name T654
Test name
Test status
Simulation time 102565009 ps
CPU time 0.75 seconds
Started Dec 27 01:21:53 PM PST 23
Finished Dec 27 01:21:54 PM PST 23
Peak memory 196100 kb
Host smart-0733a9b6-2796-48dc-9b19-96f3556d0703
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3833449392 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_random_dout_din_no_pullu
p_pulldown.3833449392
Directory /workspace/10.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/10.gpio_random_long_reg_writes_reg_reads.4188294950
Short name T634
Test name
Test status
Simulation time 230856411 ps
CPU time 5.21 seconds
Started Dec 27 01:22:09 PM PST 23
Finished Dec 27 01:22:18 PM PST 23
Peak memory 197908 kb
Host smart-5e09cf71-adbb-47cb-9d42-ee37fed74837
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4188294950 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_ra
ndom_long_reg_writes_reg_reads.4188294950
Directory /workspace/10.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/10.gpio_smoke.2037100965
Short name T300
Test name
Test status
Simulation time 152411042 ps
CPU time 1.38 seconds
Started Dec 27 01:21:53 PM PST 23
Finished Dec 27 01:21:56 PM PST 23
Peak memory 198024 kb
Host smart-99c8daf6-f219-44d9-9185-3f437d4bf5f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2037100965 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_smoke.2037100965
Directory /workspace/10.gpio_smoke/latest

Test location /workspace/coverage/default/10.gpio_smoke_no_pullup_pulldown.3619113728
Short name T255
Test name
Test status
Simulation time 100468613 ps
CPU time 1.33 seconds
Started Dec 27 01:22:08 PM PST 23
Finished Dec 27 01:22:14 PM PST 23
Peak memory 198052 kb
Host smart-4dfc5fd2-18ec-43e3-8aab-c102dbfb7ec7
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3619113728 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_smoke_no_pullup_pulldown.3619113728
Directory /workspace/10.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/10.gpio_stress_all.1662208304
Short name T273
Test name
Test status
Simulation time 25733913086 ps
CPU time 140.81 seconds
Started Dec 27 01:22:52 PM PST 23
Finished Dec 27 01:25:14 PM PST 23
Peak memory 198212 kb
Host smart-3f0adf53-ca56-4dea-bf31-c9f2ebfa8f47
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1662208304 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.
gpio_stress_all.1662208304
Directory /workspace/10.gpio_stress_all/latest

Test location /workspace/coverage/default/10.gpio_stress_all_with_rand_reset.2875435639
Short name T73
Test name
Test status
Simulation time 209944290571 ps
CPU time 2000.3 seconds
Started Dec 27 01:22:54 PM PST 23
Finished Dec 27 01:56:16 PM PST 23
Peak memory 198292 kb
Host smart-f7fa10ca-a6b8-4fe1-a94c-6d1f60e1a809
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=2875435639 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.gpio_stress_all_with_rand_reset.2875435639
Directory /workspace/10.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/11.gpio_dout_din_regs_random_rw.4268848676
Short name T665
Test name
Test status
Simulation time 46389041 ps
CPU time 0.82 seconds
Started Dec 27 01:22:59 PM PST 23
Finished Dec 27 01:23:00 PM PST 23
Peak memory 195580 kb
Host smart-4dc082ec-9d37-4ab4-af28-1cd7e79345da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4268848676 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_dout_din_regs_random_rw.4268848676
Directory /workspace/11.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/11.gpio_filter_stress.2300445431
Short name T594
Test name
Test status
Simulation time 200434645 ps
CPU time 10.43 seconds
Started Dec 27 01:22:51 PM PST 23
Finished Dec 27 01:23:02 PM PST 23
Peak memory 196840 kb
Host smart-ca09ab55-78ea-4f4e-8f51-4dbbad235f5d
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2300445431 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_filter_stre
ss.2300445431
Directory /workspace/11.gpio_filter_stress/latest

Test location /workspace/coverage/default/11.gpio_full_random.3271448187
Short name T488
Test name
Test status
Simulation time 61743699 ps
CPU time 0.83 seconds
Started Dec 27 01:22:51 PM PST 23
Finished Dec 27 01:22:53 PM PST 23
Peak memory 196636 kb
Host smart-49d92f90-b035-43db-9c07-33d7ac794b1d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3271448187 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_full_random.3271448187
Directory /workspace/11.gpio_full_random/latest

Test location /workspace/coverage/default/11.gpio_intr_rand_pgm.1119848346
Short name T278
Test name
Test status
Simulation time 236909938 ps
CPU time 1.12 seconds
Started Dec 27 01:22:46 PM PST 23
Finished Dec 27 01:22:48 PM PST 23
Peak memory 196840 kb
Host smart-e6c4efff-e8a4-44c0-aee3-f52499f2ab1e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1119848346 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_intr_rand_pgm.1119848346
Directory /workspace/11.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/11.gpio_intr_with_filter_rand_intr_event.2925846844
Short name T445
Test name
Test status
Simulation time 62959024 ps
CPU time 1.51 seconds
Started Dec 27 01:22:52 PM PST 23
Finished Dec 27 01:22:54 PM PST 23
Peak memory 197024 kb
Host smart-4e56afc9-5112-40c5-9821-a8d400003098
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2925846844 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 11.gpio_intr_with_filter_rand_intr_event.2925846844
Directory /workspace/11.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/11.gpio_rand_intr_trigger.780701899
Short name T656
Test name
Test status
Simulation time 52573121 ps
CPU time 0.9 seconds
Started Dec 27 01:22:47 PM PST 23
Finished Dec 27 01:22:48 PM PST 23
Peak memory 195524 kb
Host smart-a6f54137-1053-44f1-88f2-77249b650bb6
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=780701899 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_rand_intr_trigger.
780701899
Directory /workspace/11.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/11.gpio_random_dout_din.757797215
Short name T887
Test name
Test status
Simulation time 284162130 ps
CPU time 1.33 seconds
Started Dec 27 01:22:54 PM PST 23
Finished Dec 27 01:22:57 PM PST 23
Peak memory 197196 kb
Host smart-49a4d3ea-5efb-4f5a-8a13-0c288368716a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=757797215 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_random_dout_din.757797215
Directory /workspace/11.gpio_random_dout_din/latest

Test location /workspace/coverage/default/11.gpio_random_dout_din_no_pullup_pulldown.414158992
Short name T549
Test name
Test status
Simulation time 91001159 ps
CPU time 1.16 seconds
Started Dec 27 01:22:44 PM PST 23
Finished Dec 27 01:22:46 PM PST 23
Peak memory 196224 kb
Host smart-42207362-e2cf-4311-a28c-10170d6b77cc
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=414158992 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_random_dout_din_no_pullup
_pulldown.414158992
Directory /workspace/11.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/11.gpio_random_long_reg_writes_reg_reads.15191985
Short name T564
Test name
Test status
Simulation time 475709313 ps
CPU time 4.8 seconds
Started Dec 27 01:22:48 PM PST 23
Finished Dec 27 01:22:54 PM PST 23
Peak memory 198048 kb
Host smart-11d7854f-0636-473e-94e6-cc55899b36de
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15191985 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_w
rites_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_rand
om_long_reg_writes_reg_reads.15191985
Directory /workspace/11.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/11.gpio_smoke.3710033942
Short name T443
Test name
Test status
Simulation time 56512490 ps
CPU time 0.88 seconds
Started Dec 27 01:23:14 PM PST 23
Finished Dec 27 01:23:16 PM PST 23
Peak memory 195820 kb
Host smart-a1de7a84-767f-450c-902c-40f92e77d989
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3710033942 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_smoke.3710033942
Directory /workspace/11.gpio_smoke/latest

Test location /workspace/coverage/default/11.gpio_smoke_no_pullup_pulldown.3149146491
Short name T819
Test name
Test status
Simulation time 86739495 ps
CPU time 1.32 seconds
Started Dec 27 01:22:29 PM PST 23
Finished Dec 27 01:22:31 PM PST 23
Peak memory 197076 kb
Host smart-29142b6b-f5bd-49f0-baff-e63fbc44e1d9
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3149146491 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_smoke_no_pullup_pulldown.3149146491
Directory /workspace/11.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/11.gpio_stress_all.1898516713
Short name T378
Test name
Test status
Simulation time 4660398069 ps
CPU time 28.23 seconds
Started Dec 27 01:22:49 PM PST 23
Finished Dec 27 01:23:18 PM PST 23
Peak memory 198188 kb
Host smart-0a20849e-7d66-4ead-9f5e-ebdecbdd3fa5
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1898516713 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.
gpio_stress_all.1898516713
Directory /workspace/11.gpio_stress_all/latest

Test location /workspace/coverage/default/11.gpio_stress_all_with_rand_reset.4120894601
Short name T407
Test name
Test status
Simulation time 97714494580 ps
CPU time 1363.28 seconds
Started Dec 27 01:23:17 PM PST 23
Finished Dec 27 01:46:01 PM PST 23
Peak memory 198424 kb
Host smart-6f326a87-d9a4-43dd-bd94-d367172a85bc
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=4120894601 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.gpio_stress_all_with_rand_reset.4120894601
Directory /workspace/11.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/12.gpio_alert_test.3686602510
Short name T242
Test name
Test status
Simulation time 21438987 ps
CPU time 0.55 seconds
Started Dec 27 01:23:29 PM PST 23
Finished Dec 27 01:23:30 PM PST 23
Peak memory 192680 kb
Host smart-bc25b967-556a-4509-b200-8204e4dd9ae8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3686602510 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_alert_test.3686602510
Directory /workspace/12.gpio_alert_test/latest

Test location /workspace/coverage/default/12.gpio_dout_din_regs_random_rw.4112033261
Short name T496
Test name
Test status
Simulation time 229892202 ps
CPU time 0.79 seconds
Started Dec 27 01:22:54 PM PST 23
Finished Dec 27 01:22:55 PM PST 23
Peak memory 195452 kb
Host smart-f42fa9d5-2184-46a2-8531-ee19712d27b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4112033261 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_dout_din_regs_random_rw.4112033261
Directory /workspace/12.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/12.gpio_filter_stress.1590185309
Short name T521
Test name
Test status
Simulation time 4248072416 ps
CPU time 26.51 seconds
Started Dec 27 01:23:54 PM PST 23
Finished Dec 27 01:24:22 PM PST 23
Peak memory 195964 kb
Host smart-45a88910-5b48-4137-adfb-8b90877d70a2
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1590185309 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_filter_stre
ss.1590185309
Directory /workspace/12.gpio_filter_stress/latest

Test location /workspace/coverage/default/12.gpio_full_random.3508832544
Short name T442
Test name
Test status
Simulation time 127358403 ps
CPU time 0.72 seconds
Started Dec 27 01:24:18 PM PST 23
Finished Dec 27 01:24:19 PM PST 23
Peak memory 194728 kb
Host smart-31b55d4a-6b7c-48aa-940f-6c9e6fc120b3
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3508832544 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_full_random.3508832544
Directory /workspace/12.gpio_full_random/latest

Test location /workspace/coverage/default/12.gpio_intr_rand_pgm.3951134450
Short name T599
Test name
Test status
Simulation time 44677902 ps
CPU time 1.15 seconds
Started Dec 27 01:23:18 PM PST 23
Finished Dec 27 01:23:20 PM PST 23
Peak memory 196088 kb
Host smart-64caf0ce-fd89-49f2-9743-a7281a38ed26
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3951134450 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_intr_rand_pgm.3951134450
Directory /workspace/12.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/12.gpio_intr_with_filter_rand_intr_event.121941757
Short name T406
Test name
Test status
Simulation time 146859190 ps
CPU time 1.49 seconds
Started Dec 27 01:23:48 PM PST 23
Finished Dec 27 01:23:51 PM PST 23
Peak memory 198200 kb
Host smart-a20c7394-80fe-41fc-a7a9-e0b42bc218a0
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=121941757 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 12.gpio_intr_with_filter_rand_intr_event.121941757
Directory /workspace/12.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/12.gpio_rand_intr_trigger.696837684
Short name T636
Test name
Test status
Simulation time 242619455 ps
CPU time 2.1 seconds
Started Dec 27 01:23:24 PM PST 23
Finished Dec 27 01:23:26 PM PST 23
Peak memory 197132 kb
Host smart-34a4b4c7-f8f6-4841-adcb-75925cba7bca
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=696837684 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_rand_intr_trigger.
696837684
Directory /workspace/12.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/12.gpio_random_dout_din.308258015
Short name T429
Test name
Test status
Simulation time 116382582 ps
CPU time 1.24 seconds
Started Dec 27 01:22:52 PM PST 23
Finished Dec 27 01:22:54 PM PST 23
Peak memory 197152 kb
Host smart-5440f131-fccc-4d20-ba9e-4fc4f0b51b78
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=308258015 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_random_dout_din.308258015
Directory /workspace/12.gpio_random_dout_din/latest

Test location /workspace/coverage/default/12.gpio_random_dout_din_no_pullup_pulldown.389856451
Short name T264
Test name
Test status
Simulation time 89220367 ps
CPU time 1.03 seconds
Started Dec 27 01:23:16 PM PST 23
Finished Dec 27 01:23:18 PM PST 23
Peak memory 196136 kb
Host smart-d8d824ae-7c84-4abb-8275-47c62dd53c64
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=389856451 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_random_dout_din_no_pullup
_pulldown.389856451
Directory /workspace/12.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/12.gpio_random_long_reg_writes_reg_reads.394486960
Short name T725
Test name
Test status
Simulation time 305299689 ps
CPU time 3.83 seconds
Started Dec 27 01:23:55 PM PST 23
Finished Dec 27 01:24:00 PM PST 23
Peak memory 198044 kb
Host smart-766bcf79-c885-4b4b-83bd-81d1787664f2
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=394486960 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_ran
dom_long_reg_writes_reg_reads.394486960
Directory /workspace/12.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/12.gpio_smoke.13792779
Short name T864
Test name
Test status
Simulation time 137126352 ps
CPU time 0.96 seconds
Started Dec 27 01:22:51 PM PST 23
Finished Dec 27 01:22:53 PM PST 23
Peak memory 195640 kb
Host smart-95076e3f-3235-4c7e-bf39-8efdfc7462bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=13792779 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_smoke.13792779
Directory /workspace/12.gpio_smoke/latest

Test location /workspace/coverage/default/12.gpio_smoke_no_pullup_pulldown.3171377204
Short name T674
Test name
Test status
Simulation time 75966275 ps
CPU time 1.36 seconds
Started Dec 27 01:23:15 PM PST 23
Finished Dec 27 01:23:17 PM PST 23
Peak memory 196424 kb
Host smart-35222be3-65a7-444e-bdbf-fe47568aa268
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3171377204 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_smoke_no_pullup_pulldown.3171377204
Directory /workspace/12.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/12.gpio_stress_all.3270635523
Short name T569
Test name
Test status
Simulation time 38771423654 ps
CPU time 108.6 seconds
Started Dec 27 01:24:08 PM PST 23
Finished Dec 27 01:25:57 PM PST 23
Peak memory 198292 kb
Host smart-9b703fe3-10a4-47ea-9b69-4eacab7bbf11
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3270635523 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.
gpio_stress_all.3270635523
Directory /workspace/12.gpio_stress_all/latest

Test location /workspace/coverage/default/12.gpio_stress_all_with_rand_reset.1838734874
Short name T463
Test name
Test status
Simulation time 347738707511 ps
CPU time 474.18 seconds
Started Dec 27 01:23:27 PM PST 23
Finished Dec 27 01:31:21 PM PST 23
Peak memory 198436 kb
Host smart-1a9ff804-eab8-4111-baea-e7b6c8cc30b1
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=1838734874 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.gpio_stress_all_with_rand_reset.1838734874
Directory /workspace/12.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/13.gpio_alert_test.3949762417
Short name T623
Test name
Test status
Simulation time 12090197 ps
CPU time 0.57 seconds
Started Dec 27 01:23:16 PM PST 23
Finished Dec 27 01:23:17 PM PST 23
Peak memory 194748 kb
Host smart-0f455daa-5eb0-4bfe-a7b3-b38ccb70e260
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3949762417 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_alert_test.3949762417
Directory /workspace/13.gpio_alert_test/latest

Test location /workspace/coverage/default/13.gpio_dout_din_regs_random_rw.3759252023
Short name T228
Test name
Test status
Simulation time 29349022 ps
CPU time 0.72 seconds
Started Dec 27 01:24:13 PM PST 23
Finished Dec 27 01:24:14 PM PST 23
Peak memory 196076 kb
Host smart-741707cf-efc8-4a91-8fe9-6d524fde2fa0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3759252023 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_dout_din_regs_random_rw.3759252023
Directory /workspace/13.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/13.gpio_filter_stress.4121912854
Short name T659
Test name
Test status
Simulation time 2301280801 ps
CPU time 15.77 seconds
Started Dec 27 01:22:29 PM PST 23
Finished Dec 27 01:22:46 PM PST 23
Peak memory 196908 kb
Host smart-6685ad14-3cc2-4790-a3e2-2cc109012bd1
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4121912854 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_filter_stre
ss.4121912854
Directory /workspace/13.gpio_filter_stress/latest

Test location /workspace/coverage/default/13.gpio_full_random.773162698
Short name T286
Test name
Test status
Simulation time 123527228 ps
CPU time 0.7 seconds
Started Dec 27 01:22:20 PM PST 23
Finished Dec 27 01:22:24 PM PST 23
Peak memory 195408 kb
Host smart-543381a7-f732-4fcb-9b8c-41ffef4e2cab
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=773162698 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_full_random.773162698
Directory /workspace/13.gpio_full_random/latest

Test location /workspace/coverage/default/13.gpio_intr_rand_pgm.2200263125
Short name T550
Test name
Test status
Simulation time 19334093 ps
CPU time 0.72 seconds
Started Dec 27 01:23:52 PM PST 23
Finished Dec 27 01:23:55 PM PST 23
Peak memory 195288 kb
Host smart-642aa762-ecb9-438b-8284-fa82388a4602
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2200263125 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_intr_rand_pgm.2200263125
Directory /workspace/13.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/13.gpio_intr_with_filter_rand_intr_event.4049814983
Short name T261
Test name
Test status
Simulation time 46374082 ps
CPU time 1.81 seconds
Started Dec 27 01:24:27 PM PST 23
Finished Dec 27 01:24:29 PM PST 23
Peak memory 198072 kb
Host smart-e61741e0-40d7-481d-a2d4-b0f26e191666
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4049814983 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 13.gpio_intr_with_filter_rand_intr_event.4049814983
Directory /workspace/13.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/13.gpio_rand_intr_trigger.565977501
Short name T635
Test name
Test status
Simulation time 272605007 ps
CPU time 1.52 seconds
Started Dec 27 01:23:52 PM PST 23
Finished Dec 27 01:23:55 PM PST 23
Peak memory 195980 kb
Host smart-8656f268-6986-4944-a7dc-3436ef8dc465
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=565977501 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_rand_intr_trigger.
565977501
Directory /workspace/13.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/13.gpio_random_dout_din.1669524093
Short name T506
Test name
Test status
Simulation time 187816198 ps
CPU time 1.2 seconds
Started Dec 27 01:23:53 PM PST 23
Finished Dec 27 01:23:56 PM PST 23
Peak memory 196720 kb
Host smart-5c3c5e57-8562-4af3-9685-db18bd19d026
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1669524093 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_random_dout_din.1669524093
Directory /workspace/13.gpio_random_dout_din/latest

Test location /workspace/coverage/default/13.gpio_random_dout_din_no_pullup_pulldown.2990571179
Short name T491
Test name
Test status
Simulation time 78730561 ps
CPU time 0.99 seconds
Started Dec 27 01:23:28 PM PST 23
Finished Dec 27 01:23:30 PM PST 23
Peak memory 196144 kb
Host smart-b260d500-b5b0-4bcd-9f4f-3dc1ce865032
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2990571179 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_random_dout_din_no_pullu
p_pulldown.2990571179
Directory /workspace/13.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/13.gpio_random_long_reg_writes_reg_reads.3089953339
Short name T419
Test name
Test status
Simulation time 71685246 ps
CPU time 3.12 seconds
Started Dec 27 01:22:29 PM PST 23
Finished Dec 27 01:22:33 PM PST 23
Peak memory 198128 kb
Host smart-992273fb-4906-44d8-bb2c-05c4fdafd940
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3089953339 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_ra
ndom_long_reg_writes_reg_reads.3089953339
Directory /workspace/13.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/13.gpio_smoke.2532926907
Short name T746
Test name
Test status
Simulation time 57287321 ps
CPU time 1.14 seconds
Started Dec 27 01:22:45 PM PST 23
Finished Dec 27 01:22:47 PM PST 23
Peak memory 195936 kb
Host smart-c9ff1de5-de0f-4730-adf2-279201dd809d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2532926907 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_smoke.2532926907
Directory /workspace/13.gpio_smoke/latest

Test location /workspace/coverage/default/13.gpio_smoke_no_pullup_pulldown.2613015929
Short name T779
Test name
Test status
Simulation time 37976432 ps
CPU time 1.1 seconds
Started Dec 27 01:24:18 PM PST 23
Finished Dec 27 01:24:21 PM PST 23
Peak memory 195628 kb
Host smart-518fdede-adc4-4bda-b0e1-d10fecdfea1d
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2613015929 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_smoke_no_pullup_pulldown.2613015929
Directory /workspace/13.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/13.gpio_stress_all.2599405772
Short name T405
Test name
Test status
Simulation time 7098336633 ps
CPU time 84.64 seconds
Started Dec 27 01:22:25 PM PST 23
Finished Dec 27 01:23:52 PM PST 23
Peak memory 198268 kb
Host smart-840cff8e-9e22-43be-b4f9-2a75d5ce28e1
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2599405772 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.
gpio_stress_all.2599405772
Directory /workspace/13.gpio_stress_all/latest

Test location /workspace/coverage/default/13.gpio_stress_all_with_rand_reset.757174081
Short name T535
Test name
Test status
Simulation time 562472712541 ps
CPU time 1033.28 seconds
Started Dec 27 01:22:12 PM PST 23
Finished Dec 27 01:39:26 PM PST 23
Peak memory 198324 kb
Host smart-73a1623a-81d7-4df5-9156-b3e489e4fbd0
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=757174081 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.gpio_stress_all_with_rand_reset.757174081
Directory /workspace/13.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/14.gpio_alert_test.2763163799
Short name T758
Test name
Test status
Simulation time 13523364 ps
CPU time 0.56 seconds
Started Dec 27 01:22:30 PM PST 23
Finished Dec 27 01:22:32 PM PST 23
Peak memory 194028 kb
Host smart-bdbd028d-5e45-440d-97e6-b7aba8bedc62
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2763163799 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_alert_test.2763163799
Directory /workspace/14.gpio_alert_test/latest

Test location /workspace/coverage/default/14.gpio_dout_din_regs_random_rw.358996968
Short name T795
Test name
Test status
Simulation time 104839083 ps
CPU time 0.88 seconds
Started Dec 27 01:22:45 PM PST 23
Finished Dec 27 01:22:47 PM PST 23
Peak memory 196488 kb
Host smart-7248f140-2a57-49eb-8668-128043ada359
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=358996968 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_dout_din_regs_random_rw.358996968
Directory /workspace/14.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/14.gpio_filter_stress.1348541410
Short name T673
Test name
Test status
Simulation time 736379671 ps
CPU time 10.55 seconds
Started Dec 27 01:23:20 PM PST 23
Finished Dec 27 01:23:31 PM PST 23
Peak memory 196944 kb
Host smart-a3ff490c-fb5b-444b-9eb9-6a987923484f
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1348541410 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_filter_stre
ss.1348541410
Directory /workspace/14.gpio_filter_stress/latest

Test location /workspace/coverage/default/14.gpio_full_random.2659596836
Short name T384
Test name
Test status
Simulation time 27195786 ps
CPU time 0.62 seconds
Started Dec 27 01:23:20 PM PST 23
Finished Dec 27 01:23:21 PM PST 23
Peak memory 194508 kb
Host smart-49251658-70ed-4353-ba33-fa4d7fe8f9ab
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2659596836 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_full_random.2659596836
Directory /workspace/14.gpio_full_random/latest

Test location /workspace/coverage/default/14.gpio_intr_rand_pgm.4135837977
Short name T292
Test name
Test status
Simulation time 96375061 ps
CPU time 0.75 seconds
Started Dec 27 01:22:50 PM PST 23
Finished Dec 27 01:22:51 PM PST 23
Peak memory 195516 kb
Host smart-5da8e8fe-f9f5-4037-bcdb-1851073ccdb2
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4135837977 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_intr_rand_pgm.4135837977
Directory /workspace/14.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/14.gpio_intr_with_filter_rand_intr_event.3186576770
Short name T737
Test name
Test status
Simulation time 192352760 ps
CPU time 2.15 seconds
Started Dec 27 01:23:22 PM PST 23
Finished Dec 27 01:23:24 PM PST 23
Peak memory 198132 kb
Host smart-bd0b5458-2029-4aae-be47-ba108002909f
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3186576770 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 14.gpio_intr_with_filter_rand_intr_event.3186576770
Directory /workspace/14.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/14.gpio_rand_intr_trigger.1300701080
Short name T397
Test name
Test status
Simulation time 542470794 ps
CPU time 2.92 seconds
Started Dec 27 01:23:16 PM PST 23
Finished Dec 27 01:23:20 PM PST 23
Peak memory 197376 kb
Host smart-2ed83c91-fc49-4214-9bf0-01daa7ac3ec0
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1300701080 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_rand_intr_trigger
.1300701080
Directory /workspace/14.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/14.gpio_random_dout_din.3416245893
Short name T227
Test name
Test status
Simulation time 165298298 ps
CPU time 0.89 seconds
Started Dec 27 01:22:56 PM PST 23
Finished Dec 27 01:22:57 PM PST 23
Peak memory 196132 kb
Host smart-68ed4574-bdbf-4461-b124-4d7750daf7be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3416245893 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_random_dout_din.3416245893
Directory /workspace/14.gpio_random_dout_din/latest

Test location /workspace/coverage/default/14.gpio_random_dout_din_no_pullup_pulldown.137232399
Short name T527
Test name
Test status
Simulation time 18590259 ps
CPU time 0.68 seconds
Started Dec 27 01:23:15 PM PST 23
Finished Dec 27 01:23:17 PM PST 23
Peak memory 195168 kb
Host smart-20867bc5-e836-4931-beca-0641c6ea4563
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=137232399 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_random_dout_din_no_pullup
_pulldown.137232399
Directory /workspace/14.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/14.gpio_random_long_reg_writes_reg_reads.4285677212
Short name T388
Test name
Test status
Simulation time 299652376 ps
CPU time 3.73 seconds
Started Dec 27 01:23:23 PM PST 23
Finished Dec 27 01:23:27 PM PST 23
Peak memory 198136 kb
Host smart-b5bf87e7-b035-494b-a328-7133cc6ce6c6
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4285677212 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_ra
ndom_long_reg_writes_reg_reads.4285677212
Directory /workspace/14.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/14.gpio_smoke.2558839595
Short name T216
Test name
Test status
Simulation time 113240419 ps
CPU time 1.06 seconds
Started Dec 27 01:23:20 PM PST 23
Finished Dec 27 01:23:21 PM PST 23
Peak memory 195644 kb
Host smart-0d0d4d8c-afe6-473d-bad9-2aef8e56c5af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2558839595 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_smoke.2558839595
Directory /workspace/14.gpio_smoke/latest

Test location /workspace/coverage/default/14.gpio_smoke_no_pullup_pulldown.716700778
Short name T218
Test name
Test status
Simulation time 135140387 ps
CPU time 1.21 seconds
Started Dec 27 01:22:46 PM PST 23
Finished Dec 27 01:22:48 PM PST 23
Peak memory 195876 kb
Host smart-f4f5c3c8-4795-4c21-9a0e-32a995f4e22f
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=716700778 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_smoke_no_pullup_pulldown.716700778
Directory /workspace/14.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/14.gpio_stress_all.3310617308
Short name T782
Test name
Test status
Simulation time 25640444650 ps
CPU time 84.61 seconds
Started Dec 27 01:22:30 PM PST 23
Finished Dec 27 01:23:59 PM PST 23
Peak memory 198168 kb
Host smart-d411928c-0962-4b9d-8493-895e19450a37
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3310617308 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.
gpio_stress_all.3310617308
Directory /workspace/14.gpio_stress_all/latest

Test location /workspace/coverage/default/14.gpio_stress_all_with_rand_reset.2634715461
Short name T582
Test name
Test status
Simulation time 219919609185 ps
CPU time 1692.3 seconds
Started Dec 27 01:22:31 PM PST 23
Finished Dec 27 01:50:48 PM PST 23
Peak memory 198308 kb
Host smart-9c67d1c8-cfbf-41c2-b3ff-da940e38a5c5
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=2634715461 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.gpio_stress_all_with_rand_reset.2634715461
Directory /workspace/14.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/15.gpio_alert_test.2404810595
Short name T251
Test name
Test status
Simulation time 21387168 ps
CPU time 0.58 seconds
Started Dec 27 01:22:30 PM PST 23
Finished Dec 27 01:22:31 PM PST 23
Peak memory 194072 kb
Host smart-09db1e8c-2994-479e-82c3-e7ba6ac30701
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2404810595 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_alert_test.2404810595
Directory /workspace/15.gpio_alert_test/latest

Test location /workspace/coverage/default/15.gpio_dout_din_regs_random_rw.3614496498
Short name T581
Test name
Test status
Simulation time 25089484 ps
CPU time 0.8 seconds
Started Dec 27 01:23:19 PM PST 23
Finished Dec 27 01:23:20 PM PST 23
Peak memory 195500 kb
Host smart-221df3f0-1cb4-43a7-ae60-5d46e1d356f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3614496498 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_dout_din_regs_random_rw.3614496498
Directory /workspace/15.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/15.gpio_filter_stress.2321557890
Short name T801
Test name
Test status
Simulation time 1103663119 ps
CPU time 13.99 seconds
Started Dec 27 01:23:16 PM PST 23
Finished Dec 27 01:23:30 PM PST 23
Peak memory 197100 kb
Host smart-6920cd36-fedc-4902-9d3e-b3748126a9ed
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2321557890 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_filter_stre
ss.2321557890
Directory /workspace/15.gpio_filter_stress/latest

Test location /workspace/coverage/default/15.gpio_full_random.3389487555
Short name T620
Test name
Test status
Simulation time 70520488 ps
CPU time 1.09 seconds
Started Dec 27 01:22:55 PM PST 23
Finished Dec 27 01:22:57 PM PST 23
Peak memory 198084 kb
Host smart-014d6fd3-7c24-4e09-8204-87d4c8cbffaa
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3389487555 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_full_random.3389487555
Directory /workspace/15.gpio_full_random/latest

Test location /workspace/coverage/default/15.gpio_intr_rand_pgm.171028494
Short name T608
Test name
Test status
Simulation time 254208719 ps
CPU time 1.08 seconds
Started Dec 27 01:22:55 PM PST 23
Finished Dec 27 01:22:57 PM PST 23
Peak memory 195916 kb
Host smart-00ba7c6b-d49c-47c8-9e46-38092bd1d0b4
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=171028494 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_intr_rand_pgm.171028494
Directory /workspace/15.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/15.gpio_intr_with_filter_rand_intr_event.570047163
Short name T802
Test name
Test status
Simulation time 126875093 ps
CPU time 2.7 seconds
Started Dec 27 01:22:58 PM PST 23
Finished Dec 27 01:23:01 PM PST 23
Peak memory 198184 kb
Host smart-48efc4aa-9f99-4f48-bf10-bc8febaf925f
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=570047163 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 15.gpio_intr_with_filter_rand_intr_event.570047163
Directory /workspace/15.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/15.gpio_rand_intr_trigger.891248127
Short name T745
Test name
Test status
Simulation time 99468663 ps
CPU time 2.83 seconds
Started Dec 27 01:22:29 PM PST 23
Finished Dec 27 01:22:34 PM PST 23
Peak memory 197192 kb
Host smart-81201663-e833-46b5-b1df-4fa0e346fcf0
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=891248127 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_rand_intr_trigger.
891248127
Directory /workspace/15.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/15.gpio_random_dout_din.1766575677
Short name T760
Test name
Test status
Simulation time 51586219 ps
CPU time 1.18 seconds
Started Dec 27 01:22:19 PM PST 23
Finished Dec 27 01:22:21 PM PST 23
Peak memory 196772 kb
Host smart-c35c41bd-3b56-49e6-8738-959fcf2278a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1766575677 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_random_dout_din.1766575677
Directory /workspace/15.gpio_random_dout_din/latest

Test location /workspace/coverage/default/15.gpio_random_dout_din_no_pullup_pulldown.1641489006
Short name T372
Test name
Test status
Simulation time 66011212 ps
CPU time 1.28 seconds
Started Dec 27 01:22:31 PM PST 23
Finished Dec 27 01:22:37 PM PST 23
Peak memory 196164 kb
Host smart-06e7862a-feb1-4ad8-9773-4eec8a13727b
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1641489006 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_random_dout_din_no_pullu
p_pulldown.1641489006
Directory /workspace/15.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/15.gpio_random_long_reg_writes_reg_reads.1215365931
Short name T382
Test name
Test status
Simulation time 89980762 ps
CPU time 2.24 seconds
Started Dec 27 01:22:30 PM PST 23
Finished Dec 27 01:22:33 PM PST 23
Peak memory 198012 kb
Host smart-a1cca2b7-cd18-4a96-b531-c27fda66f33b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1215365931 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_ra
ndom_long_reg_writes_reg_reads.1215365931
Directory /workspace/15.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/15.gpio_smoke.2132360376
Short name T741
Test name
Test status
Simulation time 39546896 ps
CPU time 1.19 seconds
Started Dec 27 01:22:33 PM PST 23
Finished Dec 27 01:22:37 PM PST 23
Peak memory 196916 kb
Host smart-d45644db-bd4c-45b2-b7ff-9c782fddb011
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2132360376 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_smoke.2132360376
Directory /workspace/15.gpio_smoke/latest

Test location /workspace/coverage/default/15.gpio_smoke_no_pullup_pulldown.2037122768
Short name T332
Test name
Test status
Simulation time 192882762 ps
CPU time 0.8 seconds
Started Dec 27 01:22:36 PM PST 23
Finished Dec 27 01:22:38 PM PST 23
Peak memory 195228 kb
Host smart-08dd183f-fcd4-4470-8c00-c41cd7348901
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2037122768 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.gpio_smoke_no_pullup_pulldown.2037122768
Directory /workspace/15.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/15.gpio_stress_all.3283787161
Short name T268
Test name
Test status
Simulation time 1861077367 ps
CPU time 24.53 seconds
Started Dec 27 01:22:29 PM PST 23
Finished Dec 27 01:22:55 PM PST 23
Peak memory 198152 kb
Host smart-3eff86ab-8a15-4951-937d-69a517c495a0
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3283787161 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.
gpio_stress_all.3283787161
Directory /workspace/15.gpio_stress_all/latest

Test location /workspace/coverage/default/16.gpio_alert_test.1105763237
Short name T241
Test name
Test status
Simulation time 16678800 ps
CPU time 0.58 seconds
Started Dec 27 01:23:17 PM PST 23
Finished Dec 27 01:23:19 PM PST 23
Peak memory 194216 kb
Host smart-4cd47632-9679-4e4c-ba80-7fa7aa0846a2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1105763237 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_alert_test.1105763237
Directory /workspace/16.gpio_alert_test/latest

Test location /workspace/coverage/default/16.gpio_dout_din_regs_random_rw.923361113
Short name T765
Test name
Test status
Simulation time 101617447 ps
CPU time 0.7 seconds
Started Dec 27 01:22:51 PM PST 23
Finished Dec 27 01:22:52 PM PST 23
Peak memory 195280 kb
Host smart-70cbbd37-cd0d-46fe-b40e-9a43ea4982b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=923361113 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_dout_din_regs_random_rw.923361113
Directory /workspace/16.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/16.gpio_filter_stress.3171612670
Short name T328
Test name
Test status
Simulation time 112312324 ps
CPU time 3.53 seconds
Started Dec 27 01:22:47 PM PST 23
Finished Dec 27 01:22:51 PM PST 23
Peak memory 195740 kb
Host smart-90558989-cc27-48b6-9b8e-9099b3de86fc
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3171612670 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_filter_stre
ss.3171612670
Directory /workspace/16.gpio_filter_stress/latest

Test location /workspace/coverage/default/16.gpio_full_random.3177449141
Short name T513
Test name
Test status
Simulation time 86209536 ps
CPU time 0.79 seconds
Started Dec 27 01:22:55 PM PST 23
Finished Dec 27 01:22:57 PM PST 23
Peak memory 195932 kb
Host smart-5e939dcb-03f7-41db-92f6-cd43a75fc795
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3177449141 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_full_random.3177449141
Directory /workspace/16.gpio_full_random/latest

Test location /workspace/coverage/default/16.gpio_intr_rand_pgm.3483627258
Short name T639
Test name
Test status
Simulation time 33086541 ps
CPU time 0.73 seconds
Started Dec 27 01:23:20 PM PST 23
Finished Dec 27 01:23:22 PM PST 23
Peak memory 195396 kb
Host smart-9e5920a5-56f0-4fb3-bf24-4fe1ede13424
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3483627258 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_intr_rand_pgm.3483627258
Directory /workspace/16.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/16.gpio_intr_with_filter_rand_intr_event.407986786
Short name T511
Test name
Test status
Simulation time 89600028 ps
CPU time 2.28 seconds
Started Dec 27 01:23:19 PM PST 23
Finished Dec 27 01:23:22 PM PST 23
Peak memory 198124 kb
Host smart-f0aa846d-a5fe-46ab-908c-c05deb9065bc
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=407986786 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 16.gpio_intr_with_filter_rand_intr_event.407986786
Directory /workspace/16.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/16.gpio_rand_intr_trigger.3025899206
Short name T330
Test name
Test status
Simulation time 73786502 ps
CPU time 2.2 seconds
Started Dec 27 01:23:18 PM PST 23
Finished Dec 27 01:23:20 PM PST 23
Peak memory 195960 kb
Host smart-c4f04d7e-79c7-4e5b-959c-3a2e9f8e6e09
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3025899206 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_rand_intr_trigger
.3025899206
Directory /workspace/16.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/16.gpio_random_dout_din.2876661810
Short name T619
Test name
Test status
Simulation time 52900291 ps
CPU time 1.12 seconds
Started Dec 27 01:22:55 PM PST 23
Finished Dec 27 01:22:57 PM PST 23
Peak memory 196044 kb
Host smart-2718299e-b68e-46bb-9a61-ed0ed3cc5772
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2876661810 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_random_dout_din.2876661810
Directory /workspace/16.gpio_random_dout_din/latest

Test location /workspace/coverage/default/16.gpio_random_dout_din_no_pullup_pulldown.3054540463
Short name T504
Test name
Test status
Simulation time 75460020 ps
CPU time 0.83 seconds
Started Dec 27 01:22:48 PM PST 23
Finished Dec 27 01:22:50 PM PST 23
Peak memory 196604 kb
Host smart-66a3176e-30f5-48ac-af37-5ddc81291c5d
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3054540463 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_random_dout_din_no_pullu
p_pulldown.3054540463
Directory /workspace/16.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/16.gpio_random_long_reg_writes_reg_reads.2020107286
Short name T369
Test name
Test status
Simulation time 443331936 ps
CPU time 5.76 seconds
Started Dec 27 01:22:56 PM PST 23
Finished Dec 27 01:23:03 PM PST 23
Peak memory 198060 kb
Host smart-4f3ef94f-9908-4fc9-88bf-b57d73359a87
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2020107286 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_ra
ndom_long_reg_writes_reg_reads.2020107286
Directory /workspace/16.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/16.gpio_smoke.1187917038
Short name T716
Test name
Test status
Simulation time 54238778 ps
CPU time 0.7 seconds
Started Dec 27 01:22:54 PM PST 23
Finished Dec 27 01:22:56 PM PST 23
Peak memory 194244 kb
Host smart-58b7f88a-6a08-4f3d-b600-44af1f7284bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1187917038 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_smoke.1187917038
Directory /workspace/16.gpio_smoke/latest

Test location /workspace/coverage/default/16.gpio_smoke_no_pullup_pulldown.102247277
Short name T455
Test name
Test status
Simulation time 49227366 ps
CPU time 1.04 seconds
Started Dec 27 01:23:24 PM PST 23
Finished Dec 27 01:23:26 PM PST 23
Peak memory 196572 kb
Host smart-212dcbf0-02c9-41eb-8356-8c2e7c389b4c
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=102247277 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_smoke_no_pullup_pulldown.102247277
Directory /workspace/16.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/16.gpio_stress_all.108174147
Short name T878
Test name
Test status
Simulation time 11979747455 ps
CPU time 120.25 seconds
Started Dec 27 01:22:51 PM PST 23
Finished Dec 27 01:24:52 PM PST 23
Peak memory 198160 kb
Host smart-0306d015-9e17-46c7-adf7-c38cb6a5d891
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=108174147 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.g
pio_stress_all.108174147
Directory /workspace/16.gpio_stress_all/latest

Test location /workspace/coverage/default/16.gpio_stress_all_with_rand_reset.3799427537
Short name T295
Test name
Test status
Simulation time 49243288414 ps
CPU time 333.86 seconds
Started Dec 27 01:22:43 PM PST 23
Finished Dec 27 01:28:18 PM PST 23
Peak memory 198356 kb
Host smart-6ee847d3-53cf-4ede-87be-b7186b1e99fd
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=3799427537 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.gpio_stress_all_with_rand_reset.3799427537
Directory /workspace/16.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/17.gpio_alert_test.2284756969
Short name T763
Test name
Test status
Simulation time 37738807 ps
CPU time 0.6 seconds
Started Dec 27 01:22:58 PM PST 23
Finished Dec 27 01:22:59 PM PST 23
Peak memory 194980 kb
Host smart-ce981f71-4387-40bd-9ce5-050e656f1001
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2284756969 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_alert_test.2284756969
Directory /workspace/17.gpio_alert_test/latest

Test location /workspace/coverage/default/17.gpio_dout_din_regs_random_rw.495065635
Short name T705
Test name
Test status
Simulation time 167750721 ps
CPU time 0.83 seconds
Started Dec 27 01:22:56 PM PST 23
Finished Dec 27 01:22:58 PM PST 23
Peak memory 195400 kb
Host smart-9fee77aa-cb05-4514-b9d5-82605fc8985d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=495065635 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_dout_din_regs_random_rw.495065635
Directory /workspace/17.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/17.gpio_filter_stress.4013445959
Short name T805
Test name
Test status
Simulation time 2272010657 ps
CPU time 19.29 seconds
Started Dec 27 01:23:19 PM PST 23
Finished Dec 27 01:23:39 PM PST 23
Peak memory 197032 kb
Host smart-ebfc801a-2a6c-4ee5-ae10-881177d1a2f0
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4013445959 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_filter_stre
ss.4013445959
Directory /workspace/17.gpio_filter_stress/latest

Test location /workspace/coverage/default/17.gpio_full_random.1958805780
Short name T601
Test name
Test status
Simulation time 119217370 ps
CPU time 0.87 seconds
Started Dec 27 01:22:52 PM PST 23
Finished Dec 27 01:22:54 PM PST 23
Peak memory 197132 kb
Host smart-0a3d1221-5571-478d-84c1-7ebcc969fadf
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1958805780 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_full_random.1958805780
Directory /workspace/17.gpio_full_random/latest

Test location /workspace/coverage/default/17.gpio_intr_rand_pgm.4286105053
Short name T457
Test name
Test status
Simulation time 26565989 ps
CPU time 0.84 seconds
Started Dec 27 01:22:45 PM PST 23
Finished Dec 27 01:22:46 PM PST 23
Peak memory 195380 kb
Host smart-7d759a9a-3ef8-4953-afc1-af0bf1ad3cb2
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4286105053 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_intr_rand_pgm.4286105053
Directory /workspace/17.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/17.gpio_intr_with_filter_rand_intr_event.797988575
Short name T433
Test name
Test status
Simulation time 90221242 ps
CPU time 3.46 seconds
Started Dec 27 01:22:51 PM PST 23
Finished Dec 27 01:22:55 PM PST 23
Peak memory 198312 kb
Host smart-f68d29c0-806e-48e0-9790-142f9383c99d
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=797988575 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 17.gpio_intr_with_filter_rand_intr_event.797988575
Directory /workspace/17.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/17.gpio_rand_intr_trigger.1136916933
Short name T557
Test name
Test status
Simulation time 401276507 ps
CPU time 2.25 seconds
Started Dec 27 01:22:44 PM PST 23
Finished Dec 27 01:22:47 PM PST 23
Peak memory 195900 kb
Host smart-9a1b1062-7477-4ca3-bb2a-d841e207aace
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1136916933 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_rand_intr_trigger
.1136916933
Directory /workspace/17.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/17.gpio_random_dout_din.3619158453
Short name T269
Test name
Test status
Simulation time 33644331 ps
CPU time 0.82 seconds
Started Dec 27 01:22:43 PM PST 23
Finished Dec 27 01:22:45 PM PST 23
Peak memory 196456 kb
Host smart-6a6f642a-dc0e-48f3-af5c-7d2465ee9a09
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3619158453 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_random_dout_din.3619158453
Directory /workspace/17.gpio_random_dout_din/latest

Test location /workspace/coverage/default/17.gpio_random_dout_din_no_pullup_pulldown.37484069
Short name T456
Test name
Test status
Simulation time 42771594 ps
CPU time 0.98 seconds
Started Dec 27 01:23:18 PM PST 23
Finished Dec 27 01:23:20 PM PST 23
Peak memory 195852 kb
Host smart-9e0e2926-106d-4f07-ad1c-7ede62b7879b
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37484069 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_random_dout_din_no_pullup_
pulldown.37484069
Directory /workspace/17.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/17.gpio_random_long_reg_writes_reg_reads.169150862
Short name T508
Test name
Test status
Simulation time 93927581 ps
CPU time 4.27 seconds
Started Dec 27 01:23:19 PM PST 23
Finished Dec 27 01:23:23 PM PST 23
Peak memory 198028 kb
Host smart-62b491c0-34cc-45d2-907b-9b75eed96cf6
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=169150862 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_ran
dom_long_reg_writes_reg_reads.169150862
Directory /workspace/17.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/17.gpio_smoke.782300330
Short name T657
Test name
Test status
Simulation time 377612487 ps
CPU time 1.19 seconds
Started Dec 27 01:23:13 PM PST 23
Finished Dec 27 01:23:15 PM PST 23
Peak memory 195712 kb
Host smart-87eda9c5-9833-45e4-b21c-923a68521bff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=782300330 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_smoke.782300330
Directory /workspace/17.gpio_smoke/latest

Test location /workspace/coverage/default/17.gpio_smoke_no_pullup_pulldown.2228453761
Short name T370
Test name
Test status
Simulation time 67710467 ps
CPU time 1.1 seconds
Started Dec 27 01:22:49 PM PST 23
Finished Dec 27 01:22:51 PM PST 23
Peak memory 195776 kb
Host smart-338fa44e-6899-4734-a0c0-525ae5c49501
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2228453761 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_smoke_no_pullup_pulldown.2228453761
Directory /workspace/17.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/17.gpio_stress_all.1534323957
Short name T323
Test name
Test status
Simulation time 11838517954 ps
CPU time 85.01 seconds
Started Dec 27 01:22:55 PM PST 23
Finished Dec 27 01:24:21 PM PST 23
Peak memory 198200 kb
Host smart-f70acb53-d540-4086-a3ea-499ada1ef41f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1534323957 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.
gpio_stress_all.1534323957
Directory /workspace/17.gpio_stress_all/latest

Test location /workspace/coverage/default/17.gpio_stress_all_with_rand_reset.2204022810
Short name T290
Test name
Test status
Simulation time 60915824517 ps
CPU time 940.38 seconds
Started Dec 27 01:23:20 PM PST 23
Finished Dec 27 01:39:01 PM PST 23
Peak memory 198364 kb
Host smart-0be57a25-f937-4974-9b6d-0817f37321bd
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=2204022810 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.gpio_stress_all_with_rand_reset.2204022810
Directory /workspace/17.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/18.gpio_alert_test.2984987905
Short name T321
Test name
Test status
Simulation time 11844876 ps
CPU time 0.55 seconds
Started Dec 27 01:22:53 PM PST 23
Finished Dec 27 01:22:54 PM PST 23
Peak memory 194044 kb
Host smart-5b157e7a-165b-48b6-a64c-a147544c0844
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2984987905 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_alert_test.2984987905
Directory /workspace/18.gpio_alert_test/latest

Test location /workspace/coverage/default/18.gpio_dout_din_regs_random_rw.1029191692
Short name T288
Test name
Test status
Simulation time 43522211 ps
CPU time 0.85 seconds
Started Dec 27 01:22:46 PM PST 23
Finished Dec 27 01:22:47 PM PST 23
Peak memory 196384 kb
Host smart-3eb437ff-075d-4f30-8fa7-9a24bdcb651c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1029191692 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_dout_din_regs_random_rw.1029191692
Directory /workspace/18.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/18.gpio_filter_stress.2708976935
Short name T361
Test name
Test status
Simulation time 188586701 ps
CPU time 9.29 seconds
Started Dec 27 01:22:54 PM PST 23
Finished Dec 27 01:23:04 PM PST 23
Peak memory 197064 kb
Host smart-dd10010d-b54c-40e2-ae88-98c6fedbae32
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2708976935 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_filter_stre
ss.2708976935
Directory /workspace/18.gpio_filter_stress/latest

Test location /workspace/coverage/default/18.gpio_full_random.3761929250
Short name T877
Test name
Test status
Simulation time 233972579 ps
CPU time 0.82 seconds
Started Dec 27 01:22:54 PM PST 23
Finished Dec 27 01:22:56 PM PST 23
Peak memory 195756 kb
Host smart-00b41db3-7d8e-48a8-a19d-7ca6d7b674f3
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3761929250 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_full_random.3761929250
Directory /workspace/18.gpio_full_random/latest

Test location /workspace/coverage/default/18.gpio_intr_rand_pgm.3073093014
Short name T810
Test name
Test status
Simulation time 20862580 ps
CPU time 0.7 seconds
Started Dec 27 01:23:18 PM PST 23
Finished Dec 27 01:23:19 PM PST 23
Peak memory 194380 kb
Host smart-93049037-2b67-436a-989b-7598b5a185e7
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3073093014 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_intr_rand_pgm.3073093014
Directory /workspace/18.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/18.gpio_intr_with_filter_rand_intr_event.2614005899
Short name T301
Test name
Test status
Simulation time 472928653 ps
CPU time 1.21 seconds
Started Dec 27 01:23:19 PM PST 23
Finished Dec 27 01:23:20 PM PST 23
Peak memory 196436 kb
Host smart-0d9bdef7-d481-41bd-a50e-f29080f22166
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2614005899 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 18.gpio_intr_with_filter_rand_intr_event.2614005899
Directory /workspace/18.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/18.gpio_rand_intr_trigger.3093288125
Short name T490
Test name
Test status
Simulation time 103625365 ps
CPU time 2.92 seconds
Started Dec 27 01:22:56 PM PST 23
Finished Dec 27 01:23:00 PM PST 23
Peak memory 197148 kb
Host smart-26c15491-8c8d-40aa-9811-46dff90c6e0a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3093288125 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_rand_intr_trigger
.3093288125
Directory /workspace/18.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/18.gpio_random_dout_din.2375245903
Short name T473
Test name
Test status
Simulation time 418343424 ps
CPU time 1.23 seconds
Started Dec 27 01:22:51 PM PST 23
Finished Dec 27 01:22:53 PM PST 23
Peak memory 197260 kb
Host smart-0f6fef7f-9242-45aa-a05d-4d69fb2d0548
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2375245903 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_random_dout_din.2375245903
Directory /workspace/18.gpio_random_dout_din/latest

Test location /workspace/coverage/default/18.gpio_random_dout_din_no_pullup_pulldown.1574314434
Short name T888
Test name
Test status
Simulation time 33976080 ps
CPU time 0.92 seconds
Started Dec 27 01:22:53 PM PST 23
Finished Dec 27 01:22:55 PM PST 23
Peak memory 197152 kb
Host smart-c26d77ee-be5a-4f15-b5d9-28484bfd3a11
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1574314434 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_random_dout_din_no_pullu
p_pulldown.1574314434
Directory /workspace/18.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/18.gpio_random_long_reg_writes_reg_reads.97078961
Short name T67
Test name
Test status
Simulation time 1010069029 ps
CPU time 4.17 seconds
Started Dec 27 01:23:23 PM PST 23
Finished Dec 27 01:23:28 PM PST 23
Peak memory 198044 kb
Host smart-ef990fa7-0638-4200-9f9e-e1bbff70c03d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=97078961 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_w
rites_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_rand
om_long_reg_writes_reg_reads.97078961
Directory /workspace/18.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/18.gpio_smoke.2185428686
Short name T368
Test name
Test status
Simulation time 38021846 ps
CPU time 1.13 seconds
Started Dec 27 01:22:54 PM PST 23
Finished Dec 27 01:22:56 PM PST 23
Peak memory 196868 kb
Host smart-6b792a93-f80d-4678-a52d-9b51da914907
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2185428686 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_smoke.2185428686
Directory /workspace/18.gpio_smoke/latest

Test location /workspace/coverage/default/18.gpio_smoke_no_pullup_pulldown.2798414265
Short name T870
Test name
Test status
Simulation time 567850267 ps
CPU time 1.14 seconds
Started Dec 27 01:22:54 PM PST 23
Finished Dec 27 01:22:56 PM PST 23
Peak memory 196548 kb
Host smart-7f67c217-ba17-4c4a-a58b-6ce62c5e43d7
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2798414265 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_smoke_no_pullup_pulldown.2798414265
Directory /workspace/18.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/18.gpio_stress_all.3442793410
Short name T572
Test name
Test status
Simulation time 4090084015 ps
CPU time 45.23 seconds
Started Dec 27 01:22:55 PM PST 23
Finished Dec 27 01:23:41 PM PST 23
Peak memory 198244 kb
Host smart-df5b350f-8976-4b0e-9d14-5215fb065bb3
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3442793410 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.
gpio_stress_all.3442793410
Directory /workspace/18.gpio_stress_all/latest

Test location /workspace/coverage/default/18.gpio_stress_all_with_rand_reset.2998062035
Short name T466
Test name
Test status
Simulation time 187039904182 ps
CPU time 2682.85 seconds
Started Dec 27 01:23:25 PM PST 23
Finished Dec 27 02:08:10 PM PST 23
Peak memory 198404 kb
Host smart-fcd48720-d9ca-4c5b-8646-7e4463c4900a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=2998062035 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.gpio_stress_all_with_rand_reset.2998062035
Directory /workspace/18.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/19.gpio_alert_test.1824107904
Short name T672
Test name
Test status
Simulation time 59887936 ps
CPU time 0.56 seconds
Started Dec 27 01:22:53 PM PST 23
Finished Dec 27 01:22:54 PM PST 23
Peak memory 194300 kb
Host smart-ff04d7dc-cd99-46af-b3c1-7d2468753a1f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1824107904 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_alert_test.1824107904
Directory /workspace/19.gpio_alert_test/latest

Test location /workspace/coverage/default/19.gpio_dout_din_regs_random_rw.3083000915
Short name T538
Test name
Test status
Simulation time 20184887 ps
CPU time 0.72 seconds
Started Dec 27 01:23:27 PM PST 23
Finished Dec 27 01:23:28 PM PST 23
Peak memory 194140 kb
Host smart-e9ae8d1d-52bc-4aab-b202-75afb97daa80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3083000915 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_dout_din_regs_random_rw.3083000915
Directory /workspace/19.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/19.gpio_filter_stress.706558965
Short name T850
Test name
Test status
Simulation time 482126390 ps
CPU time 23.2 seconds
Started Dec 27 01:23:28 PM PST 23
Finished Dec 27 01:23:52 PM PST 23
Peak memory 197132 kb
Host smart-256d98fb-d4a3-409f-8821-14fda01d354e
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=706558965 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_filter_stres
s.706558965
Directory /workspace/19.gpio_filter_stress/latest

Test location /workspace/coverage/default/19.gpio_full_random.490414843
Short name T719
Test name
Test status
Simulation time 213428018 ps
CPU time 0.95 seconds
Started Dec 27 01:23:49 PM PST 23
Finished Dec 27 01:23:51 PM PST 23
Peak memory 196480 kb
Host smart-7e295754-af25-4255-be38-8a41963d4c4f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=490414843 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_full_random.490414843
Directory /workspace/19.gpio_full_random/latest

Test location /workspace/coverage/default/19.gpio_intr_rand_pgm.2111217811
Short name T435
Test name
Test status
Simulation time 385040339 ps
CPU time 1.4 seconds
Started Dec 27 01:23:47 PM PST 23
Finished Dec 27 01:23:49 PM PST 23
Peak memory 198116 kb
Host smart-61114b27-4554-473c-9afd-78761aef55b0
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2111217811 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_intr_rand_pgm.2111217811
Directory /workspace/19.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/19.gpio_intr_with_filter_rand_intr_event.1069241737
Short name T650
Test name
Test status
Simulation time 79793682 ps
CPU time 3.19 seconds
Started Dec 27 01:23:49 PM PST 23
Finished Dec 27 01:23:53 PM PST 23
Peak memory 198200 kb
Host smart-80b9b84d-90fa-4621-aff5-c9f1ce89d472
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1069241737 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 19.gpio_intr_with_filter_rand_intr_event.1069241737
Directory /workspace/19.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/19.gpio_rand_intr_trigger.3568652965
Short name T520
Test name
Test status
Simulation time 119998375 ps
CPU time 3.49 seconds
Started Dec 27 01:23:30 PM PST 23
Finished Dec 27 01:23:34 PM PST 23
Peak memory 198180 kb
Host smart-9ff9ad71-6a3a-445c-b35c-2f540451c280
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3568652965 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_rand_intr_trigger
.3568652965
Directory /workspace/19.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/19.gpio_random_dout_din.3813257907
Short name T739
Test name
Test status
Simulation time 30294572 ps
CPU time 0.89 seconds
Started Dec 27 01:23:24 PM PST 23
Finished Dec 27 01:23:25 PM PST 23
Peak memory 196752 kb
Host smart-f212586b-cb08-4393-ab69-80741627be5e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3813257907 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_random_dout_din.3813257907
Directory /workspace/19.gpio_random_dout_din/latest

Test location /workspace/coverage/default/19.gpio_random_dout_din_no_pullup_pulldown.1600246274
Short name T684
Test name
Test status
Simulation time 479681975 ps
CPU time 1.2 seconds
Started Dec 27 01:24:17 PM PST 23
Finished Dec 27 01:24:19 PM PST 23
Peak memory 196996 kb
Host smart-63cc49fd-014a-4044-9819-9f4cbf23e892
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1600246274 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_random_dout_din_no_pullu
p_pulldown.1600246274
Directory /workspace/19.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/19.gpio_random_long_reg_writes_reg_reads.2760008741
Short name T617
Test name
Test status
Simulation time 360136237 ps
CPU time 4.28 seconds
Started Dec 27 01:23:28 PM PST 23
Finished Dec 27 01:23:33 PM PST 23
Peak memory 198108 kb
Host smart-978c377d-d7ee-470f-9989-65cd134e1fed
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2760008741 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_ra
ndom_long_reg_writes_reg_reads.2760008741
Directory /workspace/19.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/19.gpio_smoke.1344866671
Short name T221
Test name
Test status
Simulation time 37620732 ps
CPU time 0.78 seconds
Started Dec 27 01:23:16 PM PST 23
Finished Dec 27 01:23:17 PM PST 23
Peak memory 195936 kb
Host smart-572c3c84-5a7a-4b3c-899d-778423b10ca8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1344866671 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_smoke.1344866671
Directory /workspace/19.gpio_smoke/latest

Test location /workspace/coverage/default/19.gpio_smoke_no_pullup_pulldown.317995387
Short name T225
Test name
Test status
Simulation time 61946164 ps
CPU time 1.16 seconds
Started Dec 27 01:23:24 PM PST 23
Finished Dec 27 01:23:26 PM PST 23
Peak memory 195604 kb
Host smart-b166a235-483c-4649-a91b-391fc1378c6d
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=317995387 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_smoke_no_pullup_pulldown.317995387
Directory /workspace/19.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/19.gpio_stress_all.4110359616
Short name T260
Test name
Test status
Simulation time 995647200 ps
CPU time 24.72 seconds
Started Dec 27 01:23:48 PM PST 23
Finished Dec 27 01:24:13 PM PST 23
Peak memory 198200 kb
Host smart-2f7e342c-9038-43f3-ad40-b9f78e1e54c2
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4110359616 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.
gpio_stress_all.4110359616
Directory /workspace/19.gpio_stress_all/latest

Test location /workspace/coverage/default/19.gpio_stress_all_with_rand_reset.2220816058
Short name T244
Test name
Test status
Simulation time 27600510581 ps
CPU time 390.05 seconds
Started Dec 27 01:23:28 PM PST 23
Finished Dec 27 01:29:59 PM PST 23
Peak memory 198380 kb
Host smart-46d72033-43a2-42aa-a0f2-74de87d9cd27
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=2220816058 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.gpio_stress_all_with_rand_reset.2220816058
Directory /workspace/19.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/2.gpio_alert_test.1592502320
Short name T708
Test name
Test status
Simulation time 66439435 ps
CPU time 0.58 seconds
Started Dec 27 01:22:00 PM PST 23
Finished Dec 27 01:22:01 PM PST 23
Peak memory 194200 kb
Host smart-73cfbaae-92ce-40cb-b51f-d31b44b0521d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1592502320 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_alert_test.1592502320
Directory /workspace/2.gpio_alert_test/latest

Test location /workspace/coverage/default/2.gpio_dout_din_regs_random_rw.4111786401
Short name T698
Test name
Test status
Simulation time 123922545 ps
CPU time 0.77 seconds
Started Dec 27 01:21:17 PM PST 23
Finished Dec 27 01:21:19 PM PST 23
Peak memory 195244 kb
Host smart-ddeda675-95af-4b98-8aeb-1d061895b7b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4111786401 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_dout_din_regs_random_rw.4111786401
Directory /workspace/2.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/2.gpio_filter_stress.2229810230
Short name T222
Test name
Test status
Simulation time 543100465 ps
CPU time 15.96 seconds
Started Dec 27 01:22:02 PM PST 23
Finished Dec 27 01:22:18 PM PST 23
Peak memory 196864 kb
Host smart-bc101f9e-cafe-425e-8cd4-f2c0c78b6c8f
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2229810230 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_filter_stres
s.2229810230
Directory /workspace/2.gpio_filter_stress/latest

Test location /workspace/coverage/default/2.gpio_full_random.2762839509
Short name T352
Test name
Test status
Simulation time 43691257 ps
CPU time 0.79 seconds
Started Dec 27 01:22:03 PM PST 23
Finished Dec 27 01:22:04 PM PST 23
Peak memory 196628 kb
Host smart-f9b4beeb-9e0a-4db8-9fc0-fc3721f91ec3
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2762839509 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_full_random.2762839509
Directory /workspace/2.gpio_full_random/latest

Test location /workspace/coverage/default/2.gpio_intr_rand_pgm.2943238763
Short name T666
Test name
Test status
Simulation time 90750029 ps
CPU time 1.29 seconds
Started Dec 27 01:21:15 PM PST 23
Finished Dec 27 01:21:16 PM PST 23
Peak memory 198032 kb
Host smart-c9b8cf6c-8e1c-4004-aefd-9c590351c9d3
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2943238763 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_intr_rand_pgm.2943238763
Directory /workspace/2.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/2.gpio_intr_with_filter_rand_intr_event.1870104396
Short name T565
Test name
Test status
Simulation time 179355720 ps
CPU time 2.88 seconds
Started Dec 27 01:21:51 PM PST 23
Finished Dec 27 01:21:54 PM PST 23
Peak memory 198064 kb
Host smart-2ce6d436-6a1d-4f1c-8833-f074ec7d7028
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1870104396 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 2.gpio_intr_with_filter_rand_intr_event.1870104396
Directory /workspace/2.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/2.gpio_rand_intr_trigger.2977882963
Short name T554
Test name
Test status
Simulation time 59611650 ps
CPU time 1.06 seconds
Started Dec 27 01:21:56 PM PST 23
Finished Dec 27 01:21:58 PM PST 23
Peak memory 196448 kb
Host smart-501d4355-cb47-4477-af38-08059cb73927
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2977882963 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_rand_intr_trigger.
2977882963
Directory /workspace/2.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/2.gpio_random_dout_din.3134375220
Short name T528
Test name
Test status
Simulation time 62839167 ps
CPU time 0.82 seconds
Started Dec 27 01:21:15 PM PST 23
Finished Dec 27 01:21:16 PM PST 23
Peak memory 196408 kb
Host smart-747f5ffb-d0ba-40a4-b91c-892c93875f2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3134375220 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_random_dout_din.3134375220
Directory /workspace/2.gpio_random_dout_din/latest

Test location /workspace/coverage/default/2.gpio_random_dout_din_no_pullup_pulldown.1633967725
Short name T576
Test name
Test status
Simulation time 29198942 ps
CPU time 0.72 seconds
Started Dec 27 01:21:54 PM PST 23
Finished Dec 27 01:21:56 PM PST 23
Peak memory 195404 kb
Host smart-8d25ab09-3a82-4563-ab13-6144ab47987d
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1633967725 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_random_dout_din_no_pullup
_pulldown.1633967725
Directory /workspace/2.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/2.gpio_random_long_reg_writes_reg_reads.110023080
Short name T333
Test name
Test status
Simulation time 632850442 ps
CPU time 4.84 seconds
Started Dec 27 01:22:03 PM PST 23
Finished Dec 27 01:22:09 PM PST 23
Peak memory 198088 kb
Host smart-9f453ffb-189a-4f45-8a23-38468270fa88
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=110023080 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_rand
om_long_reg_writes_reg_reads.110023080
Directory /workspace/2.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/2.gpio_sec_cm.4164259102
Short name T29
Test name
Test status
Simulation time 32140197 ps
CPU time 0.76 seconds
Started Dec 27 01:22:03 PM PST 23
Finished Dec 27 01:22:05 PM PST 23
Peak memory 213388 kb
Host smart-db3530ce-3ff3-4a9c-95cf-216e8aeba097
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4164259102 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_sec_cm.4164259102
Directory /workspace/2.gpio_sec_cm/latest

Test location /workspace/coverage/default/2.gpio_smoke.2259853422
Short name T821
Test name
Test status
Simulation time 64773635 ps
CPU time 1.11 seconds
Started Dec 27 01:21:18 PM PST 23
Finished Dec 27 01:21:20 PM PST 23
Peak memory 195944 kb
Host smart-d74b0389-2bbd-412e-b146-60ac86ec7d77
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2259853422 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_smoke.2259853422
Directory /workspace/2.gpio_smoke/latest

Test location /workspace/coverage/default/2.gpio_smoke_no_pullup_pulldown.1051080247
Short name T727
Test name
Test status
Simulation time 168367162 ps
CPU time 1.21 seconds
Started Dec 27 01:21:53 PM PST 23
Finished Dec 27 01:21:55 PM PST 23
Peak memory 196616 kb
Host smart-130caffd-0776-44de-8938-703d3a6bf630
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1051080247 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_smoke_no_pullup_pulldown.1051080247
Directory /workspace/2.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/2.gpio_stress_all.3982859107
Short name T256
Test name
Test status
Simulation time 22232267592 ps
CPU time 53.79 seconds
Started Dec 27 01:22:08 PM PST 23
Finished Dec 27 01:23:06 PM PST 23
Peak memory 198112 kb
Host smart-4b3749f7-286b-465f-af4c-9766d8f4a8ac
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3982859107 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.g
pio_stress_all.3982859107
Directory /workspace/2.gpio_stress_all/latest

Test location /workspace/coverage/default/2.gpio_stress_all_with_rand_reset.1681043160
Short name T229
Test name
Test status
Simulation time 212607536409 ps
CPU time 1297.54 seconds
Started Dec 27 01:21:53 PM PST 23
Finished Dec 27 01:43:32 PM PST 23
Peak memory 198332 kb
Host smart-b206d0be-49a9-4ce7-8738-3b3b82ae6065
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=1681043160 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.gpio_stress_all_with_rand_reset.1681043160
Directory /workspace/2.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/20.gpio_alert_test.458794249
Short name T357
Test name
Test status
Simulation time 61083725 ps
CPU time 0.58 seconds
Started Dec 27 01:23:29 PM PST 23
Finished Dec 27 01:23:30 PM PST 23
Peak memory 194940 kb
Host smart-888ac562-86af-4dd7-8bda-6cf134087e63
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=458794249 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_alert_test.458794249
Directory /workspace/20.gpio_alert_test/latest

Test location /workspace/coverage/default/20.gpio_dout_din_regs_random_rw.1325143661
Short name T237
Test name
Test status
Simulation time 21324527 ps
CPU time 0.68 seconds
Started Dec 27 01:23:29 PM PST 23
Finished Dec 27 01:23:30 PM PST 23
Peak memory 194732 kb
Host smart-a39ea423-da6a-4aa5-8209-7591396fe320
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1325143661 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_dout_din_regs_random_rw.1325143661
Directory /workspace/20.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/20.gpio_filter_stress.3389180736
Short name T387
Test name
Test status
Simulation time 3161838026 ps
CPU time 27.97 seconds
Started Dec 27 01:23:51 PM PST 23
Finished Dec 27 01:24:20 PM PST 23
Peak memory 197212 kb
Host smart-8b192b19-de39-4f37-af9d-80bcc68f6c0a
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3389180736 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_filter_stre
ss.3389180736
Directory /workspace/20.gpio_filter_stress/latest

Test location /workspace/coverage/default/20.gpio_full_random.128925275
Short name T410
Test name
Test status
Simulation time 57986685 ps
CPU time 0.91 seconds
Started Dec 27 01:23:49 PM PST 23
Finished Dec 27 01:23:50 PM PST 23
Peak memory 197308 kb
Host smart-15ba8729-548d-409b-a5b2-6c5721292484
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=128925275 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_full_random.128925275
Directory /workspace/20.gpio_full_random/latest

Test location /workspace/coverage/default/20.gpio_intr_rand_pgm.2964676502
Short name T744
Test name
Test status
Simulation time 100448765 ps
CPU time 1.02 seconds
Started Dec 27 01:24:13 PM PST 23
Finished Dec 27 01:24:15 PM PST 23
Peak memory 196920 kb
Host smart-90d4deaa-c201-4289-b9fa-681eefb77b47
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2964676502 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_intr_rand_pgm.2964676502
Directory /workspace/20.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/20.gpio_intr_with_filter_rand_intr_event.870204082
Short name T840
Test name
Test status
Simulation time 164925346 ps
CPU time 3.24 seconds
Started Dec 27 01:23:56 PM PST 23
Finished Dec 27 01:24:01 PM PST 23
Peak memory 198044 kb
Host smart-bebcda2d-e41e-46aa-9c28-b15a0be17263
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=870204082 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 20.gpio_intr_with_filter_rand_intr_event.870204082
Directory /workspace/20.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/20.gpio_rand_intr_trigger.3869469518
Short name T824
Test name
Test status
Simulation time 91361431 ps
CPU time 1.87 seconds
Started Dec 27 01:23:52 PM PST 23
Finished Dec 27 01:23:55 PM PST 23
Peak memory 196116 kb
Host smart-51e11c41-ea5d-47ed-aedc-d4f830693bd9
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3869469518 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_rand_intr_trigger
.3869469518
Directory /workspace/20.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/20.gpio_random_dout_din.1354275774
Short name T279
Test name
Test status
Simulation time 34982030 ps
CPU time 0.85 seconds
Started Dec 27 01:23:49 PM PST 23
Finished Dec 27 01:23:51 PM PST 23
Peak memory 195960 kb
Host smart-1c70030b-bdcf-45f1-b5ee-26f4d7df1666
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1354275774 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_random_dout_din.1354275774
Directory /workspace/20.gpio_random_dout_din/latest

Test location /workspace/coverage/default/20.gpio_random_dout_din_no_pullup_pulldown.3928198211
Short name T336
Test name
Test status
Simulation time 59968128 ps
CPU time 0.8 seconds
Started Dec 27 01:23:48 PM PST 23
Finished Dec 27 01:23:49 PM PST 23
Peak memory 196192 kb
Host smart-b2031354-3387-42c0-ab57-d7e81b3ea8de
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3928198211 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_random_dout_din_no_pullu
p_pulldown.3928198211
Directory /workspace/20.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/20.gpio_random_long_reg_writes_reg_reads.1588441958
Short name T621
Test name
Test status
Simulation time 230371502 ps
CPU time 3.78 seconds
Started Dec 27 01:23:52 PM PST 23
Finished Dec 27 01:23:58 PM PST 23
Peak memory 198036 kb
Host smart-fce2e318-6c2a-4d7f-9b11-bde05db10138
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1588441958 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_ra
ndom_long_reg_writes_reg_reads.1588441958
Directory /workspace/20.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/20.gpio_smoke.3576648016
Short name T235
Test name
Test status
Simulation time 358560404 ps
CPU time 1.16 seconds
Started Dec 27 01:23:24 PM PST 23
Finished Dec 27 01:23:25 PM PST 23
Peak memory 196740 kb
Host smart-1fcf2400-c4f1-47c5-b433-44594d7a965a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3576648016 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_smoke.3576648016
Directory /workspace/20.gpio_smoke/latest

Test location /workspace/coverage/default/20.gpio_smoke_no_pullup_pulldown.1428999955
Short name T479
Test name
Test status
Simulation time 21969737 ps
CPU time 0.84 seconds
Started Dec 27 01:24:24 PM PST 23
Finished Dec 27 01:24:25 PM PST 23
Peak memory 195960 kb
Host smart-3ee7846a-edc8-4cf8-bf7e-75f4a9a98d3b
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1428999955 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_smoke_no_pullup_pulldown.1428999955
Directory /workspace/20.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/20.gpio_stress_all.3547894016
Short name T890
Test name
Test status
Simulation time 25514190994 ps
CPU time 140.46 seconds
Started Dec 27 01:23:53 PM PST 23
Finished Dec 27 01:26:15 PM PST 23
Peak memory 198268 kb
Host smart-5fc06b42-b230-4ac1-b2f0-b87eca2203a2
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3547894016 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.
gpio_stress_all.3547894016
Directory /workspace/20.gpio_stress_all/latest

Test location /workspace/coverage/default/20.gpio_stress_all_with_rand_reset.717962271
Short name T257
Test name
Test status
Simulation time 83574649942 ps
CPU time 255.64 seconds
Started Dec 27 01:24:13 PM PST 23
Finished Dec 27 01:28:29 PM PST 23
Peak memory 198300 kb
Host smart-5b1480ac-edfb-40eb-81c9-78f81eef92d1
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=717962271 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.gpio_stress_all_with_rand_reset.717962271
Directory /workspace/20.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/21.gpio_alert_test.1008178165
Short name T517
Test name
Test status
Simulation time 25305563 ps
CPU time 0.56 seconds
Started Dec 27 01:24:25 PM PST 23
Finished Dec 27 01:24:32 PM PST 23
Peak memory 193908 kb
Host smart-8ed492c6-f43c-422c-bbbe-a34e29b7f18f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1008178165 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_alert_test.1008178165
Directory /workspace/21.gpio_alert_test/latest

Test location /workspace/coverage/default/21.gpio_dout_din_regs_random_rw.2958538566
Short name T489
Test name
Test status
Simulation time 29956021 ps
CPU time 0.84 seconds
Started Dec 27 01:24:11 PM PST 23
Finished Dec 27 01:24:13 PM PST 23
Peak memory 196580 kb
Host smart-bd859554-a8aa-4e9d-8eab-1ba63a485a6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2958538566 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_dout_din_regs_random_rw.2958538566
Directory /workspace/21.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/21.gpio_filter_stress.3574286622
Short name T354
Test name
Test status
Simulation time 283536596 ps
CPU time 14.38 seconds
Started Dec 27 01:24:41 PM PST 23
Finished Dec 27 01:24:56 PM PST 23
Peak memory 198096 kb
Host smart-39998f1b-bba2-48c8-8b1b-d2889a11295f
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3574286622 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_filter_stre
ss.3574286622
Directory /workspace/21.gpio_filter_stress/latest

Test location /workspace/coverage/default/21.gpio_full_random.3911686446
Short name T436
Test name
Test status
Simulation time 343623515 ps
CPU time 1.03 seconds
Started Dec 27 01:24:44 PM PST 23
Finished Dec 27 01:24:50 PM PST 23
Peak memory 196816 kb
Host smart-76bd2404-8554-46ca-a281-2da5882ba1af
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3911686446 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_full_random.3911686446
Directory /workspace/21.gpio_full_random/latest

Test location /workspace/coverage/default/21.gpio_intr_rand_pgm.2090410329
Short name T731
Test name
Test status
Simulation time 62481318 ps
CPU time 1.04 seconds
Started Dec 27 01:24:22 PM PST 23
Finished Dec 27 01:24:24 PM PST 23
Peak memory 195932 kb
Host smart-9e86b966-bce2-4de2-97af-1122ffa6fd43
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2090410329 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_intr_rand_pgm.2090410329
Directory /workspace/21.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/21.gpio_intr_with_filter_rand_intr_event.2249550067
Short name T418
Test name
Test status
Simulation time 54788746 ps
CPU time 2.17 seconds
Started Dec 27 01:24:51 PM PST 23
Finished Dec 27 01:24:56 PM PST 23
Peak memory 198112 kb
Host smart-7730d47c-2aa5-4975-98b6-00378c806207
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2249550067 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 21.gpio_intr_with_filter_rand_intr_event.2249550067
Directory /workspace/21.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/21.gpio_rand_intr_trigger.1393240395
Short name T307
Test name
Test status
Simulation time 35158423 ps
CPU time 1.18 seconds
Started Dec 27 01:23:51 PM PST 23
Finished Dec 27 01:23:53 PM PST 23
Peak memory 195540 kb
Host smart-1a9ee22c-1d00-42d1-8051-d42193c5fcf8
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1393240395 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_rand_intr_trigger
.1393240395
Directory /workspace/21.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/21.gpio_random_dout_din.3997111750
Short name T480
Test name
Test status
Simulation time 159446454 ps
CPU time 1.22 seconds
Started Dec 27 01:24:59 PM PST 23
Finished Dec 27 01:25:01 PM PST 23
Peak memory 197164 kb
Host smart-059b7489-247a-483a-a4ff-ff09a3c7ac9b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3997111750 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_random_dout_din.3997111750
Directory /workspace/21.gpio_random_dout_din/latest

Test location /workspace/coverage/default/21.gpio_random_dout_din_no_pullup_pulldown.1655315894
Short name T678
Test name
Test status
Simulation time 57684618 ps
CPU time 0.8 seconds
Started Dec 27 01:23:50 PM PST 23
Finished Dec 27 01:23:52 PM PST 23
Peak memory 196232 kb
Host smart-6dc3338a-65ec-45f7-8eab-58c8f13859e2
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1655315894 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_random_dout_din_no_pullu
p_pulldown.1655315894
Directory /workspace/21.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/21.gpio_random_long_reg_writes_reg_reads.3354545360
Short name T577
Test name
Test status
Simulation time 887092023 ps
CPU time 2.88 seconds
Started Dec 27 01:24:26 PM PST 23
Finished Dec 27 01:24:35 PM PST 23
Peak memory 198104 kb
Host smart-0b50e6ea-3f1f-4c97-9064-8b75b5373b7e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3354545360 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_ra
ndom_long_reg_writes_reg_reads.3354545360
Directory /workspace/21.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/21.gpio_smoke.4027637299
Short name T309
Test name
Test status
Simulation time 123621316 ps
CPU time 0.93 seconds
Started Dec 27 01:23:46 PM PST 23
Finished Dec 27 01:23:47 PM PST 23
Peak memory 196520 kb
Host smart-73522df1-3636-4d6f-9907-9ec43069de61
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4027637299 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_smoke.4027637299
Directory /workspace/21.gpio_smoke/latest

Test location /workspace/coverage/default/21.gpio_smoke_no_pullup_pulldown.1933243755
Short name T700
Test name
Test status
Simulation time 94068225 ps
CPU time 0.85 seconds
Started Dec 27 01:24:09 PM PST 23
Finished Dec 27 01:24:10 PM PST 23
Peak memory 196300 kb
Host smart-9465a555-30c5-4c31-891c-482fb0b6c08d
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1933243755 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_smoke_no_pullup_pulldown.1933243755
Directory /workspace/21.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/21.gpio_stress_all.2769609068
Short name T246
Test name
Test status
Simulation time 51334648713 ps
CPU time 72.86 seconds
Started Dec 27 01:23:57 PM PST 23
Finished Dec 27 01:25:10 PM PST 23
Peak memory 198248 kb
Host smart-d79f57c9-f3ae-4131-b74a-532f479a808a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2769609068 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.
gpio_stress_all.2769609068
Directory /workspace/21.gpio_stress_all/latest

Test location /workspace/coverage/default/21.gpio_stress_all_with_rand_reset.4012610815
Short name T580
Test name
Test status
Simulation time 343443532673 ps
CPU time 1059 seconds
Started Dec 27 01:23:54 PM PST 23
Finished Dec 27 01:41:34 PM PST 23
Peak memory 198392 kb
Host smart-bfa93b77-4329-427a-8bac-4877ef200103
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=4012610815 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.gpio_stress_all_with_rand_reset.4012610815
Directory /workspace/21.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/22.gpio_alert_test.118544567
Short name T385
Test name
Test status
Simulation time 42769390 ps
CPU time 0.56 seconds
Started Dec 27 01:23:52 PM PST 23
Finished Dec 27 01:23:54 PM PST 23
Peak memory 194668 kb
Host smart-68308a3d-3310-41db-b559-47bd8aa9317a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=118544567 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_alert_test.118544567
Directory /workspace/22.gpio_alert_test/latest

Test location /workspace/coverage/default/22.gpio_dout_din_regs_random_rw.3587865071
Short name T766
Test name
Test status
Simulation time 84427231 ps
CPU time 0.8 seconds
Started Dec 27 01:24:20 PM PST 23
Finished Dec 27 01:24:22 PM PST 23
Peak memory 196044 kb
Host smart-d54feec8-cbf1-45ca-8247-049591ab2f18
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3587865071 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_dout_din_regs_random_rw.3587865071
Directory /workspace/22.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/22.gpio_filter_stress.342267124
Short name T683
Test name
Test status
Simulation time 300368244 ps
CPU time 7.9 seconds
Started Dec 27 01:24:18 PM PST 23
Finished Dec 27 01:24:27 PM PST 23
Peak memory 196964 kb
Host smart-41c7d119-d2dc-44e4-92c8-7b36162020c0
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=342267124 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_filter_stres
s.342267124
Directory /workspace/22.gpio_filter_stress/latest

Test location /workspace/coverage/default/22.gpio_full_random.3666763140
Short name T714
Test name
Test status
Simulation time 272417501 ps
CPU time 0.87 seconds
Started Dec 27 01:23:51 PM PST 23
Finished Dec 27 01:23:53 PM PST 23
Peak memory 196116 kb
Host smart-3709a5d6-a8dd-4afa-b4be-0cce3e74fb49
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3666763140 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_full_random.3666763140
Directory /workspace/22.gpio_full_random/latest

Test location /workspace/coverage/default/22.gpio_intr_rand_pgm.3697091018
Short name T426
Test name
Test status
Simulation time 173937716 ps
CPU time 1.31 seconds
Started Dec 27 01:23:55 PM PST 23
Finished Dec 27 01:23:57 PM PST 23
Peak memory 197112 kb
Host smart-d785e623-fd2d-41ee-a1ec-7b8e334d0b91
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3697091018 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_intr_rand_pgm.3697091018
Directory /workspace/22.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/22.gpio_intr_with_filter_rand_intr_event.550159359
Short name T668
Test name
Test status
Simulation time 43083746 ps
CPU time 1.68 seconds
Started Dec 27 01:23:46 PM PST 23
Finished Dec 27 01:23:49 PM PST 23
Peak memory 198084 kb
Host smart-0b279ad4-4eb5-4ebb-b304-599a75dc5319
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=550159359 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 22.gpio_intr_with_filter_rand_intr_event.550159359
Directory /workspace/22.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/22.gpio_rand_intr_trigger.3156266725
Short name T804
Test name
Test status
Simulation time 54295867 ps
CPU time 1.8 seconds
Started Dec 27 01:24:15 PM PST 23
Finished Dec 27 01:24:18 PM PST 23
Peak memory 196176 kb
Host smart-f6f6dfca-5699-4667-9a30-2694955033da
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3156266725 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_rand_intr_trigger
.3156266725
Directory /workspace/22.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/22.gpio_random_dout_din.2400616544
Short name T390
Test name
Test status
Simulation time 43552707 ps
CPU time 1.07 seconds
Started Dec 27 01:24:18 PM PST 23
Finished Dec 27 01:24:20 PM PST 23
Peak memory 195852 kb
Host smart-4b3985a4-7bb2-420b-b5af-ea5c8e8040df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2400616544 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_random_dout_din.2400616544
Directory /workspace/22.gpio_random_dout_din/latest

Test location /workspace/coverage/default/22.gpio_random_dout_din_no_pullup_pulldown.1729635829
Short name T430
Test name
Test status
Simulation time 258418360 ps
CPU time 1.28 seconds
Started Dec 27 01:23:55 PM PST 23
Finished Dec 27 01:23:57 PM PST 23
Peak memory 196716 kb
Host smart-f4f8b4f7-592d-4e87-9ed7-72ab0de85a13
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1729635829 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_random_dout_din_no_pullu
p_pulldown.1729635829
Directory /workspace/22.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/22.gpio_random_long_reg_writes_reg_reads.1004000567
Short name T690
Test name
Test status
Simulation time 381830545 ps
CPU time 5.98 seconds
Started Dec 27 01:23:51 PM PST 23
Finished Dec 27 01:23:59 PM PST 23
Peak memory 198100 kb
Host smart-4eb5b521-d420-4737-b34f-1ffa82de8063
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1004000567 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_ra
ndom_long_reg_writes_reg_reads.1004000567
Directory /workspace/22.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/22.gpio_smoke.1161178180
Short name T395
Test name
Test status
Simulation time 77940613 ps
CPU time 0.98 seconds
Started Dec 27 01:24:35 PM PST 23
Finished Dec 27 01:24:36 PM PST 23
Peak memory 196528 kb
Host smart-2a49541f-9105-4fc6-b704-63b5f5c8d6b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1161178180 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_smoke.1161178180
Directory /workspace/22.gpio_smoke/latest

Test location /workspace/coverage/default/22.gpio_smoke_no_pullup_pulldown.4283128176
Short name T434
Test name
Test status
Simulation time 41113302 ps
CPU time 0.79 seconds
Started Dec 27 01:24:38 PM PST 23
Finished Dec 27 01:24:42 PM PST 23
Peak memory 195368 kb
Host smart-ac1dfd10-1425-4b68-b892-66e877c435a5
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4283128176 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_smoke_no_pullup_pulldown.4283128176
Directory /workspace/22.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/22.gpio_stress_all.3613325558
Short name T644
Test name
Test status
Simulation time 6734811530 ps
CPU time 103.73 seconds
Started Dec 27 01:23:49 PM PST 23
Finished Dec 27 01:25:34 PM PST 23
Peak memory 198244 kb
Host smart-b38637d1-7db1-493d-bcea-4e332d9a1813
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3613325558 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.
gpio_stress_all.3613325558
Directory /workspace/22.gpio_stress_all/latest

Test location /workspace/coverage/default/22.gpio_stress_all_with_rand_reset.4246248245
Short name T400
Test name
Test status
Simulation time 15638355742 ps
CPU time 379.01 seconds
Started Dec 27 01:23:53 PM PST 23
Finished Dec 27 01:30:14 PM PST 23
Peak memory 198392 kb
Host smart-9b7bae4f-b2e4-4ecf-b8eb-b7468b26e280
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=4246248245 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.gpio_stress_all_with_rand_reset.4246248245
Directory /workspace/22.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/23.gpio_alert_test.1090464526
Short name T533
Test name
Test status
Simulation time 71354181 ps
CPU time 0.58 seconds
Started Dec 27 01:24:33 PM PST 23
Finished Dec 27 01:24:34 PM PST 23
Peak memory 194048 kb
Host smart-a7686cc7-cf70-4c37-86f8-9ef947b49d48
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1090464526 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_alert_test.1090464526
Directory /workspace/23.gpio_alert_test/latest

Test location /workspace/coverage/default/23.gpio_dout_din_regs_random_rw.3886042092
Short name T589
Test name
Test status
Simulation time 32167457 ps
CPU time 0.61 seconds
Started Dec 27 01:24:22 PM PST 23
Finished Dec 27 01:24:23 PM PST 23
Peak memory 194072 kb
Host smart-45168355-8390-4593-8dfb-8a06d0036d51
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3886042092 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_dout_din_regs_random_rw.3886042092
Directory /workspace/23.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/23.gpio_filter_stress.74683004
Short name T828
Test name
Test status
Simulation time 2385883688 ps
CPU time 21.35 seconds
Started Dec 27 01:24:48 PM PST 23
Finished Dec 27 01:25:12 PM PST 23
Peak memory 198252 kb
Host smart-773dfa7c-4182-48ae-bf38-3ea32f830780
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=74683004 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter_
stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_filter_stress
.74683004
Directory /workspace/23.gpio_filter_stress/latest

Test location /workspace/coverage/default/23.gpio_full_random.1916569943
Short name T816
Test name
Test status
Simulation time 113507839 ps
CPU time 0.63 seconds
Started Dec 27 01:24:51 PM PST 23
Finished Dec 27 01:24:54 PM PST 23
Peak memory 195224 kb
Host smart-beeab87a-323e-4c71-bb33-55830145fd09
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1916569943 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_full_random.1916569943
Directory /workspace/23.gpio_full_random/latest

Test location /workspace/coverage/default/23.gpio_intr_rand_pgm.550597270
Short name T612
Test name
Test status
Simulation time 35476179 ps
CPU time 1.03 seconds
Started Dec 27 01:24:32 PM PST 23
Finished Dec 27 01:24:34 PM PST 23
Peak memory 195904 kb
Host smart-b65537fe-58f2-4413-99a8-077bd785a63e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=550597270 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_intr_rand_pgm.550597270
Directory /workspace/23.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/23.gpio_intr_with_filter_rand_intr_event.1980978712
Short name T465
Test name
Test status
Simulation time 58884698 ps
CPU time 1.34 seconds
Started Dec 27 01:24:30 PM PST 23
Finished Dec 27 01:24:32 PM PST 23
Peak memory 196960 kb
Host smart-040131f4-4cfa-4276-90fd-e22dd40622bb
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1980978712 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 23.gpio_intr_with_filter_rand_intr_event.1980978712
Directory /workspace/23.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/23.gpio_rand_intr_trigger.4136565206
Short name T367
Test name
Test status
Simulation time 354885424 ps
CPU time 3.44 seconds
Started Dec 27 01:24:30 PM PST 23
Finished Dec 27 01:24:34 PM PST 23
Peak memory 197040 kb
Host smart-4733eb8e-ccba-4335-84b2-4fe43a45985c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4136565206 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_rand_intr_trigger
.4136565206
Directory /workspace/23.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/23.gpio_random_dout_din.1459882007
Short name T482
Test name
Test status
Simulation time 22008895 ps
CPU time 0.73 seconds
Started Dec 27 01:23:57 PM PST 23
Finished Dec 27 01:23:59 PM PST 23
Peak memory 195416 kb
Host smart-9d090dfa-add4-48c8-ad5d-aa08f7987df1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1459882007 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_random_dout_din.1459882007
Directory /workspace/23.gpio_random_dout_din/latest

Test location /workspace/coverage/default/23.gpio_random_dout_din_no_pullup_pulldown.3324094262
Short name T287
Test name
Test status
Simulation time 20575523 ps
CPU time 0.75 seconds
Started Dec 27 01:24:34 PM PST 23
Finished Dec 27 01:24:36 PM PST 23
Peak memory 195344 kb
Host smart-b7f741e6-abf1-44ee-95ba-6ebca279462c
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3324094262 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_random_dout_din_no_pullu
p_pulldown.3324094262
Directory /workspace/23.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/23.gpio_random_long_reg_writes_reg_reads.3308588572
Short name T306
Test name
Test status
Simulation time 332114029 ps
CPU time 3.78 seconds
Started Dec 27 01:24:47 PM PST 23
Finished Dec 27 01:24:54 PM PST 23
Peak memory 198148 kb
Host smart-8c8b2831-ef5d-479d-8bd5-b2bef8a2b4a2
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3308588572 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_ra
ndom_long_reg_writes_reg_reads.3308588572
Directory /workspace/23.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/23.gpio_smoke.3798166463
Short name T275
Test name
Test status
Simulation time 121416664 ps
CPU time 0.77 seconds
Started Dec 27 01:23:52 PM PST 23
Finished Dec 27 01:23:54 PM PST 23
Peak memory 195124 kb
Host smart-754f69bf-3ec9-4233-9bd0-2d97ea443360
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3798166463 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_smoke.3798166463
Directory /workspace/23.gpio_smoke/latest

Test location /workspace/coverage/default/23.gpio_smoke_no_pullup_pulldown.2950953636
Short name T791
Test name
Test status
Simulation time 276331422 ps
CPU time 1.4 seconds
Started Dec 27 01:23:56 PM PST 23
Finished Dec 27 01:23:58 PM PST 23
Peak memory 196872 kb
Host smart-379e2725-09c4-4fa9-aad2-a76bfd9251fd
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2950953636 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_smoke_no_pullup_pulldown.2950953636
Directory /workspace/23.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/23.gpio_stress_all.2122711799
Short name T697
Test name
Test status
Simulation time 11541438518 ps
CPU time 171.49 seconds
Started Dec 27 01:23:56 PM PST 23
Finished Dec 27 01:26:49 PM PST 23
Peak memory 198272 kb
Host smart-ef5cbe99-eb29-4058-8a51-2b4b8f1791b6
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2122711799 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.
gpio_stress_all.2122711799
Directory /workspace/23.gpio_stress_all/latest

Test location /workspace/coverage/default/23.gpio_stress_all_with_rand_reset.1810211174
Short name T812
Test name
Test status
Simulation time 232152507972 ps
CPU time 605.47 seconds
Started Dec 27 01:24:28 PM PST 23
Finished Dec 27 01:34:34 PM PST 23
Peak memory 198432 kb
Host smart-9dd94db7-157a-488a-b48b-dbc644512ce6
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=1810211174 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.gpio_stress_all_with_rand_reset.1810211174
Directory /workspace/23.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/24.gpio_alert_test.4158613654
Short name T618
Test name
Test status
Simulation time 12209132 ps
CPU time 0.56 seconds
Started Dec 27 01:24:11 PM PST 23
Finished Dec 27 01:24:12 PM PST 23
Peak memory 194648 kb
Host smart-e6aae8a1-eddc-49a0-9f35-cd98f85731e0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4158613654 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_alert_test.4158613654
Directory /workspace/24.gpio_alert_test/latest

Test location /workspace/coverage/default/24.gpio_dout_din_regs_random_rw.3114623478
Short name T483
Test name
Test status
Simulation time 32669961 ps
CPU time 0.88 seconds
Started Dec 27 01:23:25 PM PST 23
Finished Dec 27 01:23:27 PM PST 23
Peak memory 196500 kb
Host smart-c8a0c504-c65e-4553-bf1c-52d4801b82f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3114623478 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_dout_din_regs_random_rw.3114623478
Directory /workspace/24.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/24.gpio_filter_stress.1258639804
Short name T284
Test name
Test status
Simulation time 783874520 ps
CPU time 26.32 seconds
Started Dec 27 01:23:28 PM PST 23
Finished Dec 27 01:23:56 PM PST 23
Peak memory 196900 kb
Host smart-9b194a44-2784-432e-b5e6-cfe477d250bc
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1258639804 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_filter_stre
ss.1258639804
Directory /workspace/24.gpio_filter_stress/latest

Test location /workspace/coverage/default/24.gpio_full_random.2627246055
Short name T693
Test name
Test status
Simulation time 831214394 ps
CPU time 0.84 seconds
Started Dec 27 01:23:27 PM PST 23
Finished Dec 27 01:23:29 PM PST 23
Peak memory 195988 kb
Host smart-2778d9e7-85f9-40e5-87bb-132c2aa4540c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2627246055 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_full_random.2627246055
Directory /workspace/24.gpio_full_random/latest

Test location /workspace/coverage/default/24.gpio_intr_rand_pgm.1313840321
Short name T562
Test name
Test status
Simulation time 102093831 ps
CPU time 0.96 seconds
Started Dec 27 01:23:26 PM PST 23
Finished Dec 27 01:23:27 PM PST 23
Peak memory 196792 kb
Host smart-e02017b7-4439-469f-9425-d4720956a1d1
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1313840321 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_intr_rand_pgm.1313840321
Directory /workspace/24.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/24.gpio_intr_with_filter_rand_intr_event.3019946141
Short name T315
Test name
Test status
Simulation time 81140064 ps
CPU time 2.98 seconds
Started Dec 27 01:23:53 PM PST 23
Finished Dec 27 01:23:57 PM PST 23
Peak memory 198264 kb
Host smart-2574f3cb-0896-473f-b1ab-b57cdca46eb3
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3019946141 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 24.gpio_intr_with_filter_rand_intr_event.3019946141
Directory /workspace/24.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/24.gpio_rand_intr_trigger.884380725
Short name T653
Test name
Test status
Simulation time 157046405 ps
CPU time 1.09 seconds
Started Dec 27 01:23:24 PM PST 23
Finished Dec 27 01:23:26 PM PST 23
Peak memory 195724 kb
Host smart-f12abcc1-dc05-4226-92e2-f58528262faf
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=884380725 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_rand_intr_trigger.
884380725
Directory /workspace/24.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/24.gpio_random_dout_din.2352734019
Short name T408
Test name
Test status
Simulation time 63621949 ps
CPU time 0.75 seconds
Started Dec 27 01:24:45 PM PST 23
Finished Dec 27 01:24:50 PM PST 23
Peak memory 195120 kb
Host smart-cc006531-e847-4e96-a90e-cfc5ea89e796
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2352734019 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_random_dout_din.2352734019
Directory /workspace/24.gpio_random_dout_din/latest

Test location /workspace/coverage/default/24.gpio_random_dout_din_no_pullup_pulldown.494167556
Short name T233
Test name
Test status
Simulation time 18511398 ps
CPU time 0.75 seconds
Started Dec 27 01:23:28 PM PST 23
Finished Dec 27 01:23:30 PM PST 23
Peak memory 196128 kb
Host smart-a3411f97-1d25-4615-bc80-c51768576823
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=494167556 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_random_dout_din_no_pullup
_pulldown.494167556
Directory /workspace/24.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/24.gpio_random_long_reg_writes_reg_reads.986436480
Short name T220
Test name
Test status
Simulation time 1256121818 ps
CPU time 5.71 seconds
Started Dec 27 01:23:25 PM PST 23
Finished Dec 27 01:23:32 PM PST 23
Peak memory 197152 kb
Host smart-acf1162a-827c-40c1-b2ca-b991010867e4
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=986436480 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_ran
dom_long_reg_writes_reg_reads.986436480
Directory /workspace/24.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/24.gpio_smoke.298784366
Short name T420
Test name
Test status
Simulation time 48937533 ps
CPU time 1.06 seconds
Started Dec 27 01:24:31 PM PST 23
Finished Dec 27 01:24:34 PM PST 23
Peak memory 196404 kb
Host smart-056d3c08-488e-4831-a282-2f1fefa84670
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=298784366 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_smoke.298784366
Directory /workspace/24.gpio_smoke/latest

Test location /workspace/coverage/default/24.gpio_smoke_no_pullup_pulldown.2229453082
Short name T346
Test name
Test status
Simulation time 117863280 ps
CPU time 1.03 seconds
Started Dec 27 01:23:48 PM PST 23
Finished Dec 27 01:23:50 PM PST 23
Peak memory 195928 kb
Host smart-f92abc1a-5acf-44a6-a02c-32baf3903a46
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2229453082 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_smoke_no_pullup_pulldown.2229453082
Directory /workspace/24.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/24.gpio_stress_all.2292426017
Short name T688
Test name
Test status
Simulation time 7641395120 ps
CPU time 81.32 seconds
Started Dec 27 01:23:46 PM PST 23
Finished Dec 27 01:25:08 PM PST 23
Peak memory 198236 kb
Host smart-3a694fd1-a5ff-4571-abe7-3ea2f32c655f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2292426017 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.
gpio_stress_all.2292426017
Directory /workspace/24.gpio_stress_all/latest

Test location /workspace/coverage/default/24.gpio_stress_all_with_rand_reset.2467800554
Short name T854
Test name
Test status
Simulation time 12732249194 ps
CPU time 211.53 seconds
Started Dec 27 01:23:51 PM PST 23
Finished Dec 27 01:27:24 PM PST 23
Peak memory 198252 kb
Host smart-944bea54-9ba9-4e57-9b11-9bf898db44a5
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=2467800554 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.gpio_stress_all_with_rand_reset.2467800554
Directory /workspace/24.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/25.gpio_alert_test.4209895319
Short name T327
Test name
Test status
Simulation time 13914485 ps
CPU time 0.55 seconds
Started Dec 27 01:24:17 PM PST 23
Finished Dec 27 01:24:18 PM PST 23
Peak memory 192752 kb
Host smart-185c6464-7d03-49ee-b277-971c165fedf6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4209895319 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_alert_test.4209895319
Directory /workspace/25.gpio_alert_test/latest

Test location /workspace/coverage/default/25.gpio_dout_din_regs_random_rw.2750956959
Short name T709
Test name
Test status
Simulation time 28463375 ps
CPU time 0.84 seconds
Started Dec 27 01:23:48 PM PST 23
Finished Dec 27 01:23:49 PM PST 23
Peak memory 196496 kb
Host smart-63ab66e9-3485-4edb-9e2d-f5768bda7a44
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2750956959 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_dout_din_regs_random_rw.2750956959
Directory /workspace/25.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/25.gpio_filter_stress.4198614721
Short name T770
Test name
Test status
Simulation time 2039867123 ps
CPU time 25.59 seconds
Started Dec 27 01:24:48 PM PST 23
Finished Dec 27 01:25:16 PM PST 23
Peak memory 196892 kb
Host smart-6fbecafe-953a-4d74-9ab1-cb982d3cc57d
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4198614721 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_filter_stre
ss.4198614721
Directory /workspace/25.gpio_filter_stress/latest

Test location /workspace/coverage/default/25.gpio_full_random.1146502370
Short name T695
Test name
Test status
Simulation time 39018016 ps
CPU time 0.71 seconds
Started Dec 27 01:24:36 PM PST 23
Finished Dec 27 01:24:37 PM PST 23
Peak memory 194864 kb
Host smart-8e0fe97a-aca4-4858-a728-78060c9e0b93
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1146502370 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_full_random.1146502370
Directory /workspace/25.gpio_full_random/latest

Test location /workspace/coverage/default/25.gpio_intr_rand_pgm.2325701313
Short name T258
Test name
Test status
Simulation time 85000884 ps
CPU time 1.25 seconds
Started Dec 27 01:24:25 PM PST 23
Finished Dec 27 01:24:28 PM PST 23
Peak memory 196132 kb
Host smart-2bb498a1-23d4-401d-bf9b-6bc4081a2914
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2325701313 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_intr_rand_pgm.2325701313
Directory /workspace/25.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/25.gpio_intr_with_filter_rand_intr_event.480842407
Short name T312
Test name
Test status
Simulation time 66662633 ps
CPU time 1.97 seconds
Started Dec 27 01:23:54 PM PST 23
Finished Dec 27 01:23:57 PM PST 23
Peak memory 198076 kb
Host smart-00cf2c4b-1bca-4a35-950f-4aa540540fd0
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=480842407 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 25.gpio_intr_with_filter_rand_intr_event.480842407
Directory /workspace/25.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/25.gpio_rand_intr_trigger.1046366576
Short name T685
Test name
Test status
Simulation time 809454690 ps
CPU time 3.5 seconds
Started Dec 27 01:23:53 PM PST 23
Finished Dec 27 01:23:58 PM PST 23
Peak memory 195936 kb
Host smart-d5e7b46e-5ed9-439d-9db5-88231952a874
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1046366576 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_rand_intr_trigger
.1046366576
Directory /workspace/25.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/25.gpio_random_dout_din.1002268767
Short name T291
Test name
Test status
Simulation time 68960654 ps
CPU time 1.32 seconds
Started Dec 27 01:23:47 PM PST 23
Finished Dec 27 01:23:49 PM PST 23
Peak memory 198180 kb
Host smart-89b52d96-3883-42fd-94f1-77be4d11f81f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1002268767 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_random_dout_din.1002268767
Directory /workspace/25.gpio_random_dout_din/latest

Test location /workspace/coverage/default/25.gpio_random_dout_din_no_pullup_pulldown.827769469
Short name T588
Test name
Test status
Simulation time 23699633 ps
CPU time 0.88 seconds
Started Dec 27 01:23:48 PM PST 23
Finished Dec 27 01:23:50 PM PST 23
Peak memory 196416 kb
Host smart-1ba2413e-54c2-4c3f-a3af-2c8ebeb34b1d
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=827769469 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_random_dout_din_no_pullup
_pulldown.827769469
Directory /workspace/25.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/25.gpio_random_long_reg_writes_reg_reads.3515887209
Short name T624
Test name
Test status
Simulation time 351535528 ps
CPU time 6.45 seconds
Started Dec 27 01:23:57 PM PST 23
Finished Dec 27 01:24:04 PM PST 23
Peak memory 198124 kb
Host smart-b114bc21-1602-428d-b1a5-e6aa4aee7c8c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3515887209 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_ra
ndom_long_reg_writes_reg_reads.3515887209
Directory /workspace/25.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/25.gpio_smoke.1695488630
Short name T431
Test name
Test status
Simulation time 46081964 ps
CPU time 1.2 seconds
Started Dec 27 01:23:51 PM PST 23
Finished Dec 27 01:23:54 PM PST 23
Peak memory 196936 kb
Host smart-c23cc314-3f81-47cb-9a78-aef9f38ac56e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1695488630 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_smoke.1695488630
Directory /workspace/25.gpio_smoke/latest

Test location /workspace/coverage/default/25.gpio_smoke_no_pullup_pulldown.2068446609
Short name T606
Test name
Test status
Simulation time 94400784 ps
CPU time 0.83 seconds
Started Dec 27 01:23:53 PM PST 23
Finished Dec 27 01:23:55 PM PST 23
Peak memory 196380 kb
Host smart-03d8a083-9810-4877-a50b-f846440086e4
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2068446609 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_smoke_no_pullup_pulldown.2068446609
Directory /workspace/25.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/25.gpio_stress_all.2684492399
Short name T787
Test name
Test status
Simulation time 23812453032 ps
CPU time 170.49 seconds
Started Dec 27 01:24:40 PM PST 23
Finished Dec 27 01:27:32 PM PST 23
Peak memory 198256 kb
Host smart-29784c11-3de3-4605-85a4-7bbd820f064b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2684492399 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.
gpio_stress_all.2684492399
Directory /workspace/25.gpio_stress_all/latest

Test location /workspace/coverage/default/25.gpio_stress_all_with_rand_reset.384597975
Short name T867
Test name
Test status
Simulation time 238249208912 ps
CPU time 1430 seconds
Started Dec 27 01:24:34 PM PST 23
Finished Dec 27 01:48:25 PM PST 23
Peak memory 198320 kb
Host smart-523a8d7e-a30f-487d-9ba1-eaededbe1368
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=384597975 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.gpio_stress_all_with_rand_reset.384597975
Directory /workspace/25.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/26.gpio_alert_test.1833331122
Short name T689
Test name
Test status
Simulation time 16700568 ps
CPU time 0.63 seconds
Started Dec 27 01:25:02 PM PST 23
Finished Dec 27 01:25:04 PM PST 23
Peak memory 194204 kb
Host smart-d69024d8-5750-4620-a96b-4f9762026079
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1833331122 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_alert_test.1833331122
Directory /workspace/26.gpio_alert_test/latest

Test location /workspace/coverage/default/26.gpio_dout_din_regs_random_rw.713220877
Short name T459
Test name
Test status
Simulation time 148934109 ps
CPU time 0.91 seconds
Started Dec 27 01:24:31 PM PST 23
Finished Dec 27 01:24:32 PM PST 23
Peak memory 196648 kb
Host smart-4992a5b0-7b81-4fd4-adb2-7b6e4f464174
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=713220877 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_dout_din_regs_random_rw.713220877
Directory /workspace/26.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/26.gpio_filter_stress.978356764
Short name T883
Test name
Test status
Simulation time 822804926 ps
CPU time 15.06 seconds
Started Dec 27 01:23:48 PM PST 23
Finished Dec 27 01:24:04 PM PST 23
Peak memory 196908 kb
Host smart-0bea28f9-039e-447e-bc1c-85d18d7b15b0
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=978356764 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_filter_stres
s.978356764
Directory /workspace/26.gpio_filter_stress/latest

Test location /workspace/coverage/default/26.gpio_full_random.466137208
Short name T293
Test name
Test status
Simulation time 276595885 ps
CPU time 0.98 seconds
Started Dec 27 01:25:07 PM PST 23
Finished Dec 27 01:25:12 PM PST 23
Peak memory 196572 kb
Host smart-7d72a798-2f93-4618-85bf-e34aa14c716f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=466137208 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_full_random.466137208
Directory /workspace/26.gpio_full_random/latest

Test location /workspace/coverage/default/26.gpio_intr_rand_pgm.1097850796
Short name T873
Test name
Test status
Simulation time 551967240 ps
CPU time 1.36 seconds
Started Dec 27 01:24:28 PM PST 23
Finished Dec 27 01:24:30 PM PST 23
Peak memory 197160 kb
Host smart-0d46bd17-8ad6-4976-818f-aa0f6333ddcc
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1097850796 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_intr_rand_pgm.1097850796
Directory /workspace/26.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/26.gpio_intr_with_filter_rand_intr_event.3482520069
Short name T379
Test name
Test status
Simulation time 121281497 ps
CPU time 2.46 seconds
Started Dec 27 01:24:50 PM PST 23
Finished Dec 27 01:24:56 PM PST 23
Peak memory 198280 kb
Host smart-00f6815d-0a27-46c9-9fc0-518ab5c1540f
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3482520069 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 26.gpio_intr_with_filter_rand_intr_event.3482520069
Directory /workspace/26.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/26.gpio_rand_intr_trigger.492420401
Short name T786
Test name
Test status
Simulation time 87254734 ps
CPU time 1.46 seconds
Started Dec 27 01:24:55 PM PST 23
Finished Dec 27 01:24:58 PM PST 23
Peak memory 195936 kb
Host smart-1ea9ffe5-6bf1-4fc3-9c4c-db5ff721a478
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=492420401 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_rand_intr_trigger.
492420401
Directory /workspace/26.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/26.gpio_random_dout_din.3407628469
Short name T772
Test name
Test status
Simulation time 406310098 ps
CPU time 1.28 seconds
Started Dec 27 01:24:49 PM PST 23
Finished Dec 27 01:24:52 PM PST 23
Peak memory 198052 kb
Host smart-4c324af4-5dd6-4476-a40a-fe3de57a7590
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3407628469 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_random_dout_din.3407628469
Directory /workspace/26.gpio_random_dout_din/latest

Test location /workspace/coverage/default/26.gpio_random_dout_din_no_pullup_pulldown.1378892163
Short name T524
Test name
Test status
Simulation time 34193350 ps
CPU time 1.21 seconds
Started Dec 27 01:24:47 PM PST 23
Finished Dec 27 01:24:52 PM PST 23
Peak memory 198100 kb
Host smart-caf7c9c3-be24-46f8-b61c-4f2ff97bbcf9
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1378892163 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_random_dout_din_no_pullu
p_pulldown.1378892163
Directory /workspace/26.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/26.gpio_random_long_reg_writes_reg_reads.1894706325
Short name T645
Test name
Test status
Simulation time 31133381 ps
CPU time 1.41 seconds
Started Dec 27 01:24:17 PM PST 23
Finished Dec 27 01:24:19 PM PST 23
Peak memory 197972 kb
Host smart-614eec2c-738c-4793-8a33-8589e05a60b0
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1894706325 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_ra
ndom_long_reg_writes_reg_reads.1894706325
Directory /workspace/26.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/26.gpio_smoke.265693358
Short name T855
Test name
Test status
Simulation time 89589968 ps
CPU time 1.07 seconds
Started Dec 27 01:24:50 PM PST 23
Finished Dec 27 01:24:54 PM PST 23
Peak memory 195780 kb
Host smart-c6e9eac5-a917-4e94-bab3-242fd862dc7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=265693358 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_smoke.265693358
Directory /workspace/26.gpio_smoke/latest

Test location /workspace/coverage/default/26.gpio_smoke_no_pullup_pulldown.1110158358
Short name T355
Test name
Test status
Simulation time 92643615 ps
CPU time 1.35 seconds
Started Dec 27 01:24:44 PM PST 23
Finished Dec 27 01:24:46 PM PST 23
Peak memory 196648 kb
Host smart-b64022eb-57e4-4df1-ac68-4df0130d50cb
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1110158358 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_smoke_no_pullup_pulldown.1110158358
Directory /workspace/26.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/26.gpio_stress_all.1422425485
Short name T97
Test name
Test status
Simulation time 7842295450 ps
CPU time 43.32 seconds
Started Dec 27 01:25:03 PM PST 23
Finished Dec 27 01:25:48 PM PST 23
Peak memory 198156 kb
Host smart-1f674a1f-3614-46f6-a656-05959ce75335
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1422425485 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.
gpio_stress_all.1422425485
Directory /workspace/26.gpio_stress_all/latest

Test location /workspace/coverage/default/26.gpio_stress_all_with_rand_reset.79066817
Short name T610
Test name
Test status
Simulation time 104301124923 ps
CPU time 1316.54 seconds
Started Dec 27 01:24:31 PM PST 23
Finished Dec 27 01:46:29 PM PST 23
Peak memory 198364 kb
Host smart-435194c5-2161-4f76-b669-cbfafe749dec
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=79066817 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.gpio_stress_all_with_rand_reset.79066817
Directory /workspace/26.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/27.gpio_alert_test.3185978813
Short name T297
Test name
Test status
Simulation time 50611371 ps
CPU time 0.56 seconds
Started Dec 27 01:25:08 PM PST 23
Finished Dec 27 01:25:11 PM PST 23
Peak memory 194980 kb
Host smart-19ac1a7a-57c0-47cb-bd57-984f95c3d106
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3185978813 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_alert_test.3185978813
Directory /workspace/27.gpio_alert_test/latest

Test location /workspace/coverage/default/27.gpio_dout_din_regs_random_rw.911998489
Short name T573
Test name
Test status
Simulation time 31425514 ps
CPU time 0.7 seconds
Started Dec 27 01:24:49 PM PST 23
Finished Dec 27 01:24:54 PM PST 23
Peak memory 194192 kb
Host smart-77878aef-960a-401f-b5f3-f140fe39b76f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=911998489 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_dout_din_regs_random_rw.911998489
Directory /workspace/27.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/27.gpio_filter_stress.1279220566
Short name T253
Test name
Test status
Simulation time 502605705 ps
CPU time 24.92 seconds
Started Dec 27 01:23:50 PM PST 23
Finished Dec 27 01:24:16 PM PST 23
Peak memory 196568 kb
Host smart-748ac4af-4931-4207-8af1-2a987d42ccb9
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1279220566 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_filter_stre
ss.1279220566
Directory /workspace/27.gpio_filter_stress/latest

Test location /workspace/coverage/default/27.gpio_full_random.3546163772
Short name T404
Test name
Test status
Simulation time 91802511 ps
CPU time 0.98 seconds
Started Dec 27 01:24:54 PM PST 23
Finished Dec 27 01:24:55 PM PST 23
Peak memory 196472 kb
Host smart-63121c7c-73a6-4c6f-9588-e42f69de4db3
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3546163772 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_full_random.3546163772
Directory /workspace/27.gpio_full_random/latest

Test location /workspace/coverage/default/27.gpio_intr_rand_pgm.3535552176
Short name T266
Test name
Test status
Simulation time 86524718 ps
CPU time 1.42 seconds
Started Dec 27 01:24:53 PM PST 23
Finished Dec 27 01:24:55 PM PST 23
Peak memory 197052 kb
Host smart-47906298-ad6f-41eb-8bc2-ce4c0d5aaf7e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3535552176 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_intr_rand_pgm.3535552176
Directory /workspace/27.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/27.gpio_intr_with_filter_rand_intr_event.1159593398
Short name T502
Test name
Test status
Simulation time 145984409 ps
CPU time 1.56 seconds
Started Dec 27 01:25:18 PM PST 23
Finished Dec 27 01:25:20 PM PST 23
Peak memory 198204 kb
Host smart-26fe316a-e182-415e-85ef-a4230b9503cd
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1159593398 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 27.gpio_intr_with_filter_rand_intr_event.1159593398
Directory /workspace/27.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/27.gpio_rand_intr_trigger.1159405147
Short name T860
Test name
Test status
Simulation time 500242897 ps
CPU time 2.01 seconds
Started Dec 27 01:25:02 PM PST 23
Finished Dec 27 01:25:06 PM PST 23
Peak memory 197004 kb
Host smart-1e09488e-92f6-4599-8726-2d4a844c571a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1159405147 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_rand_intr_trigger
.1159405147
Directory /workspace/27.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/27.gpio_random_dout_din.1081228994
Short name T461
Test name
Test status
Simulation time 100844813 ps
CPU time 0.92 seconds
Started Dec 27 01:24:51 PM PST 23
Finished Dec 27 01:24:55 PM PST 23
Peak memory 196148 kb
Host smart-81a4538f-f444-4e41-85c7-ae36c9c2f81b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1081228994 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_random_dout_din.1081228994
Directory /workspace/27.gpio_random_dout_din/latest

Test location /workspace/coverage/default/27.gpio_random_dout_din_no_pullup_pulldown.2084229517
Short name T438
Test name
Test status
Simulation time 311003458 ps
CPU time 1.02 seconds
Started Dec 27 01:25:06 PM PST 23
Finished Dec 27 01:25:12 PM PST 23
Peak memory 196004 kb
Host smart-db2794c9-9057-4742-8f8a-f91c20d0629c
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2084229517 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_random_dout_din_no_pullu
p_pulldown.2084229517
Directory /workspace/27.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/27.gpio_random_long_reg_writes_reg_reads.421761842
Short name T667
Test name
Test status
Simulation time 1427431344 ps
CPU time 5.99 seconds
Started Dec 27 01:25:03 PM PST 23
Finished Dec 27 01:25:10 PM PST 23
Peak memory 198076 kb
Host smart-fef6ee00-9b67-4cdc-bb09-e42899d8a343
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=421761842 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_ran
dom_long_reg_writes_reg_reads.421761842
Directory /workspace/27.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/27.gpio_smoke.1148891090
Short name T857
Test name
Test status
Simulation time 275783947 ps
CPU time 0.92 seconds
Started Dec 27 01:24:10 PM PST 23
Finished Dec 27 01:24:12 PM PST 23
Peak memory 196040 kb
Host smart-7e13a037-bd90-4799-bf4f-0c3823bd03fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1148891090 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_smoke.1148891090
Directory /workspace/27.gpio_smoke/latest

Test location /workspace/coverage/default/27.gpio_smoke_no_pullup_pulldown.4243232392
Short name T403
Test name
Test status
Simulation time 77235493 ps
CPU time 1.45 seconds
Started Dec 27 01:24:57 PM PST 23
Finished Dec 27 01:24:59 PM PST 23
Peak memory 196948 kb
Host smart-a7bb1039-a510-4150-bb55-525cc6cc01bc
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4243232392 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_smoke_no_pullup_pulldown.4243232392
Directory /workspace/27.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/27.gpio_stress_all.934431718
Short name T464
Test name
Test status
Simulation time 8240770510 ps
CPU time 21.95 seconds
Started Dec 27 01:25:09 PM PST 23
Finished Dec 27 01:25:35 PM PST 23
Peak memory 198136 kb
Host smart-255d681f-1ef4-4283-a5b9-77a2e73d26dc
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=934431718 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.g
pio_stress_all.934431718
Directory /workspace/27.gpio_stress_all/latest

Test location /workspace/coverage/default/27.gpio_stress_all_with_rand_reset.3375831627
Short name T790
Test name
Test status
Simulation time 102132302169 ps
CPU time 1603.13 seconds
Started Dec 27 01:25:09 PM PST 23
Finished Dec 27 01:51:55 PM PST 23
Peak memory 198368 kb
Host smart-4e6203bf-4c0e-4534-8b6b-c924ff6d1822
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=3375831627 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.gpio_stress_all_with_rand_reset.3375831627
Directory /workspace/27.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/28.gpio_alert_test.3037559457
Short name T249
Test name
Test status
Simulation time 15658528 ps
CPU time 0.58 seconds
Started Dec 27 01:23:51 PM PST 23
Finished Dec 27 01:23:53 PM PST 23
Peak memory 193972 kb
Host smart-b2ac5a31-a7ef-4c70-b530-26587d1a1685
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3037559457 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_alert_test.3037559457
Directory /workspace/28.gpio_alert_test/latest

Test location /workspace/coverage/default/28.gpio_dout_din_regs_random_rw.424786099
Short name T886
Test name
Test status
Simulation time 29835366 ps
CPU time 0.76 seconds
Started Dec 27 01:23:51 PM PST 23
Finished Dec 27 01:23:54 PM PST 23
Peak memory 195332 kb
Host smart-9a4aee93-440f-4baa-aacf-5a0abc58f4a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=424786099 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_dout_din_regs_random_rw.424786099
Directory /workspace/28.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/28.gpio_filter_stress.97246707
Short name T875
Test name
Test status
Simulation time 239535181 ps
CPU time 13.06 seconds
Started Dec 27 01:23:52 PM PST 23
Finished Dec 27 01:24:07 PM PST 23
Peak memory 196640 kb
Host smart-e29dcf60-100e-4544-a423-4ef4229c1db5
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=97246707 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter_
stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_filter_stress
.97246707
Directory /workspace/28.gpio_filter_stress/latest

Test location /workspace/coverage/default/28.gpio_full_random.2013397800
Short name T441
Test name
Test status
Simulation time 37057536 ps
CPU time 0.73 seconds
Started Dec 27 01:23:50 PM PST 23
Finished Dec 27 01:23:51 PM PST 23
Peak memory 195460 kb
Host smart-370def0f-cacc-4769-a614-50480d6ee5a2
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2013397800 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_full_random.2013397800
Directory /workspace/28.gpio_full_random/latest

Test location /workspace/coverage/default/28.gpio_intr_rand_pgm.2820547871
Short name T579
Test name
Test status
Simulation time 352959024 ps
CPU time 1.24 seconds
Started Dec 27 01:23:26 PM PST 23
Finished Dec 27 01:23:28 PM PST 23
Peak memory 196796 kb
Host smart-2597aa8d-71a3-4703-837a-9026aa256d44
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2820547871 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_intr_rand_pgm.2820547871
Directory /workspace/28.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/28.gpio_intr_with_filter_rand_intr_event.1535339104
Short name T865
Test name
Test status
Simulation time 73702724 ps
CPU time 2.72 seconds
Started Dec 27 01:23:48 PM PST 23
Finished Dec 27 01:23:51 PM PST 23
Peak memory 198224 kb
Host smart-76ba04eb-4751-43bb-adb2-389679ee9024
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1535339104 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 28.gpio_intr_with_filter_rand_intr_event.1535339104
Directory /workspace/28.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/28.gpio_rand_intr_trigger.1196709260
Short name T823
Test name
Test status
Simulation time 850891118 ps
CPU time 2.03 seconds
Started Dec 27 01:23:30 PM PST 23
Finished Dec 27 01:23:33 PM PST 23
Peak memory 195820 kb
Host smart-42c5b07a-f134-44eb-bdd1-4b12c726d129
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1196709260 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_rand_intr_trigger
.1196709260
Directory /workspace/28.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/28.gpio_random_dout_din.1984956869
Short name T64
Test name
Test status
Simulation time 78102885 ps
CPU time 0.71 seconds
Started Dec 27 01:24:19 PM PST 23
Finished Dec 27 01:24:20 PM PST 23
Peak memory 195408 kb
Host smart-cb80cc09-9e74-4841-97d6-64b77b4414df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1984956869 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_random_dout_din.1984956869
Directory /workspace/28.gpio_random_dout_din/latest

Test location /workspace/coverage/default/28.gpio_random_dout_din_no_pullup_pulldown.2669311230
Short name T254
Test name
Test status
Simulation time 65794686 ps
CPU time 1.22 seconds
Started Dec 27 01:24:11 PM PST 23
Finished Dec 27 01:24:13 PM PST 23
Peak memory 196756 kb
Host smart-10bb55b9-0d30-4ccf-9ce2-7f0a53e19dd3
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2669311230 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_random_dout_din_no_pullu
p_pulldown.2669311230
Directory /workspace/28.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/28.gpio_random_long_reg_writes_reg_reads.1718122295
Short name T755
Test name
Test status
Simulation time 1654003702 ps
CPU time 2.76 seconds
Started Dec 27 01:24:14 PM PST 23
Finished Dec 27 01:24:18 PM PST 23
Peak memory 198048 kb
Host smart-1bf4ebe0-2064-4ea8-bd2d-0cb20b4e99bc
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1718122295 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_ra
ndom_long_reg_writes_reg_reads.1718122295
Directory /workspace/28.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/28.gpio_smoke.3533304439
Short name T814
Test name
Test status
Simulation time 76157039 ps
CPU time 1.36 seconds
Started Dec 27 01:25:15 PM PST 23
Finished Dec 27 01:25:17 PM PST 23
Peak memory 196896 kb
Host smart-133374b9-d8b4-4abe-a3f5-84db4d9ba9da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3533304439 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_smoke.3533304439
Directory /workspace/28.gpio_smoke/latest

Test location /workspace/coverage/default/28.gpio_smoke_no_pullup_pulldown.335231486
Short name T267
Test name
Test status
Simulation time 362165119 ps
CPU time 1.46 seconds
Started Dec 27 01:23:46 PM PST 23
Finished Dec 27 01:23:48 PM PST 23
Peak memory 198116 kb
Host smart-482f25d8-c543-414a-8673-e2038e746c8e
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=335231486 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_smoke_no_pullup_pulldown.335231486
Directory /workspace/28.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/28.gpio_stress_all.812663946
Short name T595
Test name
Test status
Simulation time 63607377699 ps
CPU time 106.99 seconds
Started Dec 27 01:23:49 PM PST 23
Finished Dec 27 01:25:37 PM PST 23
Peak memory 198248 kb
Host smart-4988d482-4379-4ea9-8604-ea6699766b88
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=812663946 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.g
pio_stress_all.812663946
Directory /workspace/28.gpio_stress_all/latest

Test location /workspace/coverage/default/28.gpio_stress_all_with_rand_reset.3851838388
Short name T425
Test name
Test status
Simulation time 78736263226 ps
CPU time 433.06 seconds
Started Dec 27 01:23:48 PM PST 23
Finished Dec 27 01:31:02 PM PST 23
Peak memory 198260 kb
Host smart-146c405a-5c33-4537-b3df-38ce7e46dc81
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=3851838388 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.gpio_stress_all_with_rand_reset.3851838388
Directory /workspace/28.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/29.gpio_alert_test.2625759523
Short name T349
Test name
Test status
Simulation time 156963028 ps
CPU time 0.57 seconds
Started Dec 27 01:23:45 PM PST 23
Finished Dec 27 01:23:46 PM PST 23
Peak memory 194192 kb
Host smart-f651cbca-3996-4684-b170-4c17bb363e17
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2625759523 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_alert_test.2625759523
Directory /workspace/29.gpio_alert_test/latest

Test location /workspace/coverage/default/29.gpio_dout_din_regs_random_rw.1027272825
Short name T658
Test name
Test status
Simulation time 55292116 ps
CPU time 0.91 seconds
Started Dec 27 01:23:47 PM PST 23
Finished Dec 27 01:23:48 PM PST 23
Peak memory 196172 kb
Host smart-67c0c69e-e831-4e68-b611-a7ab26791185
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1027272825 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_dout_din_regs_random_rw.1027272825
Directory /workspace/29.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/29.gpio_filter_stress.3117090299
Short name T733
Test name
Test status
Simulation time 6796881238 ps
CPU time 19.8 seconds
Started Dec 27 01:24:36 PM PST 23
Finished Dec 27 01:24:57 PM PST 23
Peak memory 197684 kb
Host smart-42a98d45-1115-437c-8b22-ba546b8ad53e
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3117090299 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_filter_stre
ss.3117090299
Directory /workspace/29.gpio_filter_stress/latest

Test location /workspace/coverage/default/29.gpio_full_random.492791856
Short name T495
Test name
Test status
Simulation time 30718557 ps
CPU time 0.61 seconds
Started Dec 27 01:23:51 PM PST 23
Finished Dec 27 01:23:53 PM PST 23
Peak memory 194180 kb
Host smart-dfa0b4f9-da0f-405c-8c81-23760645a4c6
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=492791856 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_full_random.492791856
Directory /workspace/29.gpio_full_random/latest

Test location /workspace/coverage/default/29.gpio_intr_rand_pgm.4065831688
Short name T836
Test name
Test status
Simulation time 173924982 ps
CPU time 0.99 seconds
Started Dec 27 01:23:52 PM PST 23
Finished Dec 27 01:23:54 PM PST 23
Peak memory 196944 kb
Host smart-28631f5c-687c-4be7-8085-311b71b9311e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4065831688 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_intr_rand_pgm.4065831688
Directory /workspace/29.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/29.gpio_intr_with_filter_rand_intr_event.544320039
Short name T861
Test name
Test status
Simulation time 37407618 ps
CPU time 1.44 seconds
Started Dec 27 01:23:50 PM PST 23
Finished Dec 27 01:23:52 PM PST 23
Peak memory 196980 kb
Host smart-aa46a730-2ef4-4876-8f0d-e30b5beb231f
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=544320039 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 29.gpio_intr_with_filter_rand_intr_event.544320039
Directory /workspace/29.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/29.gpio_rand_intr_trigger.3088503808
Short name T476
Test name
Test status
Simulation time 323233586 ps
CPU time 2.45 seconds
Started Dec 27 01:23:26 PM PST 23
Finished Dec 27 01:23:29 PM PST 23
Peak memory 198088 kb
Host smart-5be6c29b-981d-45a2-9bf4-99872f3039d1
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3088503808 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_rand_intr_trigger
.3088503808
Directory /workspace/29.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/29.gpio_random_dout_din.2942242421
Short name T364
Test name
Test status
Simulation time 62146964 ps
CPU time 1.36 seconds
Started Dec 27 01:23:26 PM PST 23
Finished Dec 27 01:23:28 PM PST 23
Peak memory 198184 kb
Host smart-73fccf61-04ae-4256-a0c5-4e4e2346ff9b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2942242421 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_random_dout_din.2942242421
Directory /workspace/29.gpio_random_dout_din/latest

Test location /workspace/coverage/default/29.gpio_random_dout_din_no_pullup_pulldown.2117012806
Short name T365
Test name
Test status
Simulation time 24098515 ps
CPU time 0.71 seconds
Started Dec 27 01:23:26 PM PST 23
Finished Dec 27 01:23:27 PM PST 23
Peak memory 196092 kb
Host smart-5f1b83d5-3b59-45c7-b936-d56c5118e11b
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2117012806 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_random_dout_din_no_pullu
p_pulldown.2117012806
Directory /workspace/29.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/29.gpio_random_long_reg_writes_reg_reads.2298247711
Short name T553
Test name
Test status
Simulation time 74662377 ps
CPU time 1.46 seconds
Started Dec 27 01:23:45 PM PST 23
Finished Dec 27 01:23:47 PM PST 23
Peak memory 198028 kb
Host smart-0af8bdb7-2d0b-4d37-bacc-193939685b80
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2298247711 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_ra
ndom_long_reg_writes_reg_reads.2298247711
Directory /workspace/29.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/29.gpio_smoke.745608499
Short name T460
Test name
Test status
Simulation time 85979645 ps
CPU time 1.42 seconds
Started Dec 27 01:23:48 PM PST 23
Finished Dec 27 01:23:51 PM PST 23
Peak memory 195496 kb
Host smart-4a87e39b-e817-4b2c-9f5e-d3f8a89409ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=745608499 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_smoke.745608499
Directory /workspace/29.gpio_smoke/latest

Test location /workspace/coverage/default/29.gpio_smoke_no_pullup_pulldown.2628785701
Short name T707
Test name
Test status
Simulation time 335316986 ps
CPU time 1.36 seconds
Started Dec 27 01:23:27 PM PST 23
Finished Dec 27 01:23:29 PM PST 23
Peak memory 196872 kb
Host smart-b74749f1-ca2f-4e54-85af-30fc5593f9b6
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2628785701 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_smoke_no_pullup_pulldown.2628785701
Directory /workspace/29.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/29.gpio_stress_all.833041036
Short name T469
Test name
Test status
Simulation time 56429809760 ps
CPU time 166.65 seconds
Started Dec 27 01:24:11 PM PST 23
Finished Dec 27 01:26:58 PM PST 23
Peak memory 198252 kb
Host smart-b1e0ee44-4a8f-4a3d-a67d-bedd45c5bd1e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=833041036 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.g
pio_stress_all.833041036
Directory /workspace/29.gpio_stress_all/latest

Test location /workspace/coverage/default/29.gpio_stress_all_with_rand_reset.3321340125
Short name T567
Test name
Test status
Simulation time 114152844945 ps
CPU time 1719.33 seconds
Started Dec 27 01:23:52 PM PST 23
Finished Dec 27 01:52:33 PM PST 23
Peak memory 198280 kb
Host smart-fd6cff01-afa3-4ab9-988e-3d62af27d41c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=3321340125 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.gpio_stress_all_with_rand_reset.3321340125
Directory /workspace/29.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/3.gpio_alert_test.2000877674
Short name T348
Test name
Test status
Simulation time 30272467 ps
CPU time 0.56 seconds
Started Dec 27 01:21:20 PM PST 23
Finished Dec 27 01:21:21 PM PST 23
Peak memory 194876 kb
Host smart-78da1f0d-2bff-4e51-a023-a14fc3e7899f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2000877674 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_alert_test.2000877674
Directory /workspace/3.gpio_alert_test/latest

Test location /workspace/coverage/default/3.gpio_dout_din_regs_random_rw.78860791
Short name T734
Test name
Test status
Simulation time 24831522 ps
CPU time 0.71 seconds
Started Dec 27 01:22:09 PM PST 23
Finished Dec 27 01:22:13 PM PST 23
Peak memory 194892 kb
Host smart-911fb272-ec8f-498b-88eb-a36eb1e6bf39
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=78860791 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_dout_din_regs_random_rw.78860791
Directory /workspace/3.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/3.gpio_filter_stress.3799508567
Short name T730
Test name
Test status
Simulation time 911651424 ps
CPU time 11.35 seconds
Started Dec 27 01:21:15 PM PST 23
Finished Dec 27 01:21:27 PM PST 23
Peak memory 195588 kb
Host smart-2faad8bf-e316-4e0a-8e5c-8e2f5b3f7f40
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3799508567 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_filter_stres
s.3799508567
Directory /workspace/3.gpio_filter_stress/latest

Test location /workspace/coverage/default/3.gpio_full_random.1153178062
Short name T344
Test name
Test status
Simulation time 131235881 ps
CPU time 0.72 seconds
Started Dec 27 01:21:15 PM PST 23
Finished Dec 27 01:21:16 PM PST 23
Peak memory 195676 kb
Host smart-99ef463b-af04-470a-982d-79fd72b8cf12
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1153178062 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_full_random.1153178062
Directory /workspace/3.gpio_full_random/latest

Test location /workspace/coverage/default/3.gpio_intr_rand_pgm.833954461
Short name T537
Test name
Test status
Simulation time 205279323 ps
CPU time 0.89 seconds
Started Dec 27 01:21:30 PM PST 23
Finished Dec 27 01:21:32 PM PST 23
Peak memory 196904 kb
Host smart-e37061e9-2d68-402b-9021-0a92cb4e1eea
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=833954461 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_intr_rand_pgm.833954461
Directory /workspace/3.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/3.gpio_intr_with_filter_rand_intr_event.123011690
Short name T402
Test name
Test status
Simulation time 65663397 ps
CPU time 2.7 seconds
Started Dec 27 01:21:27 PM PST 23
Finished Dec 27 01:21:31 PM PST 23
Peak memory 198268 kb
Host smart-e6b616c0-7497-40ec-8287-c33a13337e7d
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=123011690 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 3.gpio_intr_with_filter_rand_intr_event.123011690
Directory /workspace/3.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/3.gpio_rand_intr_trigger.3704567879
Short name T412
Test name
Test status
Simulation time 150469229 ps
CPU time 3.33 seconds
Started Dec 27 01:22:03 PM PST 23
Finished Dec 27 01:22:07 PM PST 23
Peak memory 197088 kb
Host smart-63e3c390-605c-45dc-a542-d16f2f147af1
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3704567879 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_rand_intr_trigger.
3704567879
Directory /workspace/3.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/3.gpio_random_dout_din.3792651840
Short name T728
Test name
Test status
Simulation time 121290025 ps
CPU time 1.22 seconds
Started Dec 27 01:22:07 PM PST 23
Finished Dec 27 01:22:12 PM PST 23
Peak memory 197056 kb
Host smart-f52f14f0-030a-4f14-987b-4f407bfb0ad5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3792651840 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_random_dout_din.3792651840
Directory /workspace/3.gpio_random_dout_din/latest

Test location /workspace/coverage/default/3.gpio_random_dout_din_no_pullup_pulldown.1088310038
Short name T647
Test name
Test status
Simulation time 31908287 ps
CPU time 0.81 seconds
Started Dec 27 01:22:09 PM PST 23
Finished Dec 27 01:22:13 PM PST 23
Peak memory 196308 kb
Host smart-aa8e3c32-12ce-4eae-85bb-771e4141c665
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1088310038 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_random_dout_din_no_pullup
_pulldown.1088310038
Directory /workspace/3.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/3.gpio_random_long_reg_writes_reg_reads.1816554136
Short name T783
Test name
Test status
Simulation time 109798665 ps
CPU time 4.61 seconds
Started Dec 27 01:21:52 PM PST 23
Finished Dec 27 01:21:57 PM PST 23
Peak memory 197288 kb
Host smart-22c4ed8c-025e-4322-adcc-93c080065475
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1816554136 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_ran
dom_long_reg_writes_reg_reads.1816554136
Directory /workspace/3.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/3.gpio_sec_cm.2848590741
Short name T62
Test name
Test status
Simulation time 247729840 ps
CPU time 0.85 seconds
Started Dec 27 01:21:11 PM PST 23
Finished Dec 27 01:21:13 PM PST 23
Peak memory 213456 kb
Host smart-d4dd3366-96da-4aa7-b477-2ae1e983e522
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2848590741 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_sec_cm.2848590741
Directory /workspace/3.gpio_sec_cm/latest

Test location /workspace/coverage/default/3.gpio_smoke.401095839
Short name T625
Test name
Test status
Simulation time 104580585 ps
CPU time 1.04 seconds
Started Dec 27 01:21:52 PM PST 23
Finished Dec 27 01:21:54 PM PST 23
Peak memory 195892 kb
Host smart-c107bb01-0303-4c0a-ba17-ff4fcb7fcefa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=401095839 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_smoke.401095839
Directory /workspace/3.gpio_smoke/latest

Test location /workspace/coverage/default/3.gpio_smoke_no_pullup_pulldown.1189137830
Short name T281
Test name
Test status
Simulation time 128883579 ps
CPU time 1.05 seconds
Started Dec 27 01:21:55 PM PST 23
Finished Dec 27 01:21:57 PM PST 23
Peak memory 195756 kb
Host smart-58fbee5f-6f84-4500-87aa-3101dd3f97c8
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1189137830 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_smoke_no_pullup_pulldown.1189137830
Directory /workspace/3.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/3.gpio_stress_all.3850253618
Short name T481
Test name
Test status
Simulation time 8011514548 ps
CPU time 60.7 seconds
Started Dec 27 01:21:16 PM PST 23
Finished Dec 27 01:22:17 PM PST 23
Peak memory 198276 kb
Host smart-df483f2a-6597-41c8-a59f-cddf689bf8c7
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3850253618 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.g
pio_stress_all.3850253618
Directory /workspace/3.gpio_stress_all/latest

Test location /workspace/coverage/default/3.gpio_stress_all_with_rand_reset.2233889836
Short name T614
Test name
Test status
Simulation time 50181421667 ps
CPU time 342.56 seconds
Started Dec 27 01:21:16 PM PST 23
Finished Dec 27 01:26:59 PM PST 23
Peak memory 198332 kb
Host smart-daa51fe8-e79f-4e7b-b135-65977e3acdbb
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=2233889836 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.gpio_stress_all_with_rand_reset.2233889836
Directory /workspace/3.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/30.gpio_alert_test.3970365720
Short name T616
Test name
Test status
Simulation time 92448402 ps
CPU time 0.56 seconds
Started Dec 27 01:23:52 PM PST 23
Finished Dec 27 01:23:54 PM PST 23
Peak memory 193988 kb
Host smart-d699243a-2827-4183-bb2d-e17ed1cd65e8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3970365720 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_alert_test.3970365720
Directory /workspace/30.gpio_alert_test/latest

Test location /workspace/coverage/default/30.gpio_dout_din_regs_random_rw.962891037
Short name T383
Test name
Test status
Simulation time 161015533 ps
CPU time 0.75 seconds
Started Dec 27 01:23:46 PM PST 23
Finished Dec 27 01:23:47 PM PST 23
Peak memory 195380 kb
Host smart-208c2a60-9f25-4ca5-84ee-fa4d35cae1e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=962891037 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_dout_din_regs_random_rw.962891037
Directory /workspace/30.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/30.gpio_filter_stress.2217303075
Short name T773
Test name
Test status
Simulation time 659574726 ps
CPU time 8.88 seconds
Started Dec 27 01:24:16 PM PST 23
Finished Dec 27 01:24:26 PM PST 23
Peak memory 197040 kb
Host smart-543ffcfd-5bae-4ac7-a50b-05c0ddb8c5be
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2217303075 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_filter_stre
ss.2217303075
Directory /workspace/30.gpio_filter_stress/latest

Test location /workspace/coverage/default/30.gpio_full_random.3188288795
Short name T813
Test name
Test status
Simulation time 132398533 ps
CPU time 0.8 seconds
Started Dec 27 01:23:46 PM PST 23
Finished Dec 27 01:23:47 PM PST 23
Peak memory 196064 kb
Host smart-d33a9a80-79dd-4c23-838d-40632da255ce
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3188288795 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_full_random.3188288795
Directory /workspace/30.gpio_full_random/latest

Test location /workspace/coverage/default/30.gpio_intr_rand_pgm.2104627513
Short name T761
Test name
Test status
Simulation time 53372483 ps
CPU time 0.91 seconds
Started Dec 27 01:24:31 PM PST 23
Finished Dec 27 01:24:33 PM PST 23
Peak memory 196836 kb
Host smart-9d30d19e-f8a1-42c6-b07b-2022b1273dc5
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2104627513 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_intr_rand_pgm.2104627513
Directory /workspace/30.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/30.gpio_intr_with_filter_rand_intr_event.2170568718
Short name T543
Test name
Test status
Simulation time 415145790 ps
CPU time 2.05 seconds
Started Dec 27 01:23:48 PM PST 23
Finished Dec 27 01:23:51 PM PST 23
Peak memory 198076 kb
Host smart-b00ff057-dd47-47c3-a9e2-f04a1a9373dc
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2170568718 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 30.gpio_intr_with_filter_rand_intr_event.2170568718
Directory /workspace/30.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/30.gpio_rand_intr_trigger.4095877288
Short name T696
Test name
Test status
Simulation time 74362443 ps
CPU time 1.53 seconds
Started Dec 27 01:24:17 PM PST 23
Finished Dec 27 01:24:20 PM PST 23
Peak memory 196124 kb
Host smart-b832903d-68c9-48a5-9d7a-970767d935b8
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4095877288 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_rand_intr_trigger
.4095877288
Directory /workspace/30.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/30.gpio_random_dout_din.890428649
Short name T566
Test name
Test status
Simulation time 23812059 ps
CPU time 0.95 seconds
Started Dec 27 01:23:50 PM PST 23
Finished Dec 27 01:23:52 PM PST 23
Peak memory 195996 kb
Host smart-b36431ea-6e66-48ce-99f9-b5d67250fe8b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=890428649 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_random_dout_din.890428649
Directory /workspace/30.gpio_random_dout_din/latest

Test location /workspace/coverage/default/30.gpio_random_dout_din_no_pullup_pulldown.1505517168
Short name T597
Test name
Test status
Simulation time 29780049 ps
CPU time 0.65 seconds
Started Dec 27 01:23:48 PM PST 23
Finished Dec 27 01:23:50 PM PST 23
Peak memory 194948 kb
Host smart-c60b9de0-f154-4ddb-afea-75018c130437
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1505517168 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_random_dout_din_no_pullu
p_pulldown.1505517168
Directory /workspace/30.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/30.gpio_random_long_reg_writes_reg_reads.2899497863
Short name T296
Test name
Test status
Simulation time 427714359 ps
CPU time 2.53 seconds
Started Dec 27 01:24:09 PM PST 23
Finished Dec 27 01:24:12 PM PST 23
Peak memory 198112 kb
Host smart-01c09571-ec95-4b39-9bd9-486bef4e2d8d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2899497863 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_ra
ndom_long_reg_writes_reg_reads.2899497863
Directory /workspace/30.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/30.gpio_smoke.2225945548
Short name T858
Test name
Test status
Simulation time 233595043 ps
CPU time 1.1 seconds
Started Dec 27 01:24:29 PM PST 23
Finished Dec 27 01:24:30 PM PST 23
Peak memory 195564 kb
Host smart-227e3090-264f-486c-8d6d-3b6ef6b3ec73
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2225945548 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_smoke.2225945548
Directory /workspace/30.gpio_smoke/latest

Test location /workspace/coverage/default/30.gpio_smoke_no_pullup_pulldown.501620687
Short name T347
Test name
Test status
Simulation time 29190346 ps
CPU time 0.92 seconds
Started Dec 27 01:24:26 PM PST 23
Finished Dec 27 01:24:28 PM PST 23
Peak memory 196628 kb
Host smart-7de2e6b6-8ed3-46a1-840c-48ac493671d3
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=501620687 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_smoke_no_pullup_pulldown.501620687
Directory /workspace/30.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/30.gpio_stress_all.4283303807
Short name T598
Test name
Test status
Simulation time 4161199890 ps
CPU time 55.34 seconds
Started Dec 27 01:23:51 PM PST 23
Finished Dec 27 01:24:47 PM PST 23
Peak memory 198144 kb
Host smart-3f8f76c1-2809-4f7d-9efc-6adce7778f28
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4283303807 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.
gpio_stress_all.4283303807
Directory /workspace/30.gpio_stress_all/latest

Test location /workspace/coverage/default/30.gpio_stress_all_with_rand_reset.433447236
Short name T563
Test name
Test status
Simulation time 25372498869 ps
CPU time 317.31 seconds
Started Dec 27 01:23:56 PM PST 23
Finished Dec 27 01:29:15 PM PST 23
Peak memory 198308 kb
Host smart-9a8bf52f-4efe-452b-adc0-ab2e9ce286ea
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=433447236 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.gpio_stress_all_with_rand_reset.433447236
Directory /workspace/30.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/31.gpio_alert_test.3990375938
Short name T351
Test name
Test status
Simulation time 58299560 ps
CPU time 0.61 seconds
Started Dec 27 01:24:10 PM PST 23
Finished Dec 27 01:24:11 PM PST 23
Peak memory 194984 kb
Host smart-5f609684-09a4-40ff-8f98-18b15719443a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3990375938 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_alert_test.3990375938
Directory /workspace/31.gpio_alert_test/latest

Test location /workspace/coverage/default/31.gpio_dout_din_regs_random_rw.2343904308
Short name T732
Test name
Test status
Simulation time 41482055 ps
CPU time 0.99 seconds
Started Dec 27 01:23:46 PM PST 23
Finished Dec 27 01:23:48 PM PST 23
Peak memory 196596 kb
Host smart-04b97593-f779-45ea-be81-5f0ccdc7e3ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2343904308 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_dout_din_regs_random_rw.2343904308
Directory /workspace/31.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/31.gpio_filter_stress.2131796318
Short name T381
Test name
Test status
Simulation time 1806025898 ps
CPU time 22.71 seconds
Started Dec 27 01:23:49 PM PST 23
Finished Dec 27 01:24:12 PM PST 23
Peak memory 195664 kb
Host smart-e37bd88f-121c-44c4-8c9b-7826d8018aee
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2131796318 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_filter_stre
ss.2131796318
Directory /workspace/31.gpio_filter_stress/latest

Test location /workspace/coverage/default/31.gpio_full_random.2291528380
Short name T592
Test name
Test status
Simulation time 148389099 ps
CPU time 0.69 seconds
Started Dec 27 01:23:50 PM PST 23
Finished Dec 27 01:23:52 PM PST 23
Peak memory 194696 kb
Host smart-11bd1665-3c7c-474b-8a6c-6061c17f3fdc
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2291528380 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_full_random.2291528380
Directory /workspace/31.gpio_full_random/latest

Test location /workspace/coverage/default/31.gpio_intr_rand_pgm.4208726811
Short name T596
Test name
Test status
Simulation time 34719378 ps
CPU time 0.96 seconds
Started Dec 27 01:23:47 PM PST 23
Finished Dec 27 01:23:48 PM PST 23
Peak memory 195912 kb
Host smart-7f4bb473-67c3-4ff9-8778-cbc5a461bb30
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4208726811 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_intr_rand_pgm.4208726811
Directory /workspace/31.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/31.gpio_intr_with_filter_rand_intr_event.1887415371
Short name T808
Test name
Test status
Simulation time 60503242 ps
CPU time 1.48 seconds
Started Dec 27 01:23:46 PM PST 23
Finished Dec 27 01:23:48 PM PST 23
Peak memory 198236 kb
Host smart-f60fa716-4fbd-4010-92ae-a559b1aec20e
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1887415371 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 31.gpio_intr_with_filter_rand_intr_event.1887415371
Directory /workspace/31.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/31.gpio_rand_intr_trigger.3655829400
Short name T416
Test name
Test status
Simulation time 188972164 ps
CPU time 2.98 seconds
Started Dec 27 01:23:49 PM PST 23
Finished Dec 27 01:23:53 PM PST 23
Peak memory 198220 kb
Host smart-3788d519-f736-4cac-ad7e-dc6ed62011a1
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3655829400 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_rand_intr_trigger
.3655829400
Directory /workspace/31.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/31.gpio_random_dout_din.956954103
Short name T881
Test name
Test status
Simulation time 82894234 ps
CPU time 0.86 seconds
Started Dec 27 01:24:11 PM PST 23
Finished Dec 27 01:24:13 PM PST 23
Peak memory 195956 kb
Host smart-b29d0986-1d52-4de2-a2ce-c5300b0c2a31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=956954103 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_random_dout_din.956954103
Directory /workspace/31.gpio_random_dout_din/latest

Test location /workspace/coverage/default/31.gpio_random_dout_din_no_pullup_pulldown.1313682159
Short name T743
Test name
Test status
Simulation time 37443068 ps
CPU time 0.79 seconds
Started Dec 27 01:24:17 PM PST 23
Finished Dec 27 01:24:19 PM PST 23
Peak memory 196580 kb
Host smart-2472827f-0506-4b39-8eb4-63ff8850f7e5
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1313682159 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_random_dout_din_no_pullu
p_pulldown.1313682159
Directory /workspace/31.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/31.gpio_random_long_reg_writes_reg_reads.2586265629
Short name T272
Test name
Test status
Simulation time 179138721 ps
CPU time 4.36 seconds
Started Dec 27 01:23:52 PM PST 23
Finished Dec 27 01:23:58 PM PST 23
Peak memory 198008 kb
Host smart-ea803b16-bb1c-4b13-b0bd-b7a993658063
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2586265629 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_ra
ndom_long_reg_writes_reg_reads.2586265629
Directory /workspace/31.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/31.gpio_smoke.3999500090
Short name T712
Test name
Test status
Simulation time 190972913 ps
CPU time 1.16 seconds
Started Dec 27 01:24:18 PM PST 23
Finished Dec 27 01:24:20 PM PST 23
Peak memory 196276 kb
Host smart-471edd14-4671-473a-8b16-85f23fdcaebe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3999500090 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_smoke.3999500090
Directory /workspace/31.gpio_smoke/latest

Test location /workspace/coverage/default/31.gpio_smoke_no_pullup_pulldown.3799717002
Short name T686
Test name
Test status
Simulation time 159192011 ps
CPU time 1.29 seconds
Started Dec 27 01:23:54 PM PST 23
Finished Dec 27 01:23:57 PM PST 23
Peak memory 196916 kb
Host smart-94c1d08b-0857-4f49-ab1e-0682601ae654
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3799717002 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_smoke_no_pullup_pulldown.3799717002
Directory /workspace/31.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/31.gpio_stress_all.3550134010
Short name T474
Test name
Test status
Simulation time 3926830857 ps
CPU time 102.95 seconds
Started Dec 27 01:23:50 PM PST 23
Finished Dec 27 01:25:34 PM PST 23
Peak memory 198276 kb
Host smart-0f97dd0c-9dbd-46a5-8c50-8c69731af790
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3550134010 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.
gpio_stress_all.3550134010
Directory /workspace/31.gpio_stress_all/latest

Test location /workspace/coverage/default/31.gpio_stress_all_with_rand_reset.1320280450
Short name T475
Test name
Test status
Simulation time 2561983825 ps
CPU time 32.65 seconds
Started Dec 27 01:23:48 PM PST 23
Finished Dec 27 01:24:22 PM PST 23
Peak memory 197780 kb
Host smart-8e84ce50-d0fa-424e-92b4-764e804dd17c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=1320280450 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.gpio_stress_all_with_rand_reset.1320280450
Directory /workspace/31.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/32.gpio_alert_test.4060694209
Short name T876
Test name
Test status
Simulation time 47433154 ps
CPU time 0.56 seconds
Started Dec 27 01:23:49 PM PST 23
Finished Dec 27 01:23:51 PM PST 23
Peak memory 193960 kb
Host smart-89e510cf-54a0-4b26-ba9d-1c0bed087c5f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4060694209 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_alert_test.4060694209
Directory /workspace/32.gpio_alert_test/latest

Test location /workspace/coverage/default/32.gpio_dout_din_regs_random_rw.2115401783
Short name T398
Test name
Test status
Simulation time 106648661 ps
CPU time 0.97 seconds
Started Dec 27 01:24:20 PM PST 23
Finished Dec 27 01:24:22 PM PST 23
Peak memory 196728 kb
Host smart-87689f0d-a3ac-48d4-92ab-c943662ec4e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2115401783 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_dout_din_regs_random_rw.2115401783
Directory /workspace/32.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/32.gpio_filter_stress.2044938115
Short name T322
Test name
Test status
Simulation time 532732064 ps
CPU time 13.88 seconds
Started Dec 27 01:24:14 PM PST 23
Finished Dec 27 01:24:29 PM PST 23
Peak memory 198092 kb
Host smart-01c7dc46-3149-46f3-bbc4-09d5c2a479e6
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2044938115 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_filter_stre
ss.2044938115
Directory /workspace/32.gpio_filter_stress/latest

Test location /workspace/coverage/default/32.gpio_full_random.3964384007
Short name T704
Test name
Test status
Simulation time 56316228 ps
CPU time 0.86 seconds
Started Dec 27 01:23:56 PM PST 23
Finished Dec 27 01:23:58 PM PST 23
Peak memory 196036 kb
Host smart-be28d208-7f5d-489e-95e9-fb568fc65f36
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3964384007 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_full_random.3964384007
Directory /workspace/32.gpio_full_random/latest

Test location /workspace/coverage/default/32.gpio_intr_rand_pgm.3380946649
Short name T530
Test name
Test status
Simulation time 116781518 ps
CPU time 1.02 seconds
Started Dec 27 01:24:24 PM PST 23
Finished Dec 27 01:24:26 PM PST 23
Peak memory 195888 kb
Host smart-f7da8c82-480b-4604-8f95-7199979f8f02
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3380946649 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_intr_rand_pgm.3380946649
Directory /workspace/32.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/32.gpio_intr_with_filter_rand_intr_event.1981902873
Short name T539
Test name
Test status
Simulation time 57022221 ps
CPU time 2.18 seconds
Started Dec 27 01:23:53 PM PST 23
Finished Dec 27 01:23:56 PM PST 23
Peak memory 198156 kb
Host smart-889c841f-9d61-4364-8539-c3040ccc47ad
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1981902873 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 32.gpio_intr_with_filter_rand_intr_event.1981902873
Directory /workspace/32.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/32.gpio_rand_intr_trigger.2235634158
Short name T641
Test name
Test status
Simulation time 199521337 ps
CPU time 2.96 seconds
Started Dec 27 01:24:21 PM PST 23
Finished Dec 27 01:24:25 PM PST 23
Peak memory 198164 kb
Host smart-bfeba9df-f3f0-4383-a5ed-cb92790fc56a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2235634158 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_rand_intr_trigger
.2235634158
Directory /workspace/32.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/32.gpio_random_dout_din.1974256332
Short name T282
Test name
Test status
Simulation time 154182985 ps
CPU time 1.31 seconds
Started Dec 27 01:23:51 PM PST 23
Finished Dec 27 01:23:54 PM PST 23
Peak memory 197104 kb
Host smart-9061c0f6-fa29-4459-a970-f9f41867f169
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1974256332 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_random_dout_din.1974256332
Directory /workspace/32.gpio_random_dout_din/latest

Test location /workspace/coverage/default/32.gpio_random_dout_din_no_pullup_pulldown.1824161667
Short name T224
Test name
Test status
Simulation time 65647637 ps
CPU time 1.2 seconds
Started Dec 27 01:23:51 PM PST 23
Finished Dec 27 01:23:53 PM PST 23
Peak memory 196624 kb
Host smart-62a85c2f-6798-4d0b-bbf0-bc9a7a127b00
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1824161667 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_random_dout_din_no_pullu
p_pulldown.1824161667
Directory /workspace/32.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/32.gpio_random_long_reg_writes_reg_reads.3742262799
Short name T545
Test name
Test status
Simulation time 911128653 ps
CPU time 6.19 seconds
Started Dec 27 01:24:18 PM PST 23
Finished Dec 27 01:24:25 PM PST 23
Peak memory 197968 kb
Host smart-467edc51-b5b7-4511-ac91-0b74f62ba82d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3742262799 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_ra
ndom_long_reg_writes_reg_reads.3742262799
Directory /workspace/32.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/32.gpio_smoke.2786196351
Short name T829
Test name
Test status
Simulation time 111946827 ps
CPU time 1.02 seconds
Started Dec 27 01:23:52 PM PST 23
Finished Dec 27 01:23:55 PM PST 23
Peak memory 196524 kb
Host smart-e5dd7649-1c63-444a-918a-4d73132efa5c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2786196351 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_smoke.2786196351
Directory /workspace/32.gpio_smoke/latest

Test location /workspace/coverage/default/32.gpio_smoke_no_pullup_pulldown.404921723
Short name T781
Test name
Test status
Simulation time 21878881 ps
CPU time 0.86 seconds
Started Dec 27 01:23:53 PM PST 23
Finished Dec 27 01:23:55 PM PST 23
Peak memory 196060 kb
Host smart-2dd7b9a7-5f3c-435c-8160-ddc1e3beb0eb
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=404921723 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_smoke_no_pullup_pulldown.404921723
Directory /workspace/32.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/32.gpio_stress_all.3086018848
Short name T68
Test name
Test status
Simulation time 60869295659 ps
CPU time 171.56 seconds
Started Dec 27 01:23:46 PM PST 23
Finished Dec 27 01:26:38 PM PST 23
Peak memory 198272 kb
Host smart-54a69473-d702-4aad-a705-2a97dc030113
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3086018848 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.
gpio_stress_all.3086018848
Directory /workspace/32.gpio_stress_all/latest

Test location /workspace/coverage/default/32.gpio_stress_all_with_rand_reset.3136594866
Short name T375
Test name
Test status
Simulation time 14953183063 ps
CPU time 282.03 seconds
Started Dec 27 01:23:48 PM PST 23
Finished Dec 27 01:28:31 PM PST 23
Peak memory 198300 kb
Host smart-2eeda2f6-7ba6-43da-b55e-4ee39ecd8405
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=3136594866 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.gpio_stress_all_with_rand_reset.3136594866
Directory /workspace/32.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/33.gpio_alert_test.2725937365
Short name T532
Test name
Test status
Simulation time 16327621 ps
CPU time 0.57 seconds
Started Dec 27 01:24:18 PM PST 23
Finished Dec 27 01:24:20 PM PST 23
Peak memory 194188 kb
Host smart-d6b8a2ba-9afb-4040-992d-f228707e02a7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2725937365 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_alert_test.2725937365
Directory /workspace/33.gpio_alert_test/latest

Test location /workspace/coverage/default/33.gpio_dout_din_regs_random_rw.3062780749
Short name T478
Test name
Test status
Simulation time 102051824 ps
CPU time 0.75 seconds
Started Dec 27 01:24:36 PM PST 23
Finished Dec 27 01:24:38 PM PST 23
Peak memory 195456 kb
Host smart-af010a2c-988e-4103-b509-5feb452dbaa1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3062780749 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_dout_din_regs_random_rw.3062780749
Directory /workspace/33.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/33.gpio_filter_stress.1241721698
Short name T638
Test name
Test status
Simulation time 535650653 ps
CPU time 7.25 seconds
Started Dec 27 01:23:48 PM PST 23
Finished Dec 27 01:23:57 PM PST 23
Peak memory 196696 kb
Host smart-9de5158e-167d-4579-a983-c7c220ceafa4
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1241721698 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_filter_stre
ss.1241721698
Directory /workspace/33.gpio_filter_stress/latest

Test location /workspace/coverage/default/33.gpio_full_random.3404169578
Short name T499
Test name
Test status
Simulation time 80618182 ps
CPU time 0.96 seconds
Started Dec 27 01:23:51 PM PST 23
Finished Dec 27 01:23:53 PM PST 23
Peak memory 197180 kb
Host smart-fd8f6870-20d3-4977-9bb0-0636514247e8
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3404169578 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_full_random.3404169578
Directory /workspace/33.gpio_full_random/latest

Test location /workspace/coverage/default/33.gpio_intr_rand_pgm.3648488853
Short name T775
Test name
Test status
Simulation time 83573107 ps
CPU time 1.4 seconds
Started Dec 27 01:23:51 PM PST 23
Finished Dec 27 01:23:53 PM PST 23
Peak memory 197152 kb
Host smart-e91035b7-fc8a-4667-ae6f-662d30c9402f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3648488853 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_intr_rand_pgm.3648488853
Directory /workspace/33.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/33.gpio_rand_intr_trigger.595885777
Short name T314
Test name
Test status
Simulation time 33961888 ps
CPU time 0.98 seconds
Started Dec 27 01:23:51 PM PST 23
Finished Dec 27 01:23:52 PM PST 23
Peak memory 195560 kb
Host smart-e26f71f7-8f42-426c-bb93-906711d7846c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=595885777 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_rand_intr_trigger.
595885777
Directory /workspace/33.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/33.gpio_random_dout_din.1326376942
Short name T342
Test name
Test status
Simulation time 224462065 ps
CPU time 1.35 seconds
Started Dec 27 01:23:55 PM PST 23
Finished Dec 27 01:23:57 PM PST 23
Peak memory 196844 kb
Host smart-8b7fe520-6549-4aa9-a564-7a939e5cef0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1326376942 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_random_dout_din.1326376942
Directory /workspace/33.gpio_random_dout_din/latest

Test location /workspace/coverage/default/33.gpio_random_dout_din_no_pullup_pulldown.3077587984
Short name T551
Test name
Test status
Simulation time 78645847 ps
CPU time 1.08 seconds
Started Dec 27 01:23:50 PM PST 23
Finished Dec 27 01:23:52 PM PST 23
Peak memory 196016 kb
Host smart-60fcddcc-05c3-4bd5-bf0f-f0781beafb3f
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3077587984 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_random_dout_din_no_pullu
p_pulldown.3077587984
Directory /workspace/33.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/33.gpio_random_long_reg_writes_reg_reads.2152560864
Short name T691
Test name
Test status
Simulation time 105558532 ps
CPU time 2.6 seconds
Started Dec 27 01:24:12 PM PST 23
Finished Dec 27 01:24:16 PM PST 23
Peak memory 198060 kb
Host smart-f174f7f5-9a67-4e37-99fc-ccc6e808a1f8
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2152560864 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_ra
ndom_long_reg_writes_reg_reads.2152560864
Directory /workspace/33.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/33.gpio_smoke.1812524392
Short name T414
Test name
Test status
Simulation time 33429390 ps
CPU time 0.99 seconds
Started Dec 27 01:24:10 PM PST 23
Finished Dec 27 01:24:11 PM PST 23
Peak memory 195820 kb
Host smart-0c36ca14-1c5f-4ad4-9919-d3ad4bb5c6ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1812524392 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_smoke.1812524392
Directory /workspace/33.gpio_smoke/latest

Test location /workspace/coverage/default/33.gpio_smoke_no_pullup_pulldown.1756153319
Short name T669
Test name
Test status
Simulation time 47538101 ps
CPU time 0.77 seconds
Started Dec 27 01:23:46 PM PST 23
Finished Dec 27 01:23:48 PM PST 23
Peak memory 195228 kb
Host smart-45b59fa4-0a76-4f2d-8ee2-fdb46389648a
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1756153319 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_smoke_no_pullup_pulldown.1756153319
Directory /workspace/33.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/33.gpio_stress_all.1181874293
Short name T486
Test name
Test status
Simulation time 12441895597 ps
CPU time 160.69 seconds
Started Dec 27 01:24:49 PM PST 23
Finished Dec 27 01:27:32 PM PST 23
Peak memory 198164 kb
Host smart-6de3c6ca-4434-4ce1-8a0a-fd89433c9def
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1181874293 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.
gpio_stress_all.1181874293
Directory /workspace/33.gpio_stress_all/latest

Test location /workspace/coverage/default/33.gpio_stress_all_with_rand_reset.654832043
Short name T239
Test name
Test status
Simulation time 95011072002 ps
CPU time 1236.5 seconds
Started Dec 27 01:23:51 PM PST 23
Finished Dec 27 01:44:29 PM PST 23
Peak memory 206508 kb
Host smart-6f7927a3-674c-4bb3-bc3e-bef1ccc9126e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=654832043 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.gpio_stress_all_with_rand_reset.654832043
Directory /workspace/33.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/34.gpio_alert_test.86403462
Short name T880
Test name
Test status
Simulation time 15150850 ps
CPU time 0.56 seconds
Started Dec 27 01:24:49 PM PST 23
Finished Dec 27 01:24:52 PM PST 23
Peak memory 192812 kb
Host smart-c17a73c9-03e5-4fe9-9c2c-7030b62f5894
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=86403462 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_alert_test.86403462
Directory /workspace/34.gpio_alert_test/latest

Test location /workspace/coverage/default/34.gpio_dout_din_regs_random_rw.290610337
Short name T515
Test name
Test status
Simulation time 44336903 ps
CPU time 0.85 seconds
Started Dec 27 01:23:52 PM PST 23
Finished Dec 27 01:23:55 PM PST 23
Peak memory 195372 kb
Host smart-f81dad82-2736-448a-a0a2-d6536bc4eca9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=290610337 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_dout_din_regs_random_rw.290610337
Directory /workspace/34.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/34.gpio_filter_stress.1024328727
Short name T568
Test name
Test status
Simulation time 13159011642 ps
CPU time 25.56 seconds
Started Dec 27 01:24:15 PM PST 23
Finished Dec 27 01:24:41 PM PST 23
Peak memory 196908 kb
Host smart-da8456c4-e097-4963-a13d-534e0ae3fe44
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1024328727 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_filter_stre
ss.1024328727
Directory /workspace/34.gpio_filter_stress/latest

Test location /workspace/coverage/default/34.gpio_full_random.4094330257
Short name T749
Test name
Test status
Simulation time 67174221 ps
CPU time 0.89 seconds
Started Dec 27 01:24:28 PM PST 23
Finished Dec 27 01:24:30 PM PST 23
Peak memory 196408 kb
Host smart-31c857bf-759b-4a5b-b09e-4e03721bca45
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4094330257 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_full_random.4094330257
Directory /workspace/34.gpio_full_random/latest

Test location /workspace/coverage/default/34.gpio_intr_rand_pgm.1071352510
Short name T818
Test name
Test status
Simulation time 60972167 ps
CPU time 1.1 seconds
Started Dec 27 01:23:54 PM PST 23
Finished Dec 27 01:23:57 PM PST 23
Peak memory 196176 kb
Host smart-22f09593-e8b8-4791-803f-78ba681e0ef4
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1071352510 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_intr_rand_pgm.1071352510
Directory /workspace/34.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/34.gpio_intr_with_filter_rand_intr_event.593399796
Short name T230
Test name
Test status
Simulation time 23010835 ps
CPU time 0.95 seconds
Started Dec 27 01:24:29 PM PST 23
Finished Dec 27 01:24:31 PM PST 23
Peak memory 196212 kb
Host smart-2807c75e-dd15-41b3-a47d-c038d0c6c7f6
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=593399796 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 34.gpio_intr_with_filter_rand_intr_event.593399796
Directory /workspace/34.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/34.gpio_rand_intr_trigger.2522385764
Short name T66
Test name
Test status
Simulation time 574484677 ps
CPU time 2.94 seconds
Started Dec 27 01:23:54 PM PST 23
Finished Dec 27 01:23:58 PM PST 23
Peak memory 197272 kb
Host smart-45d99c5f-7d56-4c07-bda3-6341ba93458e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2522385764 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_rand_intr_trigger
.2522385764
Directory /workspace/34.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/34.gpio_random_dout_din.2950054856
Short name T337
Test name
Test status
Simulation time 35879429 ps
CPU time 1.18 seconds
Started Dec 27 01:24:33 PM PST 23
Finished Dec 27 01:24:35 PM PST 23
Peak memory 197244 kb
Host smart-168fb210-ffc9-4b52-b9b3-b9b578307a70
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2950054856 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_random_dout_din.2950054856
Directory /workspace/34.gpio_random_dout_din/latest

Test location /workspace/coverage/default/34.gpio_random_dout_din_no_pullup_pulldown.3503774070
Short name T729
Test name
Test status
Simulation time 65478547 ps
CPU time 1.1 seconds
Started Dec 27 01:24:18 PM PST 23
Finished Dec 27 01:24:21 PM PST 23
Peak memory 196188 kb
Host smart-2e603f87-1654-44d8-a571-8378f519d8d9
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3503774070 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_random_dout_din_no_pullu
p_pulldown.3503774070
Directory /workspace/34.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/34.gpio_random_long_reg_writes_reg_reads.3637567097
Short name T308
Test name
Test status
Simulation time 255459253 ps
CPU time 5.85 seconds
Started Dec 27 01:24:47 PM PST 23
Finished Dec 27 01:24:56 PM PST 23
Peak memory 198056 kb
Host smart-a1a61751-596b-45da-b15c-3f0ee66ecd2b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3637567097 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_ra
ndom_long_reg_writes_reg_reads.3637567097
Directory /workspace/34.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/34.gpio_smoke.3565301476
Short name T699
Test name
Test status
Simulation time 229653874 ps
CPU time 1.08 seconds
Started Dec 27 01:24:31 PM PST 23
Finished Dec 27 01:24:33 PM PST 23
Peak memory 196560 kb
Host smart-99ca0702-1d92-4d22-9803-eb9289cd153a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3565301476 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_smoke.3565301476
Directory /workspace/34.gpio_smoke/latest

Test location /workspace/coverage/default/34.gpio_smoke_no_pullup_pulldown.4206932510
Short name T559
Test name
Test status
Simulation time 49086178 ps
CPU time 1 seconds
Started Dec 27 01:23:50 PM PST 23
Finished Dec 27 01:23:52 PM PST 23
Peak memory 196364 kb
Host smart-9d980a04-7783-4caf-be7f-d0b220ce2a2f
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4206932510 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_smoke_no_pullup_pulldown.4206932510
Directory /workspace/34.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/34.gpio_stress_all.857107479
Short name T762
Test name
Test status
Simulation time 5185382201 ps
CPU time 142.66 seconds
Started Dec 27 01:24:12 PM PST 23
Finished Dec 27 01:26:35 PM PST 23
Peak memory 198240 kb
Host smart-c143ccf1-6d46-4a96-979e-bbcefa11663b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=857107479 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.g
pio_stress_all.857107479
Directory /workspace/34.gpio_stress_all/latest

Test location /workspace/coverage/default/34.gpio_stress_all_with_rand_reset.2045375970
Short name T70
Test name
Test status
Simulation time 141283617561 ps
CPU time 1371.42 seconds
Started Dec 27 01:24:11 PM PST 23
Finished Dec 27 01:47:03 PM PST 23
Peak memory 198388 kb
Host smart-141b4971-bdfb-4f02-b40a-3b0b8195e1d9
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=2045375970 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.gpio_stress_all_with_rand_reset.2045375970
Directory /workspace/34.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/35.gpio_alert_test.3088676048
Short name T792
Test name
Test status
Simulation time 12961332 ps
CPU time 0.59 seconds
Started Dec 27 01:25:07 PM PST 23
Finished Dec 27 01:25:11 PM PST 23
Peak memory 194776 kb
Host smart-0c7cface-6477-4abc-8340-d3fd0f30468f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3088676048 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_alert_test.3088676048
Directory /workspace/35.gpio_alert_test/latest

Test location /workspace/coverage/default/35.gpio_dout_din_regs_random_rw.643959884
Short name T845
Test name
Test status
Simulation time 123180900 ps
CPU time 0.76 seconds
Started Dec 27 01:24:50 PM PST 23
Finished Dec 27 01:24:54 PM PST 23
Peak memory 195256 kb
Host smart-fabc3111-ad0b-444e-b31f-39d45dc23a83
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=643959884 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_dout_din_regs_random_rw.643959884
Directory /workspace/35.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/35.gpio_filter_stress.2125549880
Short name T259
Test name
Test status
Simulation time 425032027 ps
CPU time 3.9 seconds
Started Dec 27 01:24:44 PM PST 23
Finished Dec 27 01:24:49 PM PST 23
Peak memory 195980 kb
Host smart-58e53718-16b7-4dd1-9eab-edb0d49b968d
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2125549880 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_filter_stre
ss.2125549880
Directory /workspace/35.gpio_filter_stress/latest

Test location /workspace/coverage/default/35.gpio_full_random.12420594
Short name T603
Test name
Test status
Simulation time 299848592 ps
CPU time 1 seconds
Started Dec 27 01:25:03 PM PST 23
Finished Dec 27 01:25:06 PM PST 23
Peak memory 196556 kb
Host smart-8c276751-e5cb-441a-a04e-bb3e75c6c5d3
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12420594 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_full_random.12420594
Directory /workspace/35.gpio_full_random/latest

Test location /workspace/coverage/default/35.gpio_intr_rand_pgm.2619671240
Short name T713
Test name
Test status
Simulation time 236839460 ps
CPU time 1.1 seconds
Started Dec 27 01:24:47 PM PST 23
Finished Dec 27 01:24:51 PM PST 23
Peak memory 196100 kb
Host smart-3ebd0b13-3c84-46b0-919d-7b1af6b97ec6
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2619671240 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_intr_rand_pgm.2619671240
Directory /workspace/35.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/35.gpio_intr_with_filter_rand_intr_event.837430414
Short name T446
Test name
Test status
Simulation time 325224557 ps
CPU time 3.35 seconds
Started Dec 27 01:24:59 PM PST 23
Finished Dec 27 01:25:03 PM PST 23
Peak memory 198140 kb
Host smart-f9f1ec69-9663-4872-8945-b380d37f3619
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=837430414 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 35.gpio_intr_with_filter_rand_intr_event.837430414
Directory /workspace/35.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/35.gpio_rand_intr_trigger.1679903607
Short name T512
Test name
Test status
Simulation time 119475321 ps
CPU time 3.35 seconds
Started Dec 27 01:25:00 PM PST 23
Finished Dec 27 01:25:04 PM PST 23
Peak memory 197020 kb
Host smart-79405945-5648-4a10-95cf-59cfd91f9597
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1679903607 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_rand_intr_trigger
.1679903607
Directory /workspace/35.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/35.gpio_random_dout_din.3536260941
Short name T358
Test name
Test status
Simulation time 46826379 ps
CPU time 1.07 seconds
Started Dec 27 01:24:46 PM PST 23
Finished Dec 27 01:24:51 PM PST 23
Peak memory 196624 kb
Host smart-26dcfe6c-e666-4765-9eab-e78d5dc9f961
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3536260941 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_random_dout_din.3536260941
Directory /workspace/35.gpio_random_dout_din/latest

Test location /workspace/coverage/default/35.gpio_random_dout_din_no_pullup_pulldown.2578131638
Short name T843
Test name
Test status
Simulation time 21196634 ps
CPU time 0.88 seconds
Started Dec 27 01:25:03 PM PST 23
Finished Dec 27 01:25:05 PM PST 23
Peak memory 196428 kb
Host smart-b75ed3da-cc40-4ab4-84b5-69c741980aeb
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2578131638 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_random_dout_din_no_pullu
p_pulldown.2578131638
Directory /workspace/35.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/35.gpio_random_long_reg_writes_reg_reads.1455551509
Short name T830
Test name
Test status
Simulation time 425309781 ps
CPU time 2.74 seconds
Started Dec 27 01:24:47 PM PST 23
Finished Dec 27 01:24:53 PM PST 23
Peak memory 198128 kb
Host smart-7ce60d9f-c26d-4c6a-8ef1-26f84fc4c69e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1455551509 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_ra
ndom_long_reg_writes_reg_reads.1455551509
Directory /workspace/35.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/35.gpio_smoke.2030172337
Short name T785
Test name
Test status
Simulation time 26048507 ps
CPU time 0.74 seconds
Started Dec 27 01:24:47 PM PST 23
Finished Dec 27 01:24:51 PM PST 23
Peak memory 194244 kb
Host smart-6774e763-3a15-4f6d-b659-6b4ce969d005
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2030172337 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_smoke.2030172337
Directory /workspace/35.gpio_smoke/latest

Test location /workspace/coverage/default/35.gpio_smoke_no_pullup_pulldown.3878702810
Short name T453
Test name
Test status
Simulation time 29183327 ps
CPU time 0.85 seconds
Started Dec 27 01:25:07 PM PST 23
Finished Dec 27 01:25:11 PM PST 23
Peak memory 195224 kb
Host smart-634ce2a2-0f7d-4566-807b-8ce0a8222684
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3878702810 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_smoke_no_pullup_pulldown.3878702810
Directory /workspace/35.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/35.gpio_stress_all.885828464
Short name T788
Test name
Test status
Simulation time 37405057057 ps
CPU time 127.25 seconds
Started Dec 27 01:25:05 PM PST 23
Finished Dec 27 01:27:16 PM PST 23
Peak memory 198224 kb
Host smart-0d5c32e1-fb85-4baa-a949-6f9150f6d853
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=885828464 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.g
pio_stress_all.885828464
Directory /workspace/35.gpio_stress_all/latest

Test location /workspace/coverage/default/35.gpio_stress_all_with_rand_reset.411571312
Short name T401
Test name
Test status
Simulation time 60576099525 ps
CPU time 862.36 seconds
Started Dec 27 01:25:12 PM PST 23
Finished Dec 27 01:39:37 PM PST 23
Peak memory 198380 kb
Host smart-b33c2470-5f26-42d7-8ee6-06358433b570
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=411571312 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.gpio_stress_all_with_rand_reset.411571312
Directory /workspace/35.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/36.gpio_alert_test.613422170
Short name T52
Test name
Test status
Simulation time 34635421 ps
CPU time 0.56 seconds
Started Dec 27 01:23:52 PM PST 23
Finished Dec 27 01:23:54 PM PST 23
Peak memory 193912 kb
Host smart-8010bc8b-ef3b-49f7-8e1d-ebc40517cc0a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=613422170 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_alert_test.613422170
Directory /workspace/36.gpio_alert_test/latest

Test location /workspace/coverage/default/36.gpio_dout_din_regs_random_rw.3307993682
Short name T715
Test name
Test status
Simulation time 28144619 ps
CPU time 0.71 seconds
Started Dec 27 01:25:28 PM PST 23
Finished Dec 27 01:25:30 PM PST 23
Peak memory 195844 kb
Host smart-aa0cc02f-8990-4a9e-9932-703bc335155c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3307993682 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_dout_din_regs_random_rw.3307993682
Directory /workspace/36.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/36.gpio_filter_stress.2776282756
Short name T223
Test name
Test status
Simulation time 1187997794 ps
CPU time 8.05 seconds
Started Dec 27 01:23:55 PM PST 23
Finished Dec 27 01:24:04 PM PST 23
Peak memory 196820 kb
Host smart-b6e42920-d0cd-4193-a48f-2ac867561d5b
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2776282756 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_filter_stre
ss.2776282756
Directory /workspace/36.gpio_filter_stress/latest

Test location /workspace/coverage/default/36.gpio_full_random.988706867
Short name T626
Test name
Test status
Simulation time 181978595 ps
CPU time 0.67 seconds
Started Dec 27 01:24:14 PM PST 23
Finished Dec 27 01:24:15 PM PST 23
Peak memory 195352 kb
Host smart-27cdf252-00e7-4e92-beef-6d6561a1093d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=988706867 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_full_random.988706867
Directory /workspace/36.gpio_full_random/latest

Test location /workspace/coverage/default/36.gpio_intr_rand_pgm.1811325306
Short name T238
Test name
Test status
Simulation time 42781798 ps
CPU time 0.78 seconds
Started Dec 27 01:25:53 PM PST 23
Finished Dec 27 01:25:54 PM PST 23
Peak memory 196320 kb
Host smart-f3e4008b-50d0-4a47-a180-d7de7b5a3ffe
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1811325306 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_intr_rand_pgm.1811325306
Directory /workspace/36.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/36.gpio_intr_with_filter_rand_intr_event.669993347
Short name T838
Test name
Test status
Simulation time 184970075 ps
CPU time 2.95 seconds
Started Dec 27 01:23:55 PM PST 23
Finished Dec 27 01:23:59 PM PST 23
Peak memory 196532 kb
Host smart-7b2fc541-d365-4b1b-b1dd-ca3d82753b99
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=669993347 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 36.gpio_intr_with_filter_rand_intr_event.669993347
Directory /workspace/36.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/36.gpio_rand_intr_trigger.2800051680
Short name T834
Test name
Test status
Simulation time 371182885 ps
CPU time 3.02 seconds
Started Dec 27 01:24:17 PM PST 23
Finished Dec 27 01:24:21 PM PST 23
Peak memory 197180 kb
Host smart-a31e8b3f-1168-4e37-a164-31c0f316e3b1
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2800051680 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_rand_intr_trigger
.2800051680
Directory /workspace/36.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/36.gpio_random_dout_din.1826676723
Short name T844
Test name
Test status
Simulation time 18770996 ps
CPU time 0.76 seconds
Started Dec 27 01:25:06 PM PST 23
Finished Dec 27 01:25:11 PM PST 23
Peak memory 195980 kb
Host smart-44115c66-f18d-4b5e-ac1f-56a5cae2c1ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1826676723 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_random_dout_din.1826676723
Directory /workspace/36.gpio_random_dout_din/latest

Test location /workspace/coverage/default/36.gpio_random_dout_din_no_pullup_pulldown.2565539337
Short name T797
Test name
Test status
Simulation time 241332970 ps
CPU time 1.03 seconds
Started Dec 27 01:24:49 PM PST 23
Finished Dec 27 01:24:52 PM PST 23
Peak memory 196096 kb
Host smart-c3d56ed1-d742-4fa7-8b14-83029ea8d515
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2565539337 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_random_dout_din_no_pullu
p_pulldown.2565539337
Directory /workspace/36.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/36.gpio_random_long_reg_writes_reg_reads.3060857603
Short name T558
Test name
Test status
Simulation time 217830609 ps
CPU time 2.64 seconds
Started Dec 27 01:23:52 PM PST 23
Finished Dec 27 01:23:57 PM PST 23
Peak memory 198120 kb
Host smart-5d8bc50c-e9d1-419f-8ada-140662a6bccd
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3060857603 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_ra
ndom_long_reg_writes_reg_reads.3060857603
Directory /workspace/36.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/36.gpio_smoke.3583838484
Short name T366
Test name
Test status
Simulation time 266247547 ps
CPU time 0.9 seconds
Started Dec 27 01:25:08 PM PST 23
Finished Dec 27 01:25:12 PM PST 23
Peak memory 197344 kb
Host smart-c658fdc2-0e1d-4100-a0f8-c768af2e8682
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3583838484 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_smoke.3583838484
Directory /workspace/36.gpio_smoke/latest

Test location /workspace/coverage/default/36.gpio_smoke_no_pullup_pulldown.595552665
Short name T470
Test name
Test status
Simulation time 409655735 ps
CPU time 1.48 seconds
Started Dec 27 01:24:55 PM PST 23
Finished Dec 27 01:24:58 PM PST 23
Peak memory 195664 kb
Host smart-70f70b1f-5ce5-4f99-bc0b-02907f1b1d6b
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=595552665 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_smoke_no_pullup_pulldown.595552665
Directory /workspace/36.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/36.gpio_stress_all.3661810033
Short name T500
Test name
Test status
Simulation time 3189412800 ps
CPU time 34.23 seconds
Started Dec 27 01:23:53 PM PST 23
Finished Dec 27 01:24:29 PM PST 23
Peak memory 198256 kb
Host smart-60763e46-ceb5-44b7-8f1f-6c01898cf560
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3661810033 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.
gpio_stress_all.3661810033
Directory /workspace/36.gpio_stress_all/latest

Test location /workspace/coverage/default/36.gpio_stress_all_with_rand_reset.943231997
Short name T82
Test name
Test status
Simulation time 708117803025 ps
CPU time 815.8 seconds
Started Dec 27 01:25:29 PM PST 23
Finished Dec 27 01:39:05 PM PST 23
Peak memory 198384 kb
Host smart-277dbb64-0acf-4a42-b74d-0bdd863f098a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=943231997 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.gpio_stress_all_with_rand_reset.943231997
Directory /workspace/36.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/37.gpio_alert_test.1198137972
Short name T651
Test name
Test status
Simulation time 20967414 ps
CPU time 0.57 seconds
Started Dec 27 01:24:31 PM PST 23
Finished Dec 27 01:24:32 PM PST 23
Peak memory 194056 kb
Host smart-274e27de-275b-4f47-8c05-c3d68fc7dbd8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1198137972 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_alert_test.1198137972
Directory /workspace/37.gpio_alert_test/latest

Test location /workspace/coverage/default/37.gpio_dout_din_regs_random_rw.2712549448
Short name T423
Test name
Test status
Simulation time 29830563 ps
CPU time 0.76 seconds
Started Dec 27 01:23:53 PM PST 23
Finished Dec 27 01:23:56 PM PST 23
Peak memory 196084 kb
Host smart-633d3f41-be57-42c9-9b5e-3ea2b35880d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2712549448 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_dout_din_regs_random_rw.2712549448
Directory /workspace/37.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/37.gpio_filter_stress.771376171
Short name T299
Test name
Test status
Simulation time 7724864573 ps
CPU time 20.03 seconds
Started Dec 27 01:23:54 PM PST 23
Finished Dec 27 01:24:15 PM PST 23
Peak memory 196932 kb
Host smart-e10a648d-2a1c-43da-b8ab-de7498f5210d
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=771376171 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_filter_stres
s.771376171
Directory /workspace/37.gpio_filter_stress/latest

Test location /workspace/coverage/default/37.gpio_full_random.659217868
Short name T753
Test name
Test status
Simulation time 55389321 ps
CPU time 0.84 seconds
Started Dec 27 01:23:56 PM PST 23
Finished Dec 27 01:23:58 PM PST 23
Peak memory 196656 kb
Host smart-dd746b53-77ce-46a4-b5c6-a732b8bc7bd5
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=659217868 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_full_random.659217868
Directory /workspace/37.gpio_full_random/latest

Test location /workspace/coverage/default/37.gpio_intr_rand_pgm.1966534479
Short name T831
Test name
Test status
Simulation time 174917542 ps
CPU time 1.25 seconds
Started Dec 27 01:24:15 PM PST 23
Finished Dec 27 01:24:17 PM PST 23
Peak memory 197328 kb
Host smart-241e718c-7a7b-4ae1-b2df-a758abb9d8ac
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1966534479 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_intr_rand_pgm.1966534479
Directory /workspace/37.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/37.gpio_intr_with_filter_rand_intr_event.822909713
Short name T362
Test name
Test status
Simulation time 35811872 ps
CPU time 0.87 seconds
Started Dec 27 01:24:32 PM PST 23
Finished Dec 27 01:24:34 PM PST 23
Peak memory 196008 kb
Host smart-63132dd2-42d3-4233-b58e-191585424e69
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=822909713 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 37.gpio_intr_with_filter_rand_intr_event.822909713
Directory /workspace/37.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/37.gpio_rand_intr_trigger.3638492671
Short name T450
Test name
Test status
Simulation time 148290423 ps
CPU time 1.01 seconds
Started Dec 27 01:24:22 PM PST 23
Finished Dec 27 01:24:23 PM PST 23
Peak memory 195392 kb
Host smart-31f9b18f-0c6e-4b97-a020-56a1cbfc8c7a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3638492671 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_rand_intr_trigger
.3638492671
Directory /workspace/37.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/37.gpio_random_dout_din.3302571538
Short name T740
Test name
Test status
Simulation time 21318935 ps
CPU time 0.92 seconds
Started Dec 27 01:23:49 PM PST 23
Finished Dec 27 01:23:51 PM PST 23
Peak memory 196032 kb
Host smart-12c58f91-65f6-45cc-9d9a-890c6f8afe91
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3302571538 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_random_dout_din.3302571538
Directory /workspace/37.gpio_random_dout_din/latest

Test location /workspace/coverage/default/37.gpio_random_dout_din_no_pullup_pulldown.3097489538
Short name T274
Test name
Test status
Simulation time 357803891 ps
CPU time 0.9 seconds
Started Dec 27 01:24:19 PM PST 23
Finished Dec 27 01:24:21 PM PST 23
Peak memory 196724 kb
Host smart-7ba4ec42-f327-413f-a63a-00ed14da2060
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3097489538 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_random_dout_din_no_pullu
p_pulldown.3097489538
Directory /workspace/37.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/37.gpio_random_long_reg_writes_reg_reads.1334721133
Short name T413
Test name
Test status
Simulation time 774923848 ps
CPU time 3.04 seconds
Started Dec 27 01:24:17 PM PST 23
Finished Dec 27 01:24:21 PM PST 23
Peak memory 198140 kb
Host smart-da388383-5072-4a98-ad29-539ba3917def
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1334721133 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_ra
ndom_long_reg_writes_reg_reads.1334721133
Directory /workspace/37.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/37.gpio_smoke.2424487042
Short name T217
Test name
Test status
Simulation time 72378300 ps
CPU time 0.97 seconds
Started Dec 27 01:24:18 PM PST 23
Finished Dec 27 01:24:20 PM PST 23
Peak memory 195808 kb
Host smart-0375c147-1e38-4359-a07d-75d0455da185
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2424487042 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_smoke.2424487042
Directory /workspace/37.gpio_smoke/latest

Test location /workspace/coverage/default/37.gpio_smoke_no_pullup_pulldown.1393531294
Short name T628
Test name
Test status
Simulation time 187729233 ps
CPU time 0.95 seconds
Started Dec 27 01:24:12 PM PST 23
Finished Dec 27 01:24:14 PM PST 23
Peak memory 195872 kb
Host smart-aac5e9e1-3638-416f-972d-0493a3082fba
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1393531294 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_smoke_no_pullup_pulldown.1393531294
Directory /workspace/37.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/37.gpio_stress_all.2449709434
Short name T767
Test name
Test status
Simulation time 6325337834 ps
CPU time 169.35 seconds
Started Dec 27 01:23:55 PM PST 23
Finished Dec 27 01:26:46 PM PST 23
Peak memory 198268 kb
Host smart-641d3822-1c0f-48f6-aa3b-a46fe65d7aab
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2449709434 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.
gpio_stress_all.2449709434
Directory /workspace/37.gpio_stress_all/latest

Test location /workspace/coverage/default/37.gpio_stress_all_with_rand_reset.3708389623
Short name T396
Test name
Test status
Simulation time 101751912927 ps
CPU time 564.04 seconds
Started Dec 27 01:24:55 PM PST 23
Finished Dec 27 01:34:19 PM PST 23
Peak memory 198360 kb
Host smart-1406ab62-edf6-472c-bfbd-6e8ece1d76bb
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=3708389623 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.gpio_stress_all_with_rand_reset.3708389623
Directory /workspace/37.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/38.gpio_alert_test.418457894
Short name T717
Test name
Test status
Simulation time 33079362 ps
CPU time 0.57 seconds
Started Dec 27 01:24:15 PM PST 23
Finished Dec 27 01:24:16 PM PST 23
Peak memory 194036 kb
Host smart-1084db72-29bd-4672-98a5-4fc85fb4b981
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=418457894 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_alert_test.418457894
Directory /workspace/38.gpio_alert_test/latest

Test location /workspace/coverage/default/38.gpio_dout_din_regs_random_rw.1952519955
Short name T664
Test name
Test status
Simulation time 89097407 ps
CPU time 0.71 seconds
Started Dec 27 01:25:06 PM PST 23
Finished Dec 27 01:25:11 PM PST 23
Peak memory 195968 kb
Host smart-ccd99a1f-9da7-4fe2-81a3-3d5811b9b52b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1952519955 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_dout_din_regs_random_rw.1952519955
Directory /workspace/38.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/38.gpio_filter_stress.1859312763
Short name T428
Test name
Test status
Simulation time 473746022 ps
CPU time 15.09 seconds
Started Dec 27 01:24:12 PM PST 23
Finished Dec 27 01:24:28 PM PST 23
Peak memory 198020 kb
Host smart-cbcaafbe-bdaa-48c9-a3af-8b8f7d4428e2
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1859312763 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_filter_stre
ss.1859312763
Directory /workspace/38.gpio_filter_stress/latest

Test location /workspace/coverage/default/38.gpio_full_random.2987381813
Short name T827
Test name
Test status
Simulation time 273462592 ps
CPU time 0.98 seconds
Started Dec 27 01:24:16 PM PST 23
Finished Dec 27 01:24:18 PM PST 23
Peak memory 198008 kb
Host smart-6c4a704e-0afb-4935-b38a-411b8ab9f84b
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2987381813 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_full_random.2987381813
Directory /workspace/38.gpio_full_random/latest

Test location /workspace/coverage/default/38.gpio_intr_rand_pgm.644542219
Short name T248
Test name
Test status
Simulation time 91318177 ps
CPU time 1.35 seconds
Started Dec 27 01:24:45 PM PST 23
Finished Dec 27 01:24:50 PM PST 23
Peak memory 196772 kb
Host smart-5811d073-c5c8-40ff-881d-f3111ad6f659
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=644542219 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_intr_rand_pgm.644542219
Directory /workspace/38.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/38.gpio_intr_with_filter_rand_intr_event.1893393291
Short name T245
Test name
Test status
Simulation time 76170768 ps
CPU time 1.7 seconds
Started Dec 27 01:23:49 PM PST 23
Finished Dec 27 01:23:52 PM PST 23
Peak memory 196376 kb
Host smart-a3cb72ff-4d88-49c3-bc3f-cae413078bab
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1893393291 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 38.gpio_intr_with_filter_rand_intr_event.1893393291
Directory /workspace/38.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/38.gpio_rand_intr_trigger.960875412
Short name T676
Test name
Test status
Simulation time 321295994 ps
CPU time 1.91 seconds
Started Dec 27 01:24:13 PM PST 23
Finished Dec 27 01:24:16 PM PST 23
Peak memory 196208 kb
Host smart-414e3dd2-e22e-4082-943e-0ca9a33d6b93
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=960875412 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_rand_intr_trigger.
960875412
Directory /workspace/38.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/38.gpio_random_dout_din.2235725280
Short name T655
Test name
Test status
Simulation time 134109735 ps
CPU time 0.91 seconds
Started Dec 27 01:24:16 PM PST 23
Finished Dec 27 01:24:18 PM PST 23
Peak memory 196640 kb
Host smart-4b5bed91-0b32-498a-8c53-036c3e19ce3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2235725280 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_random_dout_din.2235725280
Directory /workspace/38.gpio_random_dout_din/latest

Test location /workspace/coverage/default/38.gpio_random_dout_din_no_pullup_pulldown.1115152291
Short name T320
Test name
Test status
Simulation time 326408557 ps
CPU time 1.03 seconds
Started Dec 27 01:24:50 PM PST 23
Finished Dec 27 01:24:54 PM PST 23
Peak memory 195804 kb
Host smart-cac0f4a1-2f31-4e2d-bed0-fb53fac85588
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1115152291 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_random_dout_din_no_pullu
p_pulldown.1115152291
Directory /workspace/38.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/38.gpio_random_long_reg_writes_reg_reads.3908125111
Short name T542
Test name
Test status
Simulation time 896311488 ps
CPU time 3.95 seconds
Started Dec 27 01:24:33 PM PST 23
Finished Dec 27 01:24:38 PM PST 23
Peak memory 198100 kb
Host smart-a731dbd2-ddbf-4453-b5d8-1aecbbecc95f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3908125111 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_ra
ndom_long_reg_writes_reg_reads.3908125111
Directory /workspace/38.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/38.gpio_smoke.2339358981
Short name T723
Test name
Test status
Simulation time 363119431 ps
CPU time 1.45 seconds
Started Dec 27 01:24:50 PM PST 23
Finished Dec 27 01:24:55 PM PST 23
Peak memory 196840 kb
Host smart-f8f0a6fd-1a74-43d5-baf0-49ee4a8d6c28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2339358981 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_smoke.2339358981
Directory /workspace/38.gpio_smoke/latest

Test location /workspace/coverage/default/38.gpio_smoke_no_pullup_pulldown.2378326414
Short name T494
Test name
Test status
Simulation time 99908735 ps
CPU time 0.92 seconds
Started Dec 27 01:24:20 PM PST 23
Finished Dec 27 01:24:22 PM PST 23
Peak memory 195588 kb
Host smart-35c637a0-88ca-46d8-9850-6855c140611a
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2378326414 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_smoke_no_pullup_pulldown.2378326414
Directory /workspace/38.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/38.gpio_stress_all.947916061
Short name T820
Test name
Test status
Simulation time 7759120787 ps
CPU time 90.78 seconds
Started Dec 27 01:23:48 PM PST 23
Finished Dec 27 01:25:20 PM PST 23
Peak memory 198268 kb
Host smart-eedacf0d-1bc3-4221-82db-328615d06695
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=947916061 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.g
pio_stress_all.947916061
Directory /workspace/38.gpio_stress_all/latest

Test location /workspace/coverage/default/38.gpio_stress_all_with_rand_reset.1669117157
Short name T882
Test name
Test status
Simulation time 118552902421 ps
CPU time 655.25 seconds
Started Dec 27 01:23:51 PM PST 23
Finished Dec 27 01:34:48 PM PST 23
Peak memory 198264 kb
Host smart-877c9d2f-8faa-44eb-84bb-daac9c4caf49
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=1669117157 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.gpio_stress_all_with_rand_reset.1669117157
Directory /workspace/38.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/39.gpio_alert_test.3795968121
Short name T694
Test name
Test status
Simulation time 33460772 ps
CPU time 0.56 seconds
Started Dec 27 01:24:18 PM PST 23
Finished Dec 27 01:24:23 PM PST 23
Peak memory 194072 kb
Host smart-2af965ec-1ce9-4b58-971c-18dfd5c47715
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3795968121 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_alert_test.3795968121
Directory /workspace/39.gpio_alert_test/latest

Test location /workspace/coverage/default/39.gpio_dout_din_regs_random_rw.2894957216
Short name T679
Test name
Test status
Simulation time 37586253 ps
CPU time 0.74 seconds
Started Dec 27 01:23:48 PM PST 23
Finished Dec 27 01:23:49 PM PST 23
Peak memory 195192 kb
Host smart-4ad1e64a-a9a6-4544-a0ee-332f42943288
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2894957216 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_dout_din_regs_random_rw.2894957216
Directory /workspace/39.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/39.gpio_filter_stress.1512121629
Short name T846
Test name
Test status
Simulation time 120293580 ps
CPU time 6.9 seconds
Started Dec 27 01:23:55 PM PST 23
Finished Dec 27 01:24:03 PM PST 23
Peak memory 196996 kb
Host smart-d015822f-4067-4b9a-9971-d6610a690f32
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1512121629 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_filter_stre
ss.1512121629
Directory /workspace/39.gpio_filter_stress/latest

Test location /workspace/coverage/default/39.gpio_full_random.2970488908
Short name T421
Test name
Test status
Simulation time 266402494 ps
CPU time 1.06 seconds
Started Dec 27 01:24:12 PM PST 23
Finished Dec 27 01:24:14 PM PST 23
Peak memory 198000 kb
Host smart-fe957647-b502-45b2-89e7-c5d2cba58a28
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2970488908 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_full_random.2970488908
Directory /workspace/39.gpio_full_random/latest

Test location /workspace/coverage/default/39.gpio_intr_rand_pgm.1977884515
Short name T590
Test name
Test status
Simulation time 62315673 ps
CPU time 0.81 seconds
Started Dec 27 01:23:54 PM PST 23
Finished Dec 27 01:23:56 PM PST 23
Peak memory 196220 kb
Host smart-b5b5cdb6-97f4-4a64-9fb0-b4daae0e063c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1977884515 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_intr_rand_pgm.1977884515
Directory /workspace/39.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/39.gpio_intr_with_filter_rand_intr_event.990329555
Short name T675
Test name
Test status
Simulation time 99926465 ps
CPU time 2.05 seconds
Started Dec 27 01:24:18 PM PST 23
Finished Dec 27 01:24:21 PM PST 23
Peak memory 198168 kb
Host smart-a58d7103-eb7e-4ecf-990f-bec2868d9e4b
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=990329555 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 39.gpio_intr_with_filter_rand_intr_event.990329555
Directory /workspace/39.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/39.gpio_rand_intr_trigger.617187675
Short name T546
Test name
Test status
Simulation time 76284976 ps
CPU time 2.51 seconds
Started Dec 27 01:23:47 PM PST 23
Finished Dec 27 01:23:50 PM PST 23
Peak memory 197320 kb
Host smart-fd84e13d-b520-4345-a8cc-6feb6d4eba2a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=617187675 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_rand_intr_trigger.
617187675
Directory /workspace/39.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/39.gpio_random_dout_din.227755619
Short name T780
Test name
Test status
Simulation time 33713183 ps
CPU time 1.06 seconds
Started Dec 27 01:24:26 PM PST 23
Finished Dec 27 01:24:28 PM PST 23
Peak memory 196696 kb
Host smart-12fce6fa-7ac8-45ec-afb9-72b42036f2b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=227755619 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_random_dout_din.227755619
Directory /workspace/39.gpio_random_dout_din/latest

Test location /workspace/coverage/default/39.gpio_random_dout_din_no_pullup_pulldown.2449836448
Short name T852
Test name
Test status
Simulation time 78370542 ps
CPU time 1.28 seconds
Started Dec 27 01:24:27 PM PST 23
Finished Dec 27 01:24:29 PM PST 23
Peak memory 197124 kb
Host smart-4e933ce6-870a-411f-b9fa-6a2f0526884f
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2449836448 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_random_dout_din_no_pullu
p_pulldown.2449836448
Directory /workspace/39.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/39.gpio_random_long_reg_writes_reg_reads.3457418107
Short name T622
Test name
Test status
Simulation time 863844538 ps
CPU time 3.77 seconds
Started Dec 27 01:24:16 PM PST 23
Finished Dec 27 01:24:20 PM PST 23
Peak memory 198088 kb
Host smart-005f57be-8dbe-473d-a6ef-0514d1a59f21
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3457418107 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_ra
ndom_long_reg_writes_reg_reads.3457418107
Directory /workspace/39.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/39.gpio_smoke.2943875858
Short name T380
Test name
Test status
Simulation time 1050030495 ps
CPU time 1.4 seconds
Started Dec 27 01:24:17 PM PST 23
Finished Dec 27 01:24:19 PM PST 23
Peak memory 196936 kb
Host smart-b7a584a5-30a0-46cf-a518-25b4b972ad5a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2943875858 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_smoke.2943875858
Directory /workspace/39.gpio_smoke/latest

Test location /workspace/coverage/default/39.gpio_smoke_no_pullup_pulldown.3813782005
Short name T276
Test name
Test status
Simulation time 55545677 ps
CPU time 1.14 seconds
Started Dec 27 01:23:49 PM PST 23
Finished Dec 27 01:23:51 PM PST 23
Peak memory 195944 kb
Host smart-227df8d3-be3d-471a-9f76-4164d520247a
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3813782005 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_smoke_no_pullup_pulldown.3813782005
Directory /workspace/39.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/39.gpio_stress_all.4203228227
Short name T432
Test name
Test status
Simulation time 150901666823 ps
CPU time 214.79 seconds
Started Dec 27 01:23:53 PM PST 23
Finished Dec 27 01:27:30 PM PST 23
Peak memory 198248 kb
Host smart-0b101614-56cd-490e-b06f-93ef67432a0d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4203228227 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.
gpio_stress_all.4203228227
Directory /workspace/39.gpio_stress_all/latest

Test location /workspace/coverage/default/39.gpio_stress_all_with_rand_reset.3520938174
Short name T578
Test name
Test status
Simulation time 26946414448 ps
CPU time 406.2 seconds
Started Dec 27 01:24:12 PM PST 23
Finished Dec 27 01:30:59 PM PST 23
Peak memory 198300 kb
Host smart-f35b9da8-ec7d-4314-bc26-e7222fec0ada
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=3520938174 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.gpio_stress_all_with_rand_reset.3520938174
Directory /workspace/39.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/4.gpio_alert_test.3601319627
Short name T853
Test name
Test status
Simulation time 42057630 ps
CPU time 0.57 seconds
Started Dec 27 01:22:29 PM PST 23
Finished Dec 27 01:22:31 PM PST 23
Peak memory 194708 kb
Host smart-cab7a1c0-95f4-428e-95dd-d323c2cd9490
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3601319627 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_alert_test.3601319627
Directory /workspace/4.gpio_alert_test/latest

Test location /workspace/coverage/default/4.gpio_dout_din_regs_random_rw.3911777191
Short name T71
Test name
Test status
Simulation time 100512229 ps
CPU time 0.66 seconds
Started Dec 27 01:21:12 PM PST 23
Finished Dec 27 01:21:13 PM PST 23
Peak memory 194204 kb
Host smart-03152393-b5d0-48f4-aca5-03db6dc73ad1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3911777191 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_dout_din_regs_random_rw.3911777191
Directory /workspace/4.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/4.gpio_filter_stress.3826108327
Short name T750
Test name
Test status
Simulation time 751912904 ps
CPU time 26 seconds
Started Dec 27 01:22:28 PM PST 23
Finished Dec 27 01:22:54 PM PST 23
Peak memory 196604 kb
Host smart-721752a2-f65c-4118-b77d-1360ed20246d
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3826108327 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_filter_stres
s.3826108327
Directory /workspace/4.gpio_filter_stress/latest

Test location /workspace/coverage/default/4.gpio_full_random.3337730208
Short name T757
Test name
Test status
Simulation time 382627500 ps
CPU time 1.1 seconds
Started Dec 27 01:22:07 PM PST 23
Finished Dec 27 01:22:09 PM PST 23
Peak memory 196692 kb
Host smart-63cd1486-2156-4ddf-8d3d-821f680ea7b3
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3337730208 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_full_random.3337730208
Directory /workspace/4.gpio_full_random/latest

Test location /workspace/coverage/default/4.gpio_intr_rand_pgm.4012778702
Short name T809
Test name
Test status
Simulation time 85200804 ps
CPU time 0.82 seconds
Started Dec 27 01:21:24 PM PST 23
Finished Dec 27 01:21:26 PM PST 23
Peak memory 195596 kb
Host smart-d3017443-6ac9-4c3d-a532-7b5d1dee082c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4012778702 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_intr_rand_pgm.4012778702
Directory /workspace/4.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/4.gpio_intr_with_filter_rand_intr_event.1293270781
Short name T371
Test name
Test status
Simulation time 105790428 ps
CPU time 1.85 seconds
Started Dec 27 01:21:11 PM PST 23
Finished Dec 27 01:21:14 PM PST 23
Peak memory 198120 kb
Host smart-8b022337-5b62-41aa-81b0-140698963a32
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1293270781 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 4.gpio_intr_with_filter_rand_intr_event.1293270781
Directory /workspace/4.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/4.gpio_rand_intr_trigger.918592834
Short name T531
Test name
Test status
Simulation time 174870077 ps
CPU time 3.36 seconds
Started Dec 27 01:21:14 PM PST 23
Finished Dec 27 01:21:18 PM PST 23
Peak memory 196028 kb
Host smart-c72f0d88-dbb0-412f-8d9a-01847a0fb3d5
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=918592834 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_rand_intr_trigger.918592834
Directory /workspace/4.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/4.gpio_random_dout_din.1742543922
Short name T518
Test name
Test status
Simulation time 36446855 ps
CPU time 1.32 seconds
Started Dec 27 01:21:14 PM PST 23
Finished Dec 27 01:21:16 PM PST 23
Peak memory 198204 kb
Host smart-fcc82a71-f00c-40f1-a7f2-6cb3273d9657
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1742543922 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_random_dout_din.1742543922
Directory /workspace/4.gpio_random_dout_din/latest

Test location /workspace/coverage/default/4.gpio_random_dout_din_no_pullup_pulldown.2795378965
Short name T796
Test name
Test status
Simulation time 105239549 ps
CPU time 0.88 seconds
Started Dec 27 01:21:18 PM PST 23
Finished Dec 27 01:21:19 PM PST 23
Peak memory 196184 kb
Host smart-dac87f73-4114-4b1c-b923-ef47eeec322f
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2795378965 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_random_dout_din_no_pullup
_pulldown.2795378965
Directory /workspace/4.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/4.gpio_random_long_reg_writes_reg_reads.1667092086
Short name T593
Test name
Test status
Simulation time 107405502 ps
CPU time 2.51 seconds
Started Dec 27 01:22:31 PM PST 23
Finished Dec 27 01:22:39 PM PST 23
Peak memory 198120 kb
Host smart-fcc22850-0344-42a5-879b-0443fb845b23
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1667092086 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_ran
dom_long_reg_writes_reg_reads.1667092086
Directory /workspace/4.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/4.gpio_sec_cm.3503508210
Short name T28
Test name
Test status
Simulation time 37508152 ps
CPU time 0.79 seconds
Started Dec 27 01:22:29 PM PST 23
Finished Dec 27 01:22:31 PM PST 23
Peak memory 213464 kb
Host smart-13fa1b1a-ffec-4d0a-aae4-da8cf9713244
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3503508210 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_sec_cm.3503508210
Directory /workspace/4.gpio_sec_cm/latest

Test location /workspace/coverage/default/4.gpio_smoke.1375692576
Short name T493
Test name
Test status
Simulation time 79878281 ps
CPU time 1.25 seconds
Started Dec 27 01:21:13 PM PST 23
Finished Dec 27 01:21:15 PM PST 23
Peak memory 195920 kb
Host smart-ded973a6-8623-4b59-b2dc-1570c52dfc4e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1375692576 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_smoke.1375692576
Directory /workspace/4.gpio_smoke/latest

Test location /workspace/coverage/default/4.gpio_smoke_no_pullup_pulldown.2282744186
Short name T555
Test name
Test status
Simulation time 41796660 ps
CPU time 1.22 seconds
Started Dec 27 01:21:51 PM PST 23
Finished Dec 27 01:21:53 PM PST 23
Peak memory 195976 kb
Host smart-24dca95a-6f0c-4db2-b102-a3ccfc55c99a
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2282744186 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_smoke_no_pullup_pulldown.2282744186
Directory /workspace/4.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/4.gpio_stress_all.1449116139
Short name T703
Test name
Test status
Simulation time 25283184545 ps
CPU time 44.13 seconds
Started Dec 27 01:22:25 PM PST 23
Finished Dec 27 01:23:12 PM PST 23
Peak memory 198244 kb
Host smart-f268ac04-4c4a-4a77-94ef-979997026e24
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1449116139 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.g
pio_stress_all.1449116139
Directory /workspace/4.gpio_stress_all/latest

Test location /workspace/coverage/default/4.gpio_stress_all_with_rand_reset.2022722395
Short name T394
Test name
Test status
Simulation time 402990720321 ps
CPU time 1052.58 seconds
Started Dec 27 01:22:30 PM PST 23
Finished Dec 27 01:40:07 PM PST 23
Peak memory 198412 kb
Host smart-034341d5-b5a3-4399-bcde-027660a73be9
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=2022722395 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.gpio_stress_all_with_rand_reset.2022722395
Directory /workspace/4.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/40.gpio_alert_test.917587125
Short name T439
Test name
Test status
Simulation time 12003463 ps
CPU time 0.56 seconds
Started Dec 27 01:24:44 PM PST 23
Finished Dec 27 01:24:46 PM PST 23
Peak memory 194064 kb
Host smart-df862c3e-eb8f-484f-baf7-08e6cef2d9fd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=917587125 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_alert_test.917587125
Directory /workspace/40.gpio_alert_test/latest

Test location /workspace/coverage/default/40.gpio_dout_din_regs_random_rw.3693303583
Short name T661
Test name
Test status
Simulation time 35990684 ps
CPU time 0.83 seconds
Started Dec 27 01:24:33 PM PST 23
Finished Dec 27 01:24:35 PM PST 23
Peak memory 195464 kb
Host smart-0137f5ea-776a-4e81-8ecc-b9ae922ff1b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3693303583 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_dout_din_regs_random_rw.3693303583
Directory /workspace/40.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/40.gpio_filter_stress.3957973937
Short name T631
Test name
Test status
Simulation time 931739102 ps
CPU time 13.01 seconds
Started Dec 27 01:24:28 PM PST 23
Finished Dec 27 01:24:42 PM PST 23
Peak memory 196708 kb
Host smart-49a9610e-b534-4f8f-aa08-768b9cbf5231
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3957973937 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_filter_stre
ss.3957973937
Directory /workspace/40.gpio_filter_stress/latest

Test location /workspace/coverage/default/40.gpio_full_random.2791632106
Short name T525
Test name
Test status
Simulation time 45342663 ps
CPU time 0.86 seconds
Started Dec 27 01:24:53 PM PST 23
Finished Dec 27 01:24:55 PM PST 23
Peak memory 197064 kb
Host smart-b2b669a2-3ecc-4677-9b5c-dce058c06498
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2791632106 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_full_random.2791632106
Directory /workspace/40.gpio_full_random/latest

Test location /workspace/coverage/default/40.gpio_intr_rand_pgm.1066515948
Short name T841
Test name
Test status
Simulation time 1495568429 ps
CPU time 1.4 seconds
Started Dec 27 01:24:31 PM PST 23
Finished Dec 27 01:24:33 PM PST 23
Peak memory 196600 kb
Host smart-ec6cedb6-6fd6-4d38-b04d-452cac53d2f1
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1066515948 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_intr_rand_pgm.1066515948
Directory /workspace/40.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/40.gpio_intr_with_filter_rand_intr_event.3438851452
Short name T571
Test name
Test status
Simulation time 71197417 ps
CPU time 2.9 seconds
Started Dec 27 01:24:20 PM PST 23
Finished Dec 27 01:24:24 PM PST 23
Peak memory 198044 kb
Host smart-78becdb8-3042-40a8-b013-682e3621978e
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3438851452 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 40.gpio_intr_with_filter_rand_intr_event.3438851452
Directory /workspace/40.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/40.gpio_rand_intr_trigger.1653833036
Short name T240
Test name
Test status
Simulation time 38852253 ps
CPU time 1.27 seconds
Started Dec 27 01:24:19 PM PST 23
Finished Dec 27 01:24:22 PM PST 23
Peak memory 197040 kb
Host smart-6b94dfa3-1402-4810-b1a1-3359c342d1be
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1653833036 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_rand_intr_trigger
.1653833036
Directory /workspace/40.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/40.gpio_random_dout_din.1641028136
Short name T377
Test name
Test status
Simulation time 50132383 ps
CPU time 1.01 seconds
Started Dec 27 01:24:19 PM PST 23
Finished Dec 27 01:24:21 PM PST 23
Peak memory 196868 kb
Host smart-99b9684a-5868-42ba-ba4a-789df09c33a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1641028136 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_random_dout_din.1641028136
Directory /workspace/40.gpio_random_dout_din/latest

Test location /workspace/coverage/default/40.gpio_random_dout_din_no_pullup_pulldown.1732669661
Short name T485
Test name
Test status
Simulation time 323178163 ps
CPU time 0.95 seconds
Started Dec 27 01:24:28 PM PST 23
Finished Dec 27 01:24:30 PM PST 23
Peak memory 196104 kb
Host smart-21d8e2d7-cf8c-4861-9841-07b13ebfda3a
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1732669661 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_random_dout_din_no_pullu
p_pulldown.1732669661
Directory /workspace/40.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/40.gpio_random_long_reg_writes_reg_reads.1061130699
Short name T391
Test name
Test status
Simulation time 303959354 ps
CPU time 5.03 seconds
Started Dec 27 01:23:49 PM PST 23
Finished Dec 27 01:23:55 PM PST 23
Peak memory 198028 kb
Host smart-041e6799-4cc8-4cf8-8968-880b9616fdb1
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1061130699 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_ra
ndom_long_reg_writes_reg_reads.1061130699
Directory /workspace/40.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/40.gpio_smoke.3028424063
Short name T547
Test name
Test status
Simulation time 43441712 ps
CPU time 1.12 seconds
Started Dec 27 01:23:55 PM PST 23
Finished Dec 27 01:23:57 PM PST 23
Peak memory 196508 kb
Host smart-7134d41b-0f46-4abd-882b-feb246803aa7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3028424063 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_smoke.3028424063
Directory /workspace/40.gpio_smoke/latest

Test location /workspace/coverage/default/40.gpio_smoke_no_pullup_pulldown.2838717719
Short name T847
Test name
Test status
Simulation time 244139204 ps
CPU time 0.95 seconds
Started Dec 27 01:23:56 PM PST 23
Finished Dec 27 01:23:58 PM PST 23
Peak memory 196340 kb
Host smart-c2d3faaa-ecbe-48ae-a9d2-7a41edd0235e
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2838717719 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_smoke_no_pullup_pulldown.2838717719
Directory /workspace/40.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/40.gpio_stress_all.3520327893
Short name T325
Test name
Test status
Simulation time 8594194141 ps
CPU time 55.64 seconds
Started Dec 27 01:24:29 PM PST 23
Finished Dec 27 01:25:25 PM PST 23
Peak memory 198204 kb
Host smart-6e669702-6885-4399-b334-6a6f4716d646
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3520327893 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.
gpio_stress_all.3520327893
Directory /workspace/40.gpio_stress_all/latest

Test location /workspace/coverage/default/40.gpio_stress_all_with_rand_reset.1024860971
Short name T583
Test name
Test status
Simulation time 229911233556 ps
CPU time 2891.51 seconds
Started Dec 27 01:24:50 PM PST 23
Finished Dec 27 02:13:05 PM PST 23
Peak memory 198336 kb
Host smart-de48c9f5-86ae-4ad7-b362-bc7c8552fa7c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=1024860971 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.gpio_stress_all_with_rand_reset.1024860971
Directory /workspace/40.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/41.gpio_alert_test.874332692
Short name T803
Test name
Test status
Simulation time 41710550 ps
CPU time 0.58 seconds
Started Dec 27 01:25:09 PM PST 23
Finished Dec 27 01:25:12 PM PST 23
Peak memory 194124 kb
Host smart-90544198-20ab-42e1-a598-1b649ecb7b5f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=874332692 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_alert_test.874332692
Directory /workspace/41.gpio_alert_test/latest

Test location /workspace/coverage/default/41.gpio_dout_din_regs_random_rw.1885740872
Short name T363
Test name
Test status
Simulation time 67574603 ps
CPU time 0.71 seconds
Started Dec 27 01:25:04 PM PST 23
Finished Dec 27 01:25:06 PM PST 23
Peak memory 194024 kb
Host smart-0799abcc-7a08-4b56-9185-92b9c016b7d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1885740872 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_dout_din_regs_random_rw.1885740872
Directory /workspace/41.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/41.gpio_filter_stress.3793796196
Short name T611
Test name
Test status
Simulation time 1409631889 ps
CPU time 16.1 seconds
Started Dec 27 01:24:51 PM PST 23
Finished Dec 27 01:25:10 PM PST 23
Peak memory 195668 kb
Host smart-b2c84988-8d91-4fa7-ac17-0361f552cb7f
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3793796196 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_filter_stre
ss.3793796196
Directory /workspace/41.gpio_filter_stress/latest

Test location /workspace/coverage/default/41.gpio_full_random.1263948000
Short name T721
Test name
Test status
Simulation time 227848577 ps
CPU time 0.91 seconds
Started Dec 27 01:24:31 PM PST 23
Finished Dec 27 01:24:32 PM PST 23
Peak memory 196896 kb
Host smart-7c69e252-e8bf-4d53-a8a1-faf27476d1f6
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1263948000 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_full_random.1263948000
Directory /workspace/41.gpio_full_random/latest

Test location /workspace/coverage/default/41.gpio_intr_rand_pgm.3991892728
Short name T271
Test name
Test status
Simulation time 129946578 ps
CPU time 1.02 seconds
Started Dec 27 01:24:48 PM PST 23
Finished Dec 27 01:24:52 PM PST 23
Peak memory 196240 kb
Host smart-97cf8bb3-254c-4217-bda0-f8485c90042f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3991892728 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_intr_rand_pgm.3991892728
Directory /workspace/41.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/41.gpio_intr_with_filter_rand_intr_event.2111123300
Short name T48
Test name
Test status
Simulation time 45563437 ps
CPU time 1.73 seconds
Started Dec 27 01:25:00 PM PST 23
Finished Dec 27 01:25:02 PM PST 23
Peak memory 198060 kb
Host smart-98f60999-276b-443b-a359-306e95b716a9
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2111123300 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 41.gpio_intr_with_filter_rand_intr_event.2111123300
Directory /workspace/41.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/41.gpio_rand_intr_trigger.3763873957
Short name T318
Test name
Test status
Simulation time 157402597 ps
CPU time 3.05 seconds
Started Dec 27 01:25:03 PM PST 23
Finished Dec 27 01:25:07 PM PST 23
Peak memory 198020 kb
Host smart-c90e8e1e-a715-4f3e-999d-9048d470369e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3763873957 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_rand_intr_trigger
.3763873957
Directory /workspace/41.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/41.gpio_random_dout_din.3730561063
Short name T752
Test name
Test status
Simulation time 119132191 ps
CPU time 1.22 seconds
Started Dec 27 01:24:30 PM PST 23
Finished Dec 27 01:24:32 PM PST 23
Peak memory 197184 kb
Host smart-6f87a40c-6e70-4e2c-af10-8148a85984a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3730561063 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_random_dout_din.3730561063
Directory /workspace/41.gpio_random_dout_din/latest

Test location /workspace/coverage/default/41.gpio_random_dout_din_no_pullup_pulldown.1484626913
Short name T570
Test name
Test status
Simulation time 33678224 ps
CPU time 1.22 seconds
Started Dec 27 01:24:48 PM PST 23
Finished Dec 27 01:24:52 PM PST 23
Peak memory 196992 kb
Host smart-2a6acc97-d0cc-44e4-99c3-9f8827ba65b6
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1484626913 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_random_dout_din_no_pullu
p_pulldown.1484626913
Directory /workspace/41.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/41.gpio_random_long_reg_writes_reg_reads.284799790
Short name T285
Test name
Test status
Simulation time 340613570 ps
CPU time 4.13 seconds
Started Dec 27 01:24:50 PM PST 23
Finished Dec 27 01:24:57 PM PST 23
Peak memory 197952 kb
Host smart-a6e54b46-6169-4b19-81f1-440e2f93bd57
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=284799790 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_ran
dom_long_reg_writes_reg_reads.284799790
Directory /workspace/41.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/41.gpio_smoke.959889438
Short name T467
Test name
Test status
Simulation time 233111633 ps
CPU time 0.78 seconds
Started Dec 27 01:24:28 PM PST 23
Finished Dec 27 01:24:29 PM PST 23
Peak memory 196100 kb
Host smart-c66c2b97-1aab-4d03-9755-60e694622d37
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=959889438 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_smoke.959889438
Directory /workspace/41.gpio_smoke/latest

Test location /workspace/coverage/default/41.gpio_smoke_no_pullup_pulldown.1593606568
Short name T629
Test name
Test status
Simulation time 441797551 ps
CPU time 0.87 seconds
Started Dec 27 01:24:43 PM PST 23
Finished Dec 27 01:24:46 PM PST 23
Peak memory 195872 kb
Host smart-85c0a2e2-412c-4d55-9569-4581b3a69d08
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1593606568 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_smoke_no_pullup_pulldown.1593606568
Directory /workspace/41.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/41.gpio_stress_all.4284323771
Short name T591
Test name
Test status
Simulation time 53488986500 ps
CPU time 184.39 seconds
Started Dec 27 01:24:48 PM PST 23
Finished Dec 27 01:27:55 PM PST 23
Peak memory 198260 kb
Host smart-1fbfaefe-cfca-4bb4-bcf4-f71d97b8edb7
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4284323771 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.
gpio_stress_all.4284323771
Directory /workspace/41.gpio_stress_all/latest

Test location /workspace/coverage/default/41.gpio_stress_all_with_rand_reset.1558650820
Short name T764
Test name
Test status
Simulation time 66826446631 ps
CPU time 390.82 seconds
Started Dec 27 01:24:47 PM PST 23
Finished Dec 27 01:31:22 PM PST 23
Peak memory 198380 kb
Host smart-80b58159-2d64-4a5b-8de0-9ff8d2310c0c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=1558650820 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.gpio_stress_all_with_rand_reset.1558650820
Directory /workspace/41.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/42.gpio_alert_test.2830408053
Short name T742
Test name
Test status
Simulation time 18859414 ps
CPU time 0.57 seconds
Started Dec 27 01:24:33 PM PST 23
Finished Dec 27 01:24:35 PM PST 23
Peak memory 194704 kb
Host smart-ab1c9b70-d306-42e7-be29-4938dd4a26a1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2830408053 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_alert_test.2830408053
Directory /workspace/42.gpio_alert_test/latest

Test location /workspace/coverage/default/42.gpio_dout_din_regs_random_rw.2767988921
Short name T720
Test name
Test status
Simulation time 16044931 ps
CPU time 0.62 seconds
Started Dec 27 01:23:49 PM PST 23
Finished Dec 27 01:23:50 PM PST 23
Peak memory 194164 kb
Host smart-654b6e49-c15a-48d9-baa4-2df3d6c714af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2767988921 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_dout_din_regs_random_rw.2767988921
Directory /workspace/42.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/42.gpio_filter_stress.159369450
Short name T640
Test name
Test status
Simulation time 4007815608 ps
CPU time 21.41 seconds
Started Dec 27 01:23:51 PM PST 23
Finished Dec 27 01:24:14 PM PST 23
Peak memory 197180 kb
Host smart-c9bd9715-dd76-4123-85c1-2ae7dd406aba
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=159369450 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_filter_stres
s.159369450
Directory /workspace/42.gpio_filter_stress/latest

Test location /workspace/coverage/default/42.gpio_full_random.2512712165
Short name T263
Test name
Test status
Simulation time 609390412 ps
CPU time 1.05 seconds
Started Dec 27 01:24:33 PM PST 23
Finished Dec 27 01:24:35 PM PST 23
Peak memory 196384 kb
Host smart-b9dfec46-f1b6-43cf-af9b-0648ac5eff93
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2512712165 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_full_random.2512712165
Directory /workspace/42.gpio_full_random/latest

Test location /workspace/coverage/default/42.gpio_intr_rand_pgm.3748440965
Short name T609
Test name
Test status
Simulation time 54958076 ps
CPU time 0.98 seconds
Started Dec 27 01:25:20 PM PST 23
Finished Dec 27 01:25:21 PM PST 23
Peak memory 196556 kb
Host smart-8ab2ca4d-7f59-42da-8d4b-f0629540ab00
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3748440965 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_intr_rand_pgm.3748440965
Directory /workspace/42.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/42.gpio_intr_with_filter_rand_intr_event.3894910067
Short name T711
Test name
Test status
Simulation time 40194306 ps
CPU time 0.87 seconds
Started Dec 27 01:24:13 PM PST 23
Finished Dec 27 01:24:14 PM PST 23
Peak memory 196844 kb
Host smart-3db91a43-0abb-4f74-a5fb-8680bc33aa52
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3894910067 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 42.gpio_intr_with_filter_rand_intr_event.3894910067
Directory /workspace/42.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/42.gpio_rand_intr_trigger.3370500005
Short name T417
Test name
Test status
Simulation time 474138929 ps
CPU time 2.3 seconds
Started Dec 27 01:23:46 PM PST 23
Finished Dec 27 01:23:48 PM PST 23
Peak memory 195912 kb
Host smart-20ddcad3-bee9-46e2-9688-832cf09ce823
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3370500005 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_rand_intr_trigger
.3370500005
Directory /workspace/42.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/42.gpio_random_dout_din.2700193365
Short name T862
Test name
Test status
Simulation time 129112144 ps
CPU time 0.67 seconds
Started Dec 27 01:23:50 PM PST 23
Finished Dec 27 01:23:52 PM PST 23
Peak memory 194344 kb
Host smart-adedca33-d45f-4a09-b546-c7705e0f7f7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2700193365 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_random_dout_din.2700193365
Directory /workspace/42.gpio_random_dout_din/latest

Test location /workspace/coverage/default/42.gpio_random_dout_din_no_pullup_pulldown.7318559
Short name T360
Test name
Test status
Simulation time 33037430 ps
CPU time 0.77 seconds
Started Dec 27 01:23:51 PM PST 23
Finished Dec 27 01:23:54 PM PST 23
Peak memory 195228 kb
Host smart-5fa20866-0b19-44b3-afe9-b378766f2f81
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=7318559 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_random_dout_din_no_pullup_p
ulldown.7318559
Directory /workspace/42.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/42.gpio_random_long_reg_writes_reg_reads.270899040
Short name T584
Test name
Test status
Simulation time 261685445 ps
CPU time 3.67 seconds
Started Dec 27 01:23:50 PM PST 23
Finished Dec 27 01:23:55 PM PST 23
Peak memory 198080 kb
Host smart-f3056d68-b62a-4d54-bcfe-6b7f2d7fd410
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=270899040 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_ran
dom_long_reg_writes_reg_reads.270899040
Directory /workspace/42.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/42.gpio_smoke.3264973540
Short name T687
Test name
Test status
Simulation time 108056558 ps
CPU time 0.8 seconds
Started Dec 27 01:24:20 PM PST 23
Finished Dec 27 01:24:22 PM PST 23
Peak memory 196116 kb
Host smart-adfca714-dadd-4f91-966c-f42cb3019c7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3264973540 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_smoke.3264973540
Directory /workspace/42.gpio_smoke/latest

Test location /workspace/coverage/default/42.gpio_smoke_no_pullup_pulldown.1048950899
Short name T427
Test name
Test status
Simulation time 52322175 ps
CPU time 1.07 seconds
Started Dec 27 01:24:10 PM PST 23
Finished Dec 27 01:24:12 PM PST 23
Peak memory 196508 kb
Host smart-47928f48-906b-4ad6-84d1-cd14f859da56
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1048950899 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_smoke_no_pullup_pulldown.1048950899
Directory /workspace/42.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/42.gpio_stress_all.3066158464
Short name T869
Test name
Test status
Simulation time 10812011627 ps
CPU time 90.32 seconds
Started Dec 27 01:24:11 PM PST 23
Finished Dec 27 01:25:42 PM PST 23
Peak memory 198244 kb
Host smart-19ff4f34-b319-469c-9510-5f22b1486acd
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3066158464 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.
gpio_stress_all.3066158464
Directory /workspace/42.gpio_stress_all/latest

Test location /workspace/coverage/default/42.gpio_stress_all_with_rand_reset.2603787810
Short name T72
Test name
Test status
Simulation time 948350461897 ps
CPU time 1436.18 seconds
Started Dec 27 01:23:52 PM PST 23
Finished Dec 27 01:47:50 PM PST 23
Peak memory 206512 kb
Host smart-e77bcfa6-59da-41e4-9d0f-3ca3514099d2
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=2603787810 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.gpio_stress_all_with_rand_reset.2603787810
Directory /workspace/42.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/43.gpio_alert_test.1038139657
Short name T751
Test name
Test status
Simulation time 43447293 ps
CPU time 0.57 seconds
Started Dec 27 01:24:31 PM PST 23
Finished Dec 27 01:24:33 PM PST 23
Peak memory 194784 kb
Host smart-72856cf4-c94a-4b16-9a8a-34505934ea29
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1038139657 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_alert_test.1038139657
Directory /workspace/43.gpio_alert_test/latest

Test location /workspace/coverage/default/43.gpio_dout_din_regs_random_rw.2010024425
Short name T334
Test name
Test status
Simulation time 66243375 ps
CPU time 0.72 seconds
Started Dec 27 01:24:33 PM PST 23
Finished Dec 27 01:24:35 PM PST 23
Peak memory 196108 kb
Host smart-5b980b52-c62d-4d42-a1a2-a0a335096b50
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2010024425 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_dout_din_regs_random_rw.2010024425
Directory /workspace/43.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/43.gpio_filter_stress.1827407413
Short name T544
Test name
Test status
Simulation time 2200263489 ps
CPU time 27.05 seconds
Started Dec 27 01:24:18 PM PST 23
Finished Dec 27 01:24:46 PM PST 23
Peak memory 196620 kb
Host smart-633a5b53-4b63-492a-a0e6-bf4403f7c654
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1827407413 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_filter_stre
ss.1827407413
Directory /workspace/43.gpio_filter_stress/latest

Test location /workspace/coverage/default/43.gpio_full_random.1124511471
Short name T632
Test name
Test status
Simulation time 76411564 ps
CPU time 0.63 seconds
Started Dec 27 01:24:50 PM PST 23
Finished Dec 27 01:24:54 PM PST 23
Peak memory 194468 kb
Host smart-1f6b9d0a-2c03-4fa9-87ab-3fcbb2dce6fe
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1124511471 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_full_random.1124511471
Directory /workspace/43.gpio_full_random/latest

Test location /workspace/coverage/default/43.gpio_intr_rand_pgm.2244975102
Short name T505
Test name
Test status
Simulation time 24123654 ps
CPU time 0.68 seconds
Started Dec 27 01:23:55 PM PST 23
Finished Dec 27 01:23:57 PM PST 23
Peak memory 195128 kb
Host smart-509e7725-070f-44f0-99a0-fd1a34ce5362
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2244975102 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_intr_rand_pgm.2244975102
Directory /workspace/43.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/43.gpio_intr_with_filter_rand_intr_event.2449976915
Short name T356
Test name
Test status
Simulation time 27753861 ps
CPU time 1.2 seconds
Started Dec 27 01:24:40 PM PST 23
Finished Dec 27 01:24:43 PM PST 23
Peak memory 196612 kb
Host smart-6faf5efb-1509-4ac1-a6e2-428c78f40320
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2449976915 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 43.gpio_intr_with_filter_rand_intr_event.2449976915
Directory /workspace/43.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/43.gpio_rand_intr_trigger.250587543
Short name T534
Test name
Test status
Simulation time 27614910 ps
CPU time 0.97 seconds
Started Dec 27 01:24:33 PM PST 23
Finished Dec 27 01:24:35 PM PST 23
Peak memory 195656 kb
Host smart-0e26ebcb-acb0-4b3e-81eb-0054c0c56719
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=250587543 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_rand_intr_trigger.
250587543
Directory /workspace/43.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/43.gpio_random_dout_din.2416412315
Short name T53
Test name
Test status
Simulation time 53935215 ps
CPU time 1.04 seconds
Started Dec 27 01:24:18 PM PST 23
Finished Dec 27 01:24:20 PM PST 23
Peak memory 196060 kb
Host smart-c07ba022-5406-4b28-8084-6599e969905f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2416412315 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_random_dout_din.2416412315
Directory /workspace/43.gpio_random_dout_din/latest

Test location /workspace/coverage/default/43.gpio_random_dout_din_no_pullup_pulldown.1710190591
Short name T642
Test name
Test status
Simulation time 154354363 ps
CPU time 0.96 seconds
Started Dec 27 01:24:17 PM PST 23
Finished Dec 27 01:24:24 PM PST 23
Peak memory 196844 kb
Host smart-780ab3f2-1368-4f2a-93ca-559db102c484
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1710190591 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_random_dout_din_no_pullu
p_pulldown.1710190591
Directory /workspace/43.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/43.gpio_random_long_reg_writes_reg_reads.752523903
Short name T359
Test name
Test status
Simulation time 27582739 ps
CPU time 1.2 seconds
Started Dec 27 01:24:28 PM PST 23
Finished Dec 27 01:24:30 PM PST 23
Peak memory 198004 kb
Host smart-6d50a29e-efec-480a-b5fb-3a773571481d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=752523903 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_ran
dom_long_reg_writes_reg_reads.752523903
Directory /workspace/43.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/43.gpio_smoke.1586371669
Short name T769
Test name
Test status
Simulation time 341057599 ps
CPU time 1.3 seconds
Started Dec 27 01:24:36 PM PST 23
Finished Dec 27 01:24:38 PM PST 23
Peak memory 195920 kb
Host smart-779c56de-5adb-42e7-ac72-e345f30c4b3e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1586371669 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_smoke.1586371669
Directory /workspace/43.gpio_smoke/latest

Test location /workspace/coverage/default/43.gpio_smoke_no_pullup_pulldown.2602465150
Short name T289
Test name
Test status
Simulation time 42492264 ps
CPU time 0.92 seconds
Started Dec 27 01:23:55 PM PST 23
Finished Dec 27 01:23:57 PM PST 23
Peak memory 196360 kb
Host smart-1771c861-6950-49bd-85b0-95cc7a2e6a31
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2602465150 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_smoke_no_pullup_pulldown.2602465150
Directory /workspace/43.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/43.gpio_stress_all.819032852
Short name T319
Test name
Test status
Simulation time 12030893774 ps
CPU time 132.93 seconds
Started Dec 27 01:24:11 PM PST 23
Finished Dec 27 01:26:25 PM PST 23
Peak memory 198128 kb
Host smart-d52f19db-0c74-4ea1-94e9-396077dbc743
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=819032852 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.g
pio_stress_all.819032852
Directory /workspace/43.gpio_stress_all/latest

Test location /workspace/coverage/default/43.gpio_stress_all_with_rand_reset.2619977844
Short name T507
Test name
Test status
Simulation time 78378715881 ps
CPU time 1067.71 seconds
Started Dec 27 01:24:24 PM PST 23
Finished Dec 27 01:42:13 PM PST 23
Peak memory 198344 kb
Host smart-837766fa-b97b-4d9e-8f38-9fd762ef7049
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=2619977844 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.gpio_stress_all_with_rand_reset.2619977844
Directory /workspace/43.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/44.gpio_alert_test.3781833224
Short name T252
Test name
Test status
Simulation time 13811043 ps
CPU time 0.56 seconds
Started Dec 27 01:24:45 PM PST 23
Finished Dec 27 01:24:50 PM PST 23
Peak memory 194032 kb
Host smart-a9a026b2-139c-46ff-b23d-7bd805af417d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3781833224 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_alert_test.3781833224
Directory /workspace/44.gpio_alert_test/latest

Test location /workspace/coverage/default/44.gpio_dout_din_regs_random_rw.2935153347
Short name T280
Test name
Test status
Simulation time 20613833 ps
CPU time 0.71 seconds
Started Dec 27 01:24:36 PM PST 23
Finished Dec 27 01:24:38 PM PST 23
Peak memory 195180 kb
Host smart-0c35bd52-f231-4bd0-ae32-59dfd27fe66d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2935153347 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_dout_din_regs_random_rw.2935153347
Directory /workspace/44.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/44.gpio_filter_stress.2291212813
Short name T556
Test name
Test status
Simulation time 213179132 ps
CPU time 5.89 seconds
Started Dec 27 01:24:29 PM PST 23
Finished Dec 27 01:24:36 PM PST 23
Peak memory 196932 kb
Host smart-a7f51f4b-b23e-47d3-aed8-73c350853b9a
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2291212813 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_filter_stre
ss.2291212813
Directory /workspace/44.gpio_filter_stress/latest

Test location /workspace/coverage/default/44.gpio_full_random.81443299
Short name T341
Test name
Test status
Simulation time 46549288 ps
CPU time 0.69 seconds
Started Dec 27 01:24:48 PM PST 23
Finished Dec 27 01:24:51 PM PST 23
Peak memory 195212 kb
Host smart-d6793781-81ec-44bc-a42b-ca61caa3993f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=81443299 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_full_random.81443299
Directory /workspace/44.gpio_full_random/latest

Test location /workspace/coverage/default/44.gpio_intr_rand_pgm.674767372
Short name T872
Test name
Test status
Simulation time 78515404 ps
CPU time 1.25 seconds
Started Dec 27 01:24:42 PM PST 23
Finished Dec 27 01:24:45 PM PST 23
Peak memory 196988 kb
Host smart-e39ac0d4-5f0a-4cf1-965b-7320472fffdc
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=674767372 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_intr_rand_pgm.674767372
Directory /workspace/44.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/44.gpio_intr_with_filter_rand_intr_event.3758299638
Short name T670
Test name
Test status
Simulation time 623380412 ps
CPU time 3.68 seconds
Started Dec 27 01:24:16 PM PST 23
Finished Dec 27 01:24:20 PM PST 23
Peak memory 198160 kb
Host smart-3f88b49a-30e5-4261-ba37-fc002379f8cf
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3758299638 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 44.gpio_intr_with_filter_rand_intr_event.3758299638
Directory /workspace/44.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/44.gpio_rand_intr_trigger.2078343925
Short name T376
Test name
Test status
Simulation time 87773954 ps
CPU time 1.37 seconds
Started Dec 27 01:24:15 PM PST 23
Finished Dec 27 01:24:17 PM PST 23
Peak memory 196264 kb
Host smart-6cc2f4b7-3de3-412d-baa1-5544a9b549b8
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2078343925 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_rand_intr_trigger
.2078343925
Directory /workspace/44.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/44.gpio_random_dout_din.3342439940
Short name T335
Test name
Test status
Simulation time 41880905 ps
CPU time 0.89 seconds
Started Dec 27 01:24:10 PM PST 23
Finished Dec 27 01:24:12 PM PST 23
Peak memory 195892 kb
Host smart-2a36fe79-3d27-477c-9932-d1eed926d70d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3342439940 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_random_dout_din.3342439940
Directory /workspace/44.gpio_random_dout_din/latest

Test location /workspace/coverage/default/44.gpio_random_dout_din_no_pullup_pulldown.2034259913
Short name T807
Test name
Test status
Simulation time 26079947 ps
CPU time 0.99 seconds
Started Dec 27 01:24:17 PM PST 23
Finished Dec 27 01:24:19 PM PST 23
Peak memory 196668 kb
Host smart-74809bf6-a63d-47b3-8d83-4e621967f19e
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2034259913 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_random_dout_din_no_pullu
p_pulldown.2034259913
Directory /workspace/44.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/44.gpio_random_long_reg_writes_reg_reads.432761599
Short name T462
Test name
Test status
Simulation time 242081775 ps
CPU time 2.73 seconds
Started Dec 27 01:24:29 PM PST 23
Finished Dec 27 01:24:32 PM PST 23
Peak memory 198028 kb
Host smart-dced024a-b663-4a9a-a88e-2e34b0d55f09
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=432761599 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_ran
dom_long_reg_writes_reg_reads.432761599
Directory /workspace/44.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/44.gpio_smoke.1598063889
Short name T794
Test name
Test status
Simulation time 38608261 ps
CPU time 1.1 seconds
Started Dec 27 01:24:10 PM PST 23
Finished Dec 27 01:24:12 PM PST 23
Peak memory 195780 kb
Host smart-c876db7d-c26f-43b7-b6af-ff5461f43519
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1598063889 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_smoke.1598063889
Directory /workspace/44.gpio_smoke/latest

Test location /workspace/coverage/default/44.gpio_smoke_no_pullup_pulldown.2446182945
Short name T615
Test name
Test status
Simulation time 56361913 ps
CPU time 1.24 seconds
Started Dec 27 01:24:47 PM PST 23
Finished Dec 27 01:24:51 PM PST 23
Peak memory 198132 kb
Host smart-0cf3dc32-9862-4eac-a94d-2b5b9b93b075
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2446182945 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_smoke_no_pullup_pulldown.2446182945
Directory /workspace/44.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/44.gpio_stress_all.1698676378
Short name T303
Test name
Test status
Simulation time 7240917835 ps
CPU time 193.15 seconds
Started Dec 27 01:24:11 PM PST 23
Finished Dec 27 01:27:25 PM PST 23
Peak memory 198152 kb
Host smart-1b09f03f-8aab-4783-ad53-6622c0120faf
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1698676378 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.
gpio_stress_all.1698676378
Directory /workspace/44.gpio_stress_all/latest

Test location /workspace/coverage/default/44.gpio_stress_all_with_rand_reset.1432666466
Short name T448
Test name
Test status
Simulation time 478562763332 ps
CPU time 611 seconds
Started Dec 27 01:24:19 PM PST 23
Finished Dec 27 01:34:31 PM PST 23
Peak memory 198436 kb
Host smart-ff1d0509-2c90-45a4-bc5f-5e8991f12ad9
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=1432666466 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.gpio_stress_all_with_rand_reset.1432666466
Directory /workspace/44.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/45.gpio_alert_test.247183911
Short name T560
Test name
Test status
Simulation time 20411947 ps
CPU time 0.64 seconds
Started Dec 27 01:24:26 PM PST 23
Finished Dec 27 01:24:27 PM PST 23
Peak memory 194300 kb
Host smart-ff67a9ef-ba6b-4fd2-95cd-be90325bdcbe
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=247183911 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_alert_test.247183911
Directory /workspace/45.gpio_alert_test/latest

Test location /workspace/coverage/default/45.gpio_dout_din_regs_random_rw.750145669
Short name T768
Test name
Test status
Simulation time 132254198 ps
CPU time 0.63 seconds
Started Dec 27 01:24:23 PM PST 23
Finished Dec 27 01:24:24 PM PST 23
Peak memory 194772 kb
Host smart-2def9cff-6af5-42bb-9316-4645932545b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=750145669 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_dout_din_regs_random_rw.750145669
Directory /workspace/45.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/45.gpio_filter_stress.1225226757
Short name T305
Test name
Test status
Simulation time 391475525 ps
CPU time 7.82 seconds
Started Dec 27 01:25:00 PM PST 23
Finished Dec 27 01:25:09 PM PST 23
Peak memory 195680 kb
Host smart-2388f635-cb6c-4d64-b53b-78d9a1546155
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1225226757 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_filter_stre
ss.1225226757
Directory /workspace/45.gpio_filter_stress/latest

Test location /workspace/coverage/default/45.gpio_full_random.3344399745
Short name T800
Test name
Test status
Simulation time 43689344 ps
CPU time 0.61 seconds
Started Dec 27 01:24:45 PM PST 23
Finished Dec 27 01:24:51 PM PST 23
Peak memory 195088 kb
Host smart-ad3b4c9c-32c0-48c0-a1da-32d67025600c
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3344399745 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_full_random.3344399745
Directory /workspace/45.gpio_full_random/latest

Test location /workspace/coverage/default/45.gpio_intr_rand_pgm.1620956698
Short name T449
Test name
Test status
Simulation time 123559446 ps
CPU time 1.05 seconds
Started Dec 27 01:24:16 PM PST 23
Finished Dec 27 01:24:17 PM PST 23
Peak memory 196004 kb
Host smart-03d30e9c-604d-48b2-bdd6-c125bb6a296d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1620956698 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_intr_rand_pgm.1620956698
Directory /workspace/45.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/45.gpio_intr_with_filter_rand_intr_event.2328661041
Short name T492
Test name
Test status
Simulation time 164083090 ps
CPU time 1.93 seconds
Started Dec 27 01:24:20 PM PST 23
Finished Dec 27 01:24:23 PM PST 23
Peak memory 198252 kb
Host smart-03e7bc36-6232-496f-97de-7f726fa871ab
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2328661041 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 45.gpio_intr_with_filter_rand_intr_event.2328661041
Directory /workspace/45.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/45.gpio_rand_intr_trigger.2217945638
Short name T339
Test name
Test status
Simulation time 964405299 ps
CPU time 3.33 seconds
Started Dec 27 01:24:36 PM PST 23
Finished Dec 27 01:24:40 PM PST 23
Peak memory 198172 kb
Host smart-ee5f4314-f3a4-4ea7-a447-06d3bf531b47
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2217945638 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_rand_intr_trigger
.2217945638
Directory /workspace/45.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/45.gpio_random_dout_din.240997433
Short name T648
Test name
Test status
Simulation time 25066445 ps
CPU time 0.94 seconds
Started Dec 27 01:24:44 PM PST 23
Finished Dec 27 01:24:46 PM PST 23
Peak memory 196040 kb
Host smart-b827f51b-8a7a-47c0-a6a7-21e65dcb3512
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=240997433 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_random_dout_din.240997433
Directory /workspace/45.gpio_random_dout_din/latest

Test location /workspace/coverage/default/45.gpio_random_dout_din_no_pullup_pulldown.867789336
Short name T602
Test name
Test status
Simulation time 52859632 ps
CPU time 1.12 seconds
Started Dec 27 01:24:18 PM PST 23
Finished Dec 27 01:24:20 PM PST 23
Peak memory 195872 kb
Host smart-f69580d5-9a66-488d-94c3-414af8d62767
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=867789336 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_random_dout_din_no_pullup
_pulldown.867789336
Directory /workspace/45.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/45.gpio_random_long_reg_writes_reg_reads.2384425330
Short name T310
Test name
Test status
Simulation time 4116322851 ps
CPU time 4.09 seconds
Started Dec 27 01:24:13 PM PST 23
Finished Dec 27 01:24:18 PM PST 23
Peak memory 198180 kb
Host smart-d16a2ec0-9cc1-4419-b6c9-7a108887afce
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2384425330 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_ra
ndom_long_reg_writes_reg_reads.2384425330
Directory /workspace/45.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/45.gpio_smoke.2039892056
Short name T574
Test name
Test status
Simulation time 128327155 ps
CPU time 1.26 seconds
Started Dec 27 01:24:45 PM PST 23
Finished Dec 27 01:24:50 PM PST 23
Peak memory 195864 kb
Host smart-8cf8a536-f6cc-4495-8a09-8636e4910820
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2039892056 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_smoke.2039892056
Directory /workspace/45.gpio_smoke/latest

Test location /workspace/coverage/default/45.gpio_smoke_no_pullup_pulldown.799957977
Short name T232
Test name
Test status
Simulation time 112066497 ps
CPU time 0.76 seconds
Started Dec 27 01:24:17 PM PST 23
Finished Dec 27 01:24:19 PM PST 23
Peak memory 195788 kb
Host smart-ca40b667-a23e-4211-9767-5edbcfd845c5
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=799957977 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_smoke_no_pullup_pulldown.799957977
Directory /workspace/45.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/45.gpio_stress_all.4085152356
Short name T706
Test name
Test status
Simulation time 12797565603 ps
CPU time 94.88 seconds
Started Dec 27 01:24:26 PM PST 23
Finished Dec 27 01:26:02 PM PST 23
Peak memory 198184 kb
Host smart-e634d9a5-1e3a-449c-b5da-81742b9f9f52
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4085152356 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.
gpio_stress_all.4085152356
Directory /workspace/45.gpio_stress_all/latest

Test location /workspace/coverage/default/45.gpio_stress_all_with_rand_reset.3387901097
Short name T85
Test name
Test status
Simulation time 79363212341 ps
CPU time 1681.46 seconds
Started Dec 27 01:24:17 PM PST 23
Finished Dec 27 01:52:20 PM PST 23
Peak memory 198428 kb
Host smart-d1b70954-45d4-4c2e-81a1-30a498eb69cf
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=3387901097 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.gpio_stress_all_with_rand_reset.3387901097
Directory /workspace/45.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/46.gpio_alert_test.1848348029
Short name T806
Test name
Test status
Simulation time 43020782 ps
CPU time 0.59 seconds
Started Dec 27 01:24:31 PM PST 23
Finished Dec 27 01:24:33 PM PST 23
Peak memory 194240 kb
Host smart-2b0e00d9-2562-4bc9-9cc7-0883c79a9875
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1848348029 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_alert_test.1848348029
Directory /workspace/46.gpio_alert_test/latest

Test location /workspace/coverage/default/46.gpio_dout_din_regs_random_rw.1592618408
Short name T799
Test name
Test status
Simulation time 48554836 ps
CPU time 0.78 seconds
Started Dec 27 01:24:14 PM PST 23
Finished Dec 27 01:24:15 PM PST 23
Peak memory 195436 kb
Host smart-19559f39-b959-4eb5-9c2f-42168c60b189
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1592618408 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_dout_din_regs_random_rw.1592618408
Directory /workspace/46.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/46.gpio_filter_stress.3251141240
Short name T604
Test name
Test status
Simulation time 849060976 ps
CPU time 15.62 seconds
Started Dec 27 01:24:17 PM PST 23
Finished Dec 27 01:24:34 PM PST 23
Peak memory 198060 kb
Host smart-8a2adbe0-efc5-48fa-9b98-e90f087519dc
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3251141240 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_filter_stre
ss.3251141240
Directory /workspace/46.gpio_filter_stress/latest

Test location /workspace/coverage/default/46.gpio_full_random.468481706
Short name T392
Test name
Test status
Simulation time 143564021 ps
CPU time 0.75 seconds
Started Dec 27 01:24:33 PM PST 23
Finished Dec 27 01:24:35 PM PST 23
Peak memory 196580 kb
Host smart-d2c362fa-3a2d-4f3a-9fff-18432e64bcf0
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=468481706 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_full_random.468481706
Directory /workspace/46.gpio_full_random/latest

Test location /workspace/coverage/default/46.gpio_intr_rand_pgm.2549794939
Short name T389
Test name
Test status
Simulation time 56886716 ps
CPU time 0.88 seconds
Started Dec 27 01:24:11 PM PST 23
Finished Dec 27 01:24:13 PM PST 23
Peak memory 196160 kb
Host smart-2a77f47b-f030-4e23-aa4b-52830b8e15c6
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2549794939 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_intr_rand_pgm.2549794939
Directory /workspace/46.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/46.gpio_intr_with_filter_rand_intr_event.2909858156
Short name T682
Test name
Test status
Simulation time 123902235 ps
CPU time 2.45 seconds
Started Dec 27 01:24:16 PM PST 23
Finished Dec 27 01:24:19 PM PST 23
Peak memory 198016 kb
Host smart-b32e42a5-ecc3-4352-892d-771c8ab9bd19
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2909858156 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 46.gpio_intr_with_filter_rand_intr_event.2909858156
Directory /workspace/46.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/46.gpio_rand_intr_trigger.1818960163
Short name T652
Test name
Test status
Simulation time 181622529 ps
CPU time 1.57 seconds
Started Dec 27 01:24:47 PM PST 23
Finished Dec 27 01:24:52 PM PST 23
Peak memory 196300 kb
Host smart-049cad31-1a04-4aba-a69a-965c44ef6e8e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1818960163 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_rand_intr_trigger
.1818960163
Directory /workspace/46.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/46.gpio_random_dout_din.4042600490
Short name T468
Test name
Test status
Simulation time 32454809 ps
CPU time 0.83 seconds
Started Dec 27 01:24:12 PM PST 23
Finished Dec 27 01:24:13 PM PST 23
Peak memory 195320 kb
Host smart-0f882d3b-ee75-4186-ae6b-0482adf3e906
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4042600490 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_random_dout_din.4042600490
Directory /workspace/46.gpio_random_dout_din/latest

Test location /workspace/coverage/default/46.gpio_random_dout_din_no_pullup_pulldown.2440586583
Short name T374
Test name
Test status
Simulation time 152312886 ps
CPU time 1.18 seconds
Started Dec 27 01:24:32 PM PST 23
Finished Dec 27 01:24:34 PM PST 23
Peak memory 198088 kb
Host smart-0e177d53-d14d-47ba-a23d-bfc9eab6b8c2
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2440586583 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_random_dout_din_no_pullu
p_pulldown.2440586583
Directory /workspace/46.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/46.gpio_random_long_reg_writes_reg_reads.3337941860
Short name T373
Test name
Test status
Simulation time 327185173 ps
CPU time 3.63 seconds
Started Dec 27 01:24:34 PM PST 23
Finished Dec 27 01:24:39 PM PST 23
Peak memory 198052 kb
Host smart-0dcc9923-0e84-4aad-af20-7aca71350f4e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3337941860 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_ra
ndom_long_reg_writes_reg_reads.3337941860
Directory /workspace/46.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/46.gpio_smoke.478270052
Short name T409
Test name
Test status
Simulation time 30684649 ps
CPU time 0.97 seconds
Started Dec 27 01:24:15 PM PST 23
Finished Dec 27 01:24:16 PM PST 23
Peak memory 195784 kb
Host smart-21b6d1cd-f4be-492e-b1a4-45ad2b3a600d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=478270052 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_smoke.478270052
Directory /workspace/46.gpio_smoke/latest

Test location /workspace/coverage/default/46.gpio_smoke_no_pullup_pulldown.1985503230
Short name T874
Test name
Test status
Simulation time 89043532 ps
CPU time 1.23 seconds
Started Dec 27 01:24:18 PM PST 23
Finished Dec 27 01:24:20 PM PST 23
Peak memory 196872 kb
Host smart-8ff615fc-25d2-4533-a874-b213a2067f41
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1985503230 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_smoke_no_pullup_pulldown.1985503230
Directory /workspace/46.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/46.gpio_stress_all.2019016973
Short name T472
Test name
Test status
Simulation time 18564696968 ps
CPU time 122.34 seconds
Started Dec 27 01:24:45 PM PST 23
Finished Dec 27 01:26:52 PM PST 23
Peak memory 198276 kb
Host smart-f4d8b93f-3d9d-4af1-9c51-50f061b350c4
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2019016973 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.
gpio_stress_all.2019016973
Directory /workspace/46.gpio_stress_all/latest

Test location /workspace/coverage/default/46.gpio_stress_all_with_rand_reset.1830151777
Short name T503
Test name
Test status
Simulation time 61356266056 ps
CPU time 1024.75 seconds
Started Dec 27 01:24:59 PM PST 23
Finished Dec 27 01:42:05 PM PST 23
Peak memory 198328 kb
Host smart-34d304b5-c33a-4f4f-8b9f-738b38c2ad63
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=1830151777 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.gpio_stress_all_with_rand_reset.1830151777
Directory /workspace/46.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/47.gpio_alert_test.2232617041
Short name T868
Test name
Test status
Simulation time 12353221 ps
CPU time 0.58 seconds
Started Dec 27 01:24:52 PM PST 23
Finished Dec 27 01:24:54 PM PST 23
Peak memory 194188 kb
Host smart-9ddd2eb3-3b9c-42e5-8b88-f17bc6661ce8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2232617041 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_alert_test.2232617041
Directory /workspace/47.gpio_alert_test/latest

Test location /workspace/coverage/default/47.gpio_dout_din_regs_random_rw.1829246612
Short name T738
Test name
Test status
Simulation time 32285806 ps
CPU time 0.89 seconds
Started Dec 27 01:24:36 PM PST 23
Finished Dec 27 01:24:38 PM PST 23
Peak memory 195940 kb
Host smart-a4f866cc-ef6b-449c-a94d-d63f6e9ca2d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1829246612 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_dout_din_regs_random_rw.1829246612
Directory /workspace/47.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/47.gpio_filter_stress.1303301796
Short name T633
Test name
Test status
Simulation time 543998126 ps
CPU time 19.41 seconds
Started Dec 27 01:24:50 PM PST 23
Finished Dec 27 01:25:13 PM PST 23
Peak memory 198052 kb
Host smart-8af173a0-51ea-476f-8c26-1c7ea5300522
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1303301796 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_filter_stre
ss.1303301796
Directory /workspace/47.gpio_filter_stress/latest

Test location /workspace/coverage/default/47.gpio_full_random.2946138756
Short name T701
Test name
Test status
Simulation time 44473898 ps
CPU time 0.76 seconds
Started Dec 27 01:24:48 PM PST 23
Finished Dec 27 01:24:51 PM PST 23
Peak memory 195852 kb
Host smart-cc7dd12d-71af-4f80-b89c-d99c1bd7b6b4
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2946138756 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_full_random.2946138756
Directory /workspace/47.gpio_full_random/latest

Test location /workspace/coverage/default/47.gpio_intr_rand_pgm.3725370819
Short name T681
Test name
Test status
Simulation time 60914271 ps
CPU time 1.12 seconds
Started Dec 27 01:25:03 PM PST 23
Finished Dec 27 01:25:06 PM PST 23
Peak memory 196204 kb
Host smart-3f9d8468-9f7e-4486-b68f-85cdab15794e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3725370819 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_intr_rand_pgm.3725370819
Directory /workspace/47.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/47.gpio_intr_with_filter_rand_intr_event.2635176283
Short name T49
Test name
Test status
Simulation time 270814337 ps
CPU time 2.57 seconds
Started Dec 27 01:25:09 PM PST 23
Finished Dec 27 01:25:14 PM PST 23
Peak memory 198008 kb
Host smart-3a5dfae0-c79b-47ba-b361-40904dbda705
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2635176283 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 47.gpio_intr_with_filter_rand_intr_event.2635176283
Directory /workspace/47.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/47.gpio_rand_intr_trigger.509661601
Short name T747
Test name
Test status
Simulation time 116799149 ps
CPU time 0.97 seconds
Started Dec 27 01:24:29 PM PST 23
Finished Dec 27 01:24:30 PM PST 23
Peak memory 195552 kb
Host smart-b3bf3254-8cfe-4b22-8923-95504641bd07
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=509661601 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_rand_intr_trigger.
509661601
Directory /workspace/47.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/47.gpio_random_dout_din.1291225579
Short name T353
Test name
Test status
Simulation time 75442089 ps
CPU time 1.45 seconds
Started Dec 27 01:24:46 PM PST 23
Finished Dec 27 01:24:51 PM PST 23
Peak memory 197192 kb
Host smart-f26472bd-449f-48f6-aec9-c6885c042bb4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1291225579 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_random_dout_din.1291225579
Directory /workspace/47.gpio_random_dout_din/latest

Test location /workspace/coverage/default/47.gpio_random_dout_din_no_pullup_pulldown.229035264
Short name T718
Test name
Test status
Simulation time 38097275 ps
CPU time 0.84 seconds
Started Dec 27 01:25:05 PM PST 23
Finished Dec 27 01:25:09 PM PST 23
Peak memory 196476 kb
Host smart-9e09d8b2-439a-4c4e-845f-e60e669d9452
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=229035264 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_random_dout_din_no_pullup
_pulldown.229035264
Directory /workspace/47.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/47.gpio_random_long_reg_writes_reg_reads.4011946844
Short name T422
Test name
Test status
Simulation time 2167827391 ps
CPU time 6.04 seconds
Started Dec 27 01:24:46 PM PST 23
Finished Dec 27 01:24:56 PM PST 23
Peak memory 198028 kb
Host smart-00a9e4dc-52fe-4486-8c88-e84e577a3125
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4011946844 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_ra
ndom_long_reg_writes_reg_reads.4011946844
Directory /workspace/47.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/47.gpio_smoke.2716358211
Short name T411
Test name
Test status
Simulation time 62624058 ps
CPU time 1.02 seconds
Started Dec 27 01:25:02 PM PST 23
Finished Dec 27 01:25:04 PM PST 23
Peak memory 195708 kb
Host smart-6c8925b3-80a9-49ae-89f0-6e5801f5fb6d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2716358211 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_smoke.2716358211
Directory /workspace/47.gpio_smoke/latest

Test location /workspace/coverage/default/47.gpio_smoke_no_pullup_pulldown.1099043282
Short name T835
Test name
Test status
Simulation time 188747513 ps
CPU time 0.93 seconds
Started Dec 27 01:25:08 PM PST 23
Finished Dec 27 01:25:12 PM PST 23
Peak memory 197372 kb
Host smart-c6135089-331e-4bbf-bf98-d277a4874e7a
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1099043282 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_smoke_no_pullup_pulldown.1099043282
Directory /workspace/47.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/47.gpio_stress_all.1487122043
Short name T516
Test name
Test status
Simulation time 33616139428 ps
CPU time 103.98 seconds
Started Dec 27 01:24:49 PM PST 23
Finished Dec 27 01:26:36 PM PST 23
Peak memory 198240 kb
Host smart-eff25bde-592b-4aa3-816d-03aa64c4c869
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1487122043 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.
gpio_stress_all.1487122043
Directory /workspace/47.gpio_stress_all/latest

Test location /workspace/coverage/default/47.gpio_stress_all_with_rand_reset.3207067469
Short name T754
Test name
Test status
Simulation time 283414173278 ps
CPU time 891.5 seconds
Started Dec 27 01:25:10 PM PST 23
Finished Dec 27 01:40:05 PM PST 23
Peak memory 206576 kb
Host smart-5ea38fdf-dbc1-4f2a-aea5-7be7b5207ea4
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=3207067469 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.gpio_stress_all_with_rand_reset.3207067469
Directory /workspace/47.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/48.gpio_alert_test.3903313167
Short name T540
Test name
Test status
Simulation time 30853930 ps
CPU time 0.56 seconds
Started Dec 27 01:25:11 PM PST 23
Finished Dec 27 01:25:15 PM PST 23
Peak memory 194776 kb
Host smart-be2d3a44-9133-4c98-a941-dbff0b516454
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3903313167 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_alert_test.3903313167
Directory /workspace/48.gpio_alert_test/latest

Test location /workspace/coverage/default/48.gpio_dout_din_regs_random_rw.2957903139
Short name T885
Test name
Test status
Simulation time 103386612 ps
CPU time 0.75 seconds
Started Dec 27 01:24:49 PM PST 23
Finished Dec 27 01:24:52 PM PST 23
Peak memory 196052 kb
Host smart-b45957b5-c4db-466a-99c0-b80336d84ad8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2957903139 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_dout_din_regs_random_rw.2957903139
Directory /workspace/48.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/48.gpio_filter_stress.1564351967
Short name T710
Test name
Test status
Simulation time 1764010334 ps
CPU time 5.69 seconds
Started Dec 27 01:25:10 PM PST 23
Finished Dec 27 01:25:19 PM PST 23
Peak memory 196832 kb
Host smart-9f68dfa5-315e-41b2-886e-10d5daf66f83
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1564351967 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_filter_stre
ss.1564351967
Directory /workspace/48.gpio_filter_stress/latest

Test location /workspace/coverage/default/48.gpio_full_random.1457251173
Short name T47
Test name
Test status
Simulation time 51871974 ps
CPU time 0.8 seconds
Started Dec 27 01:25:13 PM PST 23
Finished Dec 27 01:25:15 PM PST 23
Peak memory 195996 kb
Host smart-d44ba49c-7cc1-415a-b5ad-9fa22b387e34
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1457251173 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_full_random.1457251173
Directory /workspace/48.gpio_full_random/latest

Test location /workspace/coverage/default/48.gpio_intr_rand_pgm.447202305
Short name T326
Test name
Test status
Simulation time 139131838 ps
CPU time 1.31 seconds
Started Dec 27 01:24:47 PM PST 23
Finished Dec 27 01:24:51 PM PST 23
Peak memory 198080 kb
Host smart-137f9b11-62ff-4931-ac32-9ccbce1fa204
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=447202305 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_intr_rand_pgm.447202305
Directory /workspace/48.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/48.gpio_intr_with_filter_rand_intr_event.1571439498
Short name T600
Test name
Test status
Simulation time 112851113 ps
CPU time 2.36 seconds
Started Dec 27 01:25:04 PM PST 23
Finished Dec 27 01:25:08 PM PST 23
Peak memory 198172 kb
Host smart-35506100-85f8-4814-b495-d7cc8b3f1850
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1571439498 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 48.gpio_intr_with_filter_rand_intr_event.1571439498
Directory /workspace/48.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/48.gpio_rand_intr_trigger.3309436407
Short name T510
Test name
Test status
Simulation time 32954183 ps
CPU time 1.07 seconds
Started Dec 27 01:25:06 PM PST 23
Finished Dec 27 01:25:12 PM PST 23
Peak memory 195668 kb
Host smart-46809dde-e847-475e-887b-d41f9fc9ff46
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3309436407 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_rand_intr_trigger
.3309436407
Directory /workspace/48.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/48.gpio_random_dout_din.1386619712
Short name T484
Test name
Test status
Simulation time 110495665 ps
CPU time 1.11 seconds
Started Dec 27 01:25:07 PM PST 23
Finished Dec 27 01:25:12 PM PST 23
Peak memory 196060 kb
Host smart-71864caa-5885-4a75-809a-480cc3482085
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1386619712 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_random_dout_din.1386619712
Directory /workspace/48.gpio_random_dout_din/latest

Test location /workspace/coverage/default/48.gpio_random_dout_din_no_pullup_pulldown.97689702
Short name T777
Test name
Test status
Simulation time 62131443 ps
CPU time 0.69 seconds
Started Dec 27 01:25:07 PM PST 23
Finished Dec 27 01:25:11 PM PST 23
Peak memory 195152 kb
Host smart-2c919654-1993-4b7e-b28a-c71b8279f1b1
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=97689702 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_random_dout_din_no_pullup_
pulldown.97689702
Directory /workspace/48.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/48.gpio_random_long_reg_writes_reg_reads.877100358
Short name T541
Test name
Test status
Simulation time 339081241 ps
CPU time 1.77 seconds
Started Dec 27 01:24:48 PM PST 23
Finished Dec 27 01:24:53 PM PST 23
Peak memory 198032 kb
Host smart-c5a108ed-387e-4698-9d3b-d8ef97f87b45
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=877100358 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_ran
dom_long_reg_writes_reg_reads.877100358
Directory /workspace/48.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/48.gpio_smoke.2609105517
Short name T826
Test name
Test status
Simulation time 111635613 ps
CPU time 0.97 seconds
Started Dec 27 01:25:05 PM PST 23
Finished Dec 27 01:25:10 PM PST 23
Peak memory 197256 kb
Host smart-7f918c73-94eb-4733-88ef-d11f556646e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2609105517 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_smoke.2609105517
Directory /workspace/48.gpio_smoke/latest

Test location /workspace/coverage/default/48.gpio_smoke_no_pullup_pulldown.167202318
Short name T837
Test name
Test status
Simulation time 36940899 ps
CPU time 0.88 seconds
Started Dec 27 01:24:40 PM PST 23
Finished Dec 27 01:24:43 PM PST 23
Peak memory 196468 kb
Host smart-2b38f5aa-dfd2-4b27-a897-92d9b6e69363
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=167202318 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_smoke_no_pullup_pulldown.167202318
Directory /workspace/48.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/48.gpio_stress_all.1736249221
Short name T586
Test name
Test status
Simulation time 15028872411 ps
CPU time 25.14 seconds
Started Dec 27 01:25:08 PM PST 23
Finished Dec 27 01:25:36 PM PST 23
Peak memory 198196 kb
Host smart-f4d322e0-9915-41ba-9433-7dcc4cc634dc
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1736249221 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.
gpio_stress_all.1736249221
Directory /workspace/48.gpio_stress_all/latest

Test location /workspace/coverage/default/48.gpio_stress_all_with_rand_reset.1689184245
Short name T833
Test name
Test status
Simulation time 68746381189 ps
CPU time 557.06 seconds
Started Dec 27 01:26:01 PM PST 23
Finished Dec 27 01:35:20 PM PST 23
Peak memory 198312 kb
Host smart-db91a4c0-d11a-42e4-8a1b-6823033e516f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=1689184245 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.gpio_stress_all_with_rand_reset.1689184245
Directory /workspace/48.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/49.gpio_alert_test.572964534
Short name T51
Test name
Test status
Simulation time 12251584 ps
CPU time 0.58 seconds
Started Dec 27 01:24:12 PM PST 23
Finished Dec 27 01:24:14 PM PST 23
Peak memory 194112 kb
Host smart-8606ebbf-4ff9-48a7-a374-cb2b492bd5c8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=572964534 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_alert_test.572964534
Directory /workspace/49.gpio_alert_test/latest

Test location /workspace/coverage/default/49.gpio_dout_din_regs_random_rw.1771822138
Short name T447
Test name
Test status
Simulation time 79438118 ps
CPU time 0.91 seconds
Started Dec 27 01:25:28 PM PST 23
Finished Dec 27 01:25:29 PM PST 23
Peak memory 197408 kb
Host smart-43a9ed41-7f51-4ad1-9609-f73323921e4d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1771822138 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_dout_din_regs_random_rw.1771822138
Directory /workspace/49.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/49.gpio_filter_stress.3176576535
Short name T65
Test name
Test status
Simulation time 3769576589 ps
CPU time 20.63 seconds
Started Dec 27 01:24:46 PM PST 23
Finished Dec 27 01:25:11 PM PST 23
Peak memory 196944 kb
Host smart-7fb6ae99-0c52-431e-bf57-68a23be4d0b7
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3176576535 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_filter_stre
ss.3176576535
Directory /workspace/49.gpio_filter_stress/latest

Test location /workspace/coverage/default/49.gpio_full_random.767266549
Short name T529
Test name
Test status
Simulation time 508105723 ps
CPU time 0.71 seconds
Started Dec 27 01:24:11 PM PST 23
Finished Dec 27 01:24:12 PM PST 23
Peak memory 194668 kb
Host smart-c3576d19-7cd1-4389-827f-e8ed7e5921a6
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=767266549 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_full_random.767266549
Directory /workspace/49.gpio_full_random/latest

Test location /workspace/coverage/default/49.gpio_intr_rand_pgm.793752674
Short name T311
Test name
Test status
Simulation time 25031042 ps
CPU time 0.81 seconds
Started Dec 27 01:24:47 PM PST 23
Finished Dec 27 01:24:51 PM PST 23
Peak memory 195452 kb
Host smart-35719a16-91a5-4c5f-a5d2-cf5206eb9fc2
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=793752674 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_intr_rand_pgm.793752674
Directory /workspace/49.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/49.gpio_intr_with_filter_rand_intr_event.1605039627
Short name T63
Test name
Test status
Simulation time 386075056 ps
CPU time 2.76 seconds
Started Dec 27 01:24:18 PM PST 23
Finished Dec 27 01:24:22 PM PST 23
Peak memory 196596 kb
Host smart-2b084229-9938-41d2-98c1-478cfadf4172
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1605039627 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 49.gpio_intr_with_filter_rand_intr_event.1605039627
Directory /workspace/49.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/49.gpio_rand_intr_trigger.3706330460
Short name T756
Test name
Test status
Simulation time 71346734 ps
CPU time 1.72 seconds
Started Dec 27 01:24:18 PM PST 23
Finished Dec 27 01:24:21 PM PST 23
Peak memory 196796 kb
Host smart-d8864375-9237-4679-83ae-a9a0f086f24a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3706330460 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_rand_intr_trigger
.3706330460
Directory /workspace/49.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/49.gpio_random_dout_din.3058656134
Short name T226
Test name
Test status
Simulation time 100975216 ps
CPU time 0.76 seconds
Started Dec 27 01:25:37 PM PST 23
Finished Dec 27 01:25:38 PM PST 23
Peak memory 196216 kb
Host smart-a9453e87-3b9d-40c7-8a4b-0b95d6cbb76d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3058656134 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_random_dout_din.3058656134
Directory /workspace/49.gpio_random_dout_din/latest

Test location /workspace/coverage/default/49.gpio_random_dout_din_no_pullup_pulldown.3633566190
Short name T294
Test name
Test status
Simulation time 34188097 ps
CPU time 0.82 seconds
Started Dec 27 01:25:50 PM PST 23
Finished Dec 27 01:25:52 PM PST 23
Peak memory 195944 kb
Host smart-13f3fdfd-acb0-4e3d-8e14-d88c5ad1e67d
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3633566190 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_random_dout_din_no_pullu
p_pulldown.3633566190
Directory /workspace/49.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/49.gpio_random_long_reg_writes_reg_reads.289401991
Short name T724
Test name
Test status
Simulation time 1768151382 ps
CPU time 4.83 seconds
Started Dec 27 01:24:17 PM PST 23
Finished Dec 27 01:24:22 PM PST 23
Peak memory 198028 kb
Host smart-616c4658-ecf3-4be9-8ef6-9bb20873443d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=289401991 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_ran
dom_long_reg_writes_reg_reads.289401991
Directory /workspace/49.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/49.gpio_smoke.2103289672
Short name T702
Test name
Test status
Simulation time 54647270 ps
CPU time 1.41 seconds
Started Dec 27 01:25:48 PM PST 23
Finished Dec 27 01:25:50 PM PST 23
Peak memory 195688 kb
Host smart-19adc4ab-ef86-4ebf-a7e7-820127335edf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2103289672 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_smoke.2103289672
Directory /workspace/49.gpio_smoke/latest

Test location /workspace/coverage/default/49.gpio_smoke_no_pullup_pulldown.2903260546
Short name T849
Test name
Test status
Simulation time 57809882 ps
CPU time 0.96 seconds
Started Dec 27 01:25:08 PM PST 23
Finished Dec 27 01:25:12 PM PST 23
Peak memory 195876 kb
Host smart-eb491438-4818-4a1d-bd7e-9beb09ef11c7
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2903260546 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_smoke_no_pullup_pulldown.2903260546
Directory /workspace/49.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/49.gpio_stress_all.3099727602
Short name T662
Test name
Test status
Simulation time 942993768 ps
CPU time 24.81 seconds
Started Dec 27 01:24:19 PM PST 23
Finished Dec 27 01:24:46 PM PST 23
Peak memory 198072 kb
Host smart-258b338f-d03e-43d4-8bc3-9c47f2f2d220
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3099727602 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.
gpio_stress_all.3099727602
Directory /workspace/49.gpio_stress_all/latest

Test location /workspace/coverage/default/49.gpio_stress_all_with_rand_reset.2914389036
Short name T663
Test name
Test status
Simulation time 123437994353 ps
CPU time 368.44 seconds
Started Dec 27 01:24:09 PM PST 23
Finished Dec 27 01:30:18 PM PST 23
Peak memory 198428 kb
Host smart-ee300b5b-426a-4448-8227-d686fb41c001
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=2914389036 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.gpio_stress_all_with_rand_reset.2914389036
Directory /workspace/49.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/5.gpio_alert_test.4252366801
Short name T736
Test name
Test status
Simulation time 17462421 ps
CPU time 0.61 seconds
Started Dec 27 01:22:04 PM PST 23
Finished Dec 27 01:22:05 PM PST 23
Peak memory 194068 kb
Host smart-64f01e12-082e-49d9-8cd2-532b3e8b87c7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4252366801 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_alert_test.4252366801
Directory /workspace/5.gpio_alert_test/latest

Test location /workspace/coverage/default/5.gpio_dout_din_regs_random_rw.3063132281
Short name T522
Test name
Test status
Simulation time 65359170 ps
CPU time 0.86 seconds
Started Dec 27 01:21:20 PM PST 23
Finished Dec 27 01:21:22 PM PST 23
Peak memory 196152 kb
Host smart-a2a67071-8169-4205-a620-d44f43670c45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3063132281 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_dout_din_regs_random_rw.3063132281
Directory /workspace/5.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/5.gpio_filter_stress.2556750360
Short name T386
Test name
Test status
Simulation time 191237406 ps
CPU time 5.56 seconds
Started Dec 27 01:21:58 PM PST 23
Finished Dec 27 01:22:04 PM PST 23
Peak memory 195596 kb
Host smart-91bca082-9c6d-4b1e-a2e2-124446f9de68
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2556750360 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_filter_stres
s.2556750360
Directory /workspace/5.gpio_filter_stress/latest

Test location /workspace/coverage/default/5.gpio_full_random.1086701155
Short name T817
Test name
Test status
Simulation time 154504061 ps
CPU time 1.04 seconds
Started Dec 27 01:22:00 PM PST 23
Finished Dec 27 01:22:01 PM PST 23
Peak memory 196664 kb
Host smart-85655ec1-2045-4170-9137-e13a06604113
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1086701155 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_full_random.1086701155
Directory /workspace/5.gpio_full_random/latest

Test location /workspace/coverage/default/5.gpio_intr_rand_pgm.1267092272
Short name T298
Test name
Test status
Simulation time 187574373 ps
CPU time 1.41 seconds
Started Dec 27 01:21:14 PM PST 23
Finished Dec 27 01:21:16 PM PST 23
Peak memory 198156 kb
Host smart-35fa27c4-cddd-4cd2-84c6-67baadb220ff
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1267092272 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_intr_rand_pgm.1267092272
Directory /workspace/5.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/5.gpio_intr_with_filter_rand_intr_event.2004931145
Short name T811
Test name
Test status
Simulation time 326189887 ps
CPU time 3.29 seconds
Started Dec 27 01:21:17 PM PST 23
Finished Dec 27 01:21:21 PM PST 23
Peak memory 198100 kb
Host smart-343e59ee-99f6-4d4f-a180-11b05f12a60b
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2004931145 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 5.gpio_intr_with_filter_rand_intr_event.2004931145
Directory /workspace/5.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/5.gpio_rand_intr_trigger.2572442998
Short name T789
Test name
Test status
Simulation time 108880067 ps
CPU time 1.38 seconds
Started Dec 27 01:21:17 PM PST 23
Finished Dec 27 01:21:19 PM PST 23
Peak memory 196824 kb
Host smart-8e3cccdf-3e96-47da-8d97-800857b886cb
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2572442998 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_rand_intr_trigger.
2572442998
Directory /workspace/5.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/5.gpio_random_dout_din.1223770500
Short name T643
Test name
Test status
Simulation time 35720766 ps
CPU time 0.92 seconds
Started Dec 27 01:21:49 PM PST 23
Finished Dec 27 01:21:51 PM PST 23
Peak memory 196724 kb
Host smart-5743ef54-f0d3-430a-a7e3-fcab61689245
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1223770500 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_random_dout_din.1223770500
Directory /workspace/5.gpio_random_dout_din/latest

Test location /workspace/coverage/default/5.gpio_random_dout_din_no_pullup_pulldown.3364265369
Short name T748
Test name
Test status
Simulation time 109738880 ps
CPU time 1.13 seconds
Started Dec 27 01:21:13 PM PST 23
Finished Dec 27 01:21:14 PM PST 23
Peak memory 196896 kb
Host smart-3fc72132-0dfd-4e29-80fe-763eaea829a4
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3364265369 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_random_dout_din_no_pullup
_pulldown.3364265369
Directory /workspace/5.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/5.gpio_random_long_reg_writes_reg_reads.1793248552
Short name T343
Test name
Test status
Simulation time 2860986191 ps
CPU time 6.62 seconds
Started Dec 27 01:21:17 PM PST 23
Finished Dec 27 01:21:24 PM PST 23
Peak memory 198108 kb
Host smart-dd3314af-e125-49e5-a858-eb4e538c805f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1793248552 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_ran
dom_long_reg_writes_reg_reads.1793248552
Directory /workspace/5.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/5.gpio_smoke.2232522604
Short name T526
Test name
Test status
Simulation time 235566219 ps
CPU time 1.23 seconds
Started Dec 27 01:22:30 PM PST 23
Finished Dec 27 01:22:36 PM PST 23
Peak memory 196600 kb
Host smart-f62ceb07-6a15-4e8e-a84c-3b088fad7234
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2232522604 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_smoke.2232522604
Directory /workspace/5.gpio_smoke/latest

Test location /workspace/coverage/default/5.gpio_smoke_no_pullup_pulldown.3789993713
Short name T514
Test name
Test status
Simulation time 58938917 ps
CPU time 0.85 seconds
Started Dec 27 01:21:52 PM PST 23
Finished Dec 27 01:21:53 PM PST 23
Peak memory 196468 kb
Host smart-6909d080-eb25-49c4-9dfa-8c0ce6e6eb4f
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3789993713 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_smoke_no_pullup_pulldown.3789993713
Directory /workspace/5.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/5.gpio_stress_all.1090784394
Short name T477
Test name
Test status
Simulation time 63419417275 ps
CPU time 134.4 seconds
Started Dec 27 01:22:01 PM PST 23
Finished Dec 27 01:24:16 PM PST 23
Peak memory 198220 kb
Host smart-da815c56-fb90-4b45-aa79-96c819dff08d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1090784394 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.g
pio_stress_all.1090784394
Directory /workspace/5.gpio_stress_all/latest

Test location /workspace/coverage/default/5.gpio_stress_all_with_rand_reset.530854844
Short name T458
Test name
Test status
Simulation time 260036317104 ps
CPU time 1925.15 seconds
Started Dec 27 01:22:01 PM PST 23
Finished Dec 27 01:54:07 PM PST 23
Peak memory 198396 kb
Host smart-2bfe3eb0-eebd-4130-96df-7fa72f858442
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=530854844 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.gpio_stress_all_with_rand_reset.530854844
Directory /workspace/5.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/6.gpio_alert_test.1939103149
Short name T50
Test name
Test status
Simulation time 28024590 ps
CPU time 0.6 seconds
Started Dec 27 01:21:55 PM PST 23
Finished Dec 27 01:21:57 PM PST 23
Peak memory 194960 kb
Host smart-9c763242-01fe-49cd-baeb-c4f191c8d0d5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1939103149 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_alert_test.1939103149
Directory /workspace/6.gpio_alert_test/latest

Test location /workspace/coverage/default/6.gpio_dout_din_regs_random_rw.3300593126
Short name T575
Test name
Test status
Simulation time 39224139 ps
CPU time 0.86 seconds
Started Dec 27 01:21:16 PM PST 23
Finished Dec 27 01:21:17 PM PST 23
Peak memory 196524 kb
Host smart-dec23c52-b6d0-422a-8dda-93181af826e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3300593126 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_dout_din_regs_random_rw.3300593126
Directory /workspace/6.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/6.gpio_filter_stress.301841557
Short name T607
Test name
Test status
Simulation time 179992270 ps
CPU time 9.4 seconds
Started Dec 27 01:21:51 PM PST 23
Finished Dec 27 01:22:01 PM PST 23
Peak memory 197064 kb
Host smart-dab3e973-aa6d-4261-8ae0-9ebf0c925023
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=301841557 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_filter_stress
.301841557
Directory /workspace/6.gpio_filter_stress/latest

Test location /workspace/coverage/default/6.gpio_full_random.2757317921
Short name T219
Test name
Test status
Simulation time 19062015 ps
CPU time 0.69 seconds
Started Dec 27 01:21:53 PM PST 23
Finished Dec 27 01:21:55 PM PST 23
Peak memory 194320 kb
Host smart-73aee747-605b-4d96-b805-124d5778f8e8
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2757317921 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_full_random.2757317921
Directory /workspace/6.gpio_full_random/latest

Test location /workspace/coverage/default/6.gpio_intr_rand_pgm.1920177804
Short name T519
Test name
Test status
Simulation time 172702027 ps
CPU time 1.16 seconds
Started Dec 27 01:21:31 PM PST 23
Finished Dec 27 01:21:32 PM PST 23
Peak memory 197012 kb
Host smart-f4ae27b2-862e-4740-b0a0-223ebf89c58e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1920177804 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_intr_rand_pgm.1920177804
Directory /workspace/6.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/6.gpio_intr_with_filter_rand_intr_event.1199605084
Short name T234
Test name
Test status
Simulation time 161632829 ps
CPU time 3.3 seconds
Started Dec 27 01:22:08 PM PST 23
Finished Dec 27 01:22:16 PM PST 23
Peak memory 196444 kb
Host smart-5a0346d8-6757-41a9-8abb-1bf9a7dc4d01
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1199605084 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 6.gpio_intr_with_filter_rand_intr_event.1199605084
Directory /workspace/6.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/6.gpio_rand_intr_trigger.146296119
Short name T454
Test name
Test status
Simulation time 87872025 ps
CPU time 1.95 seconds
Started Dec 27 01:22:02 PM PST 23
Finished Dec 27 01:22:05 PM PST 23
Peak memory 196332 kb
Host smart-56c2548c-e688-414b-a178-7e9efc712b4f
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=146296119 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_rand_intr_trigger.146296119
Directory /workspace/6.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/6.gpio_random_dout_din.3366683014
Short name T866
Test name
Test status
Simulation time 166349863 ps
CPU time 1.12 seconds
Started Dec 27 01:22:01 PM PST 23
Finished Dec 27 01:22:03 PM PST 23
Peak memory 196168 kb
Host smart-4a32db11-3bb2-4635-a0b8-fe83c55982f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3366683014 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_random_dout_din.3366683014
Directory /workspace/6.gpio_random_dout_din/latest

Test location /workspace/coverage/default/6.gpio_random_dout_din_no_pullup_pulldown.366081527
Short name T424
Test name
Test status
Simulation time 48701431 ps
CPU time 0.94 seconds
Started Dec 27 01:21:56 PM PST 23
Finished Dec 27 01:21:58 PM PST 23
Peak memory 196036 kb
Host smart-dea8656c-85de-4a64-b045-b47bd1ed4fb0
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=366081527 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_random_dout_din_no_pullup_
pulldown.366081527
Directory /workspace/6.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/6.gpio_random_long_reg_writes_reg_reads.403673785
Short name T350
Test name
Test status
Simulation time 475042654 ps
CPU time 3.65 seconds
Started Dec 27 01:21:54 PM PST 23
Finished Dec 27 01:21:58 PM PST 23
Peak memory 198056 kb
Host smart-5c5d660b-5be6-4551-8e37-4baece92ac9d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=403673785 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg_
writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_rand
om_long_reg_writes_reg_reads.403673785
Directory /workspace/6.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/6.gpio_smoke.3181744933
Short name T692
Test name
Test status
Simulation time 69855593 ps
CPU time 1.21 seconds
Started Dec 27 01:21:58 PM PST 23
Finished Dec 27 01:22:00 PM PST 23
Peak memory 195952 kb
Host smart-1e7305e0-57e7-4db1-bbfc-9c62b76f1654
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3181744933 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_smoke.3181744933
Directory /workspace/6.gpio_smoke/latest

Test location /workspace/coverage/default/6.gpio_smoke_no_pullup_pulldown.1818552442
Short name T340
Test name
Test status
Simulation time 87517298 ps
CPU time 1.31 seconds
Started Dec 27 01:21:56 PM PST 23
Finished Dec 27 01:21:58 PM PST 23
Peak memory 197060 kb
Host smart-1af3568a-c9af-4e63-b563-7e5bcf5d0194
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1818552442 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_smoke_no_pullup_pulldown.1818552442
Directory /workspace/6.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/6.gpio_stress_all.2012543435
Short name T613
Test name
Test status
Simulation time 11188122620 ps
CPU time 159.26 seconds
Started Dec 27 01:22:06 PM PST 23
Finished Dec 27 01:24:47 PM PST 23
Peak memory 198256 kb
Host smart-f7a29179-b9e7-4917-a948-1f264fb59785
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2012543435 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.g
pio_stress_all.2012543435
Directory /workspace/6.gpio_stress_all/latest

Test location /workspace/coverage/default/6.gpio_stress_all_with_rand_reset.1343653681
Short name T329
Test name
Test status
Simulation time 1183402592765 ps
CPU time 1661.2 seconds
Started Dec 27 01:21:54 PM PST 23
Finished Dec 27 01:49:37 PM PST 23
Peak memory 198408 kb
Host smart-cfbcafd2-d00f-484e-a3ac-57203767d266
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=1343653681 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.gpio_stress_all_with_rand_reset.1343653681
Directory /workspace/6.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/7.gpio_alert_test.3278412505
Short name T735
Test name
Test status
Simulation time 12977303 ps
CPU time 0.58 seconds
Started Dec 27 01:22:24 PM PST 23
Finished Dec 27 01:22:25 PM PST 23
Peak memory 194152 kb
Host smart-61d39a49-ec25-4376-a64a-a4dd12ef87f0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3278412505 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_alert_test.3278412505
Directory /workspace/7.gpio_alert_test/latest

Test location /workspace/coverage/default/7.gpio_dout_din_regs_random_rw.2945251730
Short name T471
Test name
Test status
Simulation time 112294780 ps
CPU time 0.72 seconds
Started Dec 27 01:21:55 PM PST 23
Finished Dec 27 01:21:56 PM PST 23
Peak memory 195260 kb
Host smart-47026fb4-d60a-4edd-97de-27dc4f36367a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2945251730 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_dout_din_regs_random_rw.2945251730
Directory /workspace/7.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/7.gpio_filter_stress.480767190
Short name T444
Test name
Test status
Simulation time 5464802839 ps
CPU time 27 seconds
Started Dec 27 01:21:56 PM PST 23
Finished Dec 27 01:22:24 PM PST 23
Peak memory 198232 kb
Host smart-13a9e78c-7631-418a-b220-c378338a9d75
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=480767190 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filter
_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_filter_stress
.480767190
Directory /workspace/7.gpio_filter_stress/latest

Test location /workspace/coverage/default/7.gpio_full_random.3873725825
Short name T856
Test name
Test status
Simulation time 94902578 ps
CPU time 0.89 seconds
Started Dec 27 01:22:09 PM PST 23
Finished Dec 27 01:22:17 PM PST 23
Peak memory 196116 kb
Host smart-3044f79a-cef4-40aa-a222-d9d1d6c7174d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3873725825 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_full_random.3873725825
Directory /workspace/7.gpio_full_random/latest

Test location /workspace/coverage/default/7.gpio_intr_rand_pgm.815165786
Short name T784
Test name
Test status
Simulation time 129150190 ps
CPU time 1.06 seconds
Started Dec 27 01:22:06 PM PST 23
Finished Dec 27 01:22:08 PM PST 23
Peak memory 196004 kb
Host smart-fbaf4742-3d68-4816-85f5-13def0504da8
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=815165786 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_intr_rand_pgm.815165786
Directory /workspace/7.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/7.gpio_intr_with_filter_rand_intr_event.2679687957
Short name T437
Test name
Test status
Simulation time 250517176 ps
CPU time 1.45 seconds
Started Dec 27 01:21:52 PM PST 23
Finished Dec 27 01:21:54 PM PST 23
Peak memory 197012 kb
Host smart-a607a388-ea0b-49d2-b3aa-268dbdce9120
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2679687957 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST
_SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 7.gpio_intr_with_filter_rand_intr_event.2679687957
Directory /workspace/7.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/7.gpio_rand_intr_trigger.300289324
Short name T851
Test name
Test status
Simulation time 70481916 ps
CPU time 1.45 seconds
Started Dec 27 01:21:49 PM PST 23
Finished Dec 27 01:21:51 PM PST 23
Peak memory 196084 kb
Host smart-97c8f1dc-c13a-4fdf-8e13-d0faec1b0dd4
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=300289324 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigge
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_rand_intr_trigger.300289324
Directory /workspace/7.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/7.gpio_random_dout_din.3678192724
Short name T265
Test name
Test status
Simulation time 22202996 ps
CPU time 0.92 seconds
Started Dec 27 01:22:04 PM PST 23
Finished Dec 27 01:22:13 PM PST 23
Peak memory 196664 kb
Host smart-9d47e990-af8d-4fc2-9583-cc4930e5334f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3678192724 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_random_dout_din.3678192724
Directory /workspace/7.gpio_random_dout_din/latest

Test location /workspace/coverage/default/7.gpio_random_dout_din_no_pullup_pulldown.2809579004
Short name T587
Test name
Test status
Simulation time 94631111 ps
CPU time 1.11 seconds
Started Dec 27 01:22:06 PM PST 23
Finished Dec 27 01:22:08 PM PST 23
Peak memory 196928 kb
Host smart-9d798d1e-706e-4711-bba3-6831719918a0
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2809579004 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_random_dout_din_no_pullup
_pulldown.2809579004
Directory /workspace/7.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/7.gpio_random_long_reg_writes_reg_reads.2847349173
Short name T889
Test name
Test status
Simulation time 487434701 ps
CPU time 2.76 seconds
Started Dec 27 01:22:11 PM PST 23
Finished Dec 27 01:22:15 PM PST 23
Peak memory 198040 kb
Host smart-8723aa1f-5fa9-41bd-9300-dfc79f1323fa
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2847349173 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_ran
dom_long_reg_writes_reg_reads.2847349173
Directory /workspace/7.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/7.gpio_smoke.1549484499
Short name T680
Test name
Test status
Simulation time 30935454 ps
CPU time 0.96 seconds
Started Dec 27 01:22:03 PM PST 23
Finished Dec 27 01:22:05 PM PST 23
Peak memory 195856 kb
Host smart-012547c7-2471-486c-957d-1a705de29391
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1549484499 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_smoke.1549484499
Directory /workspace/7.gpio_smoke/latest

Test location /workspace/coverage/default/7.gpio_smoke_no_pullup_pulldown.2369447997
Short name T815
Test name
Test status
Simulation time 116473432 ps
CPU time 0.82 seconds
Started Dec 27 01:21:31 PM PST 23
Finished Dec 27 01:21:33 PM PST 23
Peak memory 196068 kb
Host smart-6e3841c1-f369-4147-ba3a-e1f86e5b7139
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2369447997 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_smoke_no_pullup_pulldown.2369447997
Directory /workspace/7.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/7.gpio_stress_all.4093104177
Short name T250
Test name
Test status
Simulation time 8851205245 ps
CPU time 54.8 seconds
Started Dec 27 01:22:15 PM PST 23
Finished Dec 27 01:23:11 PM PST 23
Peak memory 198244 kb
Host smart-41d0b895-5fa3-4591-ae8d-f78c4d618f52
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4093104177 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.g
pio_stress_all.4093104177
Directory /workspace/7.gpio_stress_all/latest

Test location /workspace/coverage/default/7.gpio_stress_all_with_rand_reset.795251240
Short name T487
Test name
Test status
Simulation time 85194051546 ps
CPU time 2082.62 seconds
Started Dec 27 01:22:11 PM PST 23
Finished Dec 27 01:56:55 PM PST 23
Peak memory 198388 kb
Host smart-a8728279-107c-4113-b3c0-2d15e6e774cb
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=795251240 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.gpio_stress_all_with_rand_reset.795251240
Directory /workspace/7.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/8.gpio_alert_test.1518047208
Short name T649
Test name
Test status
Simulation time 14699677 ps
CPU time 0.58 seconds
Started Dec 27 01:22:09 PM PST 23
Finished Dec 27 01:22:13 PM PST 23
Peak memory 194180 kb
Host smart-335dd0c8-91d0-4f7e-b7fb-bcbd0566a22c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1518047208 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_alert_test.1518047208
Directory /workspace/8.gpio_alert_test/latest

Test location /workspace/coverage/default/8.gpio_dout_din_regs_random_rw.1207123919
Short name T231
Test name
Test status
Simulation time 114256903 ps
CPU time 0.88 seconds
Started Dec 27 01:22:49 PM PST 23
Finished Dec 27 01:22:51 PM PST 23
Peak memory 195316 kb
Host smart-c37beff3-2a9b-4121-9afe-1d03c1289ff3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1207123919 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_dout_din_regs_random_rw.1207123919
Directory /workspace/8.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/8.gpio_filter_stress.1980290934
Short name T825
Test name
Test status
Simulation time 437423036 ps
CPU time 22.31 seconds
Started Dec 27 01:21:50 PM PST 23
Finished Dec 27 01:22:13 PM PST 23
Peak memory 198180 kb
Host smart-6ec69dc8-e38f-4f0d-8e3b-48f369f2e0c9
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1980290934 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_filter_stres
s.1980290934
Directory /workspace/8.gpio_filter_stress/latest

Test location /workspace/coverage/default/8.gpio_full_random.1539179494
Short name T498
Test name
Test status
Simulation time 71427642 ps
CPU time 0.62 seconds
Started Dec 27 01:21:51 PM PST 23
Finished Dec 27 01:21:52 PM PST 23
Peak memory 194604 kb
Host smart-17c2f5f9-1b4e-4de0-b23c-90e4fd364387
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1539179494 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_full_random.1539179494
Directory /workspace/8.gpio_full_random/latest

Test location /workspace/coverage/default/8.gpio_intr_rand_pgm.2268828530
Short name T630
Test name
Test status
Simulation time 142233125 ps
CPU time 0.8 seconds
Started Dec 27 01:22:54 PM PST 23
Finished Dec 27 01:22:56 PM PST 23
Peak memory 195480 kb
Host smart-0fd46295-20f2-4151-84cc-e6b105be3854
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2268828530 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_intr_rand_pgm.2268828530
Directory /workspace/8.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/8.gpio_intr_with_filter_rand_intr_event.505568030
Short name T778
Test name
Test status
Simulation time 75613802 ps
CPU time 1.41 seconds
Started Dec 27 01:23:19 PM PST 23
Finished Dec 27 01:23:21 PM PST 23
Peak memory 196400 kb
Host smart-b14754bf-df64-4eb9-a07f-adb1f1da9876
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=505568030 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 8.gpio_intr_with_filter_rand_intr_event.505568030
Directory /workspace/8.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/8.gpio_rand_intr_trigger.1759635581
Short name T399
Test name
Test status
Simulation time 42134587 ps
CPU time 1.4 seconds
Started Dec 27 01:22:58 PM PST 23
Finished Dec 27 01:23:00 PM PST 23
Peak memory 196080 kb
Host smart-372b587a-579e-4132-8158-812666395ebe
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1759635581 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_rand_intr_trigger.
1759635581
Directory /workspace/8.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/8.gpio_random_dout_din.2384049898
Short name T440
Test name
Test status
Simulation time 54280936 ps
CPU time 1.08 seconds
Started Dec 27 01:22:28 PM PST 23
Finished Dec 27 01:22:30 PM PST 23
Peak memory 196032 kb
Host smart-b7accb20-9308-4d77-8595-19cfd1cfcb20
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2384049898 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_random_dout_din.2384049898
Directory /workspace/8.gpio_random_dout_din/latest

Test location /workspace/coverage/default/8.gpio_random_dout_din_no_pullup_pulldown.1415201589
Short name T871
Test name
Test status
Simulation time 26060257 ps
CPU time 0.84 seconds
Started Dec 27 01:22:30 PM PST 23
Finished Dec 27 01:22:36 PM PST 23
Peak memory 195460 kb
Host smart-e8d54bbe-2b99-4c8d-bec9-3b196ac92432
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1415201589 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_random_dout_din_no_pullup
_pulldown.1415201589
Directory /workspace/8.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/8.gpio_random_long_reg_writes_reg_reads.3512499394
Short name T316
Test name
Test status
Simulation time 140482823 ps
CPU time 1.05 seconds
Started Dec 27 01:22:07 PM PST 23
Finished Dec 27 01:22:13 PM PST 23
Peak memory 196380 kb
Host smart-cf21531c-25cc-4b01-84ed-d020af52b1c1
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3512499394 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_ran
dom_long_reg_writes_reg_reads.3512499394
Directory /workspace/8.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/8.gpio_smoke.2519961834
Short name T324
Test name
Test status
Simulation time 85551241 ps
CPU time 1.02 seconds
Started Dec 27 01:22:24 PM PST 23
Finished Dec 27 01:22:26 PM PST 23
Peak memory 195888 kb
Host smart-2340972e-4ceb-4f7d-8703-6e16ff9f41d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2519961834 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_smoke.2519961834
Directory /workspace/8.gpio_smoke/latest

Test location /workspace/coverage/default/8.gpio_smoke_no_pullup_pulldown.791560986
Short name T774
Test name
Test status
Simulation time 139468394 ps
CPU time 1.19 seconds
Started Dec 27 01:22:26 PM PST 23
Finished Dec 27 01:22:29 PM PST 23
Peak memory 196308 kb
Host smart-c867fa6d-7d0c-43cb-a29d-57a864d8fa94
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=791560986 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_smoke_no_pullup_pulldown.791560986
Directory /workspace/8.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/8.gpio_stress_all.4283421424
Short name T262
Test name
Test status
Simulation time 31004624748 ps
CPU time 146.44 seconds
Started Dec 27 01:21:54 PM PST 23
Finished Dec 27 01:24:21 PM PST 23
Peak memory 198288 kb
Host smart-be7576f8-77ae-46d0-a45d-9c90ebeb667d
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4283421424 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_
TEST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.g
pio_stress_all.4283421424
Directory /workspace/8.gpio_stress_all/latest

Test location /workspace/coverage/default/8.gpio_stress_all_with_rand_reset.252382658
Short name T548
Test name
Test status
Simulation time 500238402424 ps
CPU time 694.18 seconds
Started Dec 27 01:22:14 PM PST 23
Finished Dec 27 01:33:50 PM PST 23
Peak memory 198340 kb
Host smart-a5a8d8a7-87a3-4e82-8837-90485b1a84b3
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=252382658 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.gpio_stress_all_with_rand_reset.252382658
Directory /workspace/8.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/9.gpio_alert_test.3276905772
Short name T523
Test name
Test status
Simulation time 12272695 ps
CPU time 0.61 seconds
Started Dec 27 01:21:53 PM PST 23
Finished Dec 27 01:21:54 PM PST 23
Peak memory 193972 kb
Host smart-40a905ac-0755-4404-93dc-559401e30bed
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3276905772 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_alert_test.3276905772
Directory /workspace/9.gpio_alert_test/latest

Test location /workspace/coverage/default/9.gpio_dout_din_regs_random_rw.2924714662
Short name T393
Test name
Test status
Simulation time 26118183 ps
CPU time 0.87 seconds
Started Dec 27 01:21:53 PM PST 23
Finished Dec 27 01:21:55 PM PST 23
Peak memory 195500 kb
Host smart-7f83c42f-04f2-4f0d-b6f8-e974549882b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2924714662 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_dout_din_regs_random_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_dout_din_regs_random_rw.2924714662
Directory /workspace/9.gpio_dout_din_regs_random_rw/latest

Test location /workspace/coverage/default/9.gpio_filter_stress.3019906809
Short name T637
Test name
Test status
Simulation time 2877929564 ps
CPU time 18.27 seconds
Started Dec 27 01:22:07 PM PST 23
Finished Dec 27 01:22:30 PM PST 23
Peak memory 196952 kb
Host smart-fb23cac7-7c53-44c4-a517-72b3205a40dc
User root
Command /workspace/default/simv +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3019906809 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_filte
r_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_filter_stres
s.3019906809
Directory /workspace/9.gpio_filter_stress/latest

Test location /workspace/coverage/default/9.gpio_full_random.1799242285
Short name T884
Test name
Test status
Simulation time 191227948 ps
CPU time 0.8 seconds
Started Dec 27 01:22:05 PM PST 23
Finished Dec 27 01:22:06 PM PST 23
Peak memory 195984 kb
Host smart-6ffa33b4-236c-4d0f-977b-87b5b126ae41
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1799242285 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_full_random_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_full_random.1799242285
Directory /workspace/9.gpio_full_random/latest

Test location /workspace/coverage/default/9.gpio_intr_rand_pgm.1784465750
Short name T671
Test name
Test status
Simulation time 34156190 ps
CPU time 0.93 seconds
Started Dec 27 01:21:52 PM PST 23
Finished Dec 27 01:21:54 PM PST 23
Peak memory 195884 kb
Host smart-497f4553-7029-4f11-989c-f303e9c72071
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1784465750 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_intr_rand_pgm_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_intr_rand_pgm.1784465750
Directory /workspace/9.gpio_intr_rand_pgm/latest

Test location /workspace/coverage/default/9.gpio_intr_with_filter_rand_intr_event.728554719
Short name T236
Test name
Test status
Simulation time 40400182 ps
CPU time 1.08 seconds
Started Dec 27 01:22:06 PM PST 23
Finished Dec 27 01:22:08 PM PST 23
Peak memory 196460 kb
Host smart-c2386893-ad07-4d96-938d-5cf03cafd1b9
User root
Command /workspace/default/simv +en_scb=0 +zero_delays=1 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -li
cqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=728554719 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_
SEQ=gpio_intr_with_filter_rand_intr_event_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 9.gpio_intr_with_filter_rand_intr_event.728554719
Directory /workspace/9.gpio_intr_with_filter_rand_intr_event/latest

Test location /workspace/coverage/default/9.gpio_rand_intr_trigger.2519246221
Short name T452
Test name
Test status
Simulation time 109398324 ps
CPU time 1.05 seconds
Started Dec 27 01:21:54 PM PST 23
Finished Dec 27 01:21:56 PM PST 23
Peak memory 195440 kb
Host smart-6212f4a6-0666-4d55-be65-9b99076901eb
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2519246221 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_rand_intr_trigg
er_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_rand_intr_trigger.
2519246221
Directory /workspace/9.gpio_rand_intr_trigger/latest

Test location /workspace/coverage/default/9.gpio_random_dout_din.973618490
Short name T822
Test name
Test status
Simulation time 73520710 ps
CPU time 0.65 seconds
Started Dec 27 01:22:06 PM PST 23
Finished Dec 27 01:22:08 PM PST 23
Peak memory 194308 kb
Host smart-bdabd3dc-63fe-4e37-8d6c-7a33dba7a994
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=973618490 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_random_dout_din.973618490
Directory /workspace/9.gpio_random_dout_din/latest

Test location /workspace/coverage/default/9.gpio_random_dout_din_no_pullup_pulldown.382107361
Short name T627
Test name
Test status
Simulation time 159113132 ps
CPU time 0.75 seconds
Started Dec 27 01:22:08 PM PST 23
Finished Dec 27 01:22:13 PM PST 23
Peak memory 195412 kb
Host smart-49937a75-d0c1-4fee-9b05-609a022e49a8
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=382107361 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_dout_din_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_random_dout_din_no_pullup_
pulldown.382107361
Directory /workspace/9.gpio_random_dout_din_no_pullup_pulldown/latest

Test location /workspace/coverage/default/9.gpio_random_long_reg_writes_reg_reads.3492821328
Short name T771
Test name
Test status
Simulation time 717242252 ps
CPU time 5.73 seconds
Started Dec 27 01:22:08 PM PST 23
Finished Dec 27 01:22:18 PM PST 23
Peak memory 198096 kb
Host smart-72b15302-14ec-470b-a649-f5a65a98c20e
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3492821328 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_random_long_reg
_writes_reg_reads_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_ran
dom_long_reg_writes_reg_reads.3492821328
Directory /workspace/9.gpio_random_long_reg_writes_reg_reads/latest

Test location /workspace/coverage/default/9.gpio_smoke.4247604144
Short name T561
Test name
Test status
Simulation time 64151501 ps
CPU time 1.32 seconds
Started Dec 27 01:22:22 PM PST 23
Finished Dec 27 01:22:25 PM PST 23
Peak memory 195540 kb
Host smart-f02bc9ab-0ab5-4476-a74f-e22e9e08726b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4247604144 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_smoke.4247604144
Directory /workspace/9.gpio_smoke/latest

Test location /workspace/coverage/default/9.gpio_smoke_no_pullup_pulldown.1559223839
Short name T660
Test name
Test status
Simulation time 379433063 ps
CPU time 1.43 seconds
Started Dec 27 01:22:09 PM PST 23
Finished Dec 27 01:22:14 PM PST 23
Peak memory 196832 kb
Host smart-b763cdc5-878a-49f1-84d3-35191a5c56c2
User root
Command /workspace/default/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn
t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1559223839 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_smoke_no_pullup_pulldown.1559223839
Directory /workspace/9.gpio_smoke_no_pullup_pulldown/latest

Test location /workspace/coverage/default/9.gpio_stress_all.387968355
Short name T69
Test name
Test status
Simulation time 17010843763 ps
CPU time 103.62 seconds
Started Dec 27 01:22:06 PM PST 23
Finished Dec 27 01:23:51 PM PST 23
Peak memory 198252 kb
Host smart-d9653738-c69e-411f-8e05-a39a956c354a
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
-licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=387968355 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_T
EST_SEQ=gpio_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gp
io_stress_all.387968355
Directory /workspace/9.gpio_stress_all/latest

Test location /workspace/coverage/default/9.gpio_stress_all_with_rand_reset.3391720423
Short name T832
Test name
Test status
Simulation time 474788783752 ps
CPU time 775.57 seconds
Started Dec 27 01:21:56 PM PST 23
Finished Dec 27 01:34:52 PM PST 23
Peak memory 198408 kb
Host smart-fa83899c-3a2c-4aaa-bfce-4db4c1394c04
User root
Command /workspace/default/simv +do_clear_all_interrupts=0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=gpio_stress_all_vseq +cdc_
instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed
=3391720423 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.gpio_stress_all_with_rand_reset.3391720423
Directory /workspace/9.gpio_stress_all_with_rand_reset/latest

Test location /workspace/coverage/en_cdc_prims/0.gpio_smoke_en_cdc_prim.2346725496
Short name T198
Test name
Test status
Simulation time 130135236 ps
CPU time 1.28 seconds
Started Dec 27 12:31:14 PM PST 23
Finished Dec 27 12:32:05 PM PST 23
Peak memory 195332 kb
Host smart-c350ae87-5ce1-485b-bfe6-23f707296e0d
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2346725496 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 0.gpio_smoke_en_cdc_prim.2346725496
Directory /workspace/0.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/0.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2312132295
Short name T137
Test name
Test status
Simulation time 61842675 ps
CPU time 0.83 seconds
Started Dec 27 12:31:40 PM PST 23
Finished Dec 27 12:32:30 PM PST 23
Peak memory 195688 kb
Host smart-3613269b-0dd8-4aac-a5e6-013eef94a852
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2312132295 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 0.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.2312132295
Directory /workspace/0.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/1.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2823819074
Short name T175
Test name
Test status
Simulation time 145746297 ps
CPU time 1.09 seconds
Started Dec 27 12:32:52 PM PST 23
Finished Dec 27 12:33:28 PM PST 23
Peak memory 197236 kb
Host smart-d0db3f3f-8f7a-41c6-b4ff-c70c741aa4d9
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2823819074 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 1.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.2823819074
Directory /workspace/1.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/10.gpio_smoke_en_cdc_prim.3441286123
Short name T132
Test name
Test status
Simulation time 113776413 ps
CPU time 1.03 seconds
Started Dec 27 12:31:19 PM PST 23
Finished Dec 27 12:32:09 PM PST 23
Peak memory 195236 kb
Host smart-b4f420b8-0708-4f62-bf4b-c0b23675633b
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3441286123 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 10.gpio_smoke_en_cdc_prim.3441286123
Directory /workspace/10.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/10.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3874010510
Short name T182
Test name
Test status
Simulation time 284499544 ps
CPU time 1.35 seconds
Started Dec 27 12:31:47 PM PST 23
Finished Dec 27 12:32:35 PM PST 23
Peak memory 196384 kb
Host smart-10110084-af2a-4f55-939b-b5fe92967a8d
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3874010510 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 10.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.3874010510
Directory /workspace/10.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/11.gpio_smoke_en_cdc_prim.1425496255
Short name T167
Test name
Test status
Simulation time 78664027 ps
CPU time 1.26 seconds
Started Dec 27 12:32:52 PM PST 23
Finished Dec 27 12:33:28 PM PST 23
Peak memory 196032 kb
Host smart-294f6817-3c2a-4588-ab5b-f6c3b4e15b74
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1425496255 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 11.gpio_smoke_en_cdc_prim.1425496255
Directory /workspace/11.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/11.gpio_smoke_no_pullup_pulldown_en_cdc_prim.301045281
Short name T131
Test name
Test status
Simulation time 77193226 ps
CPU time 0.74 seconds
Started Dec 27 12:31:28 PM PST 23
Finished Dec 27 12:32:19 PM PST 23
Peak memory 194948 kb
Host smart-054d180f-5308-4b27-ad2a-218dbbb28587
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=301045281 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 11.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.301045281
Directory /workspace/11.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/12.gpio_smoke_en_cdc_prim.3366554091
Short name T174
Test name
Test status
Simulation time 187018700 ps
CPU time 0.98 seconds
Started Dec 27 12:30:59 PM PST 23
Finished Dec 27 12:31:52 PM PST 23
Peak memory 196152 kb
Host smart-38570a6f-8d47-44b9-b3f6-af6c29859b1d
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3366554091 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 12.gpio_smoke_en_cdc_prim.3366554091
Directory /workspace/12.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/12.gpio_smoke_no_pullup_pulldown_en_cdc_prim.4127539186
Short name T138
Test name
Test status
Simulation time 85076865 ps
CPU time 1.36 seconds
Started Dec 27 12:33:42 PM PST 23
Finished Dec 27 12:33:58 PM PST 23
Peak memory 197336 kb
Host smart-66a564fc-89f6-422a-a60a-c8f4c73aed79
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4127539186 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 12.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.4127539186
Directory /workspace/12.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/13.gpio_smoke_en_cdc_prim.2316251147
Short name T133
Test name
Test status
Simulation time 81161123 ps
CPU time 0.9 seconds
Started Dec 27 12:32:52 PM PST 23
Finished Dec 27 12:33:27 PM PST 23
Peak memory 194568 kb
Host smart-f6128d93-b4b1-4476-8287-d4fc36e2bdbb
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2316251147 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 13.gpio_smoke_en_cdc_prim.2316251147
Directory /workspace/13.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/13.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3498332618
Short name T205
Test name
Test status
Simulation time 292475766 ps
CPU time 1.22 seconds
Started Dec 27 12:31:04 PM PST 23
Finished Dec 27 12:31:55 PM PST 23
Peak memory 196692 kb
Host smart-2906fc30-2777-4206-a566-0d2a00cab6cb
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3498332618 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 13.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.3498332618
Directory /workspace/13.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/14.gpio_smoke_en_cdc_prim.1289245931
Short name T195
Test name
Test status
Simulation time 71999822 ps
CPU time 0.78 seconds
Started Dec 27 12:32:01 PM PST 23
Finished Dec 27 12:32:47 PM PST 23
Peak memory 195080 kb
Host smart-b4a6bf62-d777-4946-ad2e-76be6113de9e
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1289245931 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 14.gpio_smoke_en_cdc_prim.1289245931
Directory /workspace/14.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/14.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1810697655
Short name T157
Test name
Test status
Simulation time 193810598 ps
CPU time 1.07 seconds
Started Dec 27 12:31:15 PM PST 23
Finished Dec 27 12:32:05 PM PST 23
Peak memory 195412 kb
Host smart-f8ab22ab-381b-49e7-bfff-19bed81bab1a
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1810697655 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 14.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.1810697655
Directory /workspace/14.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/15.gpio_smoke_en_cdc_prim.626737699
Short name T185
Test name
Test status
Simulation time 320951597 ps
CPU time 1.06 seconds
Started Dec 27 12:31:15 PM PST 23
Finished Dec 27 12:32:05 PM PST 23
Peak memory 196112 kb
Host smart-3c6ea100-fbb1-4955-a70c-3fccc76a6f9a
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=626737699 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 15.gpio_smoke_en_cdc_prim.626737699
Directory /workspace/15.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/15.gpio_smoke_no_pullup_pulldown_en_cdc_prim.333674153
Short name T177
Test name
Test status
Simulation time 109883585 ps
CPU time 1.15 seconds
Started Dec 27 12:31:28 PM PST 23
Finished Dec 27 12:32:20 PM PST 23
Peak memory 196100 kb
Host smart-304f7e81-c149-4f10-b3c0-c3d804081690
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=333674153 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 15.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.333674153
Directory /workspace/15.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/16.gpio_smoke_en_cdc_prim.3292933191
Short name T170
Test name
Test status
Simulation time 138771743 ps
CPU time 1.17 seconds
Started Dec 27 12:31:23 PM PST 23
Finished Dec 27 12:32:14 PM PST 23
Peak memory 196368 kb
Host smart-eb81df44-e660-4da4-b787-213c6316b55d
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3292933191 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 16.gpio_smoke_en_cdc_prim.3292933191
Directory /workspace/16.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/16.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1783202573
Short name T128
Test name
Test status
Simulation time 148122978 ps
CPU time 1.27 seconds
Started Dec 27 12:31:05 PM PST 23
Finished Dec 27 12:31:55 PM PST 23
Peak memory 197604 kb
Host smart-80a2790b-3586-424f-908f-28fcf77b0fd2
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1783202573 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 16.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.1783202573
Directory /workspace/16.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/17.gpio_smoke_en_cdc_prim.2707548399
Short name T191
Test name
Test status
Simulation time 1086204717 ps
CPU time 1.2 seconds
Started Dec 27 12:31:41 PM PST 23
Finished Dec 27 12:32:31 PM PST 23
Peak memory 196268 kb
Host smart-111ca0e2-2234-4ca2-bad5-c5919f660e4f
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2707548399 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 17.gpio_smoke_en_cdc_prim.2707548399
Directory /workspace/17.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/17.gpio_smoke_no_pullup_pulldown_en_cdc_prim.4045035652
Short name T165
Test name
Test status
Simulation time 111674231 ps
CPU time 0.96 seconds
Started Dec 27 12:31:20 PM PST 23
Finished Dec 27 12:32:10 PM PST 23
Peak memory 195380 kb
Host smart-56e1d5a6-f921-47bd-8319-5119ee8e1e38
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4045035652 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 17.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.4045035652
Directory /workspace/17.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/18.gpio_smoke_en_cdc_prim.1367719027
Short name T160
Test name
Test status
Simulation time 72433468 ps
CPU time 1.31 seconds
Started Dec 27 12:31:20 PM PST 23
Finished Dec 27 12:32:11 PM PST 23
Peak memory 196496 kb
Host smart-c45d2de2-3c7d-4cf3-bef7-61131bc75a12
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1367719027 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 18.gpio_smoke_en_cdc_prim.1367719027
Directory /workspace/18.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/18.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2259182851
Short name T213
Test name
Test status
Simulation time 136674259 ps
CPU time 0.79 seconds
Started Dec 27 12:31:15 PM PST 23
Finished Dec 27 12:32:05 PM PST 23
Peak memory 195584 kb
Host smart-a507cf55-596a-4a04-97a4-3080fa367c52
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2259182851 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 18.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2259182851
Directory /workspace/18.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/19.gpio_smoke_en_cdc_prim.4164739038
Short name T210
Test name
Test status
Simulation time 160787969 ps
CPU time 1.04 seconds
Started Dec 27 12:31:01 PM PST 23
Finished Dec 27 12:31:53 PM PST 23
Peak memory 197704 kb
Host smart-00353f88-06d4-43cd-8500-62e43bd0b747
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=4164739038 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 19.gpio_smoke_en_cdc_prim.4164739038
Directory /workspace/19.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/19.gpio_smoke_no_pullup_pulldown_en_cdc_prim.673072958
Short name T46
Test name
Test status
Simulation time 244205951 ps
CPU time 1.03 seconds
Started Dec 27 12:31:08 PM PST 23
Finished Dec 27 12:31:57 PM PST 23
Peak memory 197184 kb
Host smart-579f3f55-7d44-4821-b9af-d6e3577cf2c0
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=673072958 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 19.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.673072958
Directory /workspace/19.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/2.gpio_smoke_en_cdc_prim.390761192
Short name T172
Test name
Test status
Simulation time 68530820 ps
CPU time 0.98 seconds
Started Dec 27 12:31:13 PM PST 23
Finished Dec 27 12:32:03 PM PST 23
Peak memory 195436 kb
Host smart-87c74f02-4d3c-40a3-be54-f1051587fe82
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=390761192 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 2.gpio_smoke_en_cdc_prim.390761192
Directory /workspace/2.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/2.gpio_smoke_no_pullup_pulldown_en_cdc_prim.4190315837
Short name T148
Test name
Test status
Simulation time 39999237 ps
CPU time 0.78 seconds
Started Dec 27 12:32:15 PM PST 23
Finished Dec 27 12:32:59 PM PST 23
Peak memory 195088 kb
Host smart-84b5fa23-79ce-47ba-b3b6-4210332ae464
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4190315837 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 2.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.4190315837
Directory /workspace/2.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/20.gpio_smoke_en_cdc_prim.2584892769
Short name T204
Test name
Test status
Simulation time 68214260 ps
CPU time 1.2 seconds
Started Dec 27 12:31:38 PM PST 23
Finished Dec 27 12:32:31 PM PST 23
Peak memory 196164 kb
Host smart-88819bb6-c2b5-4f41-a49e-496934fa05c2
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2584892769 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 20.gpio_smoke_en_cdc_prim.2584892769
Directory /workspace/20.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/20.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2121450441
Short name T146
Test name
Test status
Simulation time 93741926 ps
CPU time 1.31 seconds
Started Dec 27 12:31:18 PM PST 23
Finished Dec 27 12:32:09 PM PST 23
Peak memory 197664 kb
Host smart-7b77f587-9d65-44bc-a576-69d7605629e2
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2121450441 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 20.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2121450441
Directory /workspace/20.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/21.gpio_smoke_en_cdc_prim.3395871925
Short name T102
Test name
Test status
Simulation time 75180765 ps
CPU time 0.98 seconds
Started Dec 27 12:31:16 PM PST 23
Finished Dec 27 12:32:06 PM PST 23
Peak memory 196216 kb
Host smart-68acf263-8270-434b-bcf3-6add0a32e3fc
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3395871925 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 21.gpio_smoke_en_cdc_prim.3395871925
Directory /workspace/21.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/21.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3480559816
Short name T130
Test name
Test status
Simulation time 39014773 ps
CPU time 0.93 seconds
Started Dec 27 12:31:12 PM PST 23
Finished Dec 27 12:32:01 PM PST 23
Peak memory 196140 kb
Host smart-61fab4b4-0f9c-4a59-9a9e-915353314572
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3480559816 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 21.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.3480559816
Directory /workspace/21.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/22.gpio_smoke_en_cdc_prim.436679842
Short name T135
Test name
Test status
Simulation time 36942647 ps
CPU time 0.81 seconds
Started Dec 27 12:31:54 PM PST 23
Finished Dec 27 12:32:40 PM PST 23
Peak memory 194992 kb
Host smart-6380587b-baa5-44d8-ae84-ef37e04cc2ab
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=436679842 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 22.gpio_smoke_en_cdc_prim.436679842
Directory /workspace/22.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/22.gpio_smoke_no_pullup_pulldown_en_cdc_prim.905418303
Short name T196
Test name
Test status
Simulation time 74610943 ps
CPU time 1.35 seconds
Started Dec 27 12:31:24 PM PST 23
Finished Dec 27 12:32:15 PM PST 23
Peak memory 197668 kb
Host smart-bbded2c7-54ff-4382-a965-e8ace0574138
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=905418303 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 22.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.905418303
Directory /workspace/22.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/23.gpio_smoke_en_cdc_prim.1888736220
Short name T154
Test name
Test status
Simulation time 207936748 ps
CPU time 0.96 seconds
Started Dec 27 12:31:17 PM PST 23
Finished Dec 27 12:32:08 PM PST 23
Peak memory 196244 kb
Host smart-2f0755d1-3fb6-47e5-9668-ce5c31fa9ad1
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1888736220 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 23.gpio_smoke_en_cdc_prim.1888736220
Directory /workspace/23.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/23.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3897884772
Short name T178
Test name
Test status
Simulation time 59038135 ps
CPU time 1.04 seconds
Started Dec 27 12:31:27 PM PST 23
Finished Dec 27 12:32:19 PM PST 23
Peak memory 196156 kb
Host smart-dca7563d-5b27-4f45-8a3d-9f3e3cf1c97e
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3897884772 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 23.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.3897884772
Directory /workspace/23.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/24.gpio_smoke_en_cdc_prim.4236697507
Short name T209
Test name
Test status
Simulation time 118991133 ps
CPU time 1.08 seconds
Started Dec 27 12:31:03 PM PST 23
Finished Dec 27 12:31:54 PM PST 23
Peak memory 197708 kb
Host smart-04cb9b97-dc5a-4eb8-ac76-e8913256783d
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=4236697507 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 24.gpio_smoke_en_cdc_prim.4236697507
Directory /workspace/24.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/25.gpio_smoke_en_cdc_prim.2270869725
Short name T150
Test name
Test status
Simulation time 45215244 ps
CPU time 1.1 seconds
Started Dec 27 12:31:18 PM PST 23
Finished Dec 27 12:32:08 PM PST 23
Peak memory 196024 kb
Host smart-4f0fc2ff-5951-4510-8114-cfb0c143ad05
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2270869725 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 25.gpio_smoke_en_cdc_prim.2270869725
Directory /workspace/25.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/25.gpio_smoke_no_pullup_pulldown_en_cdc_prim.206629868
Short name T129
Test name
Test status
Simulation time 140920521 ps
CPU time 1.02 seconds
Started Dec 27 12:31:46 PM PST 23
Finished Dec 27 12:32:35 PM PST 23
Peak memory 195444 kb
Host smart-b1fbd8e9-1909-48c0-b767-44f2fdf355d6
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=206629868 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 25.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.206629868
Directory /workspace/25.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/26.gpio_smoke_en_cdc_prim.3333185332
Short name T188
Test name
Test status
Simulation time 35871254 ps
CPU time 0.8 seconds
Started Dec 27 12:31:24 PM PST 23
Finished Dec 27 12:32:15 PM PST 23
Peak memory 194948 kb
Host smart-609b785d-6a5b-47bb-a062-718c09e715b8
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3333185332 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 26.gpio_smoke_en_cdc_prim.3333185332
Directory /workspace/26.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/26.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3062524351
Short name T181
Test name
Test status
Simulation time 74402956 ps
CPU time 1.18 seconds
Started Dec 27 12:31:54 PM PST 23
Finished Dec 27 12:32:40 PM PST 23
Peak memory 195472 kb
Host smart-e9c7830d-3d6b-4be6-9bde-3f9e978d2f0b
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3062524351 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 26.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.3062524351
Directory /workspace/26.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/27.gpio_smoke_en_cdc_prim.1997303009
Short name T168
Test name
Test status
Simulation time 304215859 ps
CPU time 0.86 seconds
Started Dec 27 12:31:51 PM PST 23
Finished Dec 27 12:32:39 PM PST 23
Peak memory 195868 kb
Host smart-50a85bb3-a001-4716-9f5e-65e9efb4d00a
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1997303009 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 27.gpio_smoke_en_cdc_prim.1997303009
Directory /workspace/27.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/27.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2765913020
Short name T166
Test name
Test status
Simulation time 150554705 ps
CPU time 0.82 seconds
Started Dec 27 12:31:06 PM PST 23
Finished Dec 27 12:31:56 PM PST 23
Peak memory 196220 kb
Host smart-2745d426-e982-461f-82fc-e739038af966
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2765913020 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 27.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2765913020
Directory /workspace/27.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/28.gpio_smoke_en_cdc_prim.4000931434
Short name T139
Test name
Test status
Simulation time 422202136 ps
CPU time 1.22 seconds
Started Dec 27 12:31:25 PM PST 23
Finished Dec 27 12:32:16 PM PST 23
Peak memory 195648 kb
Host smart-969cd1ec-b1f9-437a-8fec-30ba979161c9
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=4000931434 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 28.gpio_smoke_en_cdc_prim.4000931434
Directory /workspace/28.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/28.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2993108036
Short name T194
Test name
Test status
Simulation time 83679220 ps
CPU time 0.88 seconds
Started Dec 27 12:31:06 PM PST 23
Finished Dec 27 12:31:56 PM PST 23
Peak memory 196812 kb
Host smart-27b11827-d18a-4872-a251-9bd43b01a065
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2993108036 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 28.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2993108036
Directory /workspace/28.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/29.gpio_smoke_en_cdc_prim.3419489295
Short name T193
Test name
Test status
Simulation time 74039181 ps
CPU time 1.16 seconds
Started Dec 27 12:32:01 PM PST 23
Finished Dec 27 12:32:48 PM PST 23
Peak memory 196420 kb
Host smart-d5efb8c9-fac2-4310-a353-1221a8a34e0a
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3419489295 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 29.gpio_smoke_en_cdc_prim.3419489295
Directory /workspace/29.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/29.gpio_smoke_no_pullup_pulldown_en_cdc_prim.800330511
Short name T201
Test name
Test status
Simulation time 50305551 ps
CPU time 1.23 seconds
Started Dec 27 12:31:07 PM PST 23
Finished Dec 27 12:31:57 PM PST 23
Peak memory 197660 kb
Host smart-eb4a6df0-d17a-4cfe-907c-1f9667f8097a
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=800330511 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 29.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.800330511
Directory /workspace/29.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/3.gpio_smoke_en_cdc_prim.2206058292
Short name T214
Test name
Test status
Simulation time 34956376 ps
CPU time 0.93 seconds
Started Dec 27 12:31:14 PM PST 23
Finished Dec 27 12:32:03 PM PST 23
Peak memory 196244 kb
Host smart-0200d333-ab7e-4312-abbd-ea6e9db6cde3
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2206058292 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 3.gpio_smoke_en_cdc_prim.2206058292
Directory /workspace/3.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/3.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1019343225
Short name T144
Test name
Test status
Simulation time 113628714 ps
CPU time 1 seconds
Started Dec 27 12:31:21 PM PST 23
Finished Dec 27 12:32:12 PM PST 23
Peak memory 196084 kb
Host smart-b7532032-1a69-4151-b0fd-fb5a514e63b4
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1019343225 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 3.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.1019343225
Directory /workspace/3.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/30.gpio_smoke_en_cdc_prim.2232417378
Short name T60
Test name
Test status
Simulation time 97226625 ps
CPU time 0.86 seconds
Started Dec 27 12:31:42 PM PST 23
Finished Dec 27 12:32:32 PM PST 23
Peak memory 196256 kb
Host smart-2c883ca4-7ee9-40d1-aa0e-aa67c0d18e0d
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2232417378 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 30.gpio_smoke_en_cdc_prim.2232417378
Directory /workspace/30.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/30.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2671669513
Short name T202
Test name
Test status
Simulation time 245892832 ps
CPU time 0.76 seconds
Started Dec 27 12:31:17 PM PST 23
Finished Dec 27 12:32:07 PM PST 23
Peak memory 195088 kb
Host smart-b78c3137-7477-4ca1-9895-ce4bff096a86
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2671669513 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 30.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2671669513
Directory /workspace/30.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/31.gpio_smoke_en_cdc_prim.1263877212
Short name T187
Test name
Test status
Simulation time 696192569 ps
CPU time 1.32 seconds
Started Dec 27 12:31:38 PM PST 23
Finished Dec 27 12:32:30 PM PST 23
Peak memory 196432 kb
Host smart-4b74e1c4-686e-4a6a-ab87-82185523c10e
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1263877212 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 31.gpio_smoke_en_cdc_prim.1263877212
Directory /workspace/31.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/31.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2312381283
Short name T147
Test name
Test status
Simulation time 115882044 ps
CPU time 0.91 seconds
Started Dec 27 12:31:19 PM PST 23
Finished Dec 27 12:32:10 PM PST 23
Peak memory 195976 kb
Host smart-ca4a19b1-9021-44be-8395-3057ded3f12e
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2312381283 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 31.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2312381283
Directory /workspace/31.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/32.gpio_smoke_en_cdc_prim.3038686243
Short name T184
Test name
Test status
Simulation time 163259559 ps
CPU time 0.82 seconds
Started Dec 27 12:31:19 PM PST 23
Finished Dec 27 12:32:10 PM PST 23
Peak memory 195248 kb
Host smart-acd3d105-d875-4e3f-8bf3-23d00d9acdd8
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3038686243 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 32.gpio_smoke_en_cdc_prim.3038686243
Directory /workspace/32.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/32.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2521968636
Short name T151
Test name
Test status
Simulation time 350068365 ps
CPU time 0.91 seconds
Started Dec 27 12:31:38 PM PST 23
Finished Dec 27 12:32:30 PM PST 23
Peak memory 196660 kb
Host smart-63319006-391d-4401-8cbb-a3b8c8b5c9a0
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2521968636 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 32.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2521968636
Directory /workspace/32.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/33.gpio_smoke_en_cdc_prim.2123221787
Short name T206
Test name
Test status
Simulation time 227751739 ps
CPU time 1.21 seconds
Started Dec 27 12:31:52 PM PST 23
Finished Dec 27 12:32:39 PM PST 23
Peak memory 197632 kb
Host smart-1da96b74-9da8-4c7b-8643-50a063b438f8
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2123221787 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 33.gpio_smoke_en_cdc_prim.2123221787
Directory /workspace/33.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/33.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1339372715
Short name T215
Test name
Test status
Simulation time 65417802 ps
CPU time 1.02 seconds
Started Dec 27 12:31:56 PM PST 23
Finished Dec 27 12:32:42 PM PST 23
Peak memory 196308 kb
Host smart-d84ae68a-54fb-4050-9f16-2cfc18f82109
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1339372715 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 33.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.1339372715
Directory /workspace/33.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/34.gpio_smoke_en_cdc_prim.3810924691
Short name T140
Test name
Test status
Simulation time 390871260 ps
CPU time 1.35 seconds
Started Dec 27 12:31:17 PM PST 23
Finished Dec 27 12:32:08 PM PST 23
Peak memory 196404 kb
Host smart-da90cc66-14c4-42f2-88c8-78cb2eaf58ab
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3810924691 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 34.gpio_smoke_en_cdc_prim.3810924691
Directory /workspace/34.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/34.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2336823876
Short name T56
Test name
Test status
Simulation time 54328545 ps
CPU time 0.98 seconds
Started Dec 27 12:31:15 PM PST 23
Finished Dec 27 12:32:06 PM PST 23
Peak memory 196288 kb
Host smart-91d8b1f7-018f-4262-a617-36d5deded6ca
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2336823876 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 34.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2336823876
Directory /workspace/34.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/35.gpio_smoke_en_cdc_prim.2891797629
Short name T212
Test name
Test status
Simulation time 522514550 ps
CPU time 1.2 seconds
Started Dec 27 12:31:30 PM PST 23
Finished Dec 27 12:32:21 PM PST 23
Peak memory 197616 kb
Host smart-8f9c5b39-113f-44e1-b2d2-04f603d05d4a
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2891797629 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 35.gpio_smoke_en_cdc_prim.2891797629
Directory /workspace/35.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/35.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1562017162
Short name T143
Test name
Test status
Simulation time 355884116 ps
CPU time 1.24 seconds
Started Dec 27 12:31:22 PM PST 23
Finished Dec 27 12:32:13 PM PST 23
Peak memory 196168 kb
Host smart-de2ad1da-25b5-4f2e-9757-941bde038601
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1562017162 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 35.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.1562017162
Directory /workspace/35.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/36.gpio_smoke_en_cdc_prim.2210023087
Short name T153
Test name
Test status
Simulation time 265269312 ps
CPU time 1.12 seconds
Started Dec 27 12:31:18 PM PST 23
Finished Dec 27 12:32:08 PM PST 23
Peak memory 197600 kb
Host smart-6f1a293a-6137-4ad1-ba45-e8ace2e067ac
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2210023087 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 36.gpio_smoke_en_cdc_prim.2210023087
Directory /workspace/36.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/36.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3105058642
Short name T164
Test name
Test status
Simulation time 139087632 ps
CPU time 1.07 seconds
Started Dec 27 12:31:20 PM PST 23
Finished Dec 27 12:32:10 PM PST 23
Peak memory 195512 kb
Host smart-8b9d0797-b519-4806-acd4-ac55178b6100
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3105058642 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 36.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.3105058642
Directory /workspace/36.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/37.gpio_smoke_en_cdc_prim.1645256238
Short name T190
Test name
Test status
Simulation time 157816298 ps
CPU time 1.09 seconds
Started Dec 27 12:31:39 PM PST 23
Finished Dec 27 12:32:30 PM PST 23
Peak memory 196204 kb
Host smart-e370df1d-b5ac-4691-9e4b-4d2e3b56ec91
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1645256238 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 37.gpio_smoke_en_cdc_prim.1645256238
Directory /workspace/37.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/37.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3618723295
Short name T57
Test name
Test status
Simulation time 64811572 ps
CPU time 0.88 seconds
Started Dec 27 12:31:19 PM PST 23
Finished Dec 27 12:32:09 PM PST 23
Peak memory 196220 kb
Host smart-b0007fd6-a36a-4885-8491-32ffd461624b
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3618723295 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 37.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.3618723295
Directory /workspace/37.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/38.gpio_smoke_en_cdc_prim.1015504574
Short name T136
Test name
Test status
Simulation time 38644936 ps
CPU time 1.06 seconds
Started Dec 27 12:31:23 PM PST 23
Finished Dec 27 12:32:14 PM PST 23
Peak memory 195276 kb
Host smart-db375da3-45ad-4de5-a037-5d9c402105a9
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1015504574 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 38.gpio_smoke_en_cdc_prim.1015504574
Directory /workspace/38.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/38.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2103876249
Short name T200
Test name
Test status
Simulation time 51957453 ps
CPU time 1.26 seconds
Started Dec 27 12:31:40 PM PST 23
Finished Dec 27 12:32:31 PM PST 23
Peak memory 197648 kb
Host smart-ac1f848b-6584-466d-89ee-8f354f048323
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2103876249 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 38.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2103876249
Directory /workspace/38.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/39.gpio_smoke_en_cdc_prim.299686346
Short name T156
Test name
Test status
Simulation time 286014375 ps
CPU time 1.07 seconds
Started Dec 27 12:31:25 PM PST 23
Finished Dec 27 12:32:25 PM PST 23
Peak memory 196080 kb
Host smart-965f2556-6955-45ea-88ee-03a0026b618c
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=299686346 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 39.gpio_smoke_en_cdc_prim.299686346
Directory /workspace/39.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/39.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1593640602
Short name T44
Test name
Test status
Simulation time 63302812 ps
CPU time 0.93 seconds
Started Dec 27 12:31:27 PM PST 23
Finished Dec 27 12:32:18 PM PST 23
Peak memory 195236 kb
Host smart-f837a2f0-ced4-4b7c-b920-929938bce562
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1593640602 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 39.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.1593640602
Directory /workspace/39.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/4.gpio_smoke_en_cdc_prim.4112953913
Short name T158
Test name
Test status
Simulation time 149061257 ps
CPU time 0.93 seconds
Started Dec 27 12:32:52 PM PST 23
Finished Dec 27 12:33:37 PM PST 23
Peak memory 196128 kb
Host smart-ed36d801-cf96-4a78-944a-99816751cc61
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=4112953913 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 4.gpio_smoke_en_cdc_prim.4112953913
Directory /workspace/4.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/4.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1481405755
Short name T203
Test name
Test status
Simulation time 310715153 ps
CPU time 1.32 seconds
Started Dec 27 12:31:47 PM PST 23
Finished Dec 27 12:32:36 PM PST 23
Peak memory 196492 kb
Host smart-de8a46e7-3b96-400c-8616-72af89272c5a
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1481405755 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 4.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.1481405755
Directory /workspace/4.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/40.gpio_smoke_en_cdc_prim.1962774858
Short name T59
Test name
Test status
Simulation time 179638420 ps
CPU time 1.15 seconds
Started Dec 27 12:31:28 PM PST 23
Finished Dec 27 12:32:20 PM PST 23
Peak memory 196076 kb
Host smart-eda0f2ac-d70d-421e-9610-7fdd80c59aea
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1962774858 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 40.gpio_smoke_en_cdc_prim.1962774858
Directory /workspace/40.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/40.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2139912121
Short name T211
Test name
Test status
Simulation time 55198195 ps
CPU time 1.03 seconds
Started Dec 27 12:31:15 PM PST 23
Finished Dec 27 12:32:05 PM PST 23
Peak memory 196204 kb
Host smart-d45b7393-e694-45c4-aa9b-6b1548d57db4
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2139912121 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 40.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2139912121
Directory /workspace/40.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/41.gpio_smoke_en_cdc_prim.3327670845
Short name T55
Test name
Test status
Simulation time 222931737 ps
CPU time 1.04 seconds
Started Dec 27 12:31:15 PM PST 23
Finished Dec 27 12:32:05 PM PST 23
Peak memory 195488 kb
Host smart-e990f10f-8ae9-44d7-bc08-96eb6ac2b6be
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3327670845 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 41.gpio_smoke_en_cdc_prim.3327670845
Directory /workspace/41.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/41.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1743664802
Short name T155
Test name
Test status
Simulation time 413470811 ps
CPU time 1.13 seconds
Started Dec 27 12:31:52 PM PST 23
Finished Dec 27 12:32:39 PM PST 23
Peak memory 195448 kb
Host smart-96a0f284-f559-4d8d-b225-6667d7a7f9c5
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1743664802 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 41.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.1743664802
Directory /workspace/41.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/42.gpio_smoke_en_cdc_prim.2735423952
Short name T161
Test name
Test status
Simulation time 132628447 ps
CPU time 1.24 seconds
Started Dec 27 12:31:13 PM PST 23
Finished Dec 27 12:32:03 PM PST 23
Peak memory 196808 kb
Host smart-491755ac-7b9e-44ad-94b6-bf3332f1d490
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2735423952 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 42.gpio_smoke_en_cdc_prim.2735423952
Directory /workspace/42.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/42.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2370771986
Short name T171
Test name
Test status
Simulation time 66416653 ps
CPU time 1.08 seconds
Started Dec 27 12:31:40 PM PST 23
Finished Dec 27 12:32:31 PM PST 23
Peak memory 196120 kb
Host smart-334cdc63-d4b2-4172-bb84-1a73e0a46e8a
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2370771986 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 42.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2370771986
Directory /workspace/42.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/43.gpio_smoke_en_cdc_prim.3220656282
Short name T169
Test name
Test status
Simulation time 382688829 ps
CPU time 1.25 seconds
Started Dec 27 12:31:22 PM PST 23
Finished Dec 27 12:32:13 PM PST 23
Peak memory 196428 kb
Host smart-0e696e82-2fc8-4ea8-b9f5-2b75397b1025
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3220656282 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 43.gpio_smoke_en_cdc_prim.3220656282
Directory /workspace/43.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/43.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3127223819
Short name T192
Test name
Test status
Simulation time 348832662 ps
CPU time 1.1 seconds
Started Dec 27 12:31:16 PM PST 23
Finished Dec 27 12:32:06 PM PST 23
Peak memory 196152 kb
Host smart-eefa3373-8b37-4a18-91c9-764a73b72153
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3127223819 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 43.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.3127223819
Directory /workspace/43.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/44.gpio_smoke_en_cdc_prim.1695433400
Short name T54
Test name
Test status
Simulation time 52298670 ps
CPU time 0.93 seconds
Started Dec 27 12:31:48 PM PST 23
Finished Dec 27 12:32:36 PM PST 23
Peak memory 195328 kb
Host smart-4b3dcf7e-abbc-4248-864b-4e34545ec099
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1695433400 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 44.gpio_smoke_en_cdc_prim.1695433400
Directory /workspace/44.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/44.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2822338776
Short name T208
Test name
Test status
Simulation time 235360702 ps
CPU time 1.09 seconds
Started Dec 27 12:31:18 PM PST 23
Finished Dec 27 12:32:08 PM PST 23
Peak memory 196272 kb
Host smart-48bb9db3-669a-4eb6-ba2b-9571bb3e798c
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2822338776 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 44.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2822338776
Directory /workspace/44.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/45.gpio_smoke_en_cdc_prim.2681111929
Short name T183
Test name
Test status
Simulation time 60446207 ps
CPU time 1.01 seconds
Started Dec 27 12:31:20 PM PST 23
Finished Dec 27 12:32:11 PM PST 23
Peak memory 195332 kb
Host smart-9de8adad-45d1-4766-bb75-3e70bbe26f99
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2681111929 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 45.gpio_smoke_en_cdc_prim.2681111929
Directory /workspace/45.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/45.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1552282840
Short name T199
Test name
Test status
Simulation time 65038267 ps
CPU time 0.75 seconds
Started Dec 27 12:31:24 PM PST 23
Finished Dec 27 12:32:14 PM PST 23
Peak memory 195112 kb
Host smart-b46f4096-b1e8-48d0-9704-ae8c4bfa43cb
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1552282840 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 45.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.1552282840
Directory /workspace/45.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/46.gpio_smoke_en_cdc_prim.1391398130
Short name T197
Test name
Test status
Simulation time 87050754 ps
CPU time 1.12 seconds
Started Dec 27 12:31:14 PM PST 23
Finished Dec 27 12:32:04 PM PST 23
Peak memory 196296 kb
Host smart-6670e0fc-a81b-475c-95bc-dda8ad837094
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=1391398130 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 46.gpio_smoke_en_cdc_prim.1391398130
Directory /workspace/46.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/46.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3419858154
Short name T163
Test name
Test status
Simulation time 267534672 ps
CPU time 0.85 seconds
Started Dec 27 12:31:22 PM PST 23
Finished Dec 27 12:32:13 PM PST 23
Peak memory 195144 kb
Host smart-8be7d6f5-4554-4257-8b02-b5edaa6a3707
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3419858154 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 46.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.3419858154
Directory /workspace/46.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/47.gpio_smoke_en_cdc_prim.535869569
Short name T162
Test name
Test status
Simulation time 106886601 ps
CPU time 0.96 seconds
Started Dec 27 12:31:28 PM PST 23
Finished Dec 27 12:32:19 PM PST 23
Peak memory 196148 kb
Host smart-47379cde-9c37-4b64-9117-da185b93bdd6
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=535869569 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 47.gpio_smoke_en_cdc_prim.535869569
Directory /workspace/47.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/47.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3242408376
Short name T159
Test name
Test status
Simulation time 39366996 ps
CPU time 0.88 seconds
Started Dec 27 12:31:17 PM PST 23
Finished Dec 27 12:32:08 PM PST 23
Peak memory 197504 kb
Host smart-301cf779-c0d9-4008-812a-e2760c23e0c5
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3242408376 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 47.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.3242408376
Directory /workspace/47.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/48.gpio_smoke_en_cdc_prim.3664377006
Short name T103
Test name
Test status
Simulation time 68182692 ps
CPU time 1.1 seconds
Started Dec 27 12:31:30 PM PST 23
Finished Dec 27 12:32:21 PM PST 23
Peak memory 195280 kb
Host smart-a414eaca-43f7-4b53-8c8b-a149d1252b0f
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=3664377006 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 48.gpio_smoke_en_cdc_prim.3664377006
Directory /workspace/48.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/48.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1012434982
Short name T180
Test name
Test status
Simulation time 124336088 ps
CPU time 1.02 seconds
Started Dec 27 12:31:15 PM PST 23
Finished Dec 27 12:32:05 PM PST 23
Peak memory 196132 kb
Host smart-5792ce1a-a54c-4902-acac-7e2bf8827909
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1012434982 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 48.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.1012434982
Directory /workspace/48.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/49.gpio_smoke_en_cdc_prim.2693280266
Short name T141
Test name
Test status
Simulation time 197675125 ps
CPU time 1.48 seconds
Started Dec 27 12:31:22 PM PST 23
Finished Dec 27 12:32:14 PM PST 23
Peak memory 197712 kb
Host smart-ec8fc8ae-7b5a-405c-b761-20d66ae5f16f
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2693280266 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 49.gpio_smoke_en_cdc_prim.2693280266
Directory /workspace/49.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/49.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2656003382
Short name T58
Test name
Test status
Simulation time 349141269 ps
CPU time 1.19 seconds
Started Dec 27 12:31:29 PM PST 23
Finished Dec 27 12:32:21 PM PST 23
Peak memory 197660 kb
Host smart-2cfd47e1-9ab4-40cb-be97-fd374f11466f
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2656003382 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 49.gpio_smoke_no_pullup_pulldown
_en_cdc_prim.2656003382
Directory /workspace/49.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/5.gpio_smoke_en_cdc_prim.347793028
Short name T189
Test name
Test status
Simulation time 136934580 ps
CPU time 1.08 seconds
Started Dec 27 12:31:21 PM PST 23
Finished Dec 27 12:32:15 PM PST 23
Peak memory 196288 kb
Host smart-8ae8eb94-ba8c-4bf9-b24a-e8507ab8867e
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=347793028 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 5.gpio_smoke_en_cdc_prim.347793028
Directory /workspace/5.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/5.gpio_smoke_no_pullup_pulldown_en_cdc_prim.2369145831
Short name T134
Test name
Test status
Simulation time 201922861 ps
CPU time 0.98 seconds
Started Dec 27 12:31:05 PM PST 23
Finished Dec 27 12:31:56 PM PST 23
Peak memory 195528 kb
Host smart-4d804831-43a5-4537-92cd-9d1dea39be67
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2369145831 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 5.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.2369145831
Directory /workspace/5.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/6.gpio_smoke_en_cdc_prim.2245056053
Short name T179
Test name
Test status
Simulation time 216788011 ps
CPU time 0.94 seconds
Started Dec 27 12:31:07 PM PST 23
Finished Dec 27 12:31:57 PM PST 23
Peak memory 196344 kb
Host smart-a8ae6ae5-7005-45e5-a395-2df5a6cdf101
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2245056053 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 6.gpio_smoke_en_cdc_prim.2245056053
Directory /workspace/6.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/6.gpio_smoke_no_pullup_pulldown_en_cdc_prim.1243940325
Short name T207
Test name
Test status
Simulation time 691153349 ps
CPU time 1.23 seconds
Started Dec 27 12:31:22 PM PST 23
Finished Dec 27 12:32:13 PM PST 23
Peak memory 196584 kb
Host smart-ccb1c936-2ac8-4c25-8ced-c1ff589a08d4
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1243940325 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 6.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.1243940325
Directory /workspace/6.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/7.gpio_smoke_en_cdc_prim.2747766176
Short name T142
Test name
Test status
Simulation time 99399394 ps
CPU time 0.94 seconds
Started Dec 27 12:31:12 PM PST 23
Finished Dec 27 12:32:02 PM PST 23
Peak memory 196120 kb
Host smart-f4035446-80f1-45cd-82ea-5ed81386ee1c
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2747766176 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 7.gpio_smoke_en_cdc_prim.2747766176
Directory /workspace/7.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/7.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3013435529
Short name T145
Test name
Test status
Simulation time 93358664 ps
CPU time 1.47 seconds
Started Dec 27 12:31:14 PM PST 23
Finished Dec 27 12:32:04 PM PST 23
Peak memory 196348 kb
Host smart-f2c8966c-f926-4e41-a6c8-487d548b9e40
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3013435529 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 7.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.3013435529
Directory /workspace/7.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/8.gpio_smoke_en_cdc_prim.2076166629
Short name T152
Test name
Test status
Simulation time 67507753 ps
CPU time 0.93 seconds
Started Dec 27 12:32:07 PM PST 23
Finished Dec 27 12:32:52 PM PST 23
Peak memory 196172 kb
Host smart-ddba360a-f2f0-4c9f-8adc-8b9947c09d7e
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2076166629 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 8.gpio_smoke_en_cdc_prim.2076166629
Directory /workspace/8.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/8.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3468577742
Short name T186
Test name
Test status
Simulation time 76319323 ps
CPU time 1.4 seconds
Started Dec 27 12:31:13 PM PST 23
Finished Dec 27 12:32:03 PM PST 23
Peak memory 196256 kb
Host smart-0e5286ce-5240-496f-8fc3-b2f00a5018df
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3468577742 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 8.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.3468577742
Directory /workspace/8.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/9.gpio_smoke_en_cdc_prim.2578161058
Short name T176
Test name
Test status
Simulation time 32572307 ps
CPU time 0.92 seconds
Started Dec 27 12:31:17 PM PST 23
Finished Dec 27 12:32:08 PM PST 23
Peak memory 196208 kb
Host smart-8662fbac-c068-4813-8ae1-6f551cefc1b9
User root
Command /workspace/en_cdc_prims/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/
tools/sim.tcl +ntb_random_seed=2578161058 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 9.gpio_smoke_en_cdc_prim.2578161058
Directory /workspace/9.gpio_smoke_en_cdc_prim/latest

Test location /workspace/coverage/en_cdc_prims/9.gpio_smoke_no_pullup_pulldown_en_cdc_prim.3648430957
Short name T173
Test name
Test status
Simulation time 46910607 ps
CPU time 1.19 seconds
Started Dec 27 12:31:17 PM PST 23
Finished Dec 27 12:32:08 PM PST 23
Peak memory 196628 kb
Host smart-4550ae29-170b-4364-9f1d-75691dfaeab6
User root
Command /workspace/en_cdc_prims/simv +no_pullup_pulldown=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa
ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3648430957 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_smoke_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/en_cdc_prims.vdb -cm_log /dev/null -cm_name 9.gpio_smoke_no_pullup_pulldown_
en_cdc_prim.3648430957
Directory /workspace/9.gpio_smoke_no_pullup_pulldown_en_cdc_prim/latest
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