Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=31}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=31}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=31}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	36	0	36	100.00
Crosses	128	0	128	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=31}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	32	0	32	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=31}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	128	0	128	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	32	0	32	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	6484824	1			T22	26		T23	1		T24	8
all_pins[1]	6484824	1			T22	26		T23	1		T24	8
all_pins[2]	6484824	1			T22	26		T23	1		T24	8
all_pins[3]	6484824	1			T22	26		T23	1		T24	8
all_pins[4]	6484824	1			T22	26		T23	1		T24	8
all_pins[5]	6484824	1			T22	26		T23	1		T24	8
all_pins[6]	6484824	1			T22	26		T23	1		T24	8
all_pins[7]	6484824	1			T22	26		T23	1		T24	8
all_pins[8]	6484824	1			T22	26		T23	1		T24	8
all_pins[9]	6484824	1			T22	26		T23	1		T24	8
all_pins[10]	6484824	1			T22	26		T23	1		T24	8
all_pins[11]	6484824	1			T22	26		T23	1		T24	8
all_pins[12]	6484824	1			T22	26		T23	1		T24	8
all_pins[13]	6484824	1			T22	26		T23	1		T24	8
all_pins[14]	6484824	1			T22	26		T23	1		T24	8
all_pins[15]	6484824	1			T22	26		T23	1		T24	8
all_pins[16]	6484824	1			T22	26		T23	1		T24	8
all_pins[17]	6484824	1			T22	26		T23	1		T24	8
all_pins[18]	6484824	1			T22	26		T23	1		T24	8
all_pins[19]	6484824	1			T22	26		T23	1		T24	8
all_pins[20]	6484824	1			T22	26		T23	1		T24	8
all_pins[21]	6484824	1			T22	26		T23	1		T24	8
all_pins[22]	6484824	1			T22	26		T23	1		T24	8
all_pins[23]	6484824	1			T22	26		T23	1		T24	8
all_pins[24]	6484824	1			T22	26		T23	1		T24	8
all_pins[25]	6484824	1			T22	26		T23	1		T24	8
all_pins[26]	6484824	1			T22	26		T23	1		T24	8
all_pins[27]	6484824	1			T22	26		T23	1		T24	8
all_pins[28]	6484824	1			T22	26		T23	1		T24	8
all_pins[29]	6484824	1			T22	26		T23	1		T24	8
all_pins[30]	6484824	1			T22	26		T23	1		T24	8
all_pins[31]	6484824	1			T22	26		T23	1		T24	8

---

Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	128667862	1			T22	634		T23	32		T24	157
values[0x1]	78846506	1			T22	198		T24	99		T25	195
transitions[0x0=>0x1]	47173819	1			T22	149		T24	59		T25	132
transitions[0x1=>0x0]	47173672	1			T22	149		T24	59		T25	132

---

Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	128	0	128	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	4020464	1			T22	17		T23	1		T24	4
all_pins[0]	values[0x1]	2464360	1			T22	9		T24	4		T25	8
all_pins[0]	transitions[0x0=>0x1]	1522530	1			T22	8		T24	3		T25	7
all_pins[0]	transitions[0x1=>0x0]	1520286	1			T25	5		T26	1		T28	7
all_pins[1]	values[0x0]	4021237	1			T22	18		T23	1		T24	3
all_pins[1]	values[0x1]	2463587	1			T22	8		T24	5		T25	8
all_pins[1]	transitions[0x0=>0x1]	1470630	1			T22	5		T24	3		T25	5
all_pins[1]	transitions[0x1=>0x0]	1471403	1			T22	6		T24	2		T25	5
all_pins[2]	values[0x0]	4024060	1			T22	25		T23	1		T24	5
all_pins[2]	values[0x1]	2460764	1			T22	1		T24	3		T25	4
all_pins[2]	transitions[0x0=>0x1]	1467347	1			T24	1		T25	4		T26	14
all_pins[2]	transitions[0x1=>0x0]	1470170	1			T22	7		T24	3		T25	8
all_pins[3]	values[0x0]	4020546	1			T22	23		T23	1		T24	4
all_pins[3]	values[0x1]	2464278	1			T22	3		T24	4		T25	2
all_pins[3]	transitions[0x0=>0x1]	1473482	1			T22	3		T24	3		T25	1
all_pins[3]	transitions[0x1=>0x0]	1469968	1			T22	1		T24	2		T25	3
all_pins[4]	values[0x0]	4023273	1			T22	21		T23	1		T24	6
all_pins[4]	values[0x1]	2461551	1			T22	5		T24	2		T25	8
all_pins[4]	transitions[0x0=>0x1]	1470354	1			T22	3		T24	1		T25	8
all_pins[4]	transitions[0x1=>0x0]	1473081	1			T22	1		T24	3		T25	2
all_pins[5]	values[0x0]	4022103	1			T22	26		T23	1		T24	5
all_pins[5]	values[0x1]	2462721	1			T24	3		T25	16		T26	14
all_pins[5]	transitions[0x0=>0x1]	1474164	1			T24	3		T25	8		T26	11
all_pins[5]	transitions[0x1=>0x0]	1472994	1			T22	5		T24	2		T26	7
all_pins[6]	values[0x0]	4024189	1			T22	20		T23	1		T24	4
all_pins[6]	values[0x1]	2460635	1			T22	6		T24	4		T25	14
all_pins[6]	transitions[0x0=>0x1]	1472676	1			T22	6		T24	3		T25	3
all_pins[6]	transitions[0x1=>0x0]	1474762	1			T24	2		T25	5		T26	14
all_pins[7]	values[0x0]	4025038	1			T22	18		T23	1		T24	5
all_pins[7]	values[0x1]	2459786	1			T22	8		T24	3		T25	8
all_pins[7]	transitions[0x0=>0x1]	1471568	1			T22	7		T24	1		T25	2
all_pins[7]	transitions[0x1=>0x0]	1472417	1			T22	5		T24	2		T25	8
all_pins[8]	values[0x0]	4018616	1			T22	20		T23	1		T24	7
all_pins[8]	values[0x1]	2466208	1			T22	6		T24	1		T25	8
all_pins[8]	transitions[0x0=>0x1]	1477183	1			T22	5		T24	1		T25	3
all_pins[8]	transitions[0x1=>0x0]	1470761	1			T22	7		T24	3		T25	3
all_pins[9]	values[0x0]	4014267	1			T22	18		T23	1		T24	8
all_pins[9]	values[0x1]	2470557	1			T22	8		T25	3		T26	15
all_pins[9]	transitions[0x0=>0x1]	1474512	1			T22	7		T25	2		T26	13
all_pins[9]	transitions[0x1=>0x0]	1470163	1			T22	5		T24	1		T25	7
all_pins[10]	values[0x0]	4026988	1			T22	26		T23	1		T24	4
all_pins[10]	values[0x1]	2457836	1			T24	4		T25	4		T26	12
all_pins[10]	transitions[0x0=>0x1]	1465545	1			T24	4		T25	4		T26	9
all_pins[10]	transitions[0x1=>0x0]	1478266	1			T22	8		T25	3		T26	12
all_pins[11]	values[0x0]	4019819	1			T22	17		T23	1		T24	3
all_pins[11]	values[0x1]	2465005	1			T22	9		T24	5		T25	7
all_pins[11]	transitions[0x0=>0x1]	1476261	1			T22	9		T24	1		T25	4
all_pins[11]	transitions[0x1=>0x0]	1469092	1			T25	1		T26	8		T27	3
all_pins[12]	values[0x0]	4026249	1			T22	18		T23	1		T24	4
all_pins[12]	values[0x1]	2458575	1			T22	8		T24	4		T25	2
all_pins[12]	transitions[0x0=>0x1]	1468943	1			T22	5		T24	1		T25	1
all_pins[12]	transitions[0x1=>0x0]	1475373	1			T22	6		T24	2		T25	6
all_pins[13]	values[0x0]	4027966	1			T22	20		T23	1		T24	7
all_pins[13]	values[0x1]	2456858	1			T22	6		T24	1		T25	6
all_pins[13]	transitions[0x0=>0x1]	1469400	1			T22	2		T25	6		T26	8
all_pins[13]	transitions[0x1=>0x0]	1471117	1			T22	4		T24	3		T25	2
all_pins[14]	values[0x0]	4017205	1			T22	16		T23	1		T24	6
all_pins[14]	values[0x1]	2467619	1			T22	10		T24	2		T25	10
all_pins[14]	transitions[0x0=>0x1]	1476055	1			T22	7		T24	1		T25	10
all_pins[14]	transitions[0x1=>0x0]	1465294	1			T22	3		T25	6		T26	11
all_pins[15]	values[0x0]	4025431	1			T22	24		T23	1		T24	4
all_pins[15]	values[0x1]	2459393	1			T22	2		T24	4		T25	3
all_pins[15]	transitions[0x0=>0x1]	1468529	1			T22	2		T24	3		T25	3
all_pins[15]	transitions[0x1=>0x0]	1476755	1			T22	10		T24	1		T25	10
all_pins[16]	values[0x0]	4007435	1			T22	17		T23	1		T24	4
all_pins[16]	values[0x1]	2477389	1			T22	9		T24	4		T25	4
all_pins[16]	transitions[0x0=>0x1]	1482328	1			T22	7		T24	3		T25	4
all_pins[16]	transitions[0x1=>0x0]	1464332	1			T24	3		T25	3		T26	13
all_pins[17]	values[0x0]	4023900	1			T22	19		T23	1		T24	7
all_pins[17]	values[0x1]	2460924	1			T22	7		T24	1		T25	6
all_pins[17]	transitions[0x0=>0x1]	1465533	1			T22	6		T25	5		T26	12
all_pins[17]	transitions[0x1=>0x0]	1481998	1			T22	8		T24	3		T25	3
all_pins[18]	values[0x0]	4018057	1			T22	22		T23	1		T24	4
all_pins[18]	values[0x1]	2466767	1			T22	4		T24	4		T25	6
all_pins[18]	transitions[0x0=>0x1]	1476001	1			T22	2		T24	4		T25	4
all_pins[18]	transitions[0x1=>0x0]	1470158	1			T22	5		T24	1		T25	4
all_pins[19]	values[0x0]	4019427	1			T22	24		T23	1		T24	5
all_pins[19]	values[0x1]	2465397	1			T22	2		T24	3		T25	5
all_pins[19]	transitions[0x0=>0x1]	1470909	1			T22	2		T24	2		T25	4
all_pins[19]	transitions[0x1=>0x0]	1472279	1			T22	4		T24	3		T25	5
all_pins[20]	values[0x0]	4017314	1			T22	22		T23	1		T24	5
all_pins[20]	values[0x1]	2467510	1			T22	4		T24	3		T25	11
all_pins[20]	transitions[0x0=>0x1]	1472374	1			T22	4		T24	2		T25	8
all_pins[20]	transitions[0x1=>0x0]	1470261	1			T22	2		T24	2		T25	2
all_pins[21]	values[0x0]	4020358	1			T22	15		T23	1		T24	3
all_pins[21]	values[0x1]	2464466	1			T22	11		T24	5		T25	6
all_pins[21]	transitions[0x0=>0x1]	1471840	1			T22	8		T24	3		T25	2
all_pins[21]	transitions[0x1=>0x0]	1474884	1			T22	1		T24	1		T25	7
all_pins[22]	values[0x0]	4023885	1			T22	16		T23	1		T24	3
all_pins[22]	values[0x1]	2460939	1			T22	10		T24	5		T25	3
all_pins[22]	transitions[0x0=>0x1]	1469158	1			T22	6		T24	2		T26	8
all_pins[22]	transitions[0x1=>0x0]	1472685	1			T22	7		T24	2		T25	3
all_pins[23]	values[0x0]	4023925	1			T22	16		T23	1		T24	6
all_pins[23]	values[0x1]	2460899	1			T22	10		T24	2		T25	4
all_pins[23]	transitions[0x0=>0x1]	1469867	1			T22	5		T25	2		T26	8
all_pins[23]	transitions[0x1=>0x0]	1469907	1			T22	5		T24	3		T25	1
all_pins[24]	values[0x0]	4018570	1			T22	20		T23	1		T24	6
all_pins[24]	values[0x1]	2466254	1			T22	6		T24	2		T25	6
all_pins[24]	transitions[0x0=>0x1]	1477975	1			T22	2		T24	1		T25	6
all_pins[24]	transitions[0x1=>0x0]	1472620	1			T22	6		T24	1		T25	4
all_pins[25]	values[0x0]	4022363	1			T22	22		T23	1		T24	6
all_pins[25]	values[0x1]	2462461	1			T22	4		T24	2		T25	5
all_pins[25]	transitions[0x0=>0x1]	1472217	1			T22	3		T24	1		T25	4
all_pins[25]	transitions[0x1=>0x0]	1476010	1			T22	5		T24	1		T25	5
all_pins[26]	values[0x0]	4023600	1			T22	15		T23	1		T24	5
all_pins[26]	values[0x1]	2461224	1			T22	11		T24	3		T25	5
all_pins[26]	transitions[0x0=>0x1]	1474995	1			T22	8		T24	2		T25	4
all_pins[26]	transitions[0x1=>0x0]	1476232	1			T22	1		T24	1		T25	4
all_pins[27]	values[0x0]	4025608	1			T22	25		T23	1		T24	5
all_pins[27]	values[0x1]	2459216	1			T22	1		T24	3		T25	4
all_pins[27]	transitions[0x0=>0x1]	1469670	1			T22	1		T24	2		T25	3
all_pins[27]	transitions[0x1=>0x0]	1471678	1			T22	11		T24	2		T25	4
all_pins[28]	values[0x0]	4013852	1			T22	16		T23	1		T24	4
all_pins[28]	values[0x1]	2470972	1			T22	10		T24	4		T25	1
all_pins[28]	transitions[0x0=>0x1]	1481083	1			T22	10		T24	2		T25	1
all_pins[28]	transitions[0x1=>0x0]	1469327	1			T22	1		T24	1		T25	4
all_pins[29]	values[0x0]	4020071	1			T22	20		T23	1		T24	5
all_pins[29]	values[0x1]	2464753	1			T22	6		T24	3		T25	7
all_pins[29]	transitions[0x0=>0x1]	1471557	1			T22	5		T24	2		T25	6
all_pins[29]	transitions[0x1=>0x0]	1477776	1			T22	9		T24	3		T26	11
all_pins[30]	values[0x0]	4009485	1			T22	13		T23	1		T24	3
all_pins[30]	values[0x1]	2475339	1			T22	13		T24	5		T25	5
all_pins[30]	transitions[0x0=>0x1]	1480883	1			T22	11		T24	4		T25	4
all_pins[30]	transitions[0x1=>0x0]	1470297	1			T22	4		T24	2		T25	6
all_pins[31]	values[0x0]	4022561	1			T22	25		T23	1		T24	7
all_pins[31]	values[0x1]	2462263	1			T22	1		T24	1		T25	6
all_pins[31]	transitions[0x0=>0x1]	1468250	1			T25	4		T26	1		T28	4
all_pins[31]	transitions[0x1=>0x0]	1481326	1			T22	12		T24	4		T25	3