Unified Coverage Report :: Group :: cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=31}

Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=31}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=31}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	192	0	192	100.00

Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=31}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	32	0	32	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2
cp_intr_test	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=31}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_test_cg_cc	192	0	192	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	32	0	32	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	21439365	1			T22	30		T23	1		T24	9
all_values[1]	21439365	1			T22	30		T23	1		T24	9
all_values[2]	21439365	1			T22	30		T23	1		T24	9
all_values[3]	21439365	1			T22	30		T23	1		T24	9
all_values[4]	21439365	1			T22	30		T23	1		T24	9
all_values[5]	21439365	1			T22	30		T23	1		T24	9
all_values[6]	21439365	1			T22	30		T23	1		T24	9
all_values[7]	21439365	1			T22	30		T23	1		T24	9
all_values[8]	21439365	1			T22	30		T23	1		T24	9
all_values[9]	21439365	1			T22	30		T23	1		T24	9
all_values[10]	21439365	1			T22	30		T23	1		T24	9
all_values[11]	21439365	1			T22	30		T23	1		T24	9
all_values[12]	21439365	1			T22	30		T23	1		T24	9
all_values[13]	21439365	1			T22	30		T23	1		T24	9
all_values[14]	21439365	1			T22	30		T23	1		T24	9
all_values[15]	21439365	1			T22	30		T23	1		T24	9
all_values[16]	21439365	1			T22	30		T23	1		T24	9
all_values[17]	21439365	1			T22	30		T23	1		T24	9
all_values[18]	21439365	1			T22	30		T23	1		T24	9
all_values[19]	21439365	1			T22	30		T23	1		T24	9
all_values[20]	21439365	1			T22	30		T23	1		T24	9
all_values[21]	21439365	1			T22	30		T23	1		T24	9
all_values[22]	21439365	1			T22	30		T23	1		T24	9
all_values[23]	21439365	1			T22	30		T23	1		T24	9
all_values[24]	21439365	1			T22	30		T23	1		T24	9
all_values[25]	21439365	1			T22	30		T23	1		T24	9
all_values[26]	21439365	1			T22	30		T23	1		T24	9
all_values[27]	21439365	1			T22	30		T23	1		T24	9
all_values[28]	21439365	1			T22	30		T23	1		T24	9
all_values[29]	21439365	1			T22	30		T23	1		T24	9
all_values[30]	21439365	1			T22	30		T23	1		T24	9
all_values[31]	21439365	1			T22	30		T23	1		T24	9

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

378406930

1

T22

494

T23

32

T24

288

auto[1]

307652750

1

T22

466

T25

431

T26

306

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

128262579

1

T22

555

T23

32

T24

119

auto[1]

557797101

1

T22

405

T24

169

T25

430

---

Summary for Variable cp_intr_test

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_test

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

677988617

1

T22

822

T23

32

T24

288

auto[1]

8071063

1

T22

138

T25

158

T27

100

---

Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	192	0	192	100.00
Automatically Generated Cross Bins	192	0	192	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for intr_test_cg_cc

Bins

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	auto[0]	3100230	1			T22	2		T23	1		T24	1
all_values[0]	auto[0]	auto[0]	auto[1]	8612217	1			T22	4		T24	8		T25	9
all_values[0]	auto[0]	auto[1]	auto[0]	885615	1			T22	13		T25	4		T26	4
all_values[0]	auto[0]	auto[1]	auto[1]	8589108	1			T22	8		T25	5		T26	5
all_values[0]	auto[1]	auto[0]	auto[1]	126122	1			T22	1		T25	1		T27	1
all_values[0]	auto[1]	auto[1]	auto[1]	126073	1			T22	2		T25	3		T27	1
all_values[1]	auto[0]	auto[0]	auto[0]	3100814	1			T22	7		T23	1		T24	1
all_values[1]	auto[0]	auto[0]	auto[1]	8583905	1			T22	5		T24	8		T25	4
all_values[1]	auto[0]	auto[1]	auto[0]	899305	1			T22	8		T25	9		T26	5
all_values[1]	auto[0]	auto[1]	auto[1]	8602971	1			T22	5		T25	5		T26	6
all_values[1]	auto[1]	auto[0]	auto[1]	126602	1			T22	2		T25	3		T27	1
all_values[1]	auto[1]	auto[1]	auto[1]	125768	1			T22	3		T25	3		T27	2
all_values[2]	auto[0]	auto[0]	auto[0]	3106329	1			T22	15		T23	1		T24	1
all_values[2]	auto[0]	auto[0]	auto[1]	8608905	1			T22	6		T24	8		T25	2
all_values[2]	auto[0]	auto[1]	auto[0]	896493	1			T22	3		T25	13		T26	3
all_values[2]	auto[0]	auto[1]	auto[1]	8575098	1			T25	2		T26	7		T27	5
all_values[2]	auto[1]	auto[0]	auto[1]	126532	1			T22	5		T25	2		T27	2
all_values[2]	auto[1]	auto[1]	auto[1]	126008	1			T22	1		T25	2		T27	2
all_values[3]	auto[0]	auto[0]	auto[0]	3101909	1			T22	14		T23	1		T24	1
all_values[3]	auto[0]	auto[0]	auto[1]	8592571	1			T22	3		T24	8		T25	6
all_values[3]	auto[0]	auto[1]	auto[0]	890800	1			T22	9		T25	10		T26	5
all_values[3]	auto[0]	auto[1]	auto[1]	8601880	1			T22	2		T26	5		T27	8
all_values[3]	auto[1]	auto[0]	auto[1]	126483	1			T22	1		T25	2		T27	1
all_values[3]	auto[1]	auto[1]	auto[1]	125722	1			T22	1		T25	2		T27	3
all_values[4]	auto[0]	auto[0]	auto[0]	3106791	1			T22	14		T23	1		T24	2
all_values[4]	auto[0]	auto[0]	auto[1]	8606132	1			T22	3		T24	7		T25	6
all_values[4]	auto[0]	auto[1]	auto[0]	908269	1			T22	5		T25	1		T26	5
all_values[4]	auto[0]	auto[1]	auto[1]	8566021	1			T22	5		T25	5		T26	3
all_values[4]	auto[1]	auto[0]	auto[1]	126146	1			T22	3		T25	3		T27	5
all_values[4]	auto[1]	auto[1]	auto[1]	126006	1			T25	3		T28	2		T13	4
all_values[5]	auto[0]	auto[0]	auto[0]	3099895	1			T22	6		T23	1		T24	2
all_values[5]	auto[0]	auto[0]	auto[1]	8605429	1			T22	4		T24	7		T25	1
all_values[5]	auto[0]	auto[1]	auto[0]	905624	1			T22	18		T25	5		T26	5
all_values[5]	auto[0]	auto[1]	auto[1]	8575299	1			T25	13		T26	5		T28	1
all_values[5]	auto[1]	auto[0]	auto[1]	126604	1			T22	2		T25	3		T27	1
all_values[5]	auto[1]	auto[1]	auto[1]	126514	1			T25	3		T27	1		T12	2
all_values[6]	auto[0]	auto[0]	auto[0]	3105222	1			T22	6		T23	1		T24	9
all_values[6]	auto[0]	auto[0]	auto[1]	8591071	1			T22	5		T25	8		T26	6
all_values[6]	auto[0]	auto[1]	auto[0]	896547	1			T22	10		T25	2		T26	10
all_values[6]	auto[0]	auto[1]	auto[1]	8594473	1			T22	4		T25	10		T26	1
all_values[6]	auto[1]	auto[0]	auto[1]	126568	1			T22	2		T25	2		T27	3
all_values[6]	auto[1]	auto[1]	auto[1]	125484	1			T22	3		T25	4		T27	1
all_values[7]	auto[0]	auto[0]	auto[0]	3113254	1			T22	11		T23	1		T24	9
all_values[7]	auto[0]	auto[0]	auto[1]	8602973	1			T22	3		T25	4		T26	7
all_values[7]	auto[0]	auto[1]	auto[0]	897790	1			T22	7		T25	9		T26	6
all_values[7]	auto[0]	auto[1]	auto[1]	8572668	1			T22	6		T25	4		T26	2
all_values[7]	auto[1]	auto[0]	auto[1]	126447	1			T22	1		T25	1		T27	2
all_values[7]	auto[1]	auto[1]	auto[1]	126233	1			T22	2		T25	4		T27	2
all_values[8]	auto[0]	auto[0]	auto[0]	3114044	1			T22	4		T23	1		T24	9
all_values[8]	auto[0]	auto[0]	auto[1]	8564992	1			T22	8		T25	4		T26	14
all_values[8]	auto[0]	auto[1]	auto[0]	903803	1			T22	9		T25	11		T26	4
all_values[8]	auto[0]	auto[1]	auto[1]	8604314	1			T22	3		T25	4		T26	2
all_values[8]	auto[1]	auto[0]	auto[1]	126282	1			T22	3		T25	1		T27	3
all_values[8]	auto[1]	auto[1]	auto[1]	125930	1			T22	3		T25	4		T28	1
all_values[9]	auto[0]	auto[0]	auto[0]	3112861	1			T22	8		T23	1		T24	9
all_values[9]	auto[0]	auto[0]	auto[1]	8586388	1			T25	8		T26	6		T27	13
all_values[9]	auto[0]	auto[1]	auto[0]	901615	1			T22	11		T25	8		T26	2
all_values[9]	auto[0]	auto[1]	auto[1]	8586495	1			T22	6		T25	2		T26	5
all_values[9]	auto[1]	auto[0]	auto[1]	126032	1			T22	1		T25	2		T27	3
all_values[9]	auto[1]	auto[1]	auto[1]	125974	1			T22	4		T25	2		T28	1
all_values[10]	auto[0]	auto[0]	auto[0]	3114065	1			T22	19		T23	1		T24	2
all_values[10]	auto[0]	auto[0]	auto[1]	8614906	1			T22	5		T24	7		T25	4
all_values[10]	auto[0]	auto[1]	auto[0]	891297	1			T22	1		T25	4		T26	7
all_values[10]	auto[0]	auto[1]	auto[1]	8567107	1			T25	1		T26	5		T27	3
all_values[10]	auto[1]	auto[0]	auto[1]	125535	1			T22	5		T25	2		T27	3
all_values[10]	auto[1]	auto[1]	auto[1]	126455	1			T25	3		T28	3		T12	2
all_values[11]	auto[0]	auto[0]	auto[0]	3106676	1			T22	8		T23	1		T24	1
all_values[11]	auto[0]	auto[0]	auto[1]	8590175	1			T22	2		T24	8		T25	6
all_values[11]	auto[0]	auto[1]	auto[0]	900696	1			T22	9		T25	3		T26	9
all_values[11]	auto[0]	auto[1]	auto[1]	8589691	1			T22	5		T25	5		T26	6
all_values[11]	auto[1]	auto[0]	auto[1]	126017	1			T22	2		T25	2		T27	1
all_values[11]	auto[1]	auto[1]	auto[1]	126110	1			T22	4		T25	2		T28	1
all_values[12]	auto[0]	auto[0]	auto[0]	3111423	1			T22	15		T23	1		T24	1
all_values[12]	auto[0]	auto[0]	auto[1]	8635285	1			T24	8		T25	3		T26	12
all_values[12]	auto[0]	auto[1]	auto[0]	894279	1			T22	5		T25	8		T26	5
all_values[12]	auto[0]	auto[1]	auto[1]	8546636	1			T22	7		T25	2		T26	3
all_values[12]	auto[1]	auto[0]	auto[1]	126460	1			T22	2		T25	1		T27	2
all_values[12]	auto[1]	auto[1]	auto[1]	125282	1			T22	1		T25	1		T28	1
all_values[13]	auto[0]	auto[0]	auto[0]	3123223	1			T22	6		T23	1		T24	1
all_values[13]	auto[0]	auto[0]	auto[1]	8589558	1			T22	3		T24	8		T25	7
all_values[13]	auto[0]	auto[1]	auto[0]	906417	1			T22	13		T26	5		T27	11
all_values[13]	auto[0]	auto[1]	auto[1]	8567438	1			T22	3		T25	6		T26	7
all_values[13]	auto[1]	auto[0]	auto[1]	126900	1			T22	2		T25	4		T27	1
all_values[13]	auto[1]	auto[1]	auto[1]	125829	1			T22	3		T27	2		T28	1
all_values[14]	auto[0]	auto[0]	auto[0]	3108568	1			T22	8		T23	1		T24	1
all_values[14]	auto[0]	auto[0]	auto[1]	8580344	1			T22	2		T24	8		T25	6
all_values[14]	auto[0]	auto[1]	auto[0]	893829	1			T22	7		T25	7		T26	7
all_values[14]	auto[0]	auto[1]	auto[1]	8604724	1			T22	6		T25	6		T26	6
all_values[14]	auto[1]	auto[0]	auto[1]	125908	1			T22	2		T25	2		T27	2
all_values[14]	auto[1]	auto[1]	auto[1]	125992	1			T22	5		T25	5		T27	2
all_values[15]	auto[0]	auto[0]	auto[0]	3101880	1			T22	9		T23	1		T24	2
all_values[15]	auto[0]	auto[0]	auto[1]	8622955	1			T22	6		T24	7		T25	4
all_values[15]	auto[0]	auto[1]	auto[0]	888454	1			T22	8		T25	9		T26	6
all_values[15]	auto[0]	auto[1]	auto[1]	8573913	1			T22	2		T25	2		T26	5
all_values[15]	auto[1]	auto[0]	auto[1]	126542	1			T22	5		T25	4		T27	2
all_values[15]	auto[1]	auto[1]	auto[1]	125621	1			T25	1		T27	2		T28	2
all_values[16]	auto[0]	auto[0]	auto[0]	3100403	1			T22	7		T23	1		T24	1
all_values[16]	auto[0]	auto[0]	auto[1]	8536431	1			T22	3		T24	8		T25	5
all_values[16]	auto[0]	auto[1]	auto[0]	902692	1			T22	5		T25	12		T26	6
all_values[16]	auto[0]	auto[1]	auto[1]	8647799	1			T22	8		T25	2		T26	1
all_values[16]	auto[1]	auto[0]	auto[1]	126358	1			T22	5		T25	4		T13	2
all_values[16]	auto[1]	auto[1]	auto[1]	125682	1			T22	2		T25	2		T27	1
all_values[17]	auto[0]	auto[0]	auto[0]	3109032	1			T22	12		T23	1		T24	1
all_values[17]	auto[0]	auto[0]	auto[1]	8632668	1			T22	5		T24	8		T25	5
all_values[17]	auto[0]	auto[1]	auto[0]	903767	1			T22	4		T25	5		T26	7
all_values[17]	auto[0]	auto[1]	auto[1]	8541747	1			T22	7		T25	6		T26	6
all_values[17]	auto[1]	auto[0]	auto[1]	126033	1			T22	1		T25	3		T27	3
all_values[17]	auto[1]	auto[1]	auto[1]	126118	1			T22	1		T25	1		T27	3
all_values[18]	auto[0]	auto[0]	auto[0]	3106376	1			T22	6		T23	1		T24	1
all_values[18]	auto[0]	auto[0]	auto[1]	8552145	1			T22	6		T24	8		T25	3
all_values[18]	auto[0]	auto[1]	auto[0]	901541	1			T22	12		T25	7		T26	4
all_values[18]	auto[0]	auto[1]	auto[1]	8627125	1			T22	2		T25	5		T26	7
all_values[18]	auto[1]	auto[0]	auto[1]	126215	1			T22	2		T25	3		T27	3
all_values[18]	auto[1]	auto[1]	auto[1]	125963	1			T22	2		T25	1		T27	1
all_values[19]	auto[0]	auto[0]	auto[0]	3110355	1			T22	14		T23	1		T24	1
all_values[19]	auto[0]	auto[0]	auto[1]	8576881	1			T22	1		T24	8		T25	3
all_values[19]	auto[0]	auto[1]	auto[0]	901563	1			T22	11		T25	12		T26	5
all_values[19]	auto[0]	auto[1]	auto[1]	8597299	1			T22	1		T25	2		T26	7
all_values[19]	auto[1]	auto[0]	auto[1]	126531	1			T22	2		T25	3		T28	2
all_values[19]	auto[1]	auto[1]	auto[1]	126736	1			T22	1		T25	3		T27	1
all_values[20]	auto[0]	auto[0]	auto[0]	3108315	1			T22	11		T23	1		T24	1
all_values[20]	auto[0]	auto[0]	auto[1]	8589152	1			T22	12		T24	8		T26	8
all_values[20]	auto[0]	auto[1]	auto[0]	907759	1			T25	10		T26	3		T27	4
all_values[20]	auto[0]	auto[1]	auto[1]	8582263	1			T22	2		T25	9		T26	2
all_values[20]	auto[1]	auto[0]	auto[1]	125260	1			T22	3		T27	3		T28	2
all_values[20]	auto[1]	auto[1]	auto[1]	126616	1			T22	2		T25	3		T27	2
all_values[21]	auto[0]	auto[0]	auto[0]	3107008	1			T22	5		T23	1		T24	9
all_values[21]	auto[0]	auto[0]	auto[1]	8567931	1			T22	2		T25	9		T26	10
all_values[21]	auto[0]	auto[1]	auto[0]	899259	1			T22	9		T25	3		T26	5
all_values[21]	auto[0]	auto[1]	auto[1]	8612596	1			T22	9		T25	2		T26	4
all_values[21]	auto[1]	auto[0]	auto[1]	126592	1			T22	2		T25	5		T27	2
all_values[21]	auto[1]	auto[1]	auto[1]	125979	1			T22	3		T25	4		T27	1
all_values[22]	auto[0]	auto[0]	auto[0]	3100858	1			T22	2		T23	1		T24	9
all_values[22]	auto[0]	auto[0]	auto[1]	8621968	1			T22	4		T25	6		T26	11
all_values[22]	auto[0]	auto[1]	auto[0]	897458	1			T22	10		T25	7		T26	5
all_values[22]	auto[0]	auto[1]	auto[1]	8567092	1			T22	9		T25	1		T26	3
all_values[22]	auto[1]	auto[0]	auto[1]	126699	1			T22	2		T25	2		T27	3
all_values[22]	auto[1]	auto[1]	auto[1]	125290	1			T22	3		T25	2		T12	1
all_values[23]	auto[0]	auto[0]	auto[0]	3101197	1			T22	6		T23	1		T24	4
all_values[23]	auto[0]	auto[0]	auto[1]	8597880	1			T22	3		T24	5		T25	6
all_values[23]	auto[0]	auto[1]	auto[0]	906192	1			T22	9		T25	10		T26	7
all_values[23]	auto[0]	auto[1]	auto[1]	8581314	1			T22	7		T25	2		T26	2
all_values[23]	auto[1]	auto[0]	auto[1]	127151	1			T22	2		T25	3		T27	3
all_values[23]	auto[1]	auto[1]	auto[1]	125631	1			T22	3		T25	3		T28	2
all_values[24]	auto[0]	auto[0]	auto[0]	3108531	1			T22	5		T23	1		T24	1
all_values[24]	auto[0]	auto[0]	auto[1]	8574103	1			T22	2		T24	8		T25	3
all_values[24]	auto[0]	auto[1]	auto[0]	917899	1			T22	14		T25	8		T26	5
all_values[24]	auto[0]	auto[1]	auto[1]	8586672	1			T22	4		T25	4		T26	3
all_values[24]	auto[1]	auto[0]	auto[1]	126573	1			T22	2		T25	2		T27	1
all_values[24]	auto[1]	auto[1]	auto[1]	125587	1			T22	3		T25	2		T27	2
all_values[25]	auto[0]	auto[0]	auto[0]	3109050	1			T22	14		T23	1		T24	9
all_values[25]	auto[0]	auto[0]	auto[1]	8571605	1			T22	6		T26	10		T27	3
all_values[25]	auto[0]	auto[1]	auto[0]	904716	1			T22	4		T25	8		T26	5
all_values[25]	auto[0]	auto[1]	auto[1]	8602193	1			T22	3		T25	3		T26	4
all_values[25]	auto[1]	auto[0]	auto[1]	126231	1			T22	2		T25	1		T27	2
all_values[25]	auto[1]	auto[1]	auto[1]	125570	1			T22	1		T25	2		T27	1
all_values[26]	auto[0]	auto[0]	auto[0]	3110717	1			T22	10		T23	1		T24	1
all_values[26]	auto[0]	auto[0]	auto[1]	8590051	1			T24	8		T25	3		T26	9
all_values[26]	auto[0]	auto[1]	auto[0]	906859	1			T22	7		T25	7		T26	3
all_values[26]	auto[0]	auto[1]	auto[1]	8579584	1			T22	8		T25	2		T26	7
all_values[26]	auto[1]	auto[0]	auto[1]	126220	1			T22	1		T25	2		T27	1
all_values[26]	auto[1]	auto[1]	auto[1]	125934	1			T22	4		T25	3		T28	1
all_values[27]	auto[0]	auto[0]	auto[0]	3097337	1			T22	15		T23	1		T24	1
all_values[27]	auto[0]	auto[0]	auto[1]	8601046	1			T24	8		T25	8		T26	9
all_values[27]	auto[0]	auto[1]	auto[0]	910367	1			T22	14		T25	6		T26	3
all_values[27]	auto[0]	auto[1]	auto[1]	8578535	1			T25	3		T26	6		T27	7
all_values[27]	auto[1]	auto[0]	auto[1]	126924	1			T25	4		T28	2		T12	1
all_values[27]	auto[1]	auto[1]	auto[1]	125156	1			T22	1		T25	1		T27	3
all_values[28]	auto[0]	auto[0]	auto[0]	3109188	1			T22	9		T23	1		T24	1
all_values[28]	auto[0]	auto[0]	auto[1]	8609668	1			T22	6		T24	8		T26	9
all_values[28]	auto[0]	auto[1]	auto[0]	900045	1			T22	1		T25	7		T26	5
all_values[28]	auto[0]	auto[1]	auto[1]	8568547	1			T22	8		T25	1		T26	3
all_values[28]	auto[1]	auto[0]	auto[1]	126458	1			T22	4		T25	4		T27	1
all_values[28]	auto[1]	auto[1]	auto[1]	125459	1			T22	2		T28	1		T12	1
all_values[29]	auto[0]	auto[0]	auto[0]	3104768	1			T22	11		T23	1		T24	9
all_values[29]	auto[0]	auto[0]	auto[1]	8575825	1			T22	6		T25	3		T26	6
all_values[29]	auto[0]	auto[1]	auto[0]	907177	1			T22	5		T25	10		T26	5
all_values[29]	auto[0]	auto[1]	auto[1]	8599157	1			T22	3		T25	4		T26	7
all_values[29]	auto[1]	auto[0]	auto[1]	126721	1			T22	2		T25	4		T27	1
all_values[29]	auto[1]	auto[1]	auto[1]	125717	1			T22	3		T25	3		T27	3
all_values[30]	auto[0]	auto[0]	auto[0]	3116561	1			T22	5		T23	1		T24	9
all_values[30]	auto[0]	auto[0]	auto[1]	8579410	1			T22	4		T25	5		T26	11
all_values[30]	auto[0]	auto[1]	auto[0]	896945	1			T22	6		T25	7		T26	4
all_values[30]	auto[0]	auto[1]	auto[1]	8594559	1			T22	10		T25	2		T26	5
all_values[30]	auto[1]	auto[0]	auto[1]	125691	1			T22	1		T25	1		T27	2
all_values[30]	auto[1]	auto[1]	auto[1]	126199	1			T22	4		T25	3		T27	2
all_values[31]	auto[0]	auto[0]	auto[0]	3111809	1			T22	16		T23	1		T24	9
all_values[31]	auto[0]	auto[0]	auto[1]	8561010	1			T22	4		T25	9		T26	11
all_values[31]	auto[0]	auto[1]	auto[0]	898818	1			T22	8		T25	8		T26	6
all_values[31]	auto[0]	auto[1]	auto[1]	8616140	1			T22	1		T25	2		T28	4
all_values[31]	auto[1]	auto[0]	auto[1]	125824	1			T22	1		T25	3		T27	3
all_values[31]	auto[1]	auto[1]	auto[1]	125764	1			T25	4		T27	1		T28	3

User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins

NAME	COUNT	STATUS
test_1_state_0	0	Illegal