Unified Coverage Report :: Group :: gpio_env_pkg::gpio_env_cov::data_out_data_oe_data_in_cross_cg

Group : gpio_env_pkg::gpio_env_cov::data_out_data_oe_data_in_cross_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_gpio_env_0.1/gpio_env_cov.sv

---

Summary for Group gpio_env_pkg::gpio_env_cov::data_out_data_oe_data_in_cross_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	192	0	192	100.00

Variables for Group gpio_env_pkg::gpio_env_cov::data_out_data_oe_data_in_cross_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_pin	32	0	32	100.00	100	1	1	0
data_in	2	0	2	100.00	100	1	1	2
data_oe	2	0	2	100.00	100	1	1	2
data_out	2	0	2	100.00	100	1	1	2

Crosses for Group gpio_env_pkg::gpio_env_cov::data_out_data_oe_data_in_cross_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_cross_all	192	0	192	100.00	100	1	1	0

Summary for Variable cp_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	32	0	32	100.00

User Defined Bins for cp_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
bins_for_gpio_bits[0]	21127598	1			T22	1		T23	1		T24	9
bins_for_gpio_bits[1]	21127598	1			T22	1		T23	1		T24	9
bins_for_gpio_bits[2]	21127598	1			T22	1		T23	1		T24	9
bins_for_gpio_bits[3]	21127598	1			T22	1		T23	1		T24	9
bins_for_gpio_bits[4]	21127598	1			T22	1		T23	1		T24	9
bins_for_gpio_bits[5]	21127598	1			T22	1		T23	1		T24	9
bins_for_gpio_bits[6]	21127598	1			T22	1		T23	1		T24	9
bins_for_gpio_bits[7]	21127598	1			T22	1		T23	1		T24	9
bins_for_gpio_bits[8]	21127598	1			T22	1		T23	1		T24	9
bins_for_gpio_bits[9]	21127598	1			T22	1		T23	1		T24	9
bins_for_gpio_bits[10]	21127598	1			T22	1		T23	1		T24	9
bins_for_gpio_bits[11]	21127598	1			T22	1		T23	1		T24	9
bins_for_gpio_bits[12]	21127598	1			T22	1		T23	1		T24	9
bins_for_gpio_bits[13]	21127598	1			T22	1		T23	1		T24	9
bins_for_gpio_bits[14]	21127598	1			T22	1		T23	1		T24	9
bins_for_gpio_bits[15]	21127598	1			T22	1		T23	1		T24	9
bins_for_gpio_bits[16]	21127598	1			T22	1		T23	1		T24	9
bins_for_gpio_bits[17]	21127598	1			T22	1		T23	1		T24	9
bins_for_gpio_bits[18]	21127598	1			T22	1		T23	1		T24	9
bins_for_gpio_bits[19]	21127598	1			T22	1		T23	1		T24	9
bins_for_gpio_bits[20]	21127598	1			T22	1		T23	1		T24	9
bins_for_gpio_bits[21]	21127598	1			T22	1		T23	1		T24	9
bins_for_gpio_bits[22]	21127598	1			T22	1		T23	1		T24	9
bins_for_gpio_bits[23]	21127598	1			T22	1		T23	1		T24	9
bins_for_gpio_bits[24]	21127598	1			T22	1		T23	1		T24	9
bins_for_gpio_bits[25]	21127598	1			T22	1		T23	1		T24	9
bins_for_gpio_bits[26]	21127598	1			T22	1		T23	1		T24	9
bins_for_gpio_bits[27]	21127598	1			T22	1		T23	1		T24	9
bins_for_gpio_bits[28]	21127598	1			T22	1		T23	1		T24	9
bins_for_gpio_bits[29]	21127598	1			T22	1		T23	1		T24	9
bins_for_gpio_bits[30]	21127598	1			T22	1		T23	1		T24	9
bins_for_gpio_bits[31]	21127598	1			T22	1		T23	1		T24	9

---

Summary for Variable data_in

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for data_in

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

413683387

1

T22

32

T23

32

T24

288

auto[1]

262399749

1

T44

5897

T45

7831

T46

11956

---

Summary for Variable data_oe

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for data_oe

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

535345704

1

T22

32

T23

32

T24

288

auto[1]

140737432

1

T44

9220

T45

11738

T46

5671

---

Summary for Variable data_out

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for data_out

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

494380096

1

T22

32

T23

32

T24

288

auto[1]

181703040

1

T44

9282

T45

11782

T46

5880

---

Summary for Cross cp_cross_all

Samples crossed: cp_pin data_out data_oe data_in

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	192	0	192	100.00
Automatically Generated Cross Bins	192	0	192	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cp_cross_all

Bins

cp_pin	data_out	data_oe	data_in	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
bins_for_gpio_bits[0]	auto[0]	auto[0]	auto[0]	7810289	1			T22	1		T23	1		T24	9
bins_for_gpio_bits[0]	auto[0]	auto[0]	auto[1]	5425632	1			T44	33		T45	63		T46	175
bins_for_gpio_bits[0]	auto[0]	auto[1]	auto[0]	2204257	1			T44	155		T45	162		T46	73
bins_for_gpio_bits[0]	auto[1]	auto[0]	auto[0]	2900684	1			T44	142		T45	158		T58	78
bins_for_gpio_bits[0]	auto[1]	auto[0]	auto[1]	587217	1			T46	100		T112	141		T113	170
bins_for_gpio_bits[0]	auto[1]	auto[1]	auto[1]	2199519	1			T44	154		T45	222		T46	108
bins_for_gpio_bits[1]	auto[0]	auto[0]	auto[0]	7830964	1			T22	1		T23	1		T24	9
bins_for_gpio_bits[1]	auto[0]	auto[0]	auto[1]	5415901	1			T44	41		T45	53		T46	193
bins_for_gpio_bits[1]	auto[0]	auto[1]	auto[0]	2209941	1			T44	140		T45	200		T46	76
bins_for_gpio_bits[1]	auto[1]	auto[0]	auto[0]	2896170	1			T44	146		T45	172		T58	92
bins_for_gpio_bits[1]	auto[1]	auto[0]	auto[1]	584115	1			T46	92		T112	143		T113	196
bins_for_gpio_bits[1]	auto[1]	auto[1]	auto[1]	2190507	1			T44	149		T45	176		T46	96
bins_for_gpio_bits[2]	auto[0]	auto[0]	auto[0]	7802244	1			T22	1		T23	1		T24	9
bins_for_gpio_bits[2]	auto[0]	auto[0]	auto[1]	5426548	1			T44	32		T45	62		T46	210
bins_for_gpio_bits[2]	auto[0]	auto[1]	auto[0]	2207180	1			T44	123		T45	159		T46	84
bins_for_gpio_bits[2]	auto[1]	auto[0]	auto[0]	2910697	1			T44	158		T45	174		T58	72
bins_for_gpio_bits[2]	auto[1]	auto[0]	auto[1]	587225	1			T46	87		T112	136		T113	198
bins_for_gpio_bits[2]	auto[1]	auto[1]	auto[1]	2193704	1			T44	154		T45	202		T46	80
bins_for_gpio_bits[3]	auto[0]	auto[0]	auto[0]	7811347	1			T22	1		T23	1		T24	9
bins_for_gpio_bits[3]	auto[0]	auto[0]	auto[1]	5425162	1			T44	43		T45	61		T46	185
bins_for_gpio_bits[3]	auto[0]	auto[1]	auto[0]	2215342	1			T44	115		T45	180		T46	103
bins_for_gpio_bits[3]	auto[1]	auto[0]	auto[0]	2895699	1			T44	150		T45	178		T58	114
bins_for_gpio_bits[3]	auto[1]	auto[0]	auto[1]	585046	1			T46	70		T112	100		T113	157
bins_for_gpio_bits[3]	auto[1]	auto[1]	auto[1]	2195002	1			T44	150		T45	225		T46	98
bins_for_gpio_bits[4]	auto[0]	auto[0]	auto[0]	7805559	1			T22	1		T23	1		T24	9
bins_for_gpio_bits[4]	auto[0]	auto[0]	auto[1]	5429352	1			T44	40		T45	58		T46	218
bins_for_gpio_bits[4]	auto[0]	auto[1]	auto[0]	2213043	1			T44	142		T45	190		T46	92
bins_for_gpio_bits[4]	auto[1]	auto[0]	auto[0]	2898131	1			T44	122		T45	178		T58	98
bins_for_gpio_bits[4]	auto[1]	auto[0]	auto[1]	585150	1			T46	79		T112	114		T113	176
bins_for_gpio_bits[4]	auto[1]	auto[1]	auto[1]	2196363	1			T44	154		T45	170		T46	72
bins_for_gpio_bits[5]	auto[0]	auto[0]	auto[0]	7822956	1			T22	1		T23	1		T24	9
bins_for_gpio_bits[5]	auto[0]	auto[0]	auto[1]	5416021	1			T44	32		T45	54		T46	205
bins_for_gpio_bits[5]	auto[0]	auto[1]	auto[0]	2213193	1			T44	151		T45	144		T46	81
bins_for_gpio_bits[5]	auto[1]	auto[0]	auto[0]	2897574	1			T44	118		T45	216		T58	91
bins_for_gpio_bits[5]	auto[1]	auto[0]	auto[1]	586452	1			T46	96		T112	128		T113	170
bins_for_gpio_bits[5]	auto[1]	auto[1]	auto[1]	2191402	1			T44	166		T45	200		T46	80
bins_for_gpio_bits[6]	auto[0]	auto[0]	auto[0]	7819425	1			T22	1		T23	1		T24	9
bins_for_gpio_bits[6]	auto[0]	auto[0]	auto[1]	5426433	1			T44	43		T45	63		T46	175
bins_for_gpio_bits[6]	auto[0]	auto[1]	auto[0]	2212382	1			T44	118		T45	189		T46	86
bins_for_gpio_bits[6]	auto[1]	auto[0]	auto[0]	2898184	1			T44	158		T45	188		T58	74
bins_for_gpio_bits[6]	auto[1]	auto[0]	auto[1]	585550	1			T46	84		T112	116		T113	140
bins_for_gpio_bits[6]	auto[1]	auto[1]	auto[1]	2185624	1			T44	170		T45	212		T46	115
bins_for_gpio_bits[7]	auto[0]	auto[0]	auto[0]	7810298	1			T22	1		T23	1		T24	9
bins_for_gpio_bits[7]	auto[0]	auto[0]	auto[1]	5427717	1			T44	23		T45	51		T46	180
bins_for_gpio_bits[7]	auto[0]	auto[1]	auto[0]	2211588	1			T44	115		T45	152		T46	85
bins_for_gpio_bits[7]	auto[1]	auto[0]	auto[0]	2896322	1			T44	142		T45	190		T58	77
bins_for_gpio_bits[7]	auto[1]	auto[0]	auto[1]	583810	1			T46	120		T112	161		T113	162
bins_for_gpio_bits[7]	auto[1]	auto[1]	auto[1]	2197863	1			T44	158		T45	169		T46	76
bins_for_gpio_bits[8]	auto[0]	auto[0]	auto[0]	7795865	1			T22	1		T23	1		T24	9
bins_for_gpio_bits[8]	auto[0]	auto[0]	auto[1]	5429600	1			T44	43		T45	52		T46	180
bins_for_gpio_bits[8]	auto[0]	auto[1]	auto[0]	2214922	1			T44	172		T45	160		T46	88
bins_for_gpio_bits[8]	auto[1]	auto[0]	auto[0]	2905236	1			T44	116		T45	164		T58	92
bins_for_gpio_bits[8]	auto[1]	auto[0]	auto[1]	588622	1			T46	107		T112	121		T113	154
bins_for_gpio_bits[8]	auto[1]	auto[1]	auto[1]	2193353	1			T44	164		T45	204		T46	80
bins_for_gpio_bits[9]	auto[0]	auto[0]	auto[0]	7815805	1			T22	1		T23	1		T24	9
bins_for_gpio_bits[9]	auto[0]	auto[0]	auto[1]	5419188	1			T44	32		T45	58		T46	199
bins_for_gpio_bits[9]	auto[0]	auto[1]	auto[0]	2208357	1			T44	170		T45	184		T46	75
bins_for_gpio_bits[9]	auto[1]	auto[0]	auto[0]	2901351	1			T44	109		T45	191		T58	68
bins_for_gpio_bits[9]	auto[1]	auto[0]	auto[1]	587911	1			T46	114		T112	118		T113	172
bins_for_gpio_bits[9]	auto[1]	auto[1]	auto[1]	2194986	1			T44	126		T45	172		T46	82
bins_for_gpio_bits[10]	auto[0]	auto[0]	auto[0]	7815486	1			T22	1		T23	1		T24	9
bins_for_gpio_bits[10]	auto[0]	auto[0]	auto[1]	5427141	1			T44	45		T45	59		T46	191
bins_for_gpio_bits[10]	auto[0]	auto[1]	auto[0]	2214629	1			T44	162		T45	174		T46	104
bins_for_gpio_bits[10]	auto[1]	auto[0]	auto[0]	2894368	1			T44	130		T45	144		T58	76
bins_for_gpio_bits[10]	auto[1]	auto[0]	auto[1]	582253	1			T46	94		T112	136		T113	188
bins_for_gpio_bits[10]	auto[1]	auto[1]	auto[1]	2193721	1			T44	130		T45	243		T46	85
bins_for_gpio_bits[11]	auto[0]	auto[0]	auto[0]	7813421	1			T22	1		T23	1		T24	9
bins_for_gpio_bits[11]	auto[0]	auto[0]	auto[1]	5430766	1			T44	42		T45	61		T46	201
bins_for_gpio_bits[11]	auto[0]	auto[1]	auto[0]	2213323	1			T44	118		T45	182		T46	97
bins_for_gpio_bits[11]	auto[1]	auto[0]	auto[0]	2893943	1			T44	173		T45	169		T58	92
bins_for_gpio_bits[11]	auto[1]	auto[0]	auto[1]	585202	1			T46	92		T112	133		T113	185
bins_for_gpio_bits[11]	auto[1]	auto[1]	auto[1]	2190943	1			T44	146		T45	182		T46	68
bins_for_gpio_bits[12]	auto[0]	auto[0]	auto[0]	7816597	1			T22	1		T23	1		T24	9
bins_for_gpio_bits[12]	auto[0]	auto[0]	auto[1]	5418104	1			T44	34		T45	67		T46	192
bins_for_gpio_bits[12]	auto[0]	auto[1]	auto[0]	2213829	1			T44	130		T45	186		T46	90
bins_for_gpio_bits[12]	auto[1]	auto[0]	auto[0]	2901939	1			T44	156		T45	186		T58	92
bins_for_gpio_bits[12]	auto[1]	auto[0]	auto[1]	585407	1			T46	73		T112	110		T113	170
bins_for_gpio_bits[12]	auto[1]	auto[1]	auto[1]	2191722	1			T44	159		T45	170		T46	98
bins_for_gpio_bits[13]	auto[0]	auto[0]	auto[0]	7808322	1			T22	1		T23	1		T24	9
bins_for_gpio_bits[13]	auto[0]	auto[0]	auto[1]	5419530	1			T44	34		T45	69		T46	209
bins_for_gpio_bits[13]	auto[0]	auto[1]	auto[0]	2203002	1			T44	114		T45	194		T46	94
bins_for_gpio_bits[13]	auto[1]	auto[0]	auto[0]	2908895	1			T44	156		T45	161		T58	85
bins_for_gpio_bits[13]	auto[1]	auto[0]	auto[1]	588009	1			T46	80		T112	120		T113	182
bins_for_gpio_bits[13]	auto[1]	auto[1]	auto[1]	2199840	1			T44	155		T45	174		T46	87
bins_for_gpio_bits[14]	auto[0]	auto[0]	auto[0]	7814240	1			T22	1		T23	1		T24	9
bins_for_gpio_bits[14]	auto[0]	auto[0]	auto[1]	5429925	1			T44	30		T45	49		T46	192
bins_for_gpio_bits[14]	auto[0]	auto[1]	auto[0]	2219195	1			T44	148		T45	183		T46	82
bins_for_gpio_bits[14]	auto[1]	auto[0]	auto[0]	2894832	1			T44	126		T45	202		T58	108
bins_for_gpio_bits[14]	auto[1]	auto[0]	auto[1]	583151	1			T46	98		T112	140		T113	164
bins_for_gpio_bits[14]	auto[1]	auto[1]	auto[1]	2186255	1			T44	193		T45	194		T46	102
bins_for_gpio_bits[15]	auto[0]	auto[0]	auto[0]	7815202	1			T22	1		T23	1		T24	9
bins_for_gpio_bits[15]	auto[0]	auto[0]	auto[1]	5429123	1			T44	39		T45	63		T46	188
bins_for_gpio_bits[15]	auto[0]	auto[1]	auto[0]	2212380	1			T44	169		T45	184		T46	90
bins_for_gpio_bits[15]	auto[1]	auto[0]	auto[0]	2895109	1			T44	140		T45	188		T58	78
bins_for_gpio_bits[15]	auto[1]	auto[0]	auto[1]	583202	1			T46	105		T112	145		T113	186
bins_for_gpio_bits[15]	auto[1]	auto[1]	auto[1]	2192582	1			T44	136		T45	152		T46	78
bins_for_gpio_bits[16]	auto[0]	auto[0]	auto[0]	7811600	1			T22	1		T23	1		T24	9
bins_for_gpio_bits[16]	auto[0]	auto[0]	auto[1]	5426559	1			T44	29		T45	62		T46	189
bins_for_gpio_bits[16]	auto[0]	auto[1]	auto[0]	2202919	1			T44	135		T45	214		T46	94
bins_for_gpio_bits[16]	auto[1]	auto[0]	auto[0]	2910477	1			T44	126		T45	181		T58	95
bins_for_gpio_bits[16]	auto[1]	auto[0]	auto[1]	587515	1			T46	77		T112	154		T113	182
bins_for_gpio_bits[16]	auto[1]	auto[1]	auto[1]	2188528	1			T44	138		T45	170		T46	106
bins_for_gpio_bits[17]	auto[0]	auto[0]	auto[0]	7816030	1			T22	1		T23	1		T24	9
bins_for_gpio_bits[17]	auto[0]	auto[0]	auto[1]	5416542	1			T44	33		T45	64		T46	215
bins_for_gpio_bits[17]	auto[0]	auto[1]	auto[0]	2208280	1			T44	138		T45	184		T46	58
bins_for_gpio_bits[17]	auto[1]	auto[0]	auto[0]	2912638	1			T44	160		T45	171		T58	98
bins_for_gpio_bits[17]	auto[1]	auto[0]	auto[1]	589687	1			T46	80		T112	144		T113	152
bins_for_gpio_bits[17]	auto[1]	auto[1]	auto[1]	2184421	1			T44	111		T45	208		T46	115
bins_for_gpio_bits[18]	auto[0]	auto[0]	auto[0]	7826984	1			T22	1		T23	1		T24	9
bins_for_gpio_bits[18]	auto[0]	auto[0]	auto[1]	5422566	1			T44	31		T45	62		T46	193
bins_for_gpio_bits[18]	auto[0]	auto[1]	auto[0]	2203233	1			T44	142		T45	188		T46	80
bins_for_gpio_bits[18]	auto[1]	auto[0]	auto[0]	2908012	1			T44	138		T45	168		T58	110
bins_for_gpio_bits[18]	auto[1]	auto[0]	auto[1]	583653	1			T46	99		T112	171		T113	164
bins_for_gpio_bits[18]	auto[1]	auto[1]	auto[1]	2183150	1			T44	138		T45	196		T46	84
bins_for_gpio_bits[19]	auto[0]	auto[0]	auto[0]	7818721	1			T22	1		T23	1		T24	9
bins_for_gpio_bits[19]	auto[0]	auto[0]	auto[1]	5426782	1			T44	38		T45	56		T46	164
bins_for_gpio_bits[19]	auto[0]	auto[1]	auto[0]	2208054	1			T44	162		T45	192		T46	90
bins_for_gpio_bits[19]	auto[1]	auto[0]	auto[0]	2902365	1			T44	133		T45	178		T58	66
bins_for_gpio_bits[19]	auto[1]	auto[0]	auto[1]	587750	1			T46	102		T112	122		T113	198
bins_for_gpio_bits[19]	auto[1]	auto[1]	auto[1]	2183926	1			T44	134		T45	181		T46	94
bins_for_gpio_bits[20]	auto[0]	auto[0]	auto[0]	7826556	1			T22	1		T23	1		T24	9
bins_for_gpio_bits[20]	auto[0]	auto[0]	auto[1]	5417845	1			T44	32		T45	52		T46	196
bins_for_gpio_bits[20]	auto[0]	auto[1]	auto[0]	2209568	1			T44	116		T45	198		T46	96
bins_for_gpio_bits[20]	auto[1]	auto[0]	auto[0]	2901973	1			T44	138		T45	190		T58	81
bins_for_gpio_bits[20]	auto[1]	auto[0]	auto[1]	587115	1			T46	84		T112	144		T113	168
bins_for_gpio_bits[20]	auto[1]	auto[1]	auto[1]	2184541	1			T44	145		T45	162		T46	84
bins_for_gpio_bits[21]	auto[0]	auto[0]	auto[0]	7820617	1			T22	1		T23	1		T24	9
bins_for_gpio_bits[21]	auto[0]	auto[0]	auto[1]	5419192	1			T44	41		T45	64		T46	170
bins_for_gpio_bits[21]	auto[0]	auto[1]	auto[0]	2203577	1			T44	135		T45	197		T46	94
bins_for_gpio_bits[21]	auto[1]	auto[0]	auto[0]	2912909	1			T44	142		T45	168		T58	76
bins_for_gpio_bits[21]	auto[1]	auto[0]	auto[1]	585780	1			T46	98		T112	144		T113	177
bins_for_gpio_bits[21]	auto[1]	auto[1]	auto[1]	2185523	1			T44	142		T45	196		T46	102
bins_for_gpio_bits[22]	auto[0]	auto[0]	auto[0]	7815771	1			T22	1		T23	1		T24	9
bins_for_gpio_bits[22]	auto[0]	auto[0]	auto[1]	5431578	1			T44	32		T45	60		T46	171
bins_for_gpio_bits[22]	auto[0]	auto[1]	auto[0]	2202492	1			T44	116		T45	168		T46	99
bins_for_gpio_bits[22]	auto[1]	auto[0]	auto[0]	2907363	1			T44	134		T45	199		T58	69
bins_for_gpio_bits[22]	auto[1]	auto[0]	auto[1]	585446	1			T46	90		T112	114		T113	174
bins_for_gpio_bits[22]	auto[1]	auto[1]	auto[1]	2184948	1			T44	161		T45	180		T46	98
bins_for_gpio_bits[23]	auto[0]	auto[0]	auto[0]	7817845	1			T22	1		T23	1		T24	9
bins_for_gpio_bits[23]	auto[0]	auto[0]	auto[1]	5422643	1			T44	34		T45	52		T46	182
bins_for_gpio_bits[23]	auto[0]	auto[1]	auto[0]	2203994	1			T44	152		T45	200		T46	86
bins_for_gpio_bits[23]	auto[1]	auto[0]	auto[0]	2907275	1			T44	144		T45	187		T58	80
bins_for_gpio_bits[23]	auto[1]	auto[0]	auto[1]	586073	1			T46	100		T112	139		T113	150
bins_for_gpio_bits[23]	auto[1]	auto[1]	auto[1]	2189768	1			T44	168		T45	168		T46	95
bins_for_gpio_bits[24]	auto[0]	auto[0]	auto[0]	7817509	1			T22	1		T23	1		T24	9
bins_for_gpio_bits[24]	auto[0]	auto[0]	auto[1]	5425051	1			T44	39		T45	53		T46	186
bins_for_gpio_bits[24]	auto[0]	auto[1]	auto[0]	2207494	1			T44	134		T45	168		T46	94
bins_for_gpio_bits[24]	auto[1]	auto[0]	auto[0]	2905694	1			T44	176		T45	212		T58	80
bins_for_gpio_bits[24]	auto[1]	auto[0]	auto[1]	587781	1			T46	81		T112	116		T113	162
bins_for_gpio_bits[24]	auto[1]	auto[1]	auto[1]	2184069	1			T44	135		T45	172		T46	106
bins_for_gpio_bits[25]	auto[0]	auto[0]	auto[0]	7811487	1			T22	1		T23	1		T24	9
bins_for_gpio_bits[25]	auto[0]	auto[0]	auto[1]	5425110	1			T44	35		T45	59		T46	191
bins_for_gpio_bits[25]	auto[0]	auto[1]	auto[0]	2209743	1			T44	154		T45	176		T46	64
bins_for_gpio_bits[25]	auto[1]	auto[0]	auto[0]	2907998	1			T44	134		T45	203		T58	64
bins_for_gpio_bits[25]	auto[1]	auto[0]	auto[1]	589431	1			T46	112		T112	137		T113	158
bins_for_gpio_bits[25]	auto[1]	auto[1]	auto[1]	2183829	1			T44	150		T45	176		T46	84
bins_for_gpio_bits[26]	auto[0]	auto[0]	auto[0]	7820588	1			T22	1		T23	1		T24	9
bins_for_gpio_bits[26]	auto[0]	auto[0]	auto[1]	5425407	1			T44	39		T45	54		T46	176
bins_for_gpio_bits[26]	auto[0]	auto[1]	auto[0]	2204067	1			T44	111		T45	214		T46	130
bins_for_gpio_bits[26]	auto[1]	auto[0]	auto[0]	2903422	1			T44	170		T45	157		T58	72
bins_for_gpio_bits[26]	auto[1]	auto[0]	auto[1]	586866	1			T46	65		T112	176		T113	192
bins_for_gpio_bits[26]	auto[1]	auto[1]	auto[1]	2187248	1			T44	142		T45	166		T46	86
bins_for_gpio_bits[27]	auto[0]	auto[0]	auto[0]	7806244	1			T22	1		T23	1		T24	9
bins_for_gpio_bits[27]	auto[0]	auto[0]	auto[1]	5439043	1			T44	34		T45	58		T46	202
bins_for_gpio_bits[27]	auto[0]	auto[1]	auto[0]	2202198	1			T44	134		T45	190		T46	64
bins_for_gpio_bits[27]	auto[1]	auto[0]	auto[0]	2907257	1			T44	129		T45	178		T58	62
bins_for_gpio_bits[27]	auto[1]	auto[0]	auto[1]	586776	1			T46	104		T112	142		T113	174
bins_for_gpio_bits[27]	auto[1]	auto[1]	auto[1]	2186080	1			T44	166		T45	230		T46	88
bins_for_gpio_bits[28]	auto[0]	auto[0]	auto[0]	7816524	1			T22	1		T23	1		T24	9
bins_for_gpio_bits[28]	auto[0]	auto[0]	auto[1]	5423102	1			T44	34		T45	58		T46	167
bins_for_gpio_bits[28]	auto[0]	auto[1]	auto[0]	2209081	1			T44	164		T45	174		T46	84
bins_for_gpio_bits[28]	auto[1]	auto[0]	auto[0]	2901107	1			T44	118		T45	168		T58	91
bins_for_gpio_bits[28]	auto[1]	auto[0]	auto[1]	586200	1			T46	128		T112	126		T113	171
bins_for_gpio_bits[28]	auto[1]	auto[1]	auto[1]	2191584	1			T44	141		T45	179		T46	76
bins_for_gpio_bits[29]	auto[0]	auto[0]	auto[0]	7824784	1			T22	1		T23	1		T24	9
bins_for_gpio_bits[29]	auto[0]	auto[0]	auto[1]	5424677	1			T44	30		T45	62		T46	200
bins_for_gpio_bits[29]	auto[0]	auto[1]	auto[0]	2208949	1			T44	162		T45	176		T46	84
bins_for_gpio_bits[29]	auto[1]	auto[0]	auto[0]	2902600	1			T44	149		T45	208		T58	78
bins_for_gpio_bits[29]	auto[1]	auto[0]	auto[1]	584006	1			T46	86		T112	150		T113	158
bins_for_gpio_bits[29]	auto[1]	auto[1]	auto[1]	2182582	1			T44	150		T45	132		T46	93
bins_for_gpio_bits[30]	auto[0]	auto[0]	auto[0]	7825030	1			T22	1		T23	1		T24	9
bins_for_gpio_bits[30]	auto[0]	auto[0]	auto[1]	5421442	1			T44	41		T45	57		T46	195
bins_for_gpio_bits[30]	auto[0]	auto[1]	auto[0]	2206564	1			T44	131		T45	153		T46	87
bins_for_gpio_bits[30]	auto[1]	auto[0]	auto[0]	2904517	1			T44	150		T45	224		T58	78
bins_for_gpio_bits[30]	auto[1]	auto[0]	auto[1]	584970	1			T46	102		T112	135		T113	158
bins_for_gpio_bits[30]	auto[1]	auto[1]	auto[1]	2185075	1			T44	122		T45	180		T46	82
bins_for_gpio_bits[31]	auto[0]	auto[0]	auto[0]	7832252	1			T22	1		T23	1		T24	9
bins_for_gpio_bits[31]	auto[0]	auto[0]	auto[1]	5421827	1			T44	42		T45	68		T46	186
bins_for_gpio_bits[31]	auto[0]	auto[1]	auto[0]	2201249	1			T44	145		T45	176		T46	96
bins_for_gpio_bits[31]	auto[1]	auto[0]	auto[0]	2904059	1			T44	152		T45	184		T58	92
bins_for_gpio_bits[31]	auto[1]	auto[0]	auto[1]	587462	1			T46	110		T112	137		T113	158
bins_for_gpio_bits[31]	auto[1]	auto[1]	auto[1]	2180749	1			T44	140		T45	184		T46	73

User Defined Cross Bins for cp_cross_all

Excluded/Illegal bins

NAME	COUNT	STATUS
data_oe_1_data_out_0_data_in_1	0	Illegal
data_oe_1_data_out_1_data_in_0	0	Illegal