Group : gpio_env_pkg::gpio_env_cov::gpio_pins_data_in_cross_cg
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Group : gpio_env_pkg::gpio_env_cov::gpio_pins_data_in_cross_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64


Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_gpio_env_0.1/gpio_env_cov.sv



Summary for Group gpio_env_pkg::gpio_env_cov::gpio_pins_data_in_cross_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 36 0 36 100.00
Crosses 128 0 128 100.00


Variables for Group gpio_env_pkg::gpio_env_cov::gpio_pins_data_in_cross_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_pin 32 0 32 100.00 100 1 1 0
data_in 2 0 2 100.00 100 1 1 2
gpio_value 2 0 2 100.00 100 1 1 2


Crosses for Group gpio_env_pkg::gpio_env_cov::gpio_pins_data_in_cross_cg
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
cp_cross_pins_data_in 128 0 128 100.00 100 1 1 0


Summary for Variable cp_pin

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 32 0 32 100.00


User Defined Bins for cp_pin

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
bins_for_gpio_bits[0] 21127598 1 T22 1 T23 1 T24 9
bins_for_gpio_bits[1] 21127598 1 T22 1 T23 1 T24 9
bins_for_gpio_bits[2] 21127598 1 T22 1 T23 1 T24 9
bins_for_gpio_bits[3] 21127598 1 T22 1 T23 1 T24 9
bins_for_gpio_bits[4] 21127598 1 T22 1 T23 1 T24 9
bins_for_gpio_bits[5] 21127598 1 T22 1 T23 1 T24 9
bins_for_gpio_bits[6] 21127598 1 T22 1 T23 1 T24 9
bins_for_gpio_bits[7] 21127598 1 T22 1 T23 1 T24 9
bins_for_gpio_bits[8] 21127598 1 T22 1 T23 1 T24 9
bins_for_gpio_bits[9] 21127598 1 T22 1 T23 1 T24 9
bins_for_gpio_bits[10] 21127598 1 T22 1 T23 1 T24 9
bins_for_gpio_bits[11] 21127598 1 T22 1 T23 1 T24 9
bins_for_gpio_bits[12] 21127598 1 T22 1 T23 1 T24 9
bins_for_gpio_bits[13] 21127598 1 T22 1 T23 1 T24 9
bins_for_gpio_bits[14] 21127598 1 T22 1 T23 1 T24 9
bins_for_gpio_bits[15] 21127598 1 T22 1 T23 1 T24 9
bins_for_gpio_bits[16] 21127598 1 T22 1 T23 1 T24 9
bins_for_gpio_bits[17] 21127598 1 T22 1 T23 1 T24 9
bins_for_gpio_bits[18] 21127598 1 T22 1 T23 1 T24 9
bins_for_gpio_bits[19] 21127598 1 T22 1 T23 1 T24 9
bins_for_gpio_bits[20] 21127598 1 T22 1 T23 1 T24 9
bins_for_gpio_bits[21] 21127598 1 T22 1 T23 1 T24 9
bins_for_gpio_bits[22] 21127598 1 T22 1 T23 1 T24 9
bins_for_gpio_bits[23] 21127598 1 T22 1 T23 1 T24 9
bins_for_gpio_bits[24] 21127598 1 T22 1 T23 1 T24 9
bins_for_gpio_bits[25] 21127598 1 T22 1 T23 1 T24 9
bins_for_gpio_bits[26] 21127598 1 T22 1 T23 1 T24 9
bins_for_gpio_bits[27] 21127598 1 T22 1 T23 1 T24 9
bins_for_gpio_bits[28] 21127598 1 T22 1 T23 1 T24 9
bins_for_gpio_bits[29] 21127598 1 T22 1 T23 1 T24 9
bins_for_gpio_bits[30] 21127598 1 T22 1 T23 1 T24 9
bins_for_gpio_bits[31] 21127598 1 T22 1 T23 1 T24 9



Summary for Variable data_in

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for data_in

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 413683387 1 T22 32 T23 32 T24 288
auto[1] 262399749 1 T44 5897 T45 7831 T46 11956



Summary for Variable gpio_value

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for gpio_value

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 413676180 1 T22 32 T23 32 T24 206
auto[1] 262406956 1 T24 82 T26 242 T2 145



Summary for Cross cp_cross_pins_data_in

Samples crossed: cp_pin gpio_value data_in
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 128 0 128 100.00


Automatically Generated Cross Bins for cp_cross_pins_data_in

Bins
cp_pingpio_valuedata_inCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
bins_for_gpio_bits[0] auto[0] auto[0] 12524467 1 T22 1 T23 1 T24 9
bins_for_gpio_bits[0] auto[0] auto[1] 390520 1 T44 34 T45 44 T46 27
bins_for_gpio_bits[0] auto[1] auto[0] 390763 1 T26 7 T2 4 T18 6
bins_for_gpio_bits[0] auto[1] auto[1] 7821848 1 T44 153 T45 241 T46 356
bins_for_gpio_bits[1] auto[0] auto[0] 12546215 1 T22 1 T23 1 T24 5
bins_for_gpio_bits[1] auto[0] auto[1] 390609 1 T44 42 T45 49 T46 22
bins_for_gpio_bits[1] auto[1] auto[0] 390860 1 T24 4 T26 7 T2 4
bins_for_gpio_bits[1] auto[1] auto[1] 7799914 1 T44 148 T45 180 T46 359
bins_for_gpio_bits[2] auto[0] auto[0] 12529242 1 T22 1 T23 1 T24 5
bins_for_gpio_bits[2] auto[0] auto[1] 390621 1 T44 39 T45 51 T46 23
bins_for_gpio_bits[2] auto[1] auto[0] 390879 1 T24 4 T26 11 T2 4
bins_for_gpio_bits[2] auto[1] auto[1] 7816856 1 T44 147 T45 213 T46 354
bins_for_gpio_bits[3] auto[0] auto[0] 12531063 1 T22 1 T23 1 T24 5
bins_for_gpio_bits[3] auto[0] auto[1] 391087 1 T44 34 T45 53 T46 29
bins_for_gpio_bits[3] auto[1] auto[0] 391325 1 T24 4 T26 3 T2 4
bins_for_gpio_bits[3] auto[1] auto[1] 7814123 1 T44 159 T45 233 T46 324
bins_for_gpio_bits[4] auto[0] auto[0] 12525405 1 T22 1 T23 1 T24 6
bins_for_gpio_bits[4] auto[0] auto[1] 391116 1 T44 34 T45 47 T46 20
bins_for_gpio_bits[4] auto[1] auto[0] 391328 1 T24 3 T26 7 T2 9
bins_for_gpio_bits[4] auto[1] auto[1] 7819749 1 T44 160 T45 181 T46 349
bins_for_gpio_bits[5] auto[0] auto[0] 12542781 1 T22 1 T23 1 T24 5
bins_for_gpio_bits[5] auto[0] auto[1] 390751 1 T44 33 T45 51 T46 25
bins_for_gpio_bits[5] auto[1] auto[0] 390942 1 T24 4 T26 10 T2 3
bins_for_gpio_bits[5] auto[1] auto[1] 7803124 1 T44 165 T45 203 T46 356
bins_for_gpio_bits[6] auto[0] auto[0] 12539945 1 T22 1 T23 1 T24 9
bins_for_gpio_bits[6] auto[0] auto[1] 389841 1 T44 39 T45 57 T46 22
bins_for_gpio_bits[6] auto[1] auto[0] 390046 1 T26 10 T2 5 T14 1
bins_for_gpio_bits[6] auto[1] auto[1] 7807766 1 T44 174 T45 218 T46 352
bins_for_gpio_bits[7] auto[0] auto[0] 12527360 1 T22 1 T23 1 T24 9
bins_for_gpio_bits[7] auto[0] auto[1] 390608 1 T44 34 T45 44 T46 26
bins_for_gpio_bits[7] auto[1] auto[0] 390848 1 T26 11 T2 7 T18 6
bins_for_gpio_bits[7] auto[1] auto[1] 7818782 1 T44 147 T45 176 T46 350
bins_for_gpio_bits[8] auto[0] auto[0] 12525641 1 T22 1 T23 1 T24 9
bins_for_gpio_bits[8] auto[0] auto[1] 390186 1 T44 43 T45 44 T46 23
bins_for_gpio_bits[8] auto[1] auto[0] 390382 1 T26 6 T2 3 T18 11
bins_for_gpio_bits[8] auto[1] auto[1] 7821389 1 T44 164 T45 212 T46 344
bins_for_gpio_bits[9] auto[0] auto[0] 12534849 1 T22 1 T23 1 T24 9
bins_for_gpio_bits[9] auto[0] auto[1] 390414 1 T44 35 T45 47 T46 20
bins_for_gpio_bits[9] auto[1] auto[0] 390664 1 T26 10 T2 3 T11 1
bins_for_gpio_bits[9] auto[1] auto[1] 7811671 1 T44 123 T45 183 T46 375
bins_for_gpio_bits[10] auto[0] auto[0] 12533213 1 T22 1 T23 1 T24 4
bins_for_gpio_bits[10] auto[0] auto[1] 391037 1 T44 43 T45 48 T46 23
bins_for_gpio_bits[10] auto[1] auto[0] 391270 1 T24 5 T26 6 T2 4
bins_for_gpio_bits[10] auto[1] auto[1] 7812078 1 T44 132 T45 254 T46 347
bins_for_gpio_bits[11] auto[0] auto[0] 12530307 1 T22 1 T23 1 T24 9
bins_for_gpio_bits[11] auto[0] auto[1] 390138 1 T44 34 T45 50 T46 24
bins_for_gpio_bits[11] auto[1] auto[0] 390380 1 T26 6 T2 3 T11 1
bins_for_gpio_bits[11] auto[1] auto[1] 7816773 1 T44 154 T45 193 T46 337
bins_for_gpio_bits[12] auto[0] auto[0] 12542126 1 T22 1 T23 1 T24 6
bins_for_gpio_bits[12] auto[0] auto[1] 390029 1 T44 33 T45 42 T46 23
bins_for_gpio_bits[12] auto[1] auto[0] 390239 1 T24 3 T26 9 T2 4
bins_for_gpio_bits[12] auto[1] auto[1] 7805204 1 T44 160 T45 195 T46 340
bins_for_gpio_bits[13] auto[0] auto[0] 12529130 1 T22 1 T23 1 T24 7
bins_for_gpio_bits[13] auto[0] auto[1] 390873 1 T44 34 T45 48 T46 26
bins_for_gpio_bits[13] auto[1] auto[0] 391089 1 T24 2 T26 5 T2 5
bins_for_gpio_bits[13] auto[1] auto[1] 7816506 1 T44 155 T45 195 T46 350
bins_for_gpio_bits[14] auto[0] auto[0] 12538307 1 T22 1 T23 1 T24 6
bins_for_gpio_bits[14] auto[0] auto[1] 389736 1 T44 36 T45 47 T46 22
bins_for_gpio_bits[14] auto[1] auto[0] 389960 1 T24 3 T26 4 T2 2
bins_for_gpio_bits[14] auto[1] auto[1] 7809595 1 T44 187 T45 196 T46 370
bins_for_gpio_bits[15] auto[0] auto[0] 12532021 1 T22 1 T23 1 T24 4
bins_for_gpio_bits[15] auto[0] auto[1] 390438 1 T44 41 T45 46 T46 20
bins_for_gpio_bits[15] auto[1] auto[0] 390670 1 T24 5 T26 7 T2 5
bins_for_gpio_bits[15] auto[1] auto[1] 7814469 1 T44 134 T45 169 T46 351
bins_for_gpio_bits[16] auto[0] auto[0] 12533975 1 T22 1 T23 1 T24 3
bins_for_gpio_bits[16] auto[0] auto[1] 390760 1 T44 36 T45 41 T46 27
bins_for_gpio_bits[16] auto[1] auto[0] 391021 1 T24 6 T26 12 T2 3
bins_for_gpio_bits[16] auto[1] auto[1] 7811842 1 T44 131 T45 191 T46 345
bins_for_gpio_bits[17] auto[0] auto[0] 12545256 1 T22 1 T23 1 T24 4
bins_for_gpio_bits[17] auto[0] auto[1] 391445 1 T44 35 T45 47 T46 18
bins_for_gpio_bits[17] auto[1] auto[0] 391692 1 T24 5 T26 6 T2 6
bins_for_gpio_bits[17] auto[1] auto[1] 7799205 1 T44 109 T45 225 T46 392
bins_for_gpio_bits[18] auto[0] auto[0] 12547404 1 T22 1 T23 1 T24 3
bins_for_gpio_bits[18] auto[0] auto[1] 390568 1 T44 30 T45 48 T46 20
bins_for_gpio_bits[18] auto[1] auto[0] 390825 1 T24 6 T26 6 T2 3
bins_for_gpio_bits[18] auto[1] auto[1] 7798801 1 T44 139 T45 210 T46 356
bins_for_gpio_bits[19] auto[0] auto[0] 12538217 1 T22 1 T23 1 T24 6
bins_for_gpio_bits[19] auto[0] auto[1] 390671 1 T44 37 T45 51 T46 18
bins_for_gpio_bits[19] auto[1] auto[0] 390923 1 T24 3 T26 10 T2 6
bins_for_gpio_bits[19] auto[1] auto[1] 7807787 1 T44 135 T45 186 T46 342
bins_for_gpio_bits[20] auto[0] auto[0] 12546624 1 T22 1 T23 1 T24 4
bins_for_gpio_bits[20] auto[0] auto[1] 391252 1 T44 28 T45 41 T46 26
bins_for_gpio_bits[20] auto[1] auto[0] 391473 1 T24 5 T26 8 T2 4
bins_for_gpio_bits[20] auto[1] auto[1] 7798249 1 T44 149 T45 173 T46 338
bins_for_gpio_bits[21] auto[0] auto[0] 12545888 1 T22 1 T23 1 T24 9
bins_for_gpio_bits[21] auto[0] auto[1] 391000 1 T44 32 T45 49 T46 25
bins_for_gpio_bits[21] auto[1] auto[0] 391215 1 T26 8 T2 3 T11 3
bins_for_gpio_bits[21] auto[1] auto[1] 7799495 1 T44 151 T45 211 T46 345
bins_for_gpio_bits[22] auto[0] auto[0] 12535076 1 T22 1 T23 1 T24 9
bins_for_gpio_bits[22] auto[0] auto[1] 390325 1 T44 33 T45 46 T46 20
bins_for_gpio_bits[22] auto[1] auto[0] 390550 1 T26 6 T2 3 T11 1
bins_for_gpio_bits[22] auto[1] auto[1] 7811647 1 T44 160 T45 194 T46 339
bins_for_gpio_bits[23] auto[0] auto[0] 12537741 1 T22 1 T23 1 T24 5
bins_for_gpio_bits[23] auto[0] auto[1] 391133 1 T44 41 T45 45 T46 18
bins_for_gpio_bits[23] auto[1] auto[0] 391373 1 T24 4 T26 6 T2 2
bins_for_gpio_bits[23] auto[1] auto[1] 7807351 1 T44 161 T45 175 T46 359
bins_for_gpio_bits[24] auto[0] auto[0] 12539978 1 T22 1 T23 1 T24 6
bins_for_gpio_bits[24] auto[0] auto[1] 390501 1 T44 40 T45 50 T46 25
bins_for_gpio_bits[24] auto[1] auto[0] 390719 1 T24 3 T26 5 T2 7
bins_for_gpio_bits[24] auto[1] auto[1] 7806400 1 T44 134 T45 175 T46 348
bins_for_gpio_bits[25] auto[0] auto[0] 12538703 1 T22 1 T23 1 T24 9
bins_for_gpio_bits[25] auto[0] auto[1] 390292 1 T44 40 T45 46 T46 22
bins_for_gpio_bits[25] auto[1] auto[0] 390525 1 T26 7 T2 3 T18 4
bins_for_gpio_bits[25] auto[1] auto[1] 7808078 1 T44 145 T45 189 T46 365
bins_for_gpio_bits[26] auto[0] auto[0] 12537270 1 T22 1 T23 1 T24 4
bins_for_gpio_bits[26] auto[0] auto[1] 390642 1 T44 36 T45 46 T46 27
bins_for_gpio_bits[26] auto[1] auto[0] 390807 1 T24 5 T26 8 T2 5
bins_for_gpio_bits[26] auto[1] auto[1] 7808879 1 T44 145 T45 174 T46 300
bins_for_gpio_bits[27] auto[0] auto[0] 12524557 1 T22 1 T23 1 T24 4
bins_for_gpio_bits[27] auto[0] auto[1] 390932 1 T44 38 T45 56 T46 24
bins_for_gpio_bits[27] auto[1] auto[0] 391142 1 T24 5 T26 13 T2 5
bins_for_gpio_bits[27] auto[1] auto[1] 7820967 1 T44 162 T45 232 T46 370
bins_for_gpio_bits[28] auto[0] auto[0] 12535176 1 T22 1 T23 1 T24 6
bins_for_gpio_bits[28] auto[0] auto[1] 391322 1 T44 40 T45 43 T46 23
bins_for_gpio_bits[28] auto[1] auto[0] 391536 1 T24 3 T26 5 T2 3
bins_for_gpio_bits[28] auto[1] auto[1] 7809564 1 T44 135 T45 194 T46 348
bins_for_gpio_bits[29] auto[0] auto[0] 12545142 1 T22 1 T23 1 T24 9
bins_for_gpio_bits[29] auto[0] auto[1] 390999 1 T44 42 T45 42 T46 27
bins_for_gpio_bits[29] auto[1] auto[0] 391191 1 T26 9 T2 10 T11 2
bins_for_gpio_bits[29] auto[1] auto[1] 7800266 1 T44 138 T45 152 T46 352
bins_for_gpio_bits[30] auto[0] auto[0] 12545194 1 T22 1 T23 1 T24 9
bins_for_gpio_bits[30] auto[0] auto[1] 390721 1 T44 32 T45 46 T46 28
bins_for_gpio_bits[30] auto[1] auto[0] 390917 1 T26 7 T2 5 T18 2
bins_for_gpio_bits[30] auto[1] auto[1] 7800766 1 T44 131 T45 191 T46 351
bins_for_gpio_bits[31] auto[0] auto[0] 12547039 1 T22 1 T23 1 T24 9
bins_for_gpio_bits[31] auto[0] auto[1] 390301 1 T44 36 T45 48 T46 23
bins_for_gpio_bits[31] auto[1] auto[0] 390521 1 T26 7 T2 8 T11 1
bins_for_gpio_bits[31] auto[1] auto[1] 7799737 1 T44 146 T45 204 T46 346

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