Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11838569 |
1 |
|
|
T22 |
7 |
|
T23 |
1 |
|
T24 |
9 |
| auto[1] |
9600796 |
1 |
|
|
T22 |
23 |
|
T25 |
12 |
|
T26 |
9 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
20207322 |
1 |
|
|
T22 |
30 |
|
T23 |
1 |
|
T24 |
9 |
| auto[1] |
1232043 |
1 |
|
|
T80 |
1 |
|
T10 |
1 |
|
T81 |
2 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11816490 |
1 |
|
|
T22 |
30 |
|
T23 |
1 |
|
T24 |
1 |
| auto[1] |
9622875 |
1 |
|
|
T24 |
8 |
|
T26 |
9 |
|
T2 |
3 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
4202341 |
1 |
|
|
T24 |
8 |
|
T26 |
4 |
|
T2 |
2 |
| auto[1] |
auto[0] |
auto[1] |
617263 |
1 |
|
|
T10 |
1 |
|
T109 |
3 |
|
T56 |
24 |
| auto[1] |
auto[1] |
auto[0] |
4188491 |
1 |
|
|
T26 |
5 |
|
T2 |
1 |
|
T18 |
2 |
| auto[1] |
auto[1] |
auto[1] |
614780 |
1 |
|
|
T80 |
1 |
|
T81 |
2 |
|
T56 |
29 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11811321 |
1 |
|
|
T22 |
14 |
|
T23 |
1 |
|
T24 |
9 |
| auto[1] |
9628044 |
1 |
|
|
T22 |
16 |
|
T25 |
17 |
|
T26 |
11 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
20216301 |
1 |
|
|
T22 |
30 |
|
T23 |
1 |
|
T24 |
7 |
| auto[1] |
1223064 |
1 |
|
|
T24 |
2 |
|
T11 |
1 |
|
T18 |
4 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11871084 |
1 |
|
|
T22 |
30 |
|
T23 |
1 |
|
T24 |
1 |
| auto[1] |
9568281 |
1 |
|
|
T24 |
8 |
|
T26 |
6 |
|
T2 |
6 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
4158221 |
1 |
|
|
T24 |
6 |
|
T26 |
2 |
|
T2 |
5 |
| auto[1] |
auto[0] |
auto[1] |
608378 |
1 |
|
|
T24 |
2 |
|
T11 |
1 |
|
T18 |
3 |
| auto[1] |
auto[1] |
auto[0] |
4186996 |
1 |
|
|
T26 |
4 |
|
T2 |
1 |
|
T11 |
2 |
| auto[1] |
auto[1] |
auto[1] |
614686 |
1 |
|
|
T18 |
1 |
|
T107 |
1 |
|
T114 |
1 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11854506 |
1 |
|
|
T22 |
29 |
|
T23 |
1 |
|
T24 |
9 |
| auto[1] |
9584859 |
1 |
|
|
T22 |
1 |
|
T25 |
8 |
|
T26 |
12 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
20208169 |
1 |
|
|
T22 |
30 |
|
T23 |
1 |
|
T24 |
7 |
| auto[1] |
1231196 |
1 |
|
|
T24 |
2 |
|
T104 |
1 |
|
T80 |
1 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11818713 |
1 |
|
|
T22 |
30 |
|
T23 |
1 |
|
T24 |
1 |
| auto[1] |
9620652 |
1 |
|
|
T24 |
8 |
|
T26 |
11 |
|
T2 |
3 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
4215136 |
1 |
|
|
T24 |
6 |
|
T26 |
5 |
|
T2 |
2 |
| auto[1] |
auto[0] |
auto[1] |
620743 |
1 |
|
|
T24 |
2 |
|
T104 |
1 |
|
T105 |
1 |
| auto[1] |
auto[1] |
auto[0] |
4174320 |
1 |
|
|
T26 |
6 |
|
T2 |
1 |
|
T80 |
1 |
| auto[1] |
auto[1] |
auto[1] |
610453 |
1 |
|
|
T80 |
1 |
|
T3 |
1 |
|
T109 |
1 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11822868 |
1 |
|
|
T22 |
12 |
|
T23 |
1 |
|
T24 |
9 |
| auto[1] |
9616497 |
1 |
|
|
T22 |
18 |
|
T25 |
10 |
|
T26 |
15 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
20215565 |
1 |
|
|
T22 |
30 |
|
T23 |
1 |
|
T24 |
9 |
| auto[1] |
1223800 |
1 |
|
|
T104 |
2 |
|
T10 |
1 |
|
T81 |
2 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11861734 |
1 |
|
|
T22 |
30 |
|
T23 |
1 |
|
T24 |
1 |
| auto[1] |
9577631 |
1 |
|
|
T24 |
8 |
|
T26 |
11 |
|
T2 |
4 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
4199241 |
1 |
|
|
T24 |
8 |
|
T26 |
5 |
|
T2 |
3 |
| auto[1] |
auto[0] |
auto[1] |
615392 |
1 |
|
|
T104 |
2 |
|
T10 |
1 |
|
T81 |
2 |
| auto[1] |
auto[1] |
auto[0] |
4154590 |
1 |
|
|
T26 |
6 |
|
T2 |
1 |
|
T80 |
2 |
| auto[1] |
auto[1] |
auto[1] |
608408 |
1 |
|
|
T109 |
1 |
|
T56 |
19 |
|
T74 |
5459 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11873168 |
1 |
|
|
T22 |
17 |
|
T23 |
1 |
|
T24 |
9 |
| auto[1] |
9566197 |
1 |
|
|
T22 |
13 |
|
T25 |
11 |
|
T26 |
8 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
20207823 |
1 |
|
|
T22 |
30 |
|
T23 |
1 |
|
T24 |
9 |
| auto[1] |
1231542 |
1 |
|
|
T18 |
2 |
|
T108 |
1 |
|
T109 |
11 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11807414 |
1 |
|
|
T22 |
30 |
|
T23 |
1 |
|
T24 |
9 |
| auto[1] |
9631951 |
1 |
|
|
T26 |
4 |
|
T2 |
2 |
|
T18 |
19 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
4221268 |
1 |
|
|
T26 |
3 |
|
T18 |
17 |
|
T79 |
6 |
| auto[1] |
auto[0] |
auto[1] |
618900 |
1 |
|
|
T18 |
2 |
|
T109 |
9 |
|
T56 |
26 |
| auto[1] |
auto[1] |
auto[0] |
4179141 |
1 |
|
|
T26 |
1 |
|
T2 |
2 |
|
T108 |
1 |
| auto[1] |
auto[1] |
auto[1] |
612642 |
1 |
|
|
T108 |
1 |
|
T109 |
2 |
|
T56 |
23 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11839681 |
1 |
|
|
T22 |
11 |
|
T23 |
1 |
|
T24 |
9 |
| auto[1] |
9599684 |
1 |
|
|
T22 |
19 |
|
T25 |
6 |
|
T26 |
12 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
20214601 |
1 |
|
|
T22 |
30 |
|
T23 |
1 |
|
T24 |
7 |
| auto[1] |
1224764 |
1 |
|
|
T24 |
2 |
|
T18 |
3 |
|
T80 |
1 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11864638 |
1 |
|
|
T22 |
30 |
|
T23 |
1 |
|
T24 |
1 |
| auto[1] |
9574727 |
1 |
|
|
T24 |
8 |
|
T26 |
10 |
|
T2 |
4 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
4168332 |
1 |
|
|
T24 |
6 |
|
T26 |
5 |
|
T2 |
1 |
| auto[1] |
auto[0] |
auto[1] |
611678 |
1 |
|
|
T24 |
2 |
|
T18 |
3 |
|
T109 |
4 |
| auto[1] |
auto[1] |
auto[0] |
4181631 |
1 |
|
|
T26 |
5 |
|
T2 |
3 |
|
T11 |
1 |
| auto[1] |
auto[1] |
auto[1] |
613086 |
1 |
|
|
T80 |
1 |
|
T105 |
1 |
|
T109 |
1 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11814820 |
1 |
|
|
T22 |
12 |
|
T23 |
1 |
|
T24 |
9 |
| auto[1] |
9624545 |
1 |
|
|
T22 |
18 |
|
T25 |
18 |
|
T26 |
13 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
20207047 |
1 |
|
|
T22 |
30 |
|
T23 |
1 |
|
T24 |
9 |
| auto[1] |
1232318 |
1 |
|
|
T18 |
4 |
|
T104 |
2 |
|
T10 |
1 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11808551 |
1 |
|
|
T22 |
30 |
|
T23 |
1 |
|
T24 |
9 |
| auto[1] |
9630814 |
1 |
|
|
T26 |
9 |
|
T2 |
5 |
|
T11 |
1 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
4182259 |
1 |
|
|
T26 |
4 |
|
T2 |
3 |
|
T11 |
1 |
| auto[1] |
auto[0] |
auto[1] |
611964 |
1 |
|
|
T18 |
4 |
|
T104 |
2 |
|
T107 |
3 |
| auto[1] |
auto[1] |
auto[0] |
4216237 |
1 |
|
|
T26 |
5 |
|
T2 |
2 |
|
T3 |
14 |
| auto[1] |
auto[1] |
auto[1] |
620354 |
1 |
|
|
T10 |
1 |
|
T109 |
2 |
|
T56 |
17 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11851377 |
1 |
|
|
T22 |
20 |
|
T23 |
1 |
|
T24 |
9 |
| auto[1] |
9587988 |
1 |
|
|
T22 |
10 |
|
T25 |
12 |
|
T26 |
11 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
20205692 |
1 |
|
|
T22 |
30 |
|
T23 |
1 |
|
T24 |
8 |
| auto[1] |
1233673 |
1 |
|
|
T24 |
1 |
|
T3 |
3 |
|
T107 |
2 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11809626 |
1 |
|
|
T22 |
30 |
|
T23 |
1 |
|
T24 |
1 |
| auto[1] |
9629739 |
1 |
|
|
T24 |
8 |
|
T26 |
9 |
|
T2 |
5 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
4210837 |
1 |
|
|
T24 |
7 |
|
T26 |
5 |
|
T2 |
4 |
| auto[1] |
auto[0] |
auto[1] |
618178 |
1 |
|
|
T24 |
1 |
|
T81 |
3 |
|
T109 |
4 |
| auto[1] |
auto[1] |
auto[0] |
4185229 |
1 |
|
|
T26 |
4 |
|
T2 |
1 |
|
T11 |
1 |
| auto[1] |
auto[1] |
auto[1] |
615495 |
1 |
|
|
T3 |
3 |
|
T107 |
2 |
|
T109 |
5 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11763192 |
1 |
|
|
T22 |
15 |
|
T23 |
1 |
|
T24 |
9 |
| auto[1] |
9676173 |
1 |
|
|
T22 |
15 |
|
T25 |
16 |
|
T26 |
7 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
20212682 |
1 |
|
|
T22 |
30 |
|
T23 |
1 |
|
T24 |
9 |
| auto[1] |
1226683 |
1 |
|
|
T11 |
1 |
|
T18 |
1 |
|
T104 |
1 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11832144 |
1 |
|
|
T22 |
30 |
|
T23 |
1 |
|
T24 |
9 |
| auto[1] |
9607221 |
1 |
|
|
T26 |
6 |
|
T2 |
5 |
|
T11 |
4 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
4164980 |
1 |
|
|
T26 |
5 |
|
T2 |
3 |
|
T11 |
1 |
| auto[1] |
auto[0] |
auto[1] |
606831 |
1 |
|
|
T11 |
1 |
|
T10 |
1 |
|
T107 |
2 |
| auto[1] |
auto[1] |
auto[0] |
4215558 |
1 |
|
|
T26 |
1 |
|
T2 |
2 |
|
T11 |
2 |
| auto[1] |
auto[1] |
auto[1] |
619852 |
1 |
|
|
T18 |
1 |
|
T104 |
1 |
|
T109 |
2 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11867733 |
1 |
|
|
T22 |
18 |
|
T23 |
1 |
|
T24 |
9 |
| auto[1] |
9571632 |
1 |
|
|
T22 |
12 |
|
T25 |
12 |
|
T26 |
13 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
20213750 |
1 |
|
|
T22 |
30 |
|
T23 |
1 |
|
T24 |
8 |
| auto[1] |
1225615 |
1 |
|
|
T24 |
1 |
|
T10 |
1 |
|
T81 |
1 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11840844 |
1 |
|
|
T22 |
30 |
|
T23 |
1 |
|
T24 |
1 |
| auto[1] |
9598521 |
1 |
|
|
T24 |
8 |
|
T26 |
5 |
|
T2 |
1 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
4193199 |
1 |
|
|
T24 |
7 |
|
T26 |
2 |
|
T2 |
1 |
| auto[1] |
auto[0] |
auto[1] |
613800 |
1 |
|
|
T24 |
1 |
|
T10 |
1 |
|
T81 |
1 |
| auto[1] |
auto[1] |
auto[0] |
4179707 |
1 |
|
|
T26 |
3 |
|
T11 |
5 |
|
T18 |
2 |
| auto[1] |
auto[1] |
auto[1] |
611815 |
1 |
|
|
T109 |
5 |
|
T56 |
23 |
|
T74 |
4933 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11784736 |
1 |
|
|
T22 |
14 |
|
T23 |
1 |
|
T24 |
9 |
| auto[1] |
9654629 |
1 |
|
|
T22 |
16 |
|
T25 |
13 |
|
T26 |
11 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
20214911 |
1 |
|
|
T22 |
30 |
|
T23 |
1 |
|
T24 |
7 |
| auto[1] |
1224454 |
1 |
|
|
T24 |
2 |
|
T18 |
6 |
|
T80 |
1 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11866326 |
1 |
|
|
T22 |
30 |
|
T23 |
1 |
|
T24 |
1 |
| auto[1] |
9573039 |
1 |
|
|
T24 |
8 |
|
T26 |
10 |
|
T2 |
4 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
4161549 |
1 |
|
|
T24 |
6 |
|
T26 |
7 |
|
T2 |
4 |
| auto[1] |
auto[0] |
auto[1] |
609106 |
1 |
|
|
T24 |
2 |
|
T18 |
6 |
|
T115 |
1 |
| auto[1] |
auto[1] |
auto[0] |
4187036 |
1 |
|
|
T26 |
3 |
|
T11 |
2 |
|
T18 |
2 |
| auto[1] |
auto[1] |
auto[1] |
615348 |
1 |
|
|
T80 |
1 |
|
T114 |
1 |
|
T81 |
2 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11813767 |
1 |
|
|
T22 |
17 |
|
T23 |
1 |
|
T24 |
9 |
| auto[1] |
9625598 |
1 |
|
|
T22 |
13 |
|
T25 |
17 |
|
T26 |
12 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
20206723 |
1 |
|
|
T22 |
30 |
|
T23 |
1 |
|
T24 |
7 |
| auto[1] |
1232642 |
1 |
|
|
T24 |
2 |
|
T79 |
1 |
|
T80 |
1 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11821616 |
1 |
|
|
T22 |
30 |
|
T23 |
1 |
|
T24 |
1 |
| auto[1] |
9617749 |
1 |
|
|
T24 |
8 |
|
T26 |
9 |
|
T2 |
7 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
4196117 |
1 |
|
|
T24 |
6 |
|
T26 |
5 |
|
T2 |
7 |
| auto[1] |
auto[0] |
auto[1] |
617428 |
1 |
|
|
T24 |
2 |
|
T80 |
1 |
|
T3 |
2 |
| auto[1] |
auto[1] |
auto[0] |
4188990 |
1 |
|
|
T26 |
4 |
|
T11 |
4 |
|
T79 |
5 |
| auto[1] |
auto[1] |
auto[1] |
615214 |
1 |
|
|
T79 |
1 |
|
T105 |
1 |
|
T114 |
1 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11841766 |
1 |
|
|
T22 |
26 |
|
T23 |
1 |
|
T24 |
9 |
| auto[1] |
9597599 |
1 |
|
|
T22 |
4 |
|
T25 |
17 |
|
T26 |
10 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
20211202 |
1 |
|
|
T22 |
30 |
|
T23 |
1 |
|
T24 |
9 |
| auto[1] |
1228163 |
1 |
|
|
T18 |
3 |
|
T3 |
2 |
|
T10 |
1 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11843344 |
1 |
|
|
T22 |
30 |
|
T23 |
1 |
|
T24 |
9 |
| auto[1] |
9596021 |
1 |
|
|
T26 |
12 |
|
T2 |
4 |
|
T11 |
4 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
4194285 |
1 |
|
|
T26 |
8 |
|
T2 |
3 |
|
T11 |
2 |
| auto[1] |
auto[0] |
auto[1] |
615265 |
1 |
|
|
T18 |
3 |
|
T3 |
2 |
|
T10 |
1 |
| auto[1] |
auto[1] |
auto[0] |
4173573 |
1 |
|
|
T26 |
4 |
|
T2 |
1 |
|
T11 |
2 |
| auto[1] |
auto[1] |
auto[1] |
612898 |
1 |
|
|
T109 |
1 |
|
T56 |
27 |
|
T74 |
5513 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11822727 |
1 |
|
|
T22 |
26 |
|
T23 |
1 |
|
T24 |
9 |
| auto[1] |
9616638 |
1 |
|
|
T22 |
4 |
|
T25 |
22 |
|
T26 |
5 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
20212614 |
1 |
|
|
T22 |
30 |
|
T23 |
1 |
|
T24 |
8 |
| auto[1] |
1226751 |
1 |
|
|
T24 |
1 |
|
T18 |
1 |
|
T105 |
1 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11827580 |
1 |
|
|
T22 |
30 |
|
T23 |
1 |
|
T24 |
1 |
| auto[1] |
9611785 |
1 |
|
|
T24 |
8 |
|
T26 |
11 |
|
T2 |
5 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
4198218 |
1 |
|
|
T24 |
7 |
|
T26 |
11 |
|
T2 |
4 |
| auto[1] |
auto[0] |
auto[1] |
614004 |
1 |
|
|
T24 |
1 |
|
T18 |
1 |
|
T106 |
1 |
| auto[1] |
auto[1] |
auto[0] |
4186816 |
1 |
|
|
T2 |
1 |
|
T11 |
2 |
|
T105 |
3 |
| auto[1] |
auto[1] |
auto[1] |
612747 |
1 |
|
|
T105 |
1 |
|
T10 |
1 |
|
T107 |
4 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11801531 |
1 |
|
|
T22 |
9 |
|
T23 |
1 |
|
T24 |
9 |
| auto[1] |
9637834 |
1 |
|
|
T22 |
21 |
|
T25 |
9 |
|
T26 |
9 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
20216511 |
1 |
|
|
T22 |
30 |
|
T23 |
1 |
|
T24 |
9 |
| auto[1] |
1222854 |
1 |
|
|
T18 |
1 |
|
T10 |
1 |
|
T106 |
1 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11861906 |
1 |
|
|
T22 |
30 |
|
T23 |
1 |
|
T24 |
9 |
| auto[1] |
9577459 |
1 |
|
|
T26 |
13 |
|
T2 |
6 |
|
T18 |
10 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
4176311 |
1 |
|
|
T26 |
9 |
|
T2 |
4 |
|
T18 |
8 |
| auto[1] |
auto[0] |
auto[1] |
611726 |
1 |
|
|
T106 |
1 |
|
T109 |
1 |
|
T56 |
20 |
| auto[1] |
auto[1] |
auto[0] |
4178294 |
1 |
|
|
T26 |
4 |
|
T2 |
2 |
|
T18 |
1 |
| auto[1] |
auto[1] |
auto[1] |
611128 |
1 |
|
|
T18 |
1 |
|
T10 |
1 |
|
T107 |
1 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11849525 |
1 |
|
|
T22 |
8 |
|
T23 |
1 |
|
T24 |
9 |
| auto[1] |
9589840 |
1 |
|
|
T22 |
22 |
|
T25 |
10 |
|
T26 |
8 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
20210417 |
1 |
|
|
T22 |
30 |
|
T23 |
1 |
|
T24 |
9 |
| auto[1] |
1228948 |
1 |
|
|
T11 |
1 |
|
T104 |
1 |
|
T115 |
1 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11830629 |
1 |
|
|
T22 |
30 |
|
T23 |
1 |
|
T24 |
1 |
| auto[1] |
9608736 |
1 |
|
|
T24 |
8 |
|
T26 |
9 |
|
T2 |
6 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
4196807 |
1 |
|
|
T24 |
8 |
|
T26 |
7 |
|
T2 |
3 |
| auto[1] |
auto[0] |
auto[1] |
614902 |
1 |
|
|
T11 |
1 |
|
T104 |
1 |
|
T107 |
2 |
| auto[1] |
auto[1] |
auto[0] |
4182981 |
1 |
|
|
T26 |
2 |
|
T2 |
3 |
|
T108 |
2 |
| auto[1] |
auto[1] |
auto[1] |
614046 |
1 |
|
|
T115 |
1 |
|
T109 |
5 |
|
T56 |
30 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11826228 |
1 |
|
|
T22 |
11 |
|
T23 |
1 |
|
T24 |
9 |
| auto[1] |
9613137 |
1 |
|
|
T22 |
19 |
|
T25 |
15 |
|
T26 |
9 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
20207166 |
1 |
|
|
T22 |
30 |
|
T23 |
1 |
|
T24 |
8 |
| auto[1] |
1232199 |
1 |
|
|
T24 |
1 |
|
T11 |
1 |
|
T18 |
3 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11821322 |
1 |
|
|
T22 |
30 |
|
T23 |
1 |
|
T24 |
1 |
| auto[1] |
9618043 |
1 |
|
|
T24 |
8 |
|
T26 |
5 |
|
T2 |
4 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
4198175 |
1 |
|
|
T24 |
7 |
|
T26 |
4 |
|
T2 |
2 |
| auto[1] |
auto[0] |
auto[1] |
616170 |
1 |
|
|
T24 |
1 |
|
T18 |
3 |
|
T104 |
1 |
| auto[1] |
auto[1] |
auto[0] |
4187669 |
1 |
|
|
T26 |
1 |
|
T2 |
2 |
|
T11 |
3 |
| auto[1] |
auto[1] |
auto[1] |
616029 |
1 |
|
|
T11 |
1 |
|
T81 |
2 |
|
T109 |
2 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11809207 |
1 |
|
|
T22 |
9 |
|
T23 |
1 |
|
T24 |
9 |
| auto[1] |
9630158 |
1 |
|
|
T22 |
21 |
|
T25 |
14 |
|
T26 |
8 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
20210145 |
1 |
|
|
T22 |
30 |
|
T23 |
1 |
|
T24 |
9 |
| auto[1] |
1229220 |
1 |
|
|
T18 |
2 |
|
T10 |
1 |
|
T106 |
1 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11831854 |
1 |
|
|
T22 |
30 |
|
T23 |
1 |
|
T24 |
9 |
| auto[1] |
9607511 |
1 |
|
|
T26 |
9 |
|
T2 |
8 |
|
T11 |
1 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
4179364 |
1 |
|
|
T26 |
8 |
|
T2 |
4 |
|
T11 |
1 |
| auto[1] |
auto[0] |
auto[1] |
611545 |
1 |
|
|
T18 |
2 |
|
T106 |
1 |
|
T109 |
2 |
| auto[1] |
auto[1] |
auto[0] |
4198927 |
1 |
|
|
T26 |
1 |
|
T2 |
4 |
|
T79 |
6 |
| auto[1] |
auto[1] |
auto[1] |
617675 |
1 |
|
|
T10 |
1 |
|
T109 |
5 |
|
T56 |
16 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11806886 |
1 |
|
|
T22 |
22 |
|
T23 |
1 |
|
T24 |
9 |
| auto[1] |
9632479 |
1 |
|
|
T22 |
8 |
|
T25 |
13 |
|
T26 |
9 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
20210888 |
1 |
|
|
T22 |
30 |
|
T23 |
1 |
|
T24 |
9 |
| auto[1] |
1228477 |
1 |
|
|
T108 |
1 |
|
T10 |
1 |
|
T107 |
2 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11824894 |
1 |
|
|
T22 |
30 |
|
T23 |
1 |
|
T24 |
9 |
| auto[1] |
9614471 |
1 |
|
|
T26 |
12 |
|
T2 |
3 |
|
T11 |
1 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
4190044 |
1 |
|
|
T26 |
9 |
|
T2 |
1 |
|
T11 |
1 |
| auto[1] |
auto[0] |
auto[1] |
612047 |
1 |
|
|
T108 |
1 |
|
T10 |
1 |
|
T109 |
6 |
| auto[1] |
auto[1] |
auto[0] |
4195950 |
1 |
|
|
T26 |
3 |
|
T2 |
2 |
|
T33 |
1 |
| auto[1] |
auto[1] |
auto[1] |
616430 |
1 |
|
|
T107 |
2 |
|
T109 |
3 |
|
T56 |
23 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |
Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11826988 |
1 |
|
|
T22 |
11 |
|
T23 |
1 |
|
T24 |
9 |
| auto[1] |
9612377 |
1 |
|
|
T22 |
19 |
|
T25 |
12 |
|
T26 |
10 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
20212096 |
1 |
|
|
T22 |
30 |
|
T23 |
1 |
|
T24 |
6 |
| auto[1] |
1227269 |
1 |
|
|
T24 |
3 |
|
T108 |
1 |
|
T107 |
1 |