Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11805318 |
1 |
|
|
T22 |
15 |
|
T23 |
1 |
|
T24 |
9 |
| auto[1] |
9634047 |
1 |
|
|
T22 |
15 |
|
T25 |
19 |
|
T26 |
6 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
20212388 |
1 |
|
|
T22 |
30 |
|
T23 |
1 |
|
T24 |
9 |
| auto[1] |
1226977 |
1 |
|
|
T115 |
1 |
|
T81 |
3 |
|
T109 |
6 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11830266 |
1 |
|
|
T22 |
30 |
|
T23 |
1 |
|
T24 |
9 |
| auto[1] |
9609099 |
1 |
|
|
T26 |
14 |
|
T2 |
4 |
|
T14 |
1 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
4202292 |
1 |
|
|
T26 |
11 |
|
T2 |
3 |
|
T14 |
1 |
| auto[1] |
auto[0] |
auto[1] |
615328 |
1 |
|
|
T81 |
3 |
|
T109 |
2 |
|
T56 |
14 |
| auto[1] |
auto[1] |
auto[0] |
4179830 |
1 |
|
|
T26 |
3 |
|
T2 |
1 |
|
T104 |
6 |
| auto[1] |
auto[1] |
auto[1] |
611649 |
1 |
|
|
T115 |
1 |
|
T109 |
4 |
|
T56 |
26 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |