Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11842178 |
1 |
|
|
T22 |
30 |
|
T23 |
1 |
|
T24 |
1 |
| auto[1] |
9597187 |
1 |
|
|
T24 |
8 |
|
T26 |
8 |
|
T2 |
4 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
4192567 |
1 |
|
|
T24 |
5 |
|
T26 |
7 |
|
T2 |
3 |
| auto[1] |
auto[0] |
auto[1] |
615025 |
1 |
|
|
T24 |
3 |
|
T109 |
3 |
|
T56 |
13 |
| auto[1] |
auto[1] |
auto[0] |
4177351 |
1 |
|
|
T26 |
1 |
|
T2 |
1 |
|
T11 |
1 |
| auto[1] |
auto[1] |
auto[1] |
612244 |
1 |
|
|
T108 |
1 |
|
T107 |
1 |
|
T109 |
2 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |