Summary for Variable intr_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11807314 |
1 |
|
|
T22 |
19 |
|
T23 |
1 |
|
T24 |
9 |
| auto[1] |
9632051 |
1 |
|
|
T22 |
11 |
|
T25 |
17 |
|
T26 |
12 |
Summary for Variable intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for intr_state
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
20208066 |
1 |
|
|
T22 |
30 |
|
T23 |
1 |
|
T24 |
9 |
| auto[1] |
1231299 |
1 |
|
|
T11 |
1 |
|
T18 |
2 |
|
T108 |
1 |
Summary for Variable type_ctrl_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for type_ctrl_en
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
11812424 |
1 |
|
|
T22 |
30 |
|
T23 |
1 |
|
T24 |
9 |
| auto[1] |
9626941 |
1 |
|
|
T26 |
7 |
|
T2 |
3 |
|
T11 |
5 |
Summary for Cross cp_cross_type_en_state
Samples crossed: type_ctrl_en intr_en intr_state
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
4 |
0 |
4 |
100.00 |
|
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for cp_cross_type_en_state
Bins
| type_ctrl_en | intr_en | intr_state | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[1] |
auto[0] |
auto[0] |
4189911 |
1 |
|
|
T26 |
4 |
|
T14 |
1 |
|
T18 |
19 |
| auto[1] |
auto[0] |
auto[1] |
613473 |
1 |
|
|
T18 |
2 |
|
T109 |
7 |
|
T56 |
22 |
| auto[1] |
auto[1] |
auto[0] |
4205731 |
1 |
|
|
T26 |
3 |
|
T2 |
3 |
|
T11 |
4 |
| auto[1] |
auto[1] |
auto[1] |
617826 |
1 |
|
|
T11 |
1 |
|
T108 |
1 |
|
T56 |
26 |
User Defined Cross Bins for cp_cross_type_en_state
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| intr_type_disabled |
0 |
Excluded |